Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
77.03	90.91	61.70	87.88		57.14	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	44440015	12009	0	0
late_debug_enable_rd_A	44440015	1795	0	0
late_debug_enable_regwen_rd_A	44440015	1833	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	44440015	12009	0	0
T36	294876	20	0	0
T37	204067	27	0	0
T38	324030	18	0	0
T39	9946	192	0	0
T66	14152	893	0	0
T67	5165	298	0	0
T68	19005	698	0	0
T74	5688	58	0	0
T75	9463	437	0	0
T76	101798	8	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	44440015	1795	0	0
T38	324030	10	0	0
T40	28614	44	0	0
T41	38787	48	0	0
T76	101798	81	0	0
T77	23621	23	0	0
T78	24988	135	0	0
T82	9002	10	0	0
T83	9054	12	0	0
T86	366164	198	0	0
T120	25121	19	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	44440015	1833	0	0
T38	324030	13	0	0
T40	28614	18	0	0
T41	38787	23	0	0
T76	101798	74	0	0
T77	23621	26	0	0
T78	24988	132	0	0
T82	9002	14	0	0
T83	9054	2	0	0
T86	366164	231	0	0
T120	25121	8	0	0