Unified Coverage Report :: Module :: prim_generic_clock_mux2

Module : prim_generic_clock_mux2

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic	96.30	100.00	88.89				100.00
tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic	96.30	100.00	88.89				100.00
tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.30	100.00	88.89				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.30	100.00	88.89				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_clock_mux2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.30	100.00	88.89				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.30	100.00	88.89				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_rst_n_mux2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_scan.i_dft_tck_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Module : prim_generic_clock_mux2

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T33

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T33
1	1	Covered	T29,T33

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T29,T33
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_clock_mux2

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	27177043	27175945	0	0
selKnown1	38966185	38965087	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	27177043	27175945	0	0
T1	216	214	0	0
T2	334	332	0	0
T3	274580	274578	0	0
T4	33868	33866	0	0
T5	22	20	0	0
T6	10	8	0	0
T7	3428	3426	0	0
T8	84958	84956	0	0
T11	62322	62320	0	0
T13	150304	150300	0	0
T14	0	22	0	0
T15	0	16	0	0
T16	0	10	0	0
T20	2	0	0	0
T25	42	40	0	0
T28	296	294	0	0
T30	2	0	0	0
T35	216	214	0	0
T42	2	0	0	0
T45	2	0	0	0
T46	2	0	0	0
T47	2	0	0	0
T57	0	10	0	0
T69	0	16	0	0
T70	0	28	0	0
T121	0	21	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	38966185	38965087	0	0
T1	1201	1199	0	0
T2	1996	1994	0	0
T3	221884	221882	0	0
T4	117072	117070	0	0
T5	8	6	0	0
T6	8	6	0	0
T7	3234	3232	0	0
T8	205003	205001	0	0
T11	88219	88217	0	0
T13	337594	337590	0	0
T14	0	22	0	0
T15	0	16	0	0
T16	0	6	0	0
T20	2	0	0	0
T25	42	40	0	0
T28	1433	1431	0	0
T30	2	0	0	0
T35	1735	1733	0	0
T42	2	0	0	0
T45	2	0	0	0
T46	2	0	0	0
T47	2	0	0	0
T69	0	16	0	0
T70	0	28	0	0
T121	0	42	0	0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T33

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T33
1	1	Covered	T29,T33

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	10641296	10641125	0	0
selKnown1	22430613	22430442	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	10641296	10641125	0	0
T1	108	107	0	0
T2	167	166	0	0
T3	137290	137289	0	0
T4	16934	16933	0	0
T7	1714	1713	0	0
T8	42479	42478	0	0
T11	31161	31160	0	0
T13	75146	75145	0	0
T28	148	147	0	0
T35	108	107	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	22430613	22430442	0	0
T1	1093	1092	0	0
T2	1829	1828	0	0
T3	84594	84593	0	0
T4	100138	100137	0	0
T7	1520	1519	0	0
T8	162524	162523	0	0
T11	57058	57057	0	0
T13	262436	262435	0	0
T28	1285	1284	0	0
T35	1627	1626	0	0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T33

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T33
1	1	Covered	T29,T33

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	750	579	0	0
selKnown1	721	550	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	750	579	0	0
T5	11	10	0	0
T6	5	4	0	0
T13	6	5	0	0
T14	0	11	0	0
T15	0	8	0	0
T16	0	3	0	0
T20	1	0	0	0
T25	21	20	0	0
T30	1	0	0	0
T42	1	0	0	0
T45	1	0	0	0
T46	1	0	0	0
T47	1	0	0	0
T69	0	8	0	0
T70	0	14	0	0
T121	0	21	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	721	550	0	0
T5	4	3	0	0
T6	4	3	0	0
T13	6	5	0	0
T14	0	11	0	0
T15	0	8	0	0
T16	0	3	0	0
T20	1	0	0	0
T25	21	20	0	0
T30	1	0	0	0
T42	1	0	0	0
T45	1	0	0	0
T46	1	0	0	0
T47	1	0	0	0
T69	0	8	0	0
T70	0	14	0	0
T121	0	21	0	0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T33

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T33
1	1	Covered	T29,T33

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T29,T33
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	16532952	16532574	0	0
selKnown1	16532952	16532574	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	16532952	16532574	0	0
T1	108	107	0	0
T2	167	166	0	0
T3	137290	137289	0	0
T4	16934	16933	0	0
T7	1714	1713	0	0
T8	42479	42478	0	0
T11	31161	31160	0	0
T13	75146	75145	0	0
T28	148	147	0	0
T35	108	107	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	16532952	16532574	0	0
T1	108	107	0	0
T2	167	166	0	0
T3	137290	137289	0	0
T4	16934	16933	0	0
T7	1714	1713	0	0
T8	42479	42478	0	0
T11	31161	31160	0	0
T13	75146	75145	0	0
T28	148	147	0	0
T35	108	107	0	0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T33

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T33
1	1	Covered	T29,T33

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T29,T33
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	2045	1667	0	0
selKnown1	1899	1521	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	2045	1667	0	0
T5	11	10	0	0
T6	5	4	0	0
T13	6	5	0	0
T14	0	11	0	0
T15	0	8	0	0
T16	0	7	0	0
T20	1	0	0	0
T25	21	20	0	0
T30	1	0	0	0
T42	1	0	0	0
T45	1	0	0	0
T46	1	0	0	0
T47	1	0	0	0
T57	0	10	0	0
T69	0	8	0	0
T70	0	14	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	1899	1521	0	0
T5	4	3	0	0
T6	4	3	0	0
T13	6	5	0	0
T14	0	11	0	0
T15	0	8	0	0
T16	0	3	0	0
T20	1	0	0	0
T25	21	20	0	0
T30	1	0	0	0
T42	1	0	0	0
T45	1	0	0	0
T46	1	0	0	0
T47	1	0	0	0
T69	0	8	0	0
T70	0	14	0	0
T121	0	21	0	0