Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
81.45 94.44 80.19 87.69 76.92 83.66 98.42 48.82


Total test records in report: 377
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html
T117 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.1704166167 Apr 16 02:37:20 PM PDT 24 Apr 16 02:37:29 PM PDT 24 2141178499 ps
T277 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.423347981 Apr 16 02:37:24 PM PDT 24 Apr 16 02:37:28 PM PDT 24 518274125 ps
T278 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.2707248026 Apr 16 02:37:08 PM PDT 24 Apr 16 02:37:09 PM PDT 24 81630413 ps
T279 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.631222069 Apr 16 02:37:08 PM PDT 24 Apr 16 02:37:10 PM PDT 24 639505602 ps
T280 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.2988239677 Apr 16 02:37:29 PM PDT 24 Apr 16 02:37:32 PM PDT 24 35429198 ps
T94 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1266715780 Apr 16 02:36:57 PM PDT 24 Apr 16 02:37:00 PM PDT 24 1139793632 ps
T104 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2775451238 Apr 16 02:37:12 PM PDT 24 Apr 16 02:37:15 PM PDT 24 216317739 ps
T125 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3608595257 Apr 16 02:37:22 PM PDT 24 Apr 16 02:37:25 PM PDT 24 74180818 ps
T281 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.999529264 Apr 16 02:37:15 PM PDT 24 Apr 16 02:37:18 PM PDT 24 69903000 ps
T282 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3909216762 Apr 16 02:36:54 PM PDT 24 Apr 16 02:38:11 PM PDT 24 8623263975 ps
T283 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2233616773 Apr 16 02:37:27 PM PDT 24 Apr 16 02:37:29 PM PDT 24 150093241 ps
T111 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.991815714 Apr 16 02:37:13 PM PDT 24 Apr 16 02:37:16 PM PDT 24 145322869 ps
T284 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1855187255 Apr 16 02:36:58 PM PDT 24 Apr 16 02:37:01 PM PDT 24 36709803 ps
T285 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3892861094 Apr 16 02:37:03 PM PDT 24 Apr 16 02:37:04 PM PDT 24 192216181 ps
T286 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.3183620730 Apr 16 02:37:20 PM PDT 24 Apr 16 02:37:21 PM PDT 24 45309216 ps
T287 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.2352438225 Apr 16 02:37:08 PM PDT 24 Apr 16 02:37:10 PM PDT 24 333663432 ps
T288 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.1100162973 Apr 16 02:37:01 PM PDT 24 Apr 16 02:37:02 PM PDT 24 49101622 ps
T118 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2855207543 Apr 16 02:36:59 PM PDT 24 Apr 16 02:37:09 PM PDT 24 6599373529 ps
T289 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.1023865361 Apr 16 02:37:02 PM PDT 24 Apr 16 02:37:03 PM PDT 24 23722176 ps
T290 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3652942768 Apr 16 02:37:07 PM PDT 24 Apr 16 02:37:10 PM PDT 24 72569098 ps
T135 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.2784049460 Apr 16 02:37:11 PM PDT 24 Apr 16 02:37:31 PM PDT 24 3260889550 ps
T291 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.1040778931 Apr 16 02:37:13 PM PDT 24 Apr 16 02:37:16 PM PDT 24 439806852 ps
T292 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.3295518734 Apr 16 02:37:09 PM PDT 24 Apr 16 02:37:15 PM PDT 24 1298867201 ps
T138 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.232148012 Apr 16 02:37:11 PM PDT 24 Apr 16 02:37:20 PM PDT 24 671447383 ps
T126 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.2505610761 Apr 16 02:37:17 PM PDT 24 Apr 16 02:37:22 PM PDT 24 1510035316 ps
T293 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.2636533701 Apr 16 02:36:57 PM PDT 24 Apr 16 02:36:59 PM PDT 24 35894694 ps
T294 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.4108768569 Apr 16 02:37:21 PM PDT 24 Apr 16 02:37:24 PM PDT 24 55098884 ps
T295 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.2914944165 Apr 16 02:37:27 PM PDT 24 Apr 16 02:37:30 PM PDT 24 1201493501 ps
T296 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.1224243494 Apr 16 02:37:00 PM PDT 24 Apr 16 02:37:05 PM PDT 24 554790264 ps
T297 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.2940971404 Apr 16 02:37:22 PM PDT 24 Apr 16 02:37:28 PM PDT 24 6375983670 ps
T112 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.758675337 Apr 16 02:36:58 PM PDT 24 Apr 16 02:37:37 PM PDT 24 14573301443 ps
T298 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.3794709608 Apr 16 02:37:27 PM PDT 24 Apr 16 02:37:31 PM PDT 24 704394763 ps
T299 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.803220151 Apr 16 02:36:59 PM PDT 24 Apr 16 02:37:01 PM PDT 24 83384821 ps
T300 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.4086869239 Apr 16 02:37:06 PM PDT 24 Apr 16 02:37:08 PM PDT 24 199783804 ps
T301 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.3671667226 Apr 16 02:37:11 PM PDT 24 Apr 16 02:37:14 PM PDT 24 610899813 ps
T302 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.4161846747 Apr 16 02:37:26 PM PDT 24 Apr 16 02:37:29 PM PDT 24 134433543 ps
T105 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.2644816660 Apr 16 02:37:32 PM PDT 24 Apr 16 02:37:36 PM PDT 24 320479359 ps
T303 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.4248007036 Apr 16 02:37:04 PM PDT 24 Apr 16 02:37:06 PM PDT 24 117794582 ps
T304 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3684931167 Apr 16 02:37:29 PM PDT 24 Apr 16 02:37:33 PM PDT 24 1526891300 ps
T305 /workspace/coverage/cover_reg_top/29.rv_dm_tap_fsm_rand_reset.1247768580 Apr 16 02:37:36 PM PDT 24 Apr 16 02:37:48 PM PDT 24 13578799715 ps
T306 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.727916820 Apr 16 02:37:20 PM PDT 24 Apr 16 02:37:22 PM PDT 24 86391394 ps
T307 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1979564732 Apr 16 02:37:11 PM PDT 24 Apr 16 02:37:49 PM PDT 24 22040455582 ps
T106 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.3428103385 Apr 16 02:37:34 PM PDT 24 Apr 16 02:37:39 PM PDT 24 311792803 ps
T308 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1312463282 Apr 16 02:37:10 PM PDT 24 Apr 16 02:37:20 PM PDT 24 11621849509 ps
T107 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.4030753941 Apr 16 02:37:11 PM PDT 24 Apr 16 02:37:17 PM PDT 24 1093694272 ps
T134 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.164123610 Apr 16 02:36:58 PM PDT 24 Apr 16 02:37:08 PM PDT 24 413257800 ps
T113 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.682095570 Apr 16 02:37:11 PM PDT 24 Apr 16 02:38:28 PM PDT 24 21972261439 ps
T114 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.1732120069 Apr 16 02:37:39 PM PDT 24 Apr 16 02:37:42 PM PDT 24 72073500 ps
T309 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.3143782115 Apr 16 02:37:09 PM PDT 24 Apr 16 02:37:13 PM PDT 24 731873080 ps
T310 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2586248444 Apr 16 02:36:58 PM PDT 24 Apr 16 02:37:01 PM PDT 24 1013122154 ps
T115 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1940584579 Apr 16 02:37:18 PM PDT 24 Apr 16 02:37:21 PM PDT 24 127459864 ps
T311 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2541195056 Apr 16 02:37:33 PM PDT 24 Apr 16 02:37:35 PM PDT 24 199307104 ps
T312 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3104585644 Apr 16 02:37:34 PM PDT 24 Apr 16 02:37:39 PM PDT 24 1194419300 ps
T313 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.648925983 Apr 16 02:37:33 PM PDT 24 Apr 16 02:37:39 PM PDT 24 71688570 ps
T314 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.2615539637 Apr 16 02:37:10 PM PDT 24 Apr 16 02:37:16 PM PDT 24 2650165151 ps
T315 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.142672529 Apr 16 02:36:59 PM PDT 24 Apr 16 02:37:01 PM PDT 24 125882291 ps
T316 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.1541769115 Apr 16 02:37:11 PM PDT 24 Apr 16 02:37:42 PM PDT 24 10506555393 ps
T317 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.2357535386 Apr 16 02:37:40 PM PDT 24 Apr 16 02:38:02 PM PDT 24 1141650507 ps
T318 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.1368770303 Apr 16 02:38:14 PM PDT 24 Apr 16 02:38:19 PM PDT 24 152118441 ps
T319 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.4138443794 Apr 16 02:36:56 PM PDT 24 Apr 16 02:36:59 PM PDT 24 95440218 ps
T320 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3361208333 Apr 16 02:37:31 PM PDT 24 Apr 16 02:37:39 PM PDT 24 803555570 ps
T321 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3266177117 Apr 16 02:37:32 PM PDT 24 Apr 16 02:37:39 PM PDT 24 291247132 ps
T322 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1961430669 Apr 16 02:37:11 PM PDT 24 Apr 16 02:37:13 PM PDT 24 44659176 ps
T116 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.2883057028 Apr 16 02:37:40 PM PDT 24 Apr 16 02:37:43 PM PDT 24 57573496 ps
T323 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.201845063 Apr 16 02:37:27 PM PDT 24 Apr 16 02:37:32 PM PDT 24 1095842031 ps
T95 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.1148141147 Apr 16 02:37:09 PM PDT 24 Apr 16 02:37:12 PM PDT 24 194831074 ps
T324 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.2253150933 Apr 16 02:37:34 PM PDT 24 Apr 16 02:37:36 PM PDT 24 75607080 ps
T325 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.166991496 Apr 16 02:37:14 PM PDT 24 Apr 16 02:37:15 PM PDT 24 17502358 ps
T326 /workspace/coverage/cover_reg_top/10.rv_dm_tap_fsm_rand_reset.1294869083 Apr 16 02:37:29 PM PDT 24 Apr 16 02:37:43 PM PDT 24 13460355214 ps
T327 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.2505320176 Apr 16 02:37:28 PM PDT 24 Apr 16 02:37:32 PM PDT 24 90485176 ps
T328 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.2044148128 Apr 16 02:37:29 PM PDT 24 Apr 16 02:37:36 PM PDT 24 4767076140 ps
T329 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1658536299 Apr 16 02:37:09 PM PDT 24 Apr 16 02:37:10 PM PDT 24 43035547 ps
T330 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.2849520734 Apr 16 02:37:16 PM PDT 24 Apr 16 02:37:22 PM PDT 24 919107734 ps
T331 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2061595522 Apr 16 02:37:37 PM PDT 24 Apr 16 02:37:46 PM PDT 24 2764120699 ps
T332 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.1843595353 Apr 16 02:37:11 PM PDT 24 Apr 16 02:37:16 PM PDT 24 2275147673 ps
T333 /workspace/coverage/cover_reg_top/12.rv_dm_tap_fsm_rand_reset.3992887798 Apr 16 02:37:32 PM PDT 24 Apr 16 02:37:46 PM PDT 24 6157757884 ps
T334 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.289091012 Apr 16 02:37:03 PM PDT 24 Apr 16 02:37:05 PM PDT 24 76709602 ps
T96 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.1067402155 Apr 16 02:36:54 PM PDT 24 Apr 16 02:36:56 PM PDT 24 180415879 ps
T335 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.1059593433 Apr 16 02:37:10 PM PDT 24 Apr 16 02:37:12 PM PDT 24 76747641 ps
T336 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.869457284 Apr 16 02:37:27 PM PDT 24 Apr 16 02:37:32 PM PDT 24 768441391 ps
T337 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1393245205 Apr 16 02:37:11 PM PDT 24 Apr 16 02:37:20 PM PDT 24 415860852 ps
T338 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3295471667 Apr 16 02:36:55 PM PDT 24 Apr 16 02:36:57 PM PDT 24 147878322 ps
T339 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.4291419904 Apr 16 02:37:25 PM PDT 24 Apr 16 02:37:28 PM PDT 24 325237254 ps
T340 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.2843025290 Apr 16 02:37:12 PM PDT 24 Apr 16 02:37:15 PM PDT 24 38914188 ps
T341 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.646199396 Apr 16 02:36:55 PM PDT 24 Apr 16 02:37:08 PM PDT 24 7556030340 ps
T342 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1193907246 Apr 16 02:37:21 PM PDT 24 Apr 16 02:37:23 PM PDT 24 156728345 ps
T343 /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2861924628 Apr 16 02:37:11 PM PDT 24 Apr 16 02:37:22 PM PDT 24 15646499064 ps
T108 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1600295541 Apr 16 02:37:30 PM PDT 24 Apr 16 02:37:35 PM PDT 24 257318246 ps
T344 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.2828175553 Apr 16 02:37:29 PM PDT 24 Apr 16 02:37:31 PM PDT 24 69376770 ps
T345 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2373346767 Apr 16 02:37:38 PM PDT 24 Apr 16 02:37:47 PM PDT 24 386810831 ps
T346 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.1154821300 Apr 16 02:37:34 PM PDT 24 Apr 16 02:37:38 PM PDT 24 133750150 ps
T347 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3050638814 Apr 16 02:37:23 PM PDT 24 Apr 16 02:37:26 PM PDT 24 564554815 ps
T136 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.2490430587 Apr 16 02:37:27 PM PDT 24 Apr 16 02:37:37 PM PDT 24 606942372 ps
T348 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.644836415 Apr 16 02:37:15 PM PDT 24 Apr 16 02:37:18 PM PDT 24 388427010 ps
T349 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.2637852600 Apr 16 02:37:24 PM PDT 24 Apr 16 02:37:26 PM PDT 24 75582825 ps
T350 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.261486299 Apr 16 02:37:39 PM PDT 24 Apr 16 02:37:42 PM PDT 24 537171947 ps
T351 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2791427542 Apr 16 02:36:59 PM PDT 24 Apr 16 02:37:13 PM PDT 24 5632141490 ps
T352 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.2449866642 Apr 16 02:37:24 PM PDT 24 Apr 16 02:37:29 PM PDT 24 256282725 ps
T353 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.1623519732 Apr 16 02:36:58 PM PDT 24 Apr 16 02:37:00 PM PDT 24 26318641 ps
T130 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2658253519 Apr 16 02:37:18 PM PDT 24 Apr 16 02:37:37 PM PDT 24 3336769232 ps
T354 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.263431039 Apr 16 02:36:55 PM PDT 24 Apr 16 02:37:03 PM PDT 24 8849329700 ps
T355 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.173167368 Apr 16 02:37:12 PM PDT 24 Apr 16 02:38:16 PM PDT 24 37137929026 ps
T356 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1291113106 Apr 16 02:37:22 PM PDT 24 Apr 16 02:37:23 PM PDT 24 31157204 ps
T357 /workspace/coverage/cover_reg_top/15.rv_dm_tap_fsm_rand_reset.3061353771 Apr 16 02:37:31 PM PDT 24 Apr 16 02:37:44 PM PDT 24 13104215949 ps
T358 /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.3689414001 Apr 16 02:37:17 PM PDT 24 Apr 16 02:37:33 PM PDT 24 10094067330 ps
T359 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.2821456025 Apr 16 02:36:53 PM PDT 24 Apr 16 02:37:10 PM PDT 24 1656755431 ps
T360 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2400752541 Apr 16 02:37:01 PM PDT 24 Apr 16 02:37:03 PM PDT 24 69428133 ps
T109 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2574679171 Apr 16 02:37:01 PM PDT 24 Apr 16 02:38:18 PM PDT 24 7729298765 ps
T361 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.1901815341 Apr 16 02:37:09 PM PDT 24 Apr 16 02:37:13 PM PDT 24 2874432068 ps
T362 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.1984016548 Apr 16 02:37:11 PM PDT 24 Apr 16 02:37:17 PM PDT 24 299375627 ps
T363 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.1905209334 Apr 16 02:37:00 PM PDT 24 Apr 16 02:37:02 PM PDT 24 90276130 ps
T97 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2551698961 Apr 16 02:37:08 PM PDT 24 Apr 16 02:37:10 PM PDT 24 434834637 ps
T364 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1105369522 Apr 16 02:36:59 PM PDT 24 Apr 16 02:37:00 PM PDT 24 22410480 ps
T365 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.1713428635 Apr 16 02:37:22 PM PDT 24 Apr 16 02:37:24 PM PDT 24 1621931806 ps
T98 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2071936728 Apr 16 02:37:04 PM PDT 24 Apr 16 02:37:07 PM PDT 24 1453405139 ps
T366 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.3554678434 Apr 16 02:37:20 PM PDT 24 Apr 16 02:37:22 PM PDT 24 241576534 ps
T367 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.3837293515 Apr 16 02:36:59 PM PDT 24 Apr 16 02:37:54 PM PDT 24 1423447542 ps
T368 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.1642604173 Apr 16 02:37:39 PM PDT 24 Apr 16 02:37:42 PM PDT 24 43651302 ps
T369 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1357298758 Apr 16 02:37:08 PM PDT 24 Apr 16 02:37:11 PM PDT 24 198741327 ps
T370 /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.2197708022 Apr 16 02:37:36 PM PDT 24 Apr 16 02:37:41 PM PDT 24 1323938043 ps
T371 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.15174424 Apr 16 02:37:10 PM PDT 24 Apr 16 02:37:15 PM PDT 24 421371014 ps
T372 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3929232647 Apr 16 02:37:33 PM PDT 24 Apr 16 02:37:36 PM PDT 24 73872453 ps
T373 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.242007768 Apr 16 02:37:12 PM PDT 24 Apr 16 02:37:40 PM PDT 24 1445437430 ps
T374 /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.3367577916 Apr 16 02:37:18 PM PDT 24 Apr 16 02:37:39 PM PDT 24 6874006987 ps
T375 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.80289992 Apr 16 02:37:28 PM PDT 24 Apr 16 02:37:32 PM PDT 24 520397975 ps
T376 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.992864888 Apr 16 02:37:29 PM PDT 24 Apr 16 02:37:31 PM PDT 24 322609638 ps
T377 /workspace/coverage/cover_reg_top/28.rv_dm_tap_fsm_rand_reset.2079644625 Apr 16 02:37:37 PM PDT 24 Apr 16 02:37:54 PM PDT 24 4463316344 ps

Test location /workspace/coverage/default/21.rv_dm_stress_all.1726814629
Short name T4
Test name
Test status
Simulation time 963750519 ps
CPU time 2.36 seconds
Started Apr 16 12:50:17 PM PDT 24
Finished Apr 16 12:50:21 PM PDT 24
Peak memory 205312 kb
Host smart-8c7817bd-ed51-4cb8-bba1-a19f3771dfb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726814629 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.1726814629
Directory /workspace/21.rv_dm_stress_all/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.4151483211
Short name T13
Test name
Test status
Simulation time 25861391239 ps
CPU time 44.79 seconds
Started Apr 16 12:49:57 PM PDT 24
Finished Apr 16 12:50:43 PM PDT 24
Peak memory 213768 kb
Host smart-9b018292-3409-4213-b371-03e6efe2c15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151483211 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.4151483211
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/33.rv_dm_tap_fsm_rand_reset.2970137449
Short name T32
Test name
Test status
Simulation time 10300634744 ps
CPU time 34.21 seconds
Started Apr 16 02:37:41 PM PDT 24
Finished Apr 16 02:38:16 PM PDT 24
Peak memory 221336 kb
Host smart-fe8bfe75-abaf-4603-9845-43c6198e328d
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970137449 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 33.rv_dm_tap_fsm_rand_reset.2970137449
Directory /workspace/33.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all.139876121
Short name T15
Test name
Test status
Simulation time 2282200122 ps
CPU time 7.91 seconds
Started Apr 16 12:49:49 PM PDT 24
Finished Apr 16 12:49:58 PM PDT 24
Peak memory 205356 kb
Host smart-5d697f5e-ca5b-4e56-8d12-cb0febf814f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139876121 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.139876121
Directory /workspace/1.rv_dm_stress_all/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.3060262395
Short name T1
Test name
Test status
Simulation time 23520645 ps
CPU time 0.73 seconds
Started Apr 16 12:49:52 PM PDT 24
Finished Apr 16 12:49:56 PM PDT 24
Peak memory 205120 kb
Host smart-e12f5a70-7bd9-481c-a229-b74f77eaf339
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060262395 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.3060262395
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2654350712
Short name T33
Test name
Test status
Simulation time 1055463246 ps
CPU time 16.45 seconds
Started Apr 16 02:37:22 PM PDT 24
Finished Apr 16 02:37:40 PM PDT 24
Peak memory 221136 kb
Host smart-277a2ec7-1898-41cd-b0c6-a37a8b7307b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654350712 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.2654350712
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all.3151664554
Short name T5
Test name
Test status
Simulation time 5187341619 ps
CPU time 5.6 seconds
Started Apr 16 12:49:50 PM PDT 24
Finished Apr 16 12:49:57 PM PDT 24
Peak memory 205368 kb
Host smart-a637e67f-3dd7-490d-bf3e-e6409d95c200
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151664554 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.3151664554
Directory /workspace/3.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3381441097
Short name T103
Test name
Test status
Simulation time 545473560 ps
CPU time 25.87 seconds
Started Apr 16 02:36:59 PM PDT 24
Finished Apr 16 02:37:26 PM PDT 24
Peak memory 204764 kb
Host smart-dc3ac40d-dec6-4d18-a380-66abd311cd0c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381441097 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.3381441097
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.4274432990
Short name T23
Test name
Test status
Simulation time 149348218 ps
CPU time 1.23 seconds
Started Apr 16 12:49:47 PM PDT 24
Finished Apr 16 12:49:50 PM PDT 24
Peak memory 228704 kb
Host smart-ff296792-89f3-4a1f-bfa1-50114c5dfadd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274432990 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.4274432990
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.4250807473
Short name T10
Test name
Test status
Simulation time 494701890 ps
CPU time 1.48 seconds
Started Apr 16 12:50:03 PM PDT 24
Finished Apr 16 12:50:06 PM PDT 24
Peak memory 205376 kb
Host smart-67847396-4d49-4e70-ba22-8fa224b16c22
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4250807473 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_
tl_access.4250807473
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3932119758
Short name T92
Test name
Test status
Simulation time 447717553 ps
CPU time 4.32 seconds
Started Apr 16 02:37:36 PM PDT 24
Finished Apr 16 02:37:42 PM PDT 24
Peak memory 213028 kb
Host smart-5bad1b2b-c4ca-4fc4-a7e2-43ab63d1e968
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932119758 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.3932119758
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.3416910168
Short name T50
Test name
Test status
Simulation time 18682639 ps
CPU time 0.76 seconds
Started Apr 16 12:49:42 PM PDT 24
Finished Apr 16 12:49:44 PM PDT 24
Peak memory 213356 kb
Host smart-b465c463-638f-442b-843e-8352e6dd51eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416910168 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.3416910168
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.1982019983
Short name T55
Test name
Test status
Simulation time 287182644 ps
CPU time 1.29 seconds
Started Apr 16 12:49:45 PM PDT 24
Finished Apr 16 12:49:47 PM PDT 24
Peak memory 205100 kb
Host smart-c850f6a3-e1b5-46b2-907f-37b3a333f42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982019983 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.1982019983
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1750440375
Short name T85
Test name
Test status
Simulation time 848675876 ps
CPU time 4.05 seconds
Started Apr 16 02:36:58 PM PDT 24
Finished Apr 16 02:37:03 PM PDT 24
Peak memory 204848 kb
Host smart-5ee8f26b-f32f-4dd3-878e-9aaff8837ef4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750440375 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.1750440375
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.1747879360
Short name T53
Test name
Test status
Simulation time 146766276 ps
CPU time 0.8 seconds
Started Apr 16 12:49:41 PM PDT 24
Finished Apr 16 12:49:44 PM PDT 24
Peak memory 205084 kb
Host smart-47642d48-2775-4950-a29b-2b1682157a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747879360 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.1747879360
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3350223297
Short name T132
Test name
Test status
Simulation time 2248775785 ps
CPU time 19.2 seconds
Started Apr 16 02:37:27 PM PDT 24
Finished Apr 16 02:37:47 PM PDT 24
Peak memory 221356 kb
Host smart-dc2d2919-aa45-4c21-9906-150b512be5c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350223297 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.3
350223297
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.2657313151
Short name T142
Test name
Test status
Simulation time 1570666951 ps
CPU time 2.54 seconds
Started Apr 16 12:49:42 PM PDT 24
Finished Apr 16 12:49:46 PM PDT 24
Peak memory 205328 kb
Host smart-ce8fabad-bff0-42ef-809d-58b4107c0fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657313151 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.2657313151
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.186466906
Short name T57
Test name
Test status
Simulation time 79647716 ps
CPU time 0.76 seconds
Started Apr 16 12:49:40 PM PDT 24
Finished Apr 16 12:49:42 PM PDT 24
Peak memory 205120 kb
Host smart-5804f858-b8b8-4ad9-8c1e-fd2b1aa48277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186466906 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.186466906
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2658253519
Short name T130
Test name
Test status
Simulation time 3336769232 ps
CPU time 18.25 seconds
Started Apr 16 02:37:18 PM PDT 24
Finished Apr 16 02:37:37 PM PDT 24
Peak memory 213160 kb
Host smart-c30aada4-0da6-4867-aae0-4635751d1e28
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658253519 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.2658253519
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.164123610
Short name T134
Test name
Test status
Simulation time 413257800 ps
CPU time 8.44 seconds
Started Apr 16 02:36:58 PM PDT 24
Finished Apr 16 02:37:08 PM PDT 24
Peak memory 213124 kb
Host smart-dc24073c-d7e4-493c-acf3-bc14ce4f2aae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164123610 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.164123610
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.3016155324
Short name T45
Test name
Test status
Simulation time 49279863 ps
CPU time 0.68 seconds
Started Apr 16 12:50:30 PM PDT 24
Finished Apr 16 12:50:32 PM PDT 24
Peak memory 205128 kb
Host smart-7b031c5b-d7bf-4116-9c2b-739a7477ed0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016155324 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.3016155324
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.672970968
Short name T63
Test name
Test status
Simulation time 1770286347 ps
CPU time 3.25 seconds
Started Apr 16 02:36:56 PM PDT 24
Finished Apr 16 02:37:00 PM PDT 24
Peak memory 204668 kb
Host smart-48f34102-cd92-4bba-b61a-30fd840e1814
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672970968 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr
_bit_bash.672970968
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.1067402155
Short name T96
Test name
Test status
Simulation time 180415879 ps
CPU time 1.36 seconds
Started Apr 16 02:36:54 PM PDT 24
Finished Apr 16 02:36:56 PM PDT 24
Peak memory 204756 kb
Host smart-fde42cb9-2ba9-48ef-982c-cab9e4d622f0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067402155 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.1067402155
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.4010586007
Short name T48
Test name
Test status
Simulation time 616617126 ps
CPU time 1.48 seconds
Started Apr 16 12:49:43 PM PDT 24
Finished Apr 16 12:49:46 PM PDT 24
Peak memory 204996 kb
Host smart-ddd41f6c-8275-4191-82a1-ead723ff6cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010586007 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.4010586007
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3608595257
Short name T125
Test name
Test status
Simulation time 74180818 ps
CPU time 2.23 seconds
Started Apr 16 02:37:22 PM PDT 24
Finished Apr 16 02:37:25 PM PDT 24
Peak memory 213156 kb
Host smart-243b29aa-0f30-4854-8352-68c3feb4355f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608595257 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.3608595257
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.2490430587
Short name T136
Test name
Test status
Simulation time 606942372 ps
CPU time 10.19 seconds
Started Apr 16 02:37:27 PM PDT 24
Finished Apr 16 02:37:37 PM PDT 24
Peak memory 213004 kb
Host smart-12242132-34ac-40b4-a972-08131f561aa6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490430587 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.2
490430587
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3909216762
Short name T282
Test name
Test status
Simulation time 8623263975 ps
CPU time 76.04 seconds
Started Apr 16 02:36:54 PM PDT 24
Finished Apr 16 02:38:11 PM PDT 24
Peak memory 213204 kb
Host smart-69e56f05-36de-4673-8abc-b00f46d52625
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909216762 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.3909216762
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.758675337
Short name T112
Test name
Test status
Simulation time 14573301443 ps
CPU time 38.08 seconds
Started Apr 16 02:36:58 PM PDT 24
Finished Apr 16 02:37:37 PM PDT 24
Peak memory 204968 kb
Host smart-86b555a6-f7dc-4f32-a3e5-6c56c60c527f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758675337 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.758675337
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.1905209334
Short name T363
Test name
Test status
Simulation time 90276130 ps
CPU time 1.53 seconds
Started Apr 16 02:37:00 PM PDT 24
Finished Apr 16 02:37:02 PM PDT 24
Peak memory 213024 kb
Host smart-6e011863-62e0-4606-a2aa-b39c20251f73
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905209334 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.1905209334
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1449285849
Short name T76
Test name
Test status
Simulation time 217008895 ps
CPU time 2.13 seconds
Started Apr 16 02:36:58 PM PDT 24
Finished Apr 16 02:37:01 PM PDT 24
Peak memory 215444 kb
Host smart-7a4e0ec9-3a64-44dd-afdf-595e093dd3dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449285849 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.1449285849
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.1623519732
Short name T353
Test name
Test status
Simulation time 26318641 ps
CPU time 1.49 seconds
Started Apr 16 02:36:58 PM PDT 24
Finished Apr 16 02:37:00 PM PDT 24
Peak memory 218420 kb
Host smart-ea084379-6ebd-43fd-8b86-4092d09b37cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623519732 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.1623519732
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.263431039
Short name T354
Test name
Test status
Simulation time 8849329700 ps
CPU time 6.22 seconds
Started Apr 16 02:36:55 PM PDT 24
Finished Apr 16 02:37:03 PM PDT 24
Peak memory 204800 kb
Host smart-af7b8c1d-c0f1-4c81-a2fd-4a7748eaaac0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263431039 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr
_aliasing.263431039
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.646199396
Short name T341
Test name
Test status
Simulation time 7556030340 ps
CPU time 12.27 seconds
Started Apr 16 02:36:55 PM PDT 24
Finished Apr 16 02:37:08 PM PDT 24
Peak memory 204896 kb
Host smart-19c0f508-f09c-4d39-8378-b21332cb541a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646199396 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr
_bit_bash.646199396
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2586248444
Short name T310
Test name
Test status
Simulation time 1013122154 ps
CPU time 1.65 seconds
Started Apr 16 02:36:58 PM PDT 24
Finished Apr 16 02:37:01 PM PDT 24
Peak memory 204672 kb
Host smart-bac022cf-f0ec-4dd0-b846-3701ce7fc8da
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586248444 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.2
586248444
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3295471667
Short name T338
Test name
Test status
Simulation time 147878322 ps
CPU time 1 seconds
Started Apr 16 02:36:55 PM PDT 24
Finished Apr 16 02:36:57 PM PDT 24
Peak memory 204508 kb
Host smart-76898ebf-b99f-4ead-a003-de556051ea53
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295471667 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.3295471667
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3352462561
Short name T249
Test name
Test status
Simulation time 59594974 ps
CPU time 0.81 seconds
Started Apr 16 02:36:55 PM PDT 24
Finished Apr 16 02:36:57 PM PDT 24
Peak memory 204500 kb
Host smart-ba28a811-1d42-4e57-a66a-252d2a89231a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352462561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.3352462561
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1903668929
Short name T64
Test name
Test status
Simulation time 123001836 ps
CPU time 0.72 seconds
Started Apr 16 02:36:55 PM PDT 24
Finished Apr 16 02:36:57 PM PDT 24
Peak memory 204508 kb
Host smart-a24d4473-9d35-4ee2-ac1d-66653c7a7192
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903668929 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.1
903668929
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.2518696576
Short name T244
Test name
Test status
Simulation time 52020753 ps
CPU time 0.66 seconds
Started Apr 16 02:36:54 PM PDT 24
Finished Apr 16 02:36:56 PM PDT 24
Peak memory 204512 kb
Host smart-6428cdca-de8b-4ed8-9746-440916b643bf
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518696576 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.2518696576
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.2201472420
Short name T242
Test name
Test status
Simulation time 30711583 ps
CPU time 0.69 seconds
Started Apr 16 02:36:57 PM PDT 24
Finished Apr 16 02:36:58 PM PDT 24
Peak memory 204504 kb
Host smart-f3e37802-6a2e-40f3-a092-eb249ed61d3a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201472420 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.2201472420
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.2483095361
Short name T78
Test name
Test status
Simulation time 673322473 ps
CPU time 2.99 seconds
Started Apr 16 02:36:54 PM PDT 24
Finished Apr 16 02:36:58 PM PDT 24
Peak memory 221324 kb
Host smart-04748664-e2ad-4199-9e10-0257227f2d59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483095361 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.2483095361
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.2821456025
Short name T359
Test name
Test status
Simulation time 1656755431 ps
CPU time 16 seconds
Started Apr 16 02:36:53 PM PDT 24
Finished Apr 16 02:37:10 PM PDT 24
Peak memory 212984 kb
Host smart-8f75660b-1d03-474b-9015-4e74a383a25b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821456025 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.2821456025
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.3837293515
Short name T367
Test name
Test status
Simulation time 1423447542 ps
CPU time 54.75 seconds
Started Apr 16 02:36:59 PM PDT 24
Finished Apr 16 02:37:54 PM PDT 24
Peak memory 204800 kb
Host smart-435d5f9e-b02e-452e-b047-bcc2d9b48bc3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837293515 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.3837293515
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2400752541
Short name T360
Test name
Test status
Simulation time 69428133 ps
CPU time 1.5 seconds
Started Apr 16 02:37:01 PM PDT 24
Finished Apr 16 02:37:03 PM PDT 24
Peak memory 212996 kb
Host smart-a4478ef3-d1d7-4a6f-806e-02cdeb90e059
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400752541 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.2400752541
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.1224243494
Short name T296
Test name
Test status
Simulation time 554790264 ps
CPU time 3.87 seconds
Started Apr 16 02:37:00 PM PDT 24
Finished Apr 16 02:37:05 PM PDT 24
Peak memory 216616 kb
Host smart-3c42db5d-8ba1-4732-b08b-c5299acff99a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224243494 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.1224243494
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.4138443794
Short name T319
Test name
Test status
Simulation time 95440218 ps
CPU time 1.57 seconds
Started Apr 16 02:36:56 PM PDT 24
Finished Apr 16 02:36:59 PM PDT 24
Peak memory 212964 kb
Host smart-e479bbe8-b493-4102-8b02-303eb1d1566c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138443794 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.4138443794
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2791427542
Short name T351
Test name
Test status
Simulation time 5632141490 ps
CPU time 13.53 seconds
Started Apr 16 02:36:59 PM PDT 24
Finished Apr 16 02:37:13 PM PDT 24
Peak memory 204748 kb
Host smart-f2e8ff2a-8364-499e-8a36-457cf91284f0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791427542 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.2791427542
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2688237107
Short name T239
Test name
Test status
Simulation time 9991813134 ps
CPU time 29.8 seconds
Started Apr 16 02:37:00 PM PDT 24
Finished Apr 16 02:37:31 PM PDT 24
Peak memory 204736 kb
Host smart-6057dedf-ac9b-4f6d-bab1-cd192b9cbddf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688237107 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_bit_bash.2688237107
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1266715780
Short name T94
Test name
Test status
Simulation time 1139793632 ps
CPU time 1.87 seconds
Started Apr 16 02:36:57 PM PDT 24
Finished Apr 16 02:37:00 PM PDT 24
Peak memory 204764 kb
Host smart-13b839fb-44da-4e71-8f24-eae93d003e58
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266715780 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.1266715780
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1672926396
Short name T245
Test name
Test status
Simulation time 799491028 ps
CPU time 1.38 seconds
Started Apr 16 02:37:04 PM PDT 24
Finished Apr 16 02:37:05 PM PDT 24
Peak memory 204668 kb
Host smart-71ab42cd-95d6-4e4d-af9a-bf03b8ca01f7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672926396 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.1
672926396
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.142672529
Short name T315
Test name
Test status
Simulation time 125882291 ps
CPU time 0.79 seconds
Started Apr 16 02:36:59 PM PDT 24
Finished Apr 16 02:37:01 PM PDT 24
Peak memory 204388 kb
Host smart-325af38c-6d42-4e3b-965e-564924cecb65
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142672529 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_aliasing.142672529
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2557961226
Short name T275
Test name
Test status
Simulation time 1820410924 ps
CPU time 7.02 seconds
Started Apr 16 02:37:00 PM PDT 24
Finished Apr 16 02:37:08 PM PDT 24
Peak memory 204636 kb
Host smart-b5d90c16-003b-4832-8f51-dbf6ef7e5149
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557961226 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.2557961226
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.803220151
Short name T299
Test name
Test status
Simulation time 83384821 ps
CPU time 0.8 seconds
Started Apr 16 02:36:59 PM PDT 24
Finished Apr 16 02:37:01 PM PDT 24
Peak memory 204584 kb
Host smart-9e1967ef-00cd-4175-a518-02e353045fcf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803220151 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_hw_reset.803220151
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.1100162973
Short name T288
Test name
Test status
Simulation time 49101622 ps
CPU time 0.76 seconds
Started Apr 16 02:37:01 PM PDT 24
Finished Apr 16 02:37:02 PM PDT 24
Peak memory 204456 kb
Host smart-33b5de53-eace-4d2a-983c-044c1bbc610c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100162973 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.1
100162973
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1105369522
Short name T364
Test name
Test status
Simulation time 22410480 ps
CPU time 0.66 seconds
Started Apr 16 02:36:59 PM PDT 24
Finished Apr 16 02:37:00 PM PDT 24
Peak memory 204464 kb
Host smart-15c65b3b-8ceb-4eb6-a812-76f605685213
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105369522 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.1105369522
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.2636533701
Short name T293
Test name
Test status
Simulation time 35894694 ps
CPU time 0.67 seconds
Started Apr 16 02:36:57 PM PDT 24
Finished Apr 16 02:36:59 PM PDT 24
Peak memory 204432 kb
Host smart-b1b8acd5-faea-4465-9bad-e4150db876f3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636533701 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.2636533701
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2855207543
Short name T118
Test name
Test status
Simulation time 6599373529 ps
CPU time 8.07 seconds
Started Apr 16 02:36:59 PM PDT 24
Finished Apr 16 02:37:09 PM PDT 24
Peak memory 204916 kb
Host smart-be0d255f-4d6c-4ca6-892d-ac901fb7098b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855207543 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_
csr_outstanding.2855207543
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1855187255
Short name T284
Test name
Test status
Simulation time 36709803 ps
CPU time 2.21 seconds
Started Apr 16 02:36:58 PM PDT 24
Finished Apr 16 02:37:01 PM PDT 24
Peak memory 213160 kb
Host smart-accd25ec-cd86-43ce-b692-ef320aa682c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855187255 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.1855187255
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3684931167
Short name T304
Test name
Test status
Simulation time 1526891300 ps
CPU time 2.24 seconds
Started Apr 16 02:37:29 PM PDT 24
Finished Apr 16 02:37:33 PM PDT 24
Peak memory 213808 kb
Host smart-19b3e430-8b86-462a-a679-fc5f4dc462fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684931167 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.3684931167
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.4108768569
Short name T294
Test name
Test status
Simulation time 55098884 ps
CPU time 1.54 seconds
Started Apr 16 02:37:21 PM PDT 24
Finished Apr 16 02:37:24 PM PDT 24
Peak memory 212996 kb
Host smart-78534672-65a8-4d1d-a156-4c24389d7afc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108768569 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.4108768569
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3050638814
Short name T347
Test name
Test status
Simulation time 564554815 ps
CPU time 2.66 seconds
Started Apr 16 02:37:23 PM PDT 24
Finished Apr 16 02:37:26 PM PDT 24
Peak memory 204668 kb
Host smart-0dc54b8c-58ae-4beb-ac79-04aca0290c10
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050638814 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
3050638814
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.2547135365
Short name T65
Test name
Test status
Simulation time 59346872 ps
CPU time 0.82 seconds
Started Apr 16 02:37:24 PM PDT 24
Finished Apr 16 02:37:26 PM PDT 24
Peak memory 204468 kb
Host smart-71dc98fb-cc81-4595-9340-8efd24d1ed83
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547135365 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
2547135365
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.474989436
Short name T84
Test name
Test status
Simulation time 310526702 ps
CPU time 3.66 seconds
Started Apr 16 02:37:23 PM PDT 24
Finished Apr 16 02:37:28 PM PDT 24
Peak memory 204764 kb
Host smart-fd9770d9-9b45-4dba-8233-4e5b8189764e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474989436 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same_
csr_outstanding.474989436
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tap_fsm_rand_reset.1294869083
Short name T326
Test name
Test status
Simulation time 13460355214 ps
CPU time 12.62 seconds
Started Apr 16 02:37:29 PM PDT 24
Finished Apr 16 02:37:43 PM PDT 24
Peak memory 220268 kb
Host smart-097016cc-c691-4620-8d7b-b18fc8f6c8d4
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294869083 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rv_dm_tap_fsm_rand_reset.1294869083
Directory /workspace/10.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1597309091
Short name T91
Test name
Test status
Simulation time 211084579 ps
CPU time 8 seconds
Started Apr 16 02:37:29 PM PDT 24
Finished Apr 16 02:37:38 PM PDT 24
Peak memory 212812 kb
Host smart-b182404f-dfdf-4a8b-a40d-0dd418927d0b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597309091 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.1
597309091
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.2044148128
Short name T328
Test name
Test status
Simulation time 4767076140 ps
CPU time 5.26 seconds
Started Apr 16 02:37:29 PM PDT 24
Finished Apr 16 02:37:36 PM PDT 24
Peak memory 218508 kb
Host smart-9abd2675-9e6e-4ec6-85b1-451237d3efe7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044148128 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.2044148128
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.2113021924
Short name T101
Test name
Test status
Simulation time 53410327 ps
CPU time 1.56 seconds
Started Apr 16 02:37:28 PM PDT 24
Finished Apr 16 02:37:31 PM PDT 24
Peak memory 213068 kb
Host smart-e5a64a43-9059-4bbe-8d2c-9bed963d8a8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113021924 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.2113021924
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.4291419904
Short name T339
Test name
Test status
Simulation time 325237254 ps
CPU time 1.96 seconds
Started Apr 16 02:37:25 PM PDT 24
Finished Apr 16 02:37:28 PM PDT 24
Peak memory 204676 kb
Host smart-e2d30e9b-8dc9-488e-92fd-3ff14f82e8f7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291419904 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
4291419904
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.992864888
Short name T376
Test name
Test status
Simulation time 322609638 ps
CPU time 0.69 seconds
Started Apr 16 02:37:29 PM PDT 24
Finished Apr 16 02:37:31 PM PDT 24
Peak memory 204304 kb
Host smart-abbdb303-b4b7-4ba8-8de1-1901ab2a10b0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992864888 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.992864888
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.869457284
Short name T336
Test name
Test status
Simulation time 768441391 ps
CPU time 3.77 seconds
Started Apr 16 02:37:27 PM PDT 24
Finished Apr 16 02:37:32 PM PDT 24
Peak memory 204892 kb
Host smart-4f858982-b779-44e9-b99f-82376317390a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869457284 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same_
csr_outstanding.869457284
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.423347981
Short name T277
Test name
Test status
Simulation time 518274125 ps
CPU time 2.97 seconds
Started Apr 16 02:37:24 PM PDT 24
Finished Apr 16 02:37:28 PM PDT 24
Peak memory 213044 kb
Host smart-faec773b-b7df-4d8e-a80f-f9f96b47ebf0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423347981 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.423347981
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.4161846747
Short name T302
Test name
Test status
Simulation time 134433543 ps
CPU time 2.4 seconds
Started Apr 16 02:37:26 PM PDT 24
Finished Apr 16 02:37:29 PM PDT 24
Peak memory 212992 kb
Host smart-78be6320-29fc-4838-93f2-9dbad98907eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161846747 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.4161846747
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.982032337
Short name T100
Test name
Test status
Simulation time 218425354 ps
CPU time 1.61 seconds
Started Apr 16 02:37:27 PM PDT 24
Finished Apr 16 02:37:30 PM PDT 24
Peak memory 212832 kb
Host smart-4a46dcce-562d-4816-be9b-56b4b843df26
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982032337 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.982032337
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.2914944165
Short name T295
Test name
Test status
Simulation time 1201493501 ps
CPU time 1.93 seconds
Started Apr 16 02:37:27 PM PDT 24
Finished Apr 16 02:37:30 PM PDT 24
Peak memory 204684 kb
Host smart-e74794ef-ba19-4c76-ad4b-81d7e4c54ae2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914944165 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
2914944165
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.2828175553
Short name T344
Test name
Test status
Simulation time 69376770 ps
CPU time 0.71 seconds
Started Apr 16 02:37:29 PM PDT 24
Finished Apr 16 02:37:31 PM PDT 24
Peak memory 204540 kb
Host smart-30735f2d-d427-4a78-8254-98825755aad5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828175553 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
2828175553
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1600295541
Short name T108
Test name
Test status
Simulation time 257318246 ps
CPU time 3.72 seconds
Started Apr 16 02:37:30 PM PDT 24
Finished Apr 16 02:37:35 PM PDT 24
Peak memory 204784 kb
Host smart-587c6a3e-e254-4672-8c69-bd6c1e58adcd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600295541 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.1600295541
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tap_fsm_rand_reset.3992887798
Short name T333
Test name
Test status
Simulation time 6157757884 ps
CPU time 13.16 seconds
Started Apr 16 02:37:32 PM PDT 24
Finished Apr 16 02:37:46 PM PDT 24
Peak memory 219452 kb
Host smart-75bad993-4cbc-4baf-a290-2504cd34983c
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992887798 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rv_dm_tap_fsm_rand_reset.3992887798
Directory /workspace/12.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.2505320176
Short name T327
Test name
Test status
Simulation time 90485176 ps
CPU time 2.66 seconds
Started Apr 16 02:37:28 PM PDT 24
Finished Apr 16 02:37:32 PM PDT 24
Peak memory 212992 kb
Host smart-7cbc2332-bfe7-4489-99dd-252f3ddce8e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505320176 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.2505320176
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.37799147
Short name T137
Test name
Test status
Simulation time 1225306133 ps
CPU time 17.22 seconds
Started Apr 16 02:37:28 PM PDT 24
Finished Apr 16 02:37:47 PM PDT 24
Peak memory 212988 kb
Host smart-6f381944-1ec1-44f9-981e-93050abba657
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37799147 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.37799147
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.201845063
Short name T323
Test name
Test status
Simulation time 1095842031 ps
CPU time 4.27 seconds
Started Apr 16 02:37:27 PM PDT 24
Finished Apr 16 02:37:32 PM PDT 24
Peak memory 218276 kb
Host smart-db2f3dc0-8b89-410b-b8ca-c943c96334f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201845063 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.201845063
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.2135564167
Short name T87
Test name
Test status
Simulation time 152673437 ps
CPU time 2.41 seconds
Started Apr 16 02:37:25 PM PDT 24
Finished Apr 16 02:37:28 PM PDT 24
Peak memory 218252 kb
Host smart-91a387be-6ca5-4938-ab52-1a34664ddf92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135564167 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.2135564167
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.3794709608
Short name T298
Test name
Test status
Simulation time 704394763 ps
CPU time 2.97 seconds
Started Apr 16 02:37:27 PM PDT 24
Finished Apr 16 02:37:31 PM PDT 24
Peak memory 204560 kb
Host smart-9e2e3625-2166-482d-861f-b4a115bcec0b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794709608 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
3794709608
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2233616773
Short name T283
Test name
Test status
Simulation time 150093241 ps
CPU time 0.89 seconds
Started Apr 16 02:37:27 PM PDT 24
Finished Apr 16 02:37:29 PM PDT 24
Peak memory 204488 kb
Host smart-8def80db-dc21-482d-9e3c-4b0452488e43
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233616773 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
2233616773
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2926168504
Short name T90
Test name
Test status
Simulation time 276969311 ps
CPU time 4.14 seconds
Started Apr 16 02:37:28 PM PDT 24
Finished Apr 16 02:37:33 PM PDT 24
Peak memory 204848 kb
Host smart-618e32c6-b83e-4460-a298-23f22b3a5db3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926168504 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.2926168504
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.80289992
Short name T375
Test name
Test status
Simulation time 520397975 ps
CPU time 2.63 seconds
Started Apr 16 02:37:28 PM PDT 24
Finished Apr 16 02:37:32 PM PDT 24
Peak memory 213036 kb
Host smart-99586353-e9f8-483c-b091-58f3230d1aaa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80289992 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.80289992
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.1154821300
Short name T346
Test name
Test status
Simulation time 133750150 ps
CPU time 2.29 seconds
Started Apr 16 02:37:34 PM PDT 24
Finished Apr 16 02:37:38 PM PDT 24
Peak memory 217112 kb
Host smart-b657c6f8-481c-4dc9-b621-3a1cc4670993
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154821300 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.1154821300
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.2644816660
Short name T105
Test name
Test status
Simulation time 320479359 ps
CPU time 2.22 seconds
Started Apr 16 02:37:32 PM PDT 24
Finished Apr 16 02:37:36 PM PDT 24
Peak memory 213060 kb
Host smart-05976e6c-e21a-4633-abf3-06fb593bb55f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644816660 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.2644816660
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.3602880313
Short name T238
Test name
Test status
Simulation time 559611881 ps
CPU time 1.84 seconds
Started Apr 16 02:37:27 PM PDT 24
Finished Apr 16 02:37:30 PM PDT 24
Peak memory 204720 kb
Host smart-69b4eee7-0d44-4e01-9500-24aead730957
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602880313 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
3602880313
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.918067302
Short name T261
Test name
Test status
Simulation time 155899959 ps
CPU time 1.1 seconds
Started Apr 16 02:37:25 PM PDT 24
Finished Apr 16 02:37:27 PM PDT 24
Peak memory 204516 kb
Host smart-aa25af85-60fd-4bc9-ad65-f0f9a5e5ee9c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918067302 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.918067302
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3266177117
Short name T321
Test name
Test status
Simulation time 291247132 ps
CPU time 6.19 seconds
Started Apr 16 02:37:32 PM PDT 24
Finished Apr 16 02:37:39 PM PDT 24
Peak memory 204880 kb
Host smart-0777a9f2-7d7e-4c22-86b9-d6df7d69a909
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266177117 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.3266177117
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.1012180786
Short name T253
Test name
Test status
Simulation time 114551145 ps
CPU time 2.77 seconds
Started Apr 16 02:37:32 PM PDT 24
Finished Apr 16 02:37:36 PM PDT 24
Peak memory 212944 kb
Host smart-0d1b30ce-87ab-447a-8d8f-849d4e50a7ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012180786 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.1012180786
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.2357535386
Short name T317
Test name
Test status
Simulation time 1141650507 ps
CPU time 20.56 seconds
Started Apr 16 02:37:40 PM PDT 24
Finished Apr 16 02:38:02 PM PDT 24
Peak memory 213072 kb
Host smart-4a796f21-8dc2-440d-9c86-63eef0169c15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357535386 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.2
357535386
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.2050740374
Short name T121
Test name
Test status
Simulation time 2056809024 ps
CPU time 7.17 seconds
Started Apr 16 02:37:34 PM PDT 24
Finished Apr 16 02:37:42 PM PDT 24
Peak memory 218768 kb
Host smart-8cc3adfc-8967-4ac9-9487-b1ba0429c93c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050740374 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.2050740374
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.1732120069
Short name T114
Test name
Test status
Simulation time 72073500 ps
CPU time 2.07 seconds
Started Apr 16 02:37:39 PM PDT 24
Finished Apr 16 02:37:42 PM PDT 24
Peak memory 212976 kb
Host smart-09c23082-94ab-4d51-b28d-0b648806e661
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732120069 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.1732120069
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.900200450
Short name T260
Test name
Test status
Simulation time 210189396 ps
CPU time 1.16 seconds
Started Apr 16 02:37:32 PM PDT 24
Finished Apr 16 02:37:34 PM PDT 24
Peak memory 204672 kb
Host smart-e06f10fb-41b6-44fb-9f62-1b28b8a97a02
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900200450 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.900200450
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.2253150933
Short name T324
Test name
Test status
Simulation time 75607080 ps
CPU time 0.83 seconds
Started Apr 16 02:37:34 PM PDT 24
Finished Apr 16 02:37:36 PM PDT 24
Peak memory 204492 kb
Host smart-2f5ef7e2-ba45-46ac-acb3-2fc91b9e8a95
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253150933 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
2253150933
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.3428103385
Short name T106
Test name
Test status
Simulation time 311792803 ps
CPU time 3.61 seconds
Started Apr 16 02:37:34 PM PDT 24
Finished Apr 16 02:37:39 PM PDT 24
Peak memory 204904 kb
Host smart-a7a94339-b6e1-448f-b4ff-d8a14d2f2561
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428103385 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.3428103385
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tap_fsm_rand_reset.3061353771
Short name T357
Test name
Test status
Simulation time 13104215949 ps
CPU time 12.08 seconds
Started Apr 16 02:37:31 PM PDT 24
Finished Apr 16 02:37:44 PM PDT 24
Peak memory 215608 kb
Host smart-271c0fbd-8c8e-4c28-b027-d2fc73ac9067
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061353771 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rv_dm_tap_fsm_rand_reset.3061353771
Directory /workspace/15.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.1368770303
Short name T318
Test name
Test status
Simulation time 152118441 ps
CPU time 4.34 seconds
Started Apr 16 02:38:14 PM PDT 24
Finished Apr 16 02:38:19 PM PDT 24
Peak memory 213060 kb
Host smart-2e824bc9-7fe7-4698-9fcd-4ded0ad0cdf6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368770303 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.1368770303
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3501639474
Short name T66
Test name
Test status
Simulation time 2284152810 ps
CPU time 20.53 seconds
Started Apr 16 02:37:40 PM PDT 24
Finished Apr 16 02:38:01 PM PDT 24
Peak memory 221300 kb
Host smart-a051469d-1b9d-4da8-a53f-02413acd613d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501639474 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.3
501639474
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2043481049
Short name T122
Test name
Test status
Simulation time 71558726 ps
CPU time 2.31 seconds
Started Apr 16 02:37:32 PM PDT 24
Finished Apr 16 02:37:36 PM PDT 24
Peak memory 216680 kb
Host smart-e257a818-ceff-4918-a1df-ccd82a586c49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043481049 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.2043481049
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.1642604173
Short name T368
Test name
Test status
Simulation time 43651302 ps
CPU time 1.39 seconds
Started Apr 16 02:37:39 PM PDT 24
Finished Apr 16 02:37:42 PM PDT 24
Peak memory 212952 kb
Host smart-ac29adbc-190b-49d7-830b-73f206d71195
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642604173 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.1642604173
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.3922720338
Short name T257
Test name
Test status
Simulation time 142903314 ps
CPU time 1 seconds
Started Apr 16 02:37:34 PM PDT 24
Finished Apr 16 02:37:36 PM PDT 24
Peak memory 204688 kb
Host smart-52f7577f-c42f-4f9e-8394-4f4d1016903e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922720338 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
3922720338
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2531017785
Short name T274
Test name
Test status
Simulation time 237555278 ps
CPU time 0.68 seconds
Started Apr 16 02:37:40 PM PDT 24
Finished Apr 16 02:37:42 PM PDT 24
Peak memory 204500 kb
Host smart-c0748efa-f9ff-462e-b4ae-d6a4e6bc126a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531017785 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
2531017785
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3104585644
Short name T312
Test name
Test status
Simulation time 1194419300 ps
CPU time 3.45 seconds
Started Apr 16 02:37:34 PM PDT 24
Finished Apr 16 02:37:39 PM PDT 24
Peak memory 204788 kb
Host smart-30d36d7e-8fbf-4bc5-a72a-ea509aa439c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104585644 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.3104585644
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3929232647
Short name T372
Test name
Test status
Simulation time 73872453 ps
CPU time 2.15 seconds
Started Apr 16 02:37:33 PM PDT 24
Finished Apr 16 02:37:36 PM PDT 24
Peak memory 213068 kb
Host smart-2218457a-6aeb-497b-9785-0bd060cd22a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929232647 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.3929232647
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.3521884646
Short name T74
Test name
Test status
Simulation time 508668815 ps
CPU time 9.65 seconds
Started Apr 16 02:37:31 PM PDT 24
Finished Apr 16 02:37:42 PM PDT 24
Peak memory 213020 kb
Host smart-1d2e4f5b-d1a9-4855-9336-4170a81fe0d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521884646 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.3
521884646
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.4237809162
Short name T73
Test name
Test status
Simulation time 587486148 ps
CPU time 4.04 seconds
Started Apr 16 02:37:30 PM PDT 24
Finished Apr 16 02:37:35 PM PDT 24
Peak memory 218740 kb
Host smart-0bba54df-99e2-4fed-84b6-6b87f5a17510
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237809162 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.4237809162
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.2883057028
Short name T116
Test name
Test status
Simulation time 57573496 ps
CPU time 1.52 seconds
Started Apr 16 02:37:40 PM PDT 24
Finished Apr 16 02:37:43 PM PDT 24
Peak memory 212996 kb
Host smart-459babca-b513-4057-8388-e1a942daaece
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883057028 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.2883057028
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.1307507240
Short name T246
Test name
Test status
Simulation time 161874498 ps
CPU time 1.3 seconds
Started Apr 16 02:37:34 PM PDT 24
Finished Apr 16 02:37:36 PM PDT 24
Peak memory 204676 kb
Host smart-ec6ee185-d185-4084-b2df-fab9825ea047
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307507240 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
1307507240
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.4100776537
Short name T265
Test name
Test status
Simulation time 64558852 ps
CPU time 0.71 seconds
Started Apr 16 02:37:31 PM PDT 24
Finished Apr 16 02:37:33 PM PDT 24
Peak memory 204444 kb
Host smart-ca8cba91-a950-497a-88f6-f66728245401
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100776537 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
4100776537
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3361208333
Short name T320
Test name
Test status
Simulation time 803555570 ps
CPU time 7.54 seconds
Started Apr 16 02:37:31 PM PDT 24
Finished Apr 16 02:37:39 PM PDT 24
Peak memory 204868 kb
Host smart-e7933140-7881-4e02-a97a-0eb4be388950
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361208333 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.3361208333
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.648925983
Short name T313
Test name
Test status
Simulation time 71688570 ps
CPU time 5.07 seconds
Started Apr 16 02:37:33 PM PDT 24
Finished Apr 16 02:37:39 PM PDT 24
Peak memory 213052 kb
Host smart-1f3bf60e-5b7d-4fe6-a683-76c5fb5026d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648925983 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.648925983
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.430001356
Short name T128
Test name
Test status
Simulation time 651211445 ps
CPU time 7.86 seconds
Started Apr 16 02:37:34 PM PDT 24
Finished Apr 16 02:37:43 PM PDT 24
Peak memory 221140 kb
Host smart-8582b41c-bb73-4342-bf4f-b27ac57de2e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430001356 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.430001356
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2592910595
Short name T36
Test name
Test status
Simulation time 840014363 ps
CPU time 3.61 seconds
Started Apr 16 02:37:37 PM PDT 24
Finished Apr 16 02:37:42 PM PDT 24
Peak memory 218144 kb
Host smart-db0d53f9-7f02-479a-84f2-7ebb44187e1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592910595 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.2592910595
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.1847826737
Short name T86
Test name
Test status
Simulation time 95300333 ps
CPU time 2.32 seconds
Started Apr 16 02:37:38 PM PDT 24
Finished Apr 16 02:37:41 PM PDT 24
Peak memory 218240 kb
Host smart-bd689560-ee36-4574-99e7-26269955441d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847826737 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.1847826737
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2078188574
Short name T243
Test name
Test status
Simulation time 606654850 ps
CPU time 1.79 seconds
Started Apr 16 02:37:34 PM PDT 24
Finished Apr 16 02:37:38 PM PDT 24
Peak memory 203924 kb
Host smart-24239a1c-d4da-40fd-a083-9d3344d5dc75
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078188574 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
2078188574
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2541195056
Short name T311
Test name
Test status
Simulation time 199307104 ps
CPU time 0.72 seconds
Started Apr 16 02:37:33 PM PDT 24
Finished Apr 16 02:37:35 PM PDT 24
Peak memory 204516 kb
Host smart-450adfc2-e2af-441f-99db-b34c3a5957ad
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541195056 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
2541195056
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3135777024
Short name T88
Test name
Test status
Simulation time 739160088 ps
CPU time 4.16 seconds
Started Apr 16 02:37:34 PM PDT 24
Finished Apr 16 02:37:39 PM PDT 24
Peak memory 204808 kb
Host smart-bfddc100-8c65-475e-98e5-c1c00a4698ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135777024 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.3135777024
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tap_fsm_rand_reset.4182764040
Short name T139
Test name
Test status
Simulation time 13227753979 ps
CPU time 11.99 seconds
Started Apr 16 02:37:32 PM PDT 24
Finished Apr 16 02:37:45 PM PDT 24
Peak memory 215124 kb
Host smart-e77648b9-557a-4509-987a-2feaef125538
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182764040 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rv_dm_tap_fsm_rand_reset.4182764040
Directory /workspace/18.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2629661883
Short name T256
Test name
Test status
Simulation time 688956725 ps
CPU time 3.39 seconds
Started Apr 16 02:37:34 PM PDT 24
Finished Apr 16 02:37:40 PM PDT 24
Peak memory 212312 kb
Host smart-5c7f0553-5c78-4eac-834c-2597099c56ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629661883 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.2629661883
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.2107618939
Short name T133
Test name
Test status
Simulation time 3089439601 ps
CPU time 18.19 seconds
Started Apr 16 02:37:35 PM PDT 24
Finished Apr 16 02:37:55 PM PDT 24
Peak memory 213024 kb
Host smart-d92a6e7e-69a5-4dcb-8e32-34516466d6d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107618939 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.2
107618939
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2061595522
Short name T331
Test name
Test status
Simulation time 2764120699 ps
CPU time 7.72 seconds
Started Apr 16 02:37:37 PM PDT 24
Finished Apr 16 02:37:46 PM PDT 24
Peak memory 219276 kb
Host smart-0db4dbb2-3145-4b12-af52-42cba639f08c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061595522 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.2061595522
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.2282669075
Short name T110
Test name
Test status
Simulation time 270441763 ps
CPU time 2.35 seconds
Started Apr 16 02:37:41 PM PDT 24
Finished Apr 16 02:37:44 PM PDT 24
Peak memory 218164 kb
Host smart-ca2935b9-086d-482f-a17a-a0d20b95f2c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282669075 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.2282669075
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.261486299
Short name T350
Test name
Test status
Simulation time 537171947 ps
CPU time 1.61 seconds
Started Apr 16 02:37:39 PM PDT 24
Finished Apr 16 02:37:42 PM PDT 24
Peak memory 204668 kb
Host smart-2d4b3605-8420-484c-8545-4acbef807949
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261486299 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.261486299
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.1340852362
Short name T254
Test name
Test status
Simulation time 25059846 ps
CPU time 0.77 seconds
Started Apr 16 02:37:36 PM PDT 24
Finished Apr 16 02:37:38 PM PDT 24
Peak memory 204504 kb
Host smart-b8ac7240-a047-4629-ab96-ac9746d0ee64
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340852362 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
1340852362
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.2197708022
Short name T370
Test name
Test status
Simulation time 1323938043 ps
CPU time 4.27 seconds
Started Apr 16 02:37:36 PM PDT 24
Finished Apr 16 02:37:41 PM PDT 24
Peak memory 204828 kb
Host smart-c172e4b4-42e2-4586-aa59-fb9549033e97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197708022 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.2197708022
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tap_fsm_rand_reset.891624422
Short name T268
Test name
Test status
Simulation time 15266011434 ps
CPU time 28.33 seconds
Started Apr 16 02:37:35 PM PDT 24
Finished Apr 16 02:38:05 PM PDT 24
Peak memory 221324 kb
Host smart-914107cc-4c77-4e1f-bb23-8654842edda1
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891624422 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.rv_dm_tap_fsm_rand_reset.891624422
Directory /workspace/19.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2373346767
Short name T345
Test name
Test status
Simulation time 386810831 ps
CPU time 8.45 seconds
Started Apr 16 02:37:38 PM PDT 24
Finished Apr 16 02:37:47 PM PDT 24
Peak memory 221252 kb
Host smart-6f7bc4a9-04a0-4723-b229-b1d8b0fdda5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373346767 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.2
373346767
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2574679171
Short name T109
Test name
Test status
Simulation time 7729298765 ps
CPU time 76.24 seconds
Started Apr 16 02:37:01 PM PDT 24
Finished Apr 16 02:38:18 PM PDT 24
Peak memory 217992 kb
Host smart-0f876df0-44f3-41b9-a76e-8d5f3b778c55
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574679171 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.2574679171
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2006670499
Short name T102
Test name
Test status
Simulation time 14624837879 ps
CPU time 74.09 seconds
Started Apr 16 02:37:05 PM PDT 24
Finished Apr 16 02:38:20 PM PDT 24
Peak memory 204960 kb
Host smart-003c6709-3d57-483c-8f99-5ec5ed0db321
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006670499 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.2006670499
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.647239188
Short name T276
Test name
Test status
Simulation time 115915918 ps
CPU time 2.38 seconds
Started Apr 16 02:37:09 PM PDT 24
Finished Apr 16 02:37:13 PM PDT 24
Peak memory 213092 kb
Host smart-cd7edba4-9c8d-4045-8440-3b23ef964960
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647239188 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.647239188
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3652942768
Short name T290
Test name
Test status
Simulation time 72569098 ps
CPU time 1.92 seconds
Started Apr 16 02:37:07 PM PDT 24
Finished Apr 16 02:37:10 PM PDT 24
Peak memory 214748 kb
Host smart-70e86e38-2c19-4bfc-8b98-44c48bc060f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652942768 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.3652942768
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1357298758
Short name T369
Test name
Test status
Simulation time 198741327 ps
CPU time 1.54 seconds
Started Apr 16 02:37:08 PM PDT 24
Finished Apr 16 02:37:11 PM PDT 24
Peak memory 212992 kb
Host smart-78cd9c1a-5dc1-47db-baff-657e6dedc33f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357298758 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.1357298758
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.1541769115
Short name T316
Test name
Test status
Simulation time 10506555393 ps
CPU time 29.73 seconds
Started Apr 16 02:37:11 PM PDT 24
Finished Apr 16 02:37:42 PM PDT 24
Peak memory 204832 kb
Host smart-75e451f0-231a-4326-8dbb-9a3b47ca8dc5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541769115 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.1541769115
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1151934591
Short name T248
Test name
Test status
Simulation time 26299350710 ps
CPU time 25.05 seconds
Started Apr 16 02:37:04 PM PDT 24
Finished Apr 16 02:37:29 PM PDT 24
Peak memory 204732 kb
Host smart-bd5df8b4-af36-46b4-b028-fcdbaf586ecf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151934591 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_bit_bash.1151934591
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2071936728
Short name T98
Test name
Test status
Simulation time 1453405139 ps
CPU time 1.97 seconds
Started Apr 16 02:37:04 PM PDT 24
Finished Apr 16 02:37:07 PM PDT 24
Peak memory 204812 kb
Host smart-c300549e-3fa6-4569-a604-9a5af76944a7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071936728 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.2071936728
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.2352438225
Short name T287
Test name
Test status
Simulation time 333663432 ps
CPU time 1.04 seconds
Started Apr 16 02:37:08 PM PDT 24
Finished Apr 16 02:37:10 PM PDT 24
Peak memory 204668 kb
Host smart-8e259bd4-bf6b-4fa2-afff-e6418673655b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352438225 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.2
352438225
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3027955903
Short name T272
Test name
Test status
Simulation time 142832055 ps
CPU time 0.76 seconds
Started Apr 16 02:37:04 PM PDT 24
Finished Apr 16 02:37:06 PM PDT 24
Peak memory 204480 kb
Host smart-c18e9947-0403-456a-ace4-57308bd4063a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027955903 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_aliasing.3027955903
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.3295518734
Short name T292
Test name
Test status
Simulation time 1298867201 ps
CPU time 4.87 seconds
Started Apr 16 02:37:09 PM PDT 24
Finished Apr 16 02:37:15 PM PDT 24
Peak memory 204700 kb
Host smart-c691425e-fcc3-4c8d-ba99-6b685e4a1c67
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295518734 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.3295518734
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.4248007036
Short name T303
Test name
Test status
Simulation time 117794582 ps
CPU time 0.75 seconds
Started Apr 16 02:37:04 PM PDT 24
Finished Apr 16 02:37:06 PM PDT 24
Peak memory 204444 kb
Host smart-5a2b4292-36a5-4731-aaac-eb6a9caf5335
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248007036 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.4248007036
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.289091012
Short name T334
Test name
Test status
Simulation time 76709602 ps
CPU time 0.7 seconds
Started Apr 16 02:37:03 PM PDT 24
Finished Apr 16 02:37:05 PM PDT 24
Peak memory 204512 kb
Host smart-6dff1b70-89da-4acc-b46f-373b04f3f7f8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289091012 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.289091012
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1658536299
Short name T329
Test name
Test status
Simulation time 43035547 ps
CPU time 0.66 seconds
Started Apr 16 02:37:09 PM PDT 24
Finished Apr 16 02:37:10 PM PDT 24
Peak memory 204436 kb
Host smart-4995e5dd-9a57-4ae4-921d-e91f97f31fde
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658536299 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.1658536299
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.1023865361
Short name T289
Test name
Test status
Simulation time 23722176 ps
CPU time 0.68 seconds
Started Apr 16 02:37:02 PM PDT 24
Finished Apr 16 02:37:03 PM PDT 24
Peak memory 204484 kb
Host smart-2e353bcc-bbef-4fe2-ae9d-cd215c198efe
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023865361 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.1023865361
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.1984016548
Short name T362
Test name
Test status
Simulation time 299375627 ps
CPU time 4.34 seconds
Started Apr 16 02:37:11 PM PDT 24
Finished Apr 16 02:37:17 PM PDT 24
Peak memory 204844 kb
Host smart-e99ada9f-1f89-487e-ab37-bbfccd4cccfe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984016548 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.1984016548
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.2122298323
Short name T258
Test name
Test status
Simulation time 442137247 ps
CPU time 4.34 seconds
Started Apr 16 02:37:10 PM PDT 24
Finished Apr 16 02:37:15 PM PDT 24
Peak memory 213128 kb
Host smart-be461071-8ba1-460c-ba91-fd797ec21ce9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122298323 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.2122298323
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.647966768
Short name T127
Test name
Test status
Simulation time 497853788 ps
CPU time 15.93 seconds
Started Apr 16 02:37:07 PM PDT 24
Finished Apr 16 02:37:24 PM PDT 24
Peak memory 221164 kb
Host smart-bfa230b4-9021-4e20-95af-01d7806fb771
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647966768 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.647966768
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/24.rv_dm_tap_fsm_rand_reset.211074755
Short name T273
Test name
Test status
Simulation time 20112597615 ps
CPU time 11.87 seconds
Started Apr 16 02:37:35 PM PDT 24
Finished Apr 16 02:37:48 PM PDT 24
Peak memory 215760 kb
Host smart-a75bf9e8-280e-44a1-b768-724fe7c10e95
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211074755 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 24.rv_dm_tap_fsm_rand_reset.211074755
Directory /workspace/24.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/28.rv_dm_tap_fsm_rand_reset.2079644625
Short name T377
Test name
Test status
Simulation time 4463316344 ps
CPU time 16.04 seconds
Started Apr 16 02:37:37 PM PDT 24
Finished Apr 16 02:37:54 PM PDT 24
Peak memory 213132 kb
Host smart-8da77769-6679-4f5b-ac50-6ae6f09e39c3
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079644625 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 28.rv_dm_tap_fsm_rand_reset.2079644625
Directory /workspace/28.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/29.rv_dm_tap_fsm_rand_reset.1247768580
Short name T305
Test name
Test status
Simulation time 13578799715 ps
CPU time 10.61 seconds
Started Apr 16 02:37:36 PM PDT 24
Finished Apr 16 02:37:48 PM PDT 24
Peak memory 219528 kb
Host smart-85d5c6f1-93f2-4447-88ab-ed7a73996c12
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247768580 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 29.rv_dm_tap_fsm_rand_reset.1247768580
Directory /workspace/29.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1979564732
Short name T307
Test name
Test status
Simulation time 22040455582 ps
CPU time 37.75 seconds
Started Apr 16 02:37:11 PM PDT 24
Finished Apr 16 02:37:49 PM PDT 24
Peak memory 213236 kb
Host smart-a08e00d7-cbec-4b22-8f76-501a2baaa889
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979564732 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.1979564732
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.3034693197
Short name T89
Test name
Test status
Simulation time 1413965432 ps
CPU time 29.18 seconds
Started Apr 16 02:37:09 PM PDT 24
Finished Apr 16 02:37:39 PM PDT 24
Peak memory 204800 kb
Host smart-5422940b-ad42-455b-bb2b-29037047bf4c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034693197 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.3034693197
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.299675661
Short name T99
Test name
Test status
Simulation time 374982963 ps
CPU time 1.56 seconds
Started Apr 16 02:37:09 PM PDT 24
Finished Apr 16 02:37:12 PM PDT 24
Peak memory 212880 kb
Host smart-e501dd4b-bfaf-4083-808f-62377c9fccda
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299675661 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.299675661
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.2615539637
Short name T314
Test name
Test status
Simulation time 2650165151 ps
CPU time 4.66 seconds
Started Apr 16 02:37:10 PM PDT 24
Finished Apr 16 02:37:16 PM PDT 24
Peak memory 219268 kb
Host smart-3a6cb11a-444c-4fc1-97d4-985dddb633bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615539637 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.2615539637
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.3143782115
Short name T309
Test name
Test status
Simulation time 731873080 ps
CPU time 2.29 seconds
Started Apr 16 02:37:09 PM PDT 24
Finished Apr 16 02:37:13 PM PDT 24
Peak memory 218420 kb
Host smart-b5eddf5d-d37b-42c7-8223-e66265cc39ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143782115 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.3143782115
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1312463282
Short name T308
Test name
Test status
Simulation time 11621849509 ps
CPU time 8.78 seconds
Started Apr 16 02:37:10 PM PDT 24
Finished Apr 16 02:37:20 PM PDT 24
Peak memory 204860 kb
Host smart-77bac76b-3bc8-479d-acac-1477730dbf0a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312463282 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.1312463282
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.173167368
Short name T355
Test name
Test status
Simulation time 37137929026 ps
CPU time 62.56 seconds
Started Apr 16 02:37:12 PM PDT 24
Finished Apr 16 02:38:16 PM PDT 24
Peak memory 204816 kb
Host smart-de042c78-9f54-48f8-9389-eb243eff2cc7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173167368 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr
_bit_bash.173167368
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.1148141147
Short name T95
Test name
Test status
Simulation time 194831074 ps
CPU time 1.5 seconds
Started Apr 16 02:37:09 PM PDT 24
Finished Apr 16 02:37:12 PM PDT 24
Peak memory 204812 kb
Host smart-5439435c-9042-4f70-90a2-d7f40bf76d86
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148141147 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.1148141147
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.3671667226
Short name T301
Test name
Test status
Simulation time 610899813 ps
CPU time 2.05 seconds
Started Apr 16 02:37:11 PM PDT 24
Finished Apr 16 02:37:14 PM PDT 24
Peak memory 204684 kb
Host smart-ce4a62a4-e236-44cf-8133-93d4ba46c183
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671667226 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.3
671667226
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.4086869239
Short name T300
Test name
Test status
Simulation time 199783804 ps
CPU time 1.29 seconds
Started Apr 16 02:37:06 PM PDT 24
Finished Apr 16 02:37:08 PM PDT 24
Peak memory 204436 kb
Host smart-9b6b5974-9ebb-4910-9e10-331bd424ae13
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086869239 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.4086869239
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.1040778931
Short name T291
Test name
Test status
Simulation time 439806852 ps
CPU time 1.96 seconds
Started Apr 16 02:37:13 PM PDT 24
Finished Apr 16 02:37:16 PM PDT 24
Peak memory 204708 kb
Host smart-883ec4ce-099a-4664-a91e-f76d39fba760
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040778931 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.1040778931
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3892861094
Short name T285
Test name
Test status
Simulation time 192216181 ps
CPU time 0.79 seconds
Started Apr 16 02:37:03 PM PDT 24
Finished Apr 16 02:37:04 PM PDT 24
Peak memory 204468 kb
Host smart-a672fb50-41b5-4e42-9cf9-445723c7af4d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892861094 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.3892861094
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.388261850
Short name T269
Test name
Test status
Simulation time 80201195 ps
CPU time 0.89 seconds
Started Apr 16 02:37:10 PM PDT 24
Finished Apr 16 02:37:11 PM PDT 24
Peak memory 204484 kb
Host smart-ecbaaaac-ece1-4e1d-828a-b34950df3ae3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388261850 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.388261850
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.2485445851
Short name T240
Test name
Test status
Simulation time 21615453 ps
CPU time 0.74 seconds
Started Apr 16 02:37:12 PM PDT 24
Finished Apr 16 02:37:14 PM PDT 24
Peak memory 204496 kb
Host smart-1663c346-f660-4e1c-9bbb-9df9ea3f291c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485445851 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.2485445851
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1961430669
Short name T322
Test name
Test status
Simulation time 44659176 ps
CPU time 0.68 seconds
Started Apr 16 02:37:11 PM PDT 24
Finished Apr 16 02:37:13 PM PDT 24
Peak memory 204512 kb
Host smart-2b08a8d6-ceac-4882-bbfa-a4d109463eb1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961430669 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.1961430669
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.1539290482
Short name T83
Test name
Test status
Simulation time 5442237597 ps
CPU time 8.37 seconds
Started Apr 16 02:37:07 PM PDT 24
Finished Apr 16 02:37:16 PM PDT 24
Peak memory 205020 kb
Host smart-049275f7-862a-4388-9fa7-9f48e30cc88a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539290482 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_
csr_outstanding.1539290482
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.15174424
Short name T371
Test name
Test status
Simulation time 421371014 ps
CPU time 4.16 seconds
Started Apr 16 02:37:10 PM PDT 24
Finished Apr 16 02:37:15 PM PDT 24
Peak memory 213156 kb
Host smart-aacdeea9-354f-4fae-b10d-4621fe71a6b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15174424 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.15174424
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3825952545
Short name T131
Test name
Test status
Simulation time 1432918187 ps
CPU time 19.07 seconds
Started Apr 16 02:37:13 PM PDT 24
Finished Apr 16 02:37:33 PM PDT 24
Peak memory 221208 kb
Host smart-0b6d735a-f451-44e5-b209-1246a29d2f84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825952545 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.3825952545
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/38.rv_dm_tap_fsm_rand_reset.201697382
Short name T259
Test name
Test status
Simulation time 12743685415 ps
CPU time 11.29 seconds
Started Apr 16 02:37:38 PM PDT 24
Finished Apr 16 02:37:50 PM PDT 24
Peak memory 214412 kb
Host smart-948de700-876a-4393-8d9c-9de7616ccbd8
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201697382 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 38.rv_dm_tap_fsm_rand_reset.201697382
Directory /workspace/38.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.682095570
Short name T113
Test name
Test status
Simulation time 21972261439 ps
CPU time 75.56 seconds
Started Apr 16 02:37:11 PM PDT 24
Finished Apr 16 02:38:28 PM PDT 24
Peak memory 204964 kb
Host smart-06344f4e-ae92-4953-b76b-53cb9022837f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682095570 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.rv_dm_csr_aliasing.682095570
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.242007768
Short name T373
Test name
Test status
Simulation time 1445437430 ps
CPU time 27.28 seconds
Started Apr 16 02:37:12 PM PDT 24
Finished Apr 16 02:37:40 PM PDT 24
Peak memory 204772 kb
Host smart-e7e5a7c7-cafd-4fea-9f2a-19d5dcf39b73
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242007768 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.242007768
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2775451238
Short name T104
Test name
Test status
Simulation time 216317739 ps
CPU time 2.27 seconds
Started Apr 16 02:37:12 PM PDT 24
Finished Apr 16 02:37:15 PM PDT 24
Peak memory 213068 kb
Host smart-9964efba-04b4-466c-8680-a60c3d542dbc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775451238 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.2775451238
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.1843595353
Short name T332
Test name
Test status
Simulation time 2275147673 ps
CPU time 3.99 seconds
Started Apr 16 02:37:11 PM PDT 24
Finished Apr 16 02:37:16 PM PDT 24
Peak memory 218388 kb
Host smart-3a70470f-3efa-47f3-9e77-0c14f80fcccf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843595353 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.1843595353
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.2843025290
Short name T340
Test name
Test status
Simulation time 38914188 ps
CPU time 2.1 seconds
Started Apr 16 02:37:12 PM PDT 24
Finished Apr 16 02:37:15 PM PDT 24
Peak memory 212992 kb
Host smart-e5ab81a5-700d-414e-b1fe-8dfdb8b20000
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843025290 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.2843025290
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2449127914
Short name T241
Test name
Test status
Simulation time 31346113378 ps
CPU time 94.38 seconds
Started Apr 16 02:37:13 PM PDT 24
Finished Apr 16 02:38:48 PM PDT 24
Peak memory 204856 kb
Host smart-cd2dc8a4-03e5-4c3c-9460-3593d3b4db6e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449127914 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.2449127914
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.2547760734
Short name T267
Test name
Test status
Simulation time 8358012395 ps
CPU time 11.57 seconds
Started Apr 16 02:37:11 PM PDT 24
Finished Apr 16 02:37:23 PM PDT 24
Peak memory 204808 kb
Host smart-3b336033-071c-4eff-903f-976bd785200f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547760734 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_bit_bash.2547760734
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2551698961
Short name T97
Test name
Test status
Simulation time 434834637 ps
CPU time 1.61 seconds
Started Apr 16 02:37:08 PM PDT 24
Finished Apr 16 02:37:10 PM PDT 24
Peak memory 204756 kb
Host smart-7afe37ea-f148-43c3-bad3-faa41f062d40
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551698961 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.2551698961
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.631222069
Short name T279
Test name
Test status
Simulation time 639505602 ps
CPU time 0.96 seconds
Started Apr 16 02:37:08 PM PDT 24
Finished Apr 16 02:37:10 PM PDT 24
Peak memory 204684 kb
Host smart-d44c9177-1acd-4661-bec2-77e85f0e4cfb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631222069 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.631222069
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.2707248026
Short name T278
Test name
Test status
Simulation time 81630413 ps
CPU time 0.68 seconds
Started Apr 16 02:37:08 PM PDT 24
Finished Apr 16 02:37:09 PM PDT 24
Peak memory 204444 kb
Host smart-b5a9201c-c609-4285-8deb-8802e3495d29
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707248026 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.2707248026
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.1901815341
Short name T361
Test name
Test status
Simulation time 2874432068 ps
CPU time 2.59 seconds
Started Apr 16 02:37:09 PM PDT 24
Finished Apr 16 02:37:13 PM PDT 24
Peak memory 204688 kb
Host smart-810e6367-9f56-44d7-b8e1-ab6bc20e3ea7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901815341 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.1901815341
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.1059593433
Short name T335
Test name
Test status
Simulation time 76747641 ps
CPU time 0.85 seconds
Started Apr 16 02:37:10 PM PDT 24
Finished Apr 16 02:37:12 PM PDT 24
Peak memory 204548 kb
Host smart-558b53a6-35e6-4c43-bf21-cdc70492b55b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059593433 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.1059593433
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2183506910
Short name T250
Test name
Test status
Simulation time 37491464 ps
CPU time 0.77 seconds
Started Apr 16 02:37:09 PM PDT 24
Finished Apr 16 02:37:11 PM PDT 24
Peak memory 204492 kb
Host smart-de16152e-913d-4714-a9c2-9f9fd1cc87e2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183506910 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.2
183506910
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1715344214
Short name T251
Test name
Test status
Simulation time 81109677 ps
CPU time 0.68 seconds
Started Apr 16 02:37:13 PM PDT 24
Finished Apr 16 02:37:14 PM PDT 24
Peak memory 204488 kb
Host smart-3e36bf02-62f0-441a-b8aa-5d5b6ac77a40
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715344214 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.1715344214
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.166991496
Short name T325
Test name
Test status
Simulation time 17502358 ps
CPU time 0.68 seconds
Started Apr 16 02:37:14 PM PDT 24
Finished Apr 16 02:37:15 PM PDT 24
Peak memory 204484 kb
Host smart-6efc484e-0162-4b55-82d2-941c3dc808fe
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166991496 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.166991496
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.4030753941
Short name T107
Test name
Test status
Simulation time 1093694272 ps
CPU time 4.32 seconds
Started Apr 16 02:37:11 PM PDT 24
Finished Apr 16 02:37:17 PM PDT 24
Peak memory 204776 kb
Host smart-8bec2adf-e0d8-431a-91ee-c5f72d811d43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030753941 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.4030753941
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2861924628
Short name T343
Test name
Test status
Simulation time 15646499064 ps
CPU time 9.97 seconds
Started Apr 16 02:37:11 PM PDT 24
Finished Apr 16 02:37:22 PM PDT 24
Peak memory 221144 kb
Host smart-7673c571-a349-43ed-b6f9-46b98509a797
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861924628 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.2861924628
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.215126405
Short name T255
Test name
Test status
Simulation time 166267809 ps
CPU time 2.84 seconds
Started Apr 16 02:37:13 PM PDT 24
Finished Apr 16 02:37:17 PM PDT 24
Peak memory 213108 kb
Host smart-d29ef4f0-449d-4577-9e67-80ae05214ff8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215126405 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.215126405
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.2784049460
Short name T135
Test name
Test status
Simulation time 3260889550 ps
CPU time 18.5 seconds
Started Apr 16 02:37:11 PM PDT 24
Finished Apr 16 02:37:31 PM PDT 24
Peak memory 221368 kb
Host smart-e857dfd2-066d-4769-acc2-96ae7b1895b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784049460 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.2784049460
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.2849520734
Short name T330
Test name
Test status
Simulation time 919107734 ps
CPU time 4.72 seconds
Started Apr 16 02:37:16 PM PDT 24
Finished Apr 16 02:37:22 PM PDT 24
Peak memory 218604 kb
Host smart-7995029a-b5f5-449e-b441-756f6beca42f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849520734 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.2849520734
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.991815714
Short name T111
Test name
Test status
Simulation time 145322869 ps
CPU time 2.24 seconds
Started Apr 16 02:37:13 PM PDT 24
Finished Apr 16 02:37:16 PM PDT 24
Peak memory 221172 kb
Host smart-609d7a61-31ea-419d-ae91-d57d2059ebc2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991815714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.991815714
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3615688674
Short name T247
Test name
Test status
Simulation time 810131606 ps
CPU time 1.24 seconds
Started Apr 16 02:37:13 PM PDT 24
Finished Apr 16 02:37:15 PM PDT 24
Peak memory 204564 kb
Host smart-1b283c5a-5dc0-4acf-8f99-ddf58314c0e7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615688674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.3
615688674
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.2831154893
Short name T270
Test name
Test status
Simulation time 86597518 ps
CPU time 0.73 seconds
Started Apr 16 02:37:11 PM PDT 24
Finished Apr 16 02:37:13 PM PDT 24
Peak memory 204480 kb
Host smart-68b19970-9260-41c1-8229-2d834566e53e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831154893 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.2
831154893
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1393245205
Short name T337
Test name
Test status
Simulation time 415860852 ps
CPU time 7.75 seconds
Started Apr 16 02:37:11 PM PDT 24
Finished Apr 16 02:37:20 PM PDT 24
Peak memory 204816 kb
Host smart-49593734-ad9e-4213-afd9-70f2ed8ed9b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393245205 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.1393245205
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.2419478029
Short name T266
Test name
Test status
Simulation time 166378583 ps
CPU time 2.56 seconds
Started Apr 16 02:37:13 PM PDT 24
Finished Apr 16 02:37:17 PM PDT 24
Peak memory 213008 kb
Host smart-9a2cd29d-bb88-4c63-8ad8-82880fb5af89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419478029 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.2419478029
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.232148012
Short name T138
Test name
Test status
Simulation time 671447383 ps
CPU time 8.23 seconds
Started Apr 16 02:37:11 PM PDT 24
Finished Apr 16 02:37:20 PM PDT 24
Peak memory 221196 kb
Host smart-e8c8bef4-bf00-406d-b85b-2a1006b6811e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232148012 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.232148012
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2866565355
Short name T34
Test name
Test status
Simulation time 328595619 ps
CPU time 2.29 seconds
Started Apr 16 02:37:20 PM PDT 24
Finished Apr 16 02:37:22 PM PDT 24
Peak memory 215000 kb
Host smart-0260b8c9-bbb1-49b0-8939-7d371974a7d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866565355 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.2866565355
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1940584579
Short name T115
Test name
Test status
Simulation time 127459864 ps
CPU time 2.23 seconds
Started Apr 16 02:37:18 PM PDT 24
Finished Apr 16 02:37:21 PM PDT 24
Peak memory 212948 kb
Host smart-14a01dbb-5835-483f-b286-2c0362d45c77
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940584579 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.1940584579
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.3554678434
Short name T366
Test name
Test status
Simulation time 241576534 ps
CPU time 1.83 seconds
Started Apr 16 02:37:20 PM PDT 24
Finished Apr 16 02:37:22 PM PDT 24
Peak memory 204668 kb
Host smart-b08113d1-b66d-4736-ab1e-2a15158eedbf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554678434 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.3
554678434
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.3183620730
Short name T286
Test name
Test status
Simulation time 45309216 ps
CPU time 0.74 seconds
Started Apr 16 02:37:20 PM PDT 24
Finished Apr 16 02:37:21 PM PDT 24
Peak memory 204480 kb
Host smart-70f3d566-46b8-4934-83c3-2ce7a28f26f2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183620730 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.3
183620730
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2701088461
Short name T81
Test name
Test status
Simulation time 171162568 ps
CPU time 3.56 seconds
Started Apr 16 02:37:18 PM PDT 24
Finished Apr 16 02:37:22 PM PDT 24
Peak memory 204816 kb
Host smart-033f69d5-ccc7-4681-961c-bb5edd24fbcc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701088461 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.2701088461
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.3367577916
Short name T374
Test name
Test status
Simulation time 6874006987 ps
CPU time 19.97 seconds
Started Apr 16 02:37:18 PM PDT 24
Finished Apr 16 02:37:39 PM PDT 24
Peak memory 213768 kb
Host smart-1251b489-764a-4089-a942-61877292737f
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367577916 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.3367577916
Directory /workspace/6.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.2505610761
Short name T126
Test name
Test status
Simulation time 1510035316 ps
CPU time 4.53 seconds
Started Apr 16 02:37:17 PM PDT 24
Finished Apr 16 02:37:22 PM PDT 24
Peak memory 213136 kb
Host smart-c79ea316-166b-468c-9bad-e3dae2ad41c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505610761 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.2505610761
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.4045544675
Short name T75
Test name
Test status
Simulation time 554851535 ps
CPU time 2.94 seconds
Started Apr 16 02:37:20 PM PDT 24
Finished Apr 16 02:37:23 PM PDT 24
Peak memory 216136 kb
Host smart-6878ca07-98cd-430a-a091-9da09371c116
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045544675 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.4045544675
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.999529264
Short name T281
Test name
Test status
Simulation time 69903000 ps
CPU time 1.38 seconds
Started Apr 16 02:37:15 PM PDT 24
Finished Apr 16 02:37:18 PM PDT 24
Peak memory 212928 kb
Host smart-c5979e91-9087-476c-af38-b31a6a3b4313
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999529264 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.999529264
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.644836415
Short name T348
Test name
Test status
Simulation time 388427010 ps
CPU time 1.39 seconds
Started Apr 16 02:37:15 PM PDT 24
Finished Apr 16 02:37:18 PM PDT 24
Peak memory 204680 kb
Host smart-593206a9-3781-4c17-aa70-ba5d55fdb1a7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644836415 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.644836415
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.3471647430
Short name T264
Test name
Test status
Simulation time 125975800 ps
CPU time 0.72 seconds
Started Apr 16 02:37:20 PM PDT 24
Finished Apr 16 02:37:22 PM PDT 24
Peak memory 204488 kb
Host smart-da5bcf10-7c68-4ad6-a745-8f20a7e6f965
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471647430 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.3
471647430
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.1366233357
Short name T82
Test name
Test status
Simulation time 567979923 ps
CPU time 7.91 seconds
Started Apr 16 02:37:16 PM PDT 24
Finished Apr 16 02:37:24 PM PDT 24
Peak memory 204784 kb
Host smart-539136e0-2e3d-47bf-aeea-59e272130cea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366233357 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.1366233357
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.3689414001
Short name T358
Test name
Test status
Simulation time 10094067330 ps
CPU time 15.47 seconds
Started Apr 16 02:37:17 PM PDT 24
Finished Apr 16 02:37:33 PM PDT 24
Peak memory 221288 kb
Host smart-534fa85d-c355-4285-99ff-05fe45879b40
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689414001 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.3689414001
Directory /workspace/7.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.1429458624
Short name T35
Test name
Test status
Simulation time 94537262 ps
CPU time 4.99 seconds
Started Apr 16 02:37:17 PM PDT 24
Finished Apr 16 02:37:23 PM PDT 24
Peak memory 213044 kb
Host smart-5e6cc509-16e9-4aef-9c86-623a60f3b587
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429458624 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.1429458624
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2454311929
Short name T129
Test name
Test status
Simulation time 548892104 ps
CPU time 9.42 seconds
Started Apr 16 02:37:17 PM PDT 24
Finished Apr 16 02:37:27 PM PDT 24
Peak memory 213032 kb
Host smart-53e3b5db-ec0f-4eca-9454-03603e63e222
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454311929 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.2454311929
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.3533680764
Short name T77
Test name
Test status
Simulation time 3379821548 ps
CPU time 5.42 seconds
Started Apr 16 02:37:24 PM PDT 24
Finished Apr 16 02:37:30 PM PDT 24
Peak memory 217032 kb
Host smart-d2f20e31-4b82-4645-a9d9-7eabb25e550a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533680764 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.3533680764
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.2988239677
Short name T280
Test name
Test status
Simulation time 35429198 ps
CPU time 1.5 seconds
Started Apr 16 02:37:29 PM PDT 24
Finished Apr 16 02:37:32 PM PDT 24
Peak memory 212932 kb
Host smart-46fc85f7-fb2e-4000-a139-a2bcc74492e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988239677 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.2988239677
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1193907246
Short name T342
Test name
Test status
Simulation time 156728345 ps
CPU time 1.29 seconds
Started Apr 16 02:37:21 PM PDT 24
Finished Apr 16 02:37:23 PM PDT 24
Peak memory 204660 kb
Host smart-e4df17dc-965e-4071-bcf8-7e735435468e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193907246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.1
193907246
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.727916820
Short name T306
Test name
Test status
Simulation time 86391394 ps
CPU time 0.72 seconds
Started Apr 16 02:37:20 PM PDT 24
Finished Apr 16 02:37:22 PM PDT 24
Peak memory 204488 kb
Host smart-dd24aa2d-4523-47a8-8e4e-41096f8683af
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727916820 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.727916820
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.1704166167
Short name T117
Test name
Test status
Simulation time 2141178499 ps
CPU time 8.06 seconds
Started Apr 16 02:37:20 PM PDT 24
Finished Apr 16 02:37:29 PM PDT 24
Peak memory 204848 kb
Host smart-6439f8df-efc6-4210-80c1-5dda4995afe7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704166167 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_
csr_outstanding.1704166167
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.2826371817
Short name T263
Test name
Test status
Simulation time 13215223990 ps
CPU time 15.47 seconds
Started Apr 16 02:37:20 PM PDT 24
Finished Apr 16 02:37:36 PM PDT 24
Peak memory 214780 kb
Host smart-166cf738-a63a-42aa-a464-93ca7ee23b84
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826371817 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.2826371817
Directory /workspace/8.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.3636996997
Short name T262
Test name
Test status
Simulation time 864345546 ps
CPU time 5.25 seconds
Started Apr 16 02:37:18 PM PDT 24
Finished Apr 16 02:37:24 PM PDT 24
Peak memory 213056 kb
Host smart-c0f32a3b-66eb-4c53-aa4a-a46a0cfe1d61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636996997 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.3636996997
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.4238973514
Short name T252
Test name
Test status
Simulation time 1307420598 ps
CPU time 19.96 seconds
Started Apr 16 02:37:24 PM PDT 24
Finished Apr 16 02:37:45 PM PDT 24
Peak memory 213008 kb
Host smart-9b0075eb-2be4-496c-90f2-1fe8ad63b7af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238973514 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.4238973514
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.2940971404
Short name T297
Test name
Test status
Simulation time 6375983670 ps
CPU time 5.76 seconds
Started Apr 16 02:37:22 PM PDT 24
Finished Apr 16 02:37:28 PM PDT 24
Peak memory 217532 kb
Host smart-ccfb0fcf-6a70-47d3-9a9e-6f5e930e4752
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940971404 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.2940971404
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.2637852600
Short name T349
Test name
Test status
Simulation time 75582825 ps
CPU time 1.52 seconds
Started Apr 16 02:37:24 PM PDT 24
Finished Apr 16 02:37:26 PM PDT 24
Peak memory 217784 kb
Host smart-31ec3236-422c-4335-8f82-5bce864209f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637852600 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.2637852600
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.1713428635
Short name T365
Test name
Test status
Simulation time 1621931806 ps
CPU time 1.48 seconds
Started Apr 16 02:37:22 PM PDT 24
Finished Apr 16 02:37:24 PM PDT 24
Peak memory 204704 kb
Host smart-00f85e33-8f08-4932-a7be-e5e1b1954e9b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713428635 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.1
713428635
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1291113106
Short name T356
Test name
Test status
Simulation time 31157204 ps
CPU time 0.73 seconds
Started Apr 16 02:37:22 PM PDT 24
Finished Apr 16 02:37:23 PM PDT 24
Peak memory 204512 kb
Host smart-e2cadb9b-75a1-4360-9387-486b02a7971d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291113106 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.1
291113106
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.2449866642
Short name T352
Test name
Test status
Simulation time 256282725 ps
CPU time 3.67 seconds
Started Apr 16 02:37:24 PM PDT 24
Finished Apr 16 02:37:29 PM PDT 24
Peak memory 204824 kb
Host smart-665dd96b-8ae1-4878-815b-3141402c9715
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449866642 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.2449866642
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.420673627
Short name T62
Test name
Test status
Simulation time 28732094751 ps
CPU time 14.37 seconds
Started Apr 16 02:37:23 PM PDT 24
Finished Apr 16 02:37:38 PM PDT 24
Peak memory 221320 kb
Host smart-4df17cd9-4bec-4cec-9059-100cc8c31e80
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420673627 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.420673627
Directory /workspace/9.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.873437598
Short name T271
Test name
Test status
Simulation time 435296730 ps
CPU time 3.38 seconds
Started Apr 16 02:37:23 PM PDT 24
Finished Apr 16 02:37:27 PM PDT 24
Peak memory 213156 kb
Host smart-f6e59b4a-dc19-4e39-8d43-1905683fb7a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873437598 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.873437598
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.224496521
Short name T197
Test name
Test status
Simulation time 23258873 ps
CPU time 0.7 seconds
Started Apr 16 12:49:48 PM PDT 24
Finished Apr 16 12:49:50 PM PDT 24
Peak memory 204984 kb
Host smart-697df3b0-ef22-4b4d-a6af-ba5ddad4a7c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224496521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.224496521
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.3269388105
Short name T7
Test name
Test status
Simulation time 1930908453 ps
CPU time 6.83 seconds
Started Apr 16 12:49:40 PM PDT 24
Finished Apr 16 12:49:49 PM PDT 24
Peak memory 205328 kb
Host smart-6a47c3c9-2194-4a23-9212-ecc35b06d2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269388105 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.3269388105
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.4232500217
Short name T205
Test name
Test status
Simulation time 88557654 ps
CPU time 0.72 seconds
Started Apr 16 12:49:41 PM PDT 24
Finished Apr 16 12:49:43 PM PDT 24
Peak memory 205100 kb
Host smart-f2c5caf5-4158-47a2-a7f3-07458705539f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232500217 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.4232500217
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.621311994
Short name T46
Test name
Test status
Simulation time 4999391805 ps
CPU time 11.47 seconds
Started Apr 16 12:49:45 PM PDT 24
Finished Apr 16 12:49:57 PM PDT 24
Peak memory 205504 kb
Host smart-0530458c-b660-4267-9cb5-a4b8371cf32f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=621311994 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_tl
_access.621311994
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.3613997004
Short name T51
Test name
Test status
Simulation time 774534521 ps
CPU time 2.87 seconds
Started Apr 16 12:49:41 PM PDT 24
Finished Apr 16 12:49:45 PM PDT 24
Peak memory 205292 kb
Host smart-8aaa2c0e-4dfb-423f-9217-5c5cf0e00eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613997004 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.3613997004
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.4082401536
Short name T40
Test name
Test status
Simulation time 52212047 ps
CPU time 0.87 seconds
Started Apr 16 12:49:45 PM PDT 24
Finished Apr 16 12:49:47 PM PDT 24
Peak memory 204968 kb
Host smart-a2b587e5-6043-4665-9c1a-79653fd18404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082401536 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.4082401536
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.1709967224
Short name T173
Test name
Test status
Simulation time 80956257 ps
CPU time 0.9 seconds
Started Apr 16 12:49:43 PM PDT 24
Finished Apr 16 12:49:45 PM PDT 24
Peak memory 204208 kb
Host smart-4467a7a0-6993-4e99-8f6c-3b97a3067d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709967224 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.1709967224
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.1920689064
Short name T169
Test name
Test status
Simulation time 257390995 ps
CPU time 1.56 seconds
Started Apr 16 12:49:44 PM PDT 24
Finished Apr 16 12:49:47 PM PDT 24
Peak memory 205168 kb
Host smart-626c1cc3-f5ee-4fc0-9e4d-b9d159874b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920689064 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.1920689064
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.32028527
Short name T61
Test name
Test status
Simulation time 41992548 ps
CPU time 0.75 seconds
Started Apr 16 12:49:43 PM PDT 24
Finished Apr 16 12:49:45 PM PDT 24
Peak memory 205028 kb
Host smart-cdf3a36f-23fb-4a65-82b4-052c2c3bd0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32028527 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.32028527
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.71681092
Short name T58
Test name
Test status
Simulation time 255892583 ps
CPU time 1.45 seconds
Started Apr 16 12:49:45 PM PDT 24
Finished Apr 16 12:49:47 PM PDT 24
Peak memory 205096 kb
Host smart-420d041e-d670-4ce7-bb74-c0d6468e4f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71681092 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.71681092
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.3972750704
Short name T72
Test name
Test status
Simulation time 182590282 ps
CPU time 1.03 seconds
Started Apr 16 12:49:42 PM PDT 24
Finished Apr 16 12:49:44 PM PDT 24
Peak memory 205124 kb
Host smart-45ec8175-045c-4693-858f-1605f1a66f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972750704 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.3972750704
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.2229227215
Short name T143
Test name
Test status
Simulation time 167527734 ps
CPU time 1 seconds
Started Apr 16 12:49:42 PM PDT 24
Finished Apr 16 12:49:44 PM PDT 24
Peak memory 205120 kb
Host smart-7b7d8d30-72c6-4f87-9c9b-48095b6d95c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229227215 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.2229227215
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.385749372
Short name T225
Test name
Test status
Simulation time 2958763185 ps
CPU time 7.18 seconds
Started Apr 16 12:49:43 PM PDT 24
Finished Apr 16 12:49:51 PM PDT 24
Peak memory 205512 kb
Host smart-71379fc5-5ade-4555-8314-e786896aff3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385749372 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.385749372
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.2536151012
Short name T181
Test name
Test status
Simulation time 744815273 ps
CPU time 2.7 seconds
Started Apr 16 12:49:40 PM PDT 24
Finished Apr 16 12:49:44 PM PDT 24
Peak memory 205188 kb
Host smart-23e77caa-c757-403a-a63e-38639192f4ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536151012 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.2536151012
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.1905378285
Short name T59
Test name
Test status
Simulation time 1017423889 ps
CPU time 3.62 seconds
Started Apr 16 12:49:41 PM PDT 24
Finished Apr 16 12:49:46 PM PDT 24
Peak memory 205228 kb
Host smart-41a3d90a-a56a-4826-bc96-3ddd182a19c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905378285 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.1905378285
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.1677002085
Short name T168
Test name
Test status
Simulation time 70222564 ps
CPU time 0.67 seconds
Started Apr 16 12:49:52 PM PDT 24
Finished Apr 16 12:49:56 PM PDT 24
Peak memory 205144 kb
Host smart-94deca47-044b-4b32-bf8c-7da223bd62f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677002085 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.1677002085
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.3544042435
Short name T211
Test name
Test status
Simulation time 3941887594 ps
CPU time 13.49 seconds
Started Apr 16 12:49:48 PM PDT 24
Finished Apr 16 12:50:03 PM PDT 24
Peak memory 205476 kb
Host smart-67708bf4-6ee2-4531-9223-58c4eb0594f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544042435 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.3544042435
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.2587711012
Short name T8
Test name
Test status
Simulation time 1288397890 ps
CPU time 4.8 seconds
Started Apr 16 12:49:51 PM PDT 24
Finished Apr 16 12:49:59 PM PDT 24
Peak memory 205308 kb
Host smart-7d6a0d91-9e7b-464f-81f9-d151f58ff400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587711012 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.2587711012
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.1538072956
Short name T56
Test name
Test status
Simulation time 259101373 ps
CPU time 0.91 seconds
Started Apr 16 12:49:48 PM PDT 24
Finished Apr 16 12:49:50 PM PDT 24
Peak memory 205128 kb
Host smart-69371f1d-e50c-4810-af86-606582ece591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538072956 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.1538072956
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.795473747
Short name T16
Test name
Test status
Simulation time 371375688 ps
CPU time 1.07 seconds
Started Apr 16 12:49:51 PM PDT 24
Finished Apr 16 12:49:55 PM PDT 24
Peak memory 204864 kb
Host smart-29b2ed87-3f5d-4330-8e20-1a003210b810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795473747 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.795473747
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.2881312307
Short name T19
Test name
Test status
Simulation time 9417506191 ps
CPU time 2.26 seconds
Started Apr 16 12:49:47 PM PDT 24
Finished Apr 16 12:49:51 PM PDT 24
Peak memory 205440 kb
Host smart-eb043d77-a1b8-4574-8405-6924f3f05813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881312307 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.2881312307
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.4248590860
Short name T20
Test name
Test status
Simulation time 55275070 ps
CPU time 0.84 seconds
Started Apr 16 12:49:50 PM PDT 24
Finished Apr 16 12:49:53 PM PDT 24
Peak memory 205152 kb
Host smart-ee69429c-2c06-4de4-b269-763b8226a7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248590860 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.4248590860
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.66736014
Short name T171
Test name
Test status
Simulation time 1526718166 ps
CPU time 3.64 seconds
Started Apr 16 12:49:47 PM PDT 24
Finished Apr 16 12:49:52 PM PDT 24
Peak memory 205360 kb
Host smart-42f9c54e-cc2d-4568-b8db-a1893258dd8f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=66736014 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_tl_
access.66736014
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.3251250959
Short name T141
Test name
Test status
Simulation time 155500862 ps
CPU time 0.8 seconds
Started Apr 16 12:49:48 PM PDT 24
Finished Apr 16 12:49:50 PM PDT 24
Peak memory 205116 kb
Host smart-0fa7f218-29ea-416c-bbba-1201b3f19f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251250959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.3251250959
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.432515605
Short name T176
Test name
Test status
Simulation time 56608558 ps
CPU time 0.73 seconds
Started Apr 16 12:49:48 PM PDT 24
Finished Apr 16 12:49:50 PM PDT 24
Peak memory 204964 kb
Host smart-a8cebd90-3c62-4e7c-8bdb-b74272b27722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432515605 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.432515605
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.1520103717
Short name T26
Test name
Test status
Simulation time 132781017 ps
CPU time 0.77 seconds
Started Apr 16 12:49:50 PM PDT 24
Finished Apr 16 12:49:53 PM PDT 24
Peak memory 204992 kb
Host smart-8ba637cf-b491-428a-83c7-a012b4c5826d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520103717 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.1520103717
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.4039242840
Short name T189
Test name
Test status
Simulation time 157904554 ps
CPU time 0.97 seconds
Started Apr 16 12:49:50 PM PDT 24
Finished Apr 16 12:49:52 PM PDT 24
Peak memory 204180 kb
Host smart-a1be24b3-66e8-4237-b4cc-5a19c16af0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039242840 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.4039242840
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.56230796
Short name T60
Test name
Test status
Simulation time 216290872 ps
CPU time 0.94 seconds
Started Apr 16 12:49:51 PM PDT 24
Finished Apr 16 12:49:55 PM PDT 24
Peak memory 204968 kb
Host smart-f4b13234-3f34-4bac-bda2-ca87f28d0eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56230796 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.56230796
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.67217388
Short name T41
Test name
Test status
Simulation time 99644017 ps
CPU time 0.75 seconds
Started Apr 16 12:49:51 PM PDT 24
Finished Apr 16 12:49:55 PM PDT 24
Peak memory 204964 kb
Host smart-c20eb402-6d2f-4bbb-a7ec-1ead2220646a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67217388 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.67217388
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.1851313925
Short name T31
Test name
Test status
Simulation time 61952700 ps
CPU time 0.86 seconds
Started Apr 16 12:49:45 PM PDT 24
Finished Apr 16 12:49:47 PM PDT 24
Peak memory 205128 kb
Host smart-7f9681bb-d324-43f6-b89e-84cae0ff55ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851313925 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.1851313925
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.1277293591
Short name T140
Test name
Test status
Simulation time 782522519 ps
CPU time 1.18 seconds
Started Apr 16 12:49:47 PM PDT 24
Finished Apr 16 12:49:50 PM PDT 24
Peak memory 205376 kb
Host smart-1aee1e26-326a-42b8-835b-7a990c8e7deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277293591 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.1277293591
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.2685919228
Short name T222
Test name
Test status
Simulation time 407111189 ps
CPU time 1.43 seconds
Started Apr 16 12:49:54 PM PDT 24
Finished Apr 16 12:49:58 PM PDT 24
Peak memory 205172 kb
Host smart-8693f52d-cade-4706-9762-25ae98adb611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685919228 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.2685919228
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.3500946066
Short name T52
Test name
Test status
Simulation time 87021763 ps
CPU time 0.81 seconds
Started Apr 16 12:49:51 PM PDT 24
Finished Apr 16 12:49:55 PM PDT 24
Peak memory 205096 kb
Host smart-d2846f83-c7cf-4fb9-b8da-056bc7ff741f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500946066 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.3500946066
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.1908167794
Short name T2
Test name
Test status
Simulation time 50545660 ps
CPU time 0.83 seconds
Started Apr 16 12:49:54 PM PDT 24
Finished Apr 16 12:49:57 PM PDT 24
Peak memory 204988 kb
Host smart-84f4121a-6c58-4029-856c-b88f63f9886a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908167794 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.1908167794
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.1478426821
Short name T49
Test name
Test status
Simulation time 33814108 ps
CPU time 0.9 seconds
Started Apr 16 12:49:51 PM PDT 24
Finished Apr 16 12:49:54 PM PDT 24
Peak memory 213348 kb
Host smart-70fb9cb5-32e3-4e06-bb07-7495007f6e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478426821 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.1478426821
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.2165193988
Short name T237
Test name
Test status
Simulation time 2234254518 ps
CPU time 7.36 seconds
Started Apr 16 12:49:50 PM PDT 24
Finished Apr 16 12:49:59 PM PDT 24
Peak memory 205392 kb
Host smart-8b057736-d163-4e94-b580-e863f08f1a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165193988 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.2165193988
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.1820450509
Short name T42
Test name
Test status
Simulation time 588550629 ps
CPU time 1.23 seconds
Started Apr 16 12:49:47 PM PDT 24
Finished Apr 16 12:49:50 PM PDT 24
Peak memory 237320 kb
Host smart-eccfa852-6fe7-4174-a5b3-5c5f0a055acc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820450509 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.1820450509
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.1983815096
Short name T177
Test name
Test status
Simulation time 479715040 ps
CPU time 1.64 seconds
Started Apr 16 12:49:51 PM PDT 24
Finished Apr 16 12:49:55 PM PDT 24
Peak memory 205216 kb
Host smart-05e0b4b4-41c9-4683-b8c5-65a145dadfa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983815096 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.1983815096
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.2481494925
Short name T155
Test name
Test status
Simulation time 17652453 ps
CPU time 0.78 seconds
Started Apr 16 12:49:59 PM PDT 24
Finished Apr 16 12:50:01 PM PDT 24
Peak memory 205124 kb
Host smart-96e71efc-0ec6-47d0-849b-b345ddf97254
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481494925 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.2481494925
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.44377293
Short name T11
Test name
Test status
Simulation time 4003215065 ps
CPU time 11.68 seconds
Started Apr 16 12:49:56 PM PDT 24
Finished Apr 16 12:50:09 PM PDT 24
Peak memory 205592 kb
Host smart-688b40ca-d925-4022-9ac0-98f7970909d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44377293 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.44377293
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.342435443
Short name T198
Test name
Test status
Simulation time 1935354397 ps
CPU time 3.01 seconds
Started Apr 16 12:49:59 PM PDT 24
Finished Apr 16 12:50:03 PM PDT 24
Peak memory 205384 kb
Host smart-25c69e6d-f42c-47db-811d-34feea1df396
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=342435443 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_t
l_access.342435443
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.3220823290
Short name T172
Test name
Test status
Simulation time 2156790472 ps
CPU time 4.46 seconds
Started Apr 16 12:50:02 PM PDT 24
Finished Apr 16 12:50:08 PM PDT 24
Peak memory 205544 kb
Host smart-e5229db4-4e75-432f-aa9c-54408a552557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220823290 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.3220823290
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.757577479
Short name T206
Test name
Test status
Simulation time 27548988 ps
CPU time 0.69 seconds
Started Apr 16 12:50:07 PM PDT 24
Finished Apr 16 12:50:10 PM PDT 24
Peak memory 205136 kb
Host smart-1473c721-7862-4862-b31d-fd2716cdbd2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757577479 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.757577479
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.167460018
Short name T210
Test name
Test status
Simulation time 10458309491 ps
CPU time 20.06 seconds
Started Apr 16 12:50:07 PM PDT 24
Finished Apr 16 12:50:29 PM PDT 24
Peak memory 213768 kb
Host smart-d5405822-3c1d-4852-9528-c72603800099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167460018 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.167460018
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.1888410564
Short name T208
Test name
Test status
Simulation time 2966314656 ps
CPU time 4.46 seconds
Started Apr 16 12:50:00 PM PDT 24
Finished Apr 16 12:50:05 PM PDT 24
Peak memory 205576 kb
Host smart-5c2d984b-f484-43af-a93b-78e90b7f6a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888410564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.1888410564
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.2399495942
Short name T185
Test name
Test status
Simulation time 3247480740 ps
CPU time 11.4 seconds
Started Apr 16 12:50:11 PM PDT 24
Finished Apr 16 12:50:25 PM PDT 24
Peak memory 205428 kb
Host smart-667116a4-5f68-4dc6-a471-31e6c699e6ce
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2399495942 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_
tl_access.2399495942
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.599520953
Short name T180
Test name
Test status
Simulation time 4611199480 ps
CPU time 17.12 seconds
Started Apr 16 12:50:12 PM PDT 24
Finished Apr 16 12:50:31 PM PDT 24
Peak memory 205532 kb
Host smart-c9f922d9-6f27-48fb-bfeb-02172f8993d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599520953 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.599520953
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.3210808407
Short name T165
Test name
Test status
Simulation time 102331946 ps
CPU time 0.7 seconds
Started Apr 16 12:50:04 PM PDT 24
Finished Apr 16 12:50:06 PM PDT 24
Peak memory 205100 kb
Host smart-3a7485eb-ab3f-4ad3-bd47-2afeb0538ecc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210808407 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.3210808407
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.2731153001
Short name T219
Test name
Test status
Simulation time 3135866463 ps
CPU time 6.98 seconds
Started Apr 16 12:50:05 PM PDT 24
Finished Apr 16 12:50:14 PM PDT 24
Peak memory 205564 kb
Host smart-8ebda8d5-b8f0-41e8-bf3b-14213b2ff2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731153001 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.2731153001
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.1934981890
Short name T203
Test name
Test status
Simulation time 2698127543 ps
CPU time 5.64 seconds
Started Apr 16 12:50:05 PM PDT 24
Finished Apr 16 12:50:11 PM PDT 24
Peak memory 215052 kb
Host smart-bcb02ba3-6c2f-42d9-b3f5-088c2593295f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934981890 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.1934981890
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.2168531454
Short name T37
Test name
Test status
Simulation time 11092911355 ps
CPU time 7.86 seconds
Started Apr 16 12:50:05 PM PDT 24
Finished Apr 16 12:50:14 PM PDT 24
Peak memory 213748 kb
Host smart-13888e41-3165-4e2e-965d-b7c8c24b9d97
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2168531454 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.2168531454
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.2057240670
Short name T93
Test name
Test status
Simulation time 2419537718 ps
CPU time 11.3 seconds
Started Apr 16 12:50:06 PM PDT 24
Finished Apr 16 12:50:18 PM PDT 24
Peak memory 205508 kb
Host smart-847ec7ca-74aa-4667-abbe-505f0e051773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057240670 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.2057240670
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.1512395797
Short name T163
Test name
Test status
Simulation time 26459364 ps
CPU time 0.7 seconds
Started Apr 16 12:50:06 PM PDT 24
Finished Apr 16 12:50:09 PM PDT 24
Peak memory 205120 kb
Host smart-094fd620-4ca1-4497-ae54-fe4dc42d0f59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512395797 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.1512395797
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.1871202328
Short name T215
Test name
Test status
Simulation time 6061402964 ps
CPU time 12.02 seconds
Started Apr 16 12:50:03 PM PDT 24
Finished Apr 16 12:50:16 PM PDT 24
Peak memory 205620 kb
Host smart-a461bde7-06cb-4b0c-a28d-aff0db617b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871202328 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.1871202328
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.3160145264
Short name T68
Test name
Test status
Simulation time 951500487 ps
CPU time 4.44 seconds
Started Apr 16 12:50:09 PM PDT 24
Finished Apr 16 12:50:15 PM PDT 24
Peak memory 205344 kb
Host smart-cf5c8a21-f274-4e82-82dc-f0b75476022f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160145264 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.3160145264
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.1814081450
Short name T227
Test name
Test status
Simulation time 906511046 ps
CPU time 2.84 seconds
Started Apr 16 12:50:08 PM PDT 24
Finished Apr 16 12:50:12 PM PDT 24
Peak memory 205356 kb
Host smart-343882df-5ec6-43fd-9f5f-45bde2eca7ea
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1814081450 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_
tl_access.1814081450
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.4000869123
Short name T213
Test name
Test status
Simulation time 4505277035 ps
CPU time 17.69 seconds
Started Apr 16 12:50:07 PM PDT 24
Finished Apr 16 12:50:26 PM PDT 24
Peak memory 213600 kb
Host smart-79788963-0ac9-45c0-af11-37df4e9169a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000869123 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.4000869123
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.1867847491
Short name T154
Test name
Test status
Simulation time 19727138 ps
CPU time 0.76 seconds
Started Apr 16 12:50:04 PM PDT 24
Finished Apr 16 12:50:06 PM PDT 24
Peak memory 205112 kb
Host smart-b0aa67db-325a-48fd-bcf1-41e3295cf665
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867847491 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.1867847491
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.931268764
Short name T234
Test name
Test status
Simulation time 397698232 ps
CPU time 1.26 seconds
Started Apr 16 12:50:05 PM PDT 24
Finished Apr 16 12:50:08 PM PDT 24
Peak memory 205400 kb
Host smart-7d538f2a-985a-4918-ae6b-f4db15443962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931268764 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.931268764
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.2888615488
Short name T44
Test name
Test status
Simulation time 153166747 ps
CPU time 0.7 seconds
Started Apr 16 12:50:06 PM PDT 24
Finished Apr 16 12:50:08 PM PDT 24
Peak memory 205128 kb
Host smart-788584fe-6c53-40e7-8642-91a2f6981ca6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888615488 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.2888615488
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.2127318420
Short name T17
Test name
Test status
Simulation time 36948268383 ps
CPU time 49.48 seconds
Started Apr 16 12:50:05 PM PDT 24
Finished Apr 16 12:50:56 PM PDT 24
Peak memory 213708 kb
Host smart-e3d068a6-5be6-49ff-ba2e-3110a4619b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127318420 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.2127318420
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.2967129214
Short name T224
Test name
Test status
Simulation time 4463725926 ps
CPU time 17.68 seconds
Started Apr 16 12:50:04 PM PDT 24
Finished Apr 16 12:50:23 PM PDT 24
Peak memory 213728 kb
Host smart-80da2949-6f72-40f1-b364-67a97f082666
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2967129214 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_
tl_access.2967129214
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.3014318828
Short name T170
Test name
Test status
Simulation time 4838514499 ps
CPU time 18.86 seconds
Started Apr 16 12:50:05 PM PDT 24
Finished Apr 16 12:50:25 PM PDT 24
Peak memory 205536 kb
Host smart-e270df19-9959-4072-96ae-67b7276d4963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014318828 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.3014318828
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.1671493845
Short name T79
Test name
Test status
Simulation time 49154854 ps
CPU time 0.68 seconds
Started Apr 16 12:50:06 PM PDT 24
Finished Apr 16 12:50:08 PM PDT 24
Peak memory 205048 kb
Host smart-3715c84c-0d5f-44ad-b32e-a0e28575c779
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671493845 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.1671493845
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.780411900
Short name T67
Test name
Test status
Simulation time 3704828005 ps
CPU time 4.82 seconds
Started Apr 16 12:50:05 PM PDT 24
Finished Apr 16 12:50:11 PM PDT 24
Peak memory 213944 kb
Host smart-36b76124-6e21-407f-a576-c6cce193ac54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780411900 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.780411900
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.3150054257
Short name T233
Test name
Test status
Simulation time 10933116400 ps
CPU time 16.85 seconds
Started Apr 16 12:50:06 PM PDT 24
Finished Apr 16 12:50:24 PM PDT 24
Peak memory 214724 kb
Host smart-d24e05eb-555d-4c3e-9270-d3b6e24f509e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3150054257 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_
tl_access.3150054257
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.565444521
Short name T187
Test name
Test status
Simulation time 3708735277 ps
CPU time 13.96 seconds
Started Apr 16 12:50:08 PM PDT 24
Finished Apr 16 12:50:24 PM PDT 24
Peak memory 205512 kb
Host smart-c76d483d-5869-4749-a2fc-6f0ba078ca03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565444521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.565444521
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.1892359223
Short name T164
Test name
Test status
Simulation time 20352266 ps
CPU time 0.71 seconds
Started Apr 16 12:50:08 PM PDT 24
Finished Apr 16 12:50:10 PM PDT 24
Peak memory 204960 kb
Host smart-f15c2e9b-8ead-46eb-b6b6-e4dc6d71a405
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892359223 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.1892359223
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.2829655998
Short name T191
Test name
Test status
Simulation time 8528444718 ps
CPU time 17.55 seconds
Started Apr 16 12:50:06 PM PDT 24
Finished Apr 16 12:50:25 PM PDT 24
Peak memory 213724 kb
Host smart-2ce8894f-5c5c-4833-b60c-4130f139fdba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829655998 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.2829655998
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.746286884
Short name T216
Test name
Test status
Simulation time 2232276835 ps
CPU time 8.7 seconds
Started Apr 16 12:50:04 PM PDT 24
Finished Apr 16 12:50:13 PM PDT 24
Peak memory 205528 kb
Host smart-1dac73da-9c96-480f-bfad-a3d0f712aff2
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=746286884 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_t
l_access.746286884
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.1923643478
Short name T174
Test name
Test status
Simulation time 658644108 ps
CPU time 2.46 seconds
Started Apr 16 12:50:08 PM PDT 24
Finished Apr 16 12:50:12 PM PDT 24
Peak memory 205184 kb
Host smart-7c90b2a2-47a9-4634-b58c-bff784b8f778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923643478 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.1923643478
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.3509240847
Short name T147
Test name
Test status
Simulation time 218347649 ps
CPU time 0.72 seconds
Started Apr 16 12:50:07 PM PDT 24
Finished Apr 16 12:50:10 PM PDT 24
Peak memory 205100 kb
Host smart-542049d4-abf8-4bd4-8be1-620ebc4b9466
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509240847 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.3509240847
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.3773939182
Short name T235
Test name
Test status
Simulation time 1623085021 ps
CPU time 4.16 seconds
Started Apr 16 12:50:06 PM PDT 24
Finished Apr 16 12:50:12 PM PDT 24
Peak memory 205312 kb
Host smart-2c9d8f61-abdb-46c7-9b10-2db8e6b75c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773939182 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.3773939182
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.415982799
Short name T39
Test name
Test status
Simulation time 1319800964 ps
CPU time 2.51 seconds
Started Apr 16 12:50:08 PM PDT 24
Finished Apr 16 12:50:12 PM PDT 24
Peak memory 205332 kb
Host smart-9dedda9c-8243-4e04-b946-a7ed2387675a
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=415982799 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_t
l_access.415982799
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.1861709912
Short name T193
Test name
Test status
Simulation time 702042622 ps
CPU time 3.5 seconds
Started Apr 16 12:50:06 PM PDT 24
Finished Apr 16 12:50:11 PM PDT 24
Peak memory 205368 kb
Host smart-61dfb1ce-cfd7-4fe1-b5f0-be4ef0aa5256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861709912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.1861709912
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.3709575539
Short name T150
Test name
Test status
Simulation time 24278083 ps
CPU time 0.77 seconds
Started Apr 16 12:50:10 PM PDT 24
Finished Apr 16 12:50:13 PM PDT 24
Peak memory 205336 kb
Host smart-f2142365-e202-46df-9016-3f4a211a7e32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709575539 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.3709575539
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.1696883970
Short name T207
Test name
Test status
Simulation time 22695836586 ps
CPU time 74.85 seconds
Started Apr 16 12:50:20 PM PDT 24
Finished Apr 16 12:51:36 PM PDT 24
Peak memory 215876 kb
Host smart-7edc664b-9f20-416f-8da5-ae4c815313bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696883970 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.1696883970
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.2775927542
Short name T184
Test name
Test status
Simulation time 3175952028 ps
CPU time 6.41 seconds
Started Apr 16 12:50:11 PM PDT 24
Finished Apr 16 12:50:20 PM PDT 24
Peak memory 215232 kb
Host smart-3ed076af-fbae-4e2e-806b-68c6130b81f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775927542 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.2775927542
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.2206663218
Short name T186
Test name
Test status
Simulation time 865501001 ps
CPU time 2.92 seconds
Started Apr 16 12:50:11 PM PDT 24
Finished Apr 16 12:50:15 PM PDT 24
Peak memory 205340 kb
Host smart-74504248-b9cc-477d-bf78-06193074cb0e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2206663218 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_
tl_access.2206663218
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.3965056789
Short name T9
Test name
Test status
Simulation time 3641933219 ps
CPU time 6.15 seconds
Started Apr 16 12:50:17 PM PDT 24
Finished Apr 16 12:50:25 PM PDT 24
Peak memory 205588 kb
Host smart-24f29809-d549-4840-9ad5-78b1035e1141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965056789 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.3965056789
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.1279766036
Short name T196
Test name
Test status
Simulation time 21752508 ps
CPU time 0.73 seconds
Started Apr 16 12:49:53 PM PDT 24
Finished Apr 16 12:49:57 PM PDT 24
Peak memory 204984 kb
Host smart-38b98ae6-6b7e-47b1-b011-3ee886672f3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279766036 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.1279766036
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.667182293
Short name T188
Test name
Test status
Simulation time 2273583438 ps
CPU time 7.58 seconds
Started Apr 16 12:49:49 PM PDT 24
Finished Apr 16 12:49:58 PM PDT 24
Peak memory 213736 kb
Host smart-c8f4ebe6-ce9b-47c2-8d0d-21daee402755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667182293 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.667182293
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.2397192103
Short name T200
Test name
Test status
Simulation time 6042554064 ps
CPU time 19.69 seconds
Started Apr 16 12:49:52 PM PDT 24
Finished Apr 16 12:50:15 PM PDT 24
Peak memory 205568 kb
Host smart-52b2b263-a777-4adc-9476-7f44bfb66e5a
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2397192103 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.2397192103
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.1529099410
Short name T220
Test name
Test status
Simulation time 61859633 ps
CPU time 0.68 seconds
Started Apr 16 12:49:49 PM PDT 24
Finished Apr 16 12:49:51 PM PDT 24
Peak memory 204972 kb
Host smart-2333aa3d-e486-4ca0-a171-d8089bd4121a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529099410 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.1529099410
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.3455131434
Short name T190
Test name
Test status
Simulation time 2701397923 ps
CPU time 5.14 seconds
Started Apr 16 12:49:51 PM PDT 24
Finished Apr 16 12:49:59 PM PDT 24
Peak memory 205588 kb
Host smart-a17c876d-f84a-4557-a4ec-9c1f8757ce8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455131434 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.3455131434
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.1425699640
Short name T21
Test name
Test status
Simulation time 102932961 ps
CPU time 0.99 seconds
Started Apr 16 12:49:52 PM PDT 24
Finished Apr 16 12:49:56 PM PDT 24
Peak memory 228532 kb
Host smart-8493a25d-e52a-4ae0-82ed-d4070b32f0bc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425699640 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.1425699640
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.1975814417
Short name T209
Test name
Test status
Simulation time 118169753 ps
CPU time 0.71 seconds
Started Apr 16 12:50:14 PM PDT 24
Finished Apr 16 12:50:16 PM PDT 24
Peak memory 205108 kb
Host smart-32c1a744-e282-48fb-ba97-323ef8720365
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975814417 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.1975814417
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.2226832521
Short name T179
Test name
Test status
Simulation time 27582716 ps
CPU time 0.67 seconds
Started Apr 16 12:50:12 PM PDT 24
Finished Apr 16 12:50:14 PM PDT 24
Peak memory 205096 kb
Host smart-e443662d-964e-4284-a2bf-3712ad8d008b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226832521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.2226832521
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.942726996
Short name T120
Test name
Test status
Simulation time 15962625 ps
CPU time 0.69 seconds
Started Apr 16 12:50:13 PM PDT 24
Finished Apr 16 12:50:15 PM PDT 24
Peak memory 205000 kb
Host smart-3c37f8a2-a653-4070-b5e7-81c6ccadc902
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942726996 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.942726996
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.2256823982
Short name T148
Test name
Test status
Simulation time 32825211 ps
CPU time 0.72 seconds
Started Apr 16 12:50:11 PM PDT 24
Finished Apr 16 12:50:13 PM PDT 24
Peak memory 205064 kb
Host smart-8aa71642-eafe-44c5-8c7b-800dc2e4ac56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256823982 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.2256823982
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.458831383
Short name T70
Test name
Test status
Simulation time 40185693 ps
CPU time 0.71 seconds
Started Apr 16 12:50:16 PM PDT 24
Finished Apr 16 12:50:18 PM PDT 24
Peak memory 205132 kb
Host smart-ba308cc1-8c85-4a75-9f9b-760c7b956461
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458831383 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.458831383
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_stress_all.142705421
Short name T6
Test name
Test status
Simulation time 5660060312 ps
CPU time 5.33 seconds
Started Apr 16 12:50:17 PM PDT 24
Finished Apr 16 12:50:24 PM PDT 24
Peak memory 205396 kb
Host smart-d63ad9e5-ae70-4495-8789-fe6f44004d84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142705421 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.142705421
Directory /workspace/24.rv_dm_stress_all/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.4005302839
Short name T194
Test name
Test status
Simulation time 14984754 ps
CPU time 0.65 seconds
Started Apr 16 12:50:14 PM PDT 24
Finished Apr 16 12:50:16 PM PDT 24
Peak memory 205092 kb
Host smart-20eb958e-1bf4-40d8-9bdd-ac0ee800ca1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005302839 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.4005302839
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.2729135051
Short name T161
Test name
Test status
Simulation time 20172723 ps
CPU time 0.73 seconds
Started Apr 16 12:50:16 PM PDT 24
Finished Apr 16 12:50:18 PM PDT 24
Peak memory 205068 kb
Host smart-8881b847-807f-4737-b2a8-03e717aa6917
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729135051 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.2729135051
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.1760363945
Short name T157
Test name
Test status
Simulation time 48135142 ps
CPU time 0.7 seconds
Started Apr 16 12:50:12 PM PDT 24
Finished Apr 16 12:50:15 PM PDT 24
Peak memory 205100 kb
Host smart-28e978e4-2a6a-4a90-a887-e726660433dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760363945 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.1760363945
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.1205836609
Short name T24
Test name
Test status
Simulation time 20297939 ps
CPU time 0.69 seconds
Started Apr 16 12:50:09 PM PDT 24
Finished Apr 16 12:50:12 PM PDT 24
Peak memory 205072 kb
Host smart-b927a018-79a5-477e-a715-d683480689e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205836609 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.1205836609
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.327689880
Short name T195
Test name
Test status
Simulation time 18801854 ps
CPU time 0.69 seconds
Started Apr 16 12:50:10 PM PDT 24
Finished Apr 16 12:50:12 PM PDT 24
Peak memory 205028 kb
Host smart-c4f8391d-d986-4703-b57e-a0d10be6134b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327689880 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.327689880
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.3192673849
Short name T18
Test name
Test status
Simulation time 6620239265 ps
CPU time 28.35 seconds
Started Apr 16 12:49:51 PM PDT 24
Finished Apr 16 12:50:21 PM PDT 24
Peak memory 205524 kb
Host smart-40e79d45-1239-408c-ab08-25223ac795e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192673849 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.3192673849
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.2342888188
Short name T12
Test name
Test status
Simulation time 2849438370 ps
CPU time 9.94 seconds
Started Apr 16 12:49:52 PM PDT 24
Finished Apr 16 12:50:04 PM PDT 24
Peak memory 205500 kb
Host smart-b84d7951-4eec-4bf7-a247-2cc6c88d19db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342888188 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.2342888188
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.2500011554
Short name T236
Test name
Test status
Simulation time 1591553089 ps
CPU time 2.81 seconds
Started Apr 16 12:49:51 PM PDT 24
Finished Apr 16 12:49:57 PM PDT 24
Peak memory 205388 kb
Host smart-df9547fc-4299-4025-baa0-fc41ca66325f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2500011554 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.2500011554
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.1201822109
Short name T221
Test name
Test status
Simulation time 63443586 ps
CPU time 0.78 seconds
Started Apr 16 12:49:53 PM PDT 24
Finished Apr 16 12:49:57 PM PDT 24
Peak memory 204864 kb
Host smart-368560c7-b791-4975-9677-6c077cb92a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201822109 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.1201822109
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.2931179438
Short name T47
Test name
Test status
Simulation time 7357860473 ps
CPU time 20.07 seconds
Started Apr 16 12:49:50 PM PDT 24
Finished Apr 16 12:50:12 PM PDT 24
Peak memory 213688 kb
Host smart-fd02c57f-67d6-4873-bbe5-7a263a2eff21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931179438 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.2931179438
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.1320540156
Short name T43
Test name
Test status
Simulation time 265734513 ps
CPU time 1.74 seconds
Started Apr 16 12:49:52 PM PDT 24
Finished Apr 16 12:49:57 PM PDT 24
Peak memory 229252 kb
Host smart-7df13814-836f-48d5-8604-060d4878f1ea
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320540156 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.1320540156
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.1110922592
Short name T29
Test name
Test status
Simulation time 21589386 ps
CPU time 0.72 seconds
Started Apr 16 12:50:11 PM PDT 24
Finished Apr 16 12:50:14 PM PDT 24
Peak memory 205140 kb
Host smart-20c05cb7-86f8-479c-9aa8-f2c0240bcc16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110922592 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.1110922592
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.3339129084
Short name T162
Test name
Test status
Simulation time 45049035 ps
CPU time 0.69 seconds
Started Apr 16 12:50:12 PM PDT 24
Finished Apr 16 12:50:14 PM PDT 24
Peak memory 205120 kb
Host smart-294ef5a8-3204-4b24-b1d9-b321e426aede
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339129084 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.3339129084
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_stress_all.107215711
Short name T80
Test name
Test status
Simulation time 799721850 ps
CPU time 3.42 seconds
Started Apr 16 12:50:14 PM PDT 24
Finished Apr 16 12:50:19 PM PDT 24
Peak memory 205316 kb
Host smart-56773a55-d767-42d7-a8a9-6afa50d867db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107215711 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.107215711
Directory /workspace/31.rv_dm_stress_all/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.1448179685
Short name T167
Test name
Test status
Simulation time 26411701 ps
CPU time 0.72 seconds
Started Apr 16 12:50:14 PM PDT 24
Finished Apr 16 12:50:16 PM PDT 24
Peak memory 205104 kb
Host smart-a8b00e60-dfef-46c2-b54c-b1fed9e8623d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448179685 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.1448179685
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.302264382
Short name T166
Test name
Test status
Simulation time 44336925 ps
CPU time 0.7 seconds
Started Apr 16 12:50:18 PM PDT 24
Finished Apr 16 12:50:21 PM PDT 24
Peak memory 205120 kb
Host smart-3a69c1d7-f0ba-4213-8930-0e5a8ffbc346
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302264382 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.302264382
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.4086353452
Short name T153
Test name
Test status
Simulation time 30734376 ps
CPU time 0.68 seconds
Started Apr 16 12:50:13 PM PDT 24
Finished Apr 16 12:50:18 PM PDT 24
Peak memory 205120 kb
Host smart-666c2981-d069-4e49-89ea-dafa2be1f67c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086353452 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.4086353452
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.236471076
Short name T144
Test name
Test status
Simulation time 74408154 ps
CPU time 0.66 seconds
Started Apr 16 12:50:24 PM PDT 24
Finished Apr 16 12:50:26 PM PDT 24
Peak memory 205088 kb
Host smart-3036fa1d-92e0-4b5c-9933-9f79ef1a1928
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236471076 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.236471076
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.2786607869
Short name T123
Test name
Test status
Simulation time 44718650 ps
CPU time 0.7 seconds
Started Apr 16 12:50:16 PM PDT 24
Finished Apr 16 12:50:18 PM PDT 24
Peak memory 205044 kb
Host smart-bc558f76-ac5a-42b9-887b-93fa329836b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786607869 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.2786607869
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_stress_all.2747168951
Short name T28
Test name
Test status
Simulation time 1343530781 ps
CPU time 4.74 seconds
Started Apr 16 12:50:17 PM PDT 24
Finished Apr 16 12:50:24 PM PDT 24
Peak memory 205288 kb
Host smart-018dc5de-73d8-46b2-b3eb-84b4c2a4b10e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747168951 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.2747168951
Directory /workspace/36.rv_dm_stress_all/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.3664192797
Short name T25
Test name
Test status
Simulation time 28636456 ps
CPU time 0.7 seconds
Started Apr 16 12:50:24 PM PDT 24
Finished Apr 16 12:50:26 PM PDT 24
Peak memory 205044 kb
Host smart-c1ef5bf0-6614-42ad-8f28-c82f11cb9a2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664192797 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.3664192797
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.1889714744
Short name T119
Test name
Test status
Simulation time 118625714 ps
CPU time 0.73 seconds
Started Apr 16 12:50:20 PM PDT 24
Finished Apr 16 12:50:22 PM PDT 24
Peak memory 205040 kb
Host smart-10470361-db86-4b5c-b808-dd1be83572be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889714744 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.1889714744
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.1020220306
Short name T69
Test name
Test status
Simulation time 103179095 ps
CPU time 0.69 seconds
Started Apr 16 12:50:24 PM PDT 24
Finished Apr 16 12:50:26 PM PDT 24
Peak memory 205044 kb
Host smart-41ab0a7c-7cc0-4538-97b6-e0302020b85d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020220306 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.1020220306
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.3764040602
Short name T158
Test name
Test status
Simulation time 114544472 ps
CPU time 0.7 seconds
Started Apr 16 12:49:50 PM PDT 24
Finished Apr 16 12:49:52 PM PDT 24
Peak memory 205088 kb
Host smart-947a087e-db13-4641-8600-7a769961c506
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764040602 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.3764040602
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.4175331887
Short name T192
Test name
Test status
Simulation time 1826715355 ps
CPU time 5.04 seconds
Started Apr 16 12:49:53 PM PDT 24
Finished Apr 16 12:50:01 PM PDT 24
Peak memory 205468 kb
Host smart-76473385-fc66-4c02-bd60-9660d90e67c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175331887 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.4175331887
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.2295457900
Short name T3
Test name
Test status
Simulation time 1411963832 ps
CPU time 4.95 seconds
Started Apr 16 12:49:52 PM PDT 24
Finished Apr 16 12:50:00 PM PDT 24
Peak memory 205420 kb
Host smart-80dce65a-199b-4cbd-b493-013f941788cd
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2295457900 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.2295457900
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.3203914852
Short name T230
Test name
Test status
Simulation time 61829671 ps
CPU time 0.76 seconds
Started Apr 16 12:49:51 PM PDT 24
Finished Apr 16 12:49:54 PM PDT 24
Peak memory 204904 kb
Host smart-626f72ea-cb53-477c-97db-8bc219638238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203914852 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.3203914852
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.2954490301
Short name T214
Test name
Test status
Simulation time 1793207697 ps
CPU time 3.83 seconds
Started Apr 16 12:49:52 PM PDT 24
Finished Apr 16 12:49:58 PM PDT 24
Peak memory 205624 kb
Host smart-e1534b2a-59f9-4f2a-9a76-f8b85011c2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954490301 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.2954490301
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.701874374
Short name T22
Test name
Test status
Simulation time 113769952 ps
CPU time 1.34 seconds
Started Apr 16 12:49:54 PM PDT 24
Finished Apr 16 12:49:57 PM PDT 24
Peak memory 229360 kb
Host smart-78257ea3-a48b-4974-a457-06b7c604ca43
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701874374 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.701874374
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.3359322654
Short name T146
Test name
Test status
Simulation time 26937333 ps
CPU time 0.76 seconds
Started Apr 16 12:50:20 PM PDT 24
Finished Apr 16 12:50:22 PM PDT 24
Peak memory 204940 kb
Host smart-d68f3179-1140-40db-a5d9-6f5359c0a7a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359322654 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.3359322654
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/40.rv_dm_stress_all.3709950409
Short name T14
Test name
Test status
Simulation time 15454801848 ps
CPU time 8.95 seconds
Started Apr 16 12:50:25 PM PDT 24
Finished Apr 16 12:50:36 PM PDT 24
Peak memory 205432 kb
Host smart-de508bc5-7818-4af7-878d-2879cbd73636
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709950409 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.3709950409
Directory /workspace/40.rv_dm_stress_all/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.609158997
Short name T145
Test name
Test status
Simulation time 38979123 ps
CPU time 0.7 seconds
Started Apr 16 12:50:25 PM PDT 24
Finished Apr 16 12:50:28 PM PDT 24
Peak memory 205088 kb
Host smart-4b31351e-7ea2-438d-bbea-23be02170a49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609158997 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.609158997
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_stress_all.104647103
Short name T27
Test name
Test status
Simulation time 1718116890 ps
CPU time 5.59 seconds
Started Apr 16 12:50:30 PM PDT 24
Finished Apr 16 12:50:36 PM PDT 24
Peak memory 205168 kb
Host smart-4266cea7-fa3c-44ff-9889-6d0c2be92984
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104647103 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.104647103
Directory /workspace/41.rv_dm_stress_all/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.4227735747
Short name T30
Test name
Test status
Simulation time 16366784 ps
CPU time 0.72 seconds
Started Apr 16 12:50:24 PM PDT 24
Finished Apr 16 12:50:26 PM PDT 24
Peak memory 204412 kb
Host smart-3b0534fb-d959-40fb-8764-489ade093bcf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227735747 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.4227735747
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.134970969
Short name T232
Test name
Test status
Simulation time 30692952 ps
CPU time 0.71 seconds
Started Apr 16 12:50:20 PM PDT 24
Finished Apr 16 12:50:21 PM PDT 24
Peak memory 205092 kb
Host smart-b255ce84-64c3-40e2-9fb8-9184cdbe6ba1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134970969 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.134970969
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.1084757194
Short name T183
Test name
Test status
Simulation time 19213591 ps
CPU time 0.68 seconds
Started Apr 16 12:50:24 PM PDT 24
Finished Apr 16 12:50:26 PM PDT 24
Peak memory 205092 kb
Host smart-02616ac0-d5f6-4193-996c-487a66922cf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084757194 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.1084757194
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.1881463775
Short name T71
Test name
Test status
Simulation time 48153593 ps
CPU time 0.76 seconds
Started Apr 16 12:50:35 PM PDT 24
Finished Apr 16 12:50:37 PM PDT 24
Peak memory 205128 kb
Host smart-1c7ead1b-d788-4091-97b7-69ba0ad45224
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881463775 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.1881463775
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.2665426400
Short name T160
Test name
Test status
Simulation time 55380023 ps
CPU time 0.69 seconds
Started Apr 16 12:50:26 PM PDT 24
Finished Apr 16 12:50:28 PM PDT 24
Peak memory 205092 kb
Host smart-9e47a3dc-69e6-4bbb-ad94-d8519d5f7456
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665426400 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.2665426400
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_stress_all.2642722752
Short name T54
Test name
Test status
Simulation time 9220025114 ps
CPU time 9.7 seconds
Started Apr 16 12:50:16 PM PDT 24
Finished Apr 16 12:50:28 PM PDT 24
Peak memory 205432 kb
Host smart-16c88d06-7068-4351-864a-6ed98215334d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642722752 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.2642722752
Directory /workspace/47.rv_dm_stress_all/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.438719001
Short name T151
Test name
Test status
Simulation time 59748800 ps
CPU time 0.71 seconds
Started Apr 16 12:50:16 PM PDT 24
Finished Apr 16 12:50:19 PM PDT 24
Peak memory 205100 kb
Host smart-7fe4c55a-ab02-44fa-93d3-40ebb03958b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438719001 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.438719001
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.1384989144
Short name T217
Test name
Test status
Simulation time 93890654 ps
CPU time 0.67 seconds
Started Apr 16 12:50:25 PM PDT 24
Finished Apr 16 12:50:28 PM PDT 24
Peak memory 205096 kb
Host smart-f45d6868-db97-42a8-8e8c-712e0cf677a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384989144 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.1384989144
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.1733272278
Short name T149
Test name
Test status
Simulation time 46566935 ps
CPU time 0.73 seconds
Started Apr 16 12:49:56 PM PDT 24
Finished Apr 16 12:49:58 PM PDT 24
Peak memory 204284 kb
Host smart-42d1ba52-f183-409d-8c82-460b8479e628
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733272278 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.1733272278
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.515350476
Short name T175
Test name
Test status
Simulation time 3266114579 ps
CPU time 6.9 seconds
Started Apr 16 12:49:55 PM PDT 24
Finished Apr 16 12:50:04 PM PDT 24
Peak memory 213660 kb
Host smart-9b00915d-c689-4c5a-9d7a-396db56b48d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515350476 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.515350476
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.305682982
Short name T223
Test name
Test status
Simulation time 2312192995 ps
CPU time 7.88 seconds
Started Apr 16 12:49:52 PM PDT 24
Finished Apr 16 12:50:02 PM PDT 24
Peak memory 213764 kb
Host smart-ef32a3b9-792a-4bcf-ae75-d76fd205077a
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=305682982 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_tl
_access.305682982
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.3549628066
Short name T212
Test name
Test status
Simulation time 5110637371 ps
CPU time 7.52 seconds
Started Apr 16 12:49:53 PM PDT 24
Finished Apr 16 12:50:03 PM PDT 24
Peak memory 213704 kb
Host smart-66db6a60-aa87-4d8c-bc09-1792df895ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549628066 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.3549628066
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.3020374303
Short name T152
Test name
Test status
Simulation time 39784787 ps
CPU time 0.64 seconds
Started Apr 16 12:50:05 PM PDT 24
Finished Apr 16 12:50:07 PM PDT 24
Peak memory 205028 kb
Host smart-2609dbd9-4c04-4446-a48d-2b44b8bafdf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020374303 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.3020374303
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.724972201
Short name T38
Test name
Test status
Simulation time 3069167813 ps
CPU time 9.77 seconds
Started Apr 16 12:49:55 PM PDT 24
Finished Apr 16 12:50:07 PM PDT 24
Peak memory 204644 kb
Host smart-da71232d-395a-4263-bc04-c23b2684d22d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724972201 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.724972201
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.3368066893
Short name T218
Test name
Test status
Simulation time 14788629229 ps
CPU time 46.96 seconds
Started Apr 16 12:49:51 PM PDT 24
Finished Apr 16 12:50:41 PM PDT 24
Peak memory 213728 kb
Host smart-ee9b67b6-5d76-4fd0-bc3a-a6b78cc1797f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3368066893 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t
l_access.3368066893
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.814055147
Short name T231
Test name
Test status
Simulation time 7434960807 ps
CPU time 10.96 seconds
Started Apr 16 12:49:54 PM PDT 24
Finished Apr 16 12:50:07 PM PDT 24
Peak memory 205508 kb
Host smart-7021932b-6095-408a-9fca-6fe168a81c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814055147 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.814055147
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.2357111310
Short name T156
Test name
Test status
Simulation time 68251599 ps
CPU time 0.7 seconds
Started Apr 16 12:49:57 PM PDT 24
Finished Apr 16 12:49:58 PM PDT 24
Peak memory 205100 kb
Host smart-f8ddc87f-a348-4644-8440-bcf372ed1464
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357111310 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.2357111310
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.1204967875
Short name T228
Test name
Test status
Simulation time 19985333507 ps
CPU time 66.1 seconds
Started Apr 16 12:50:01 PM PDT 24
Finished Apr 16 12:51:08 PM PDT 24
Peak memory 213740 kb
Host smart-5370e071-0047-4e19-8c2f-521ba88d1958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204967875 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.1204967875
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.2947040567
Short name T226
Test name
Test status
Simulation time 5051014786 ps
CPU time 6.82 seconds
Started Apr 16 12:49:58 PM PDT 24
Finished Apr 16 12:50:06 PM PDT 24
Peak memory 213740 kb
Host smart-da12d2fd-b86e-4c60-8b04-5ac6554e9015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947040567 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.2947040567
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.2299755468
Short name T199
Test name
Test status
Simulation time 387629303 ps
CPU time 1.29 seconds
Started Apr 16 12:50:12 PM PDT 24
Finished Apr 16 12:50:15 PM PDT 24
Peak memory 205352 kb
Host smart-8036d023-8e8e-478f-bf5c-39c9cc796b03
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2299755468 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.2299755468
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.475942560
Short name T124
Test name
Test status
Simulation time 21498423 ps
CPU time 0.74 seconds
Started Apr 16 12:50:01 PM PDT 24
Finished Apr 16 12:50:02 PM PDT 24
Peak memory 205092 kb
Host smart-260c7585-8142-4031-acef-df76ec757565
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475942560 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.475942560
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.4238353376
Short name T229
Test name
Test status
Simulation time 8502269497 ps
CPU time 38.42 seconds
Started Apr 16 12:49:58 PM PDT 24
Finished Apr 16 12:50:38 PM PDT 24
Peak memory 216192 kb
Host smart-c7d4f1b6-367e-4832-89ed-a2650767734d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238353376 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.4238353376
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.4245312108
Short name T182
Test name
Test status
Simulation time 1175048454 ps
CPU time 1.99 seconds
Started Apr 16 12:50:12 PM PDT 24
Finished Apr 16 12:50:16 PM PDT 24
Peak memory 205296 kb
Host smart-13c9c59b-5877-4524-ab4c-2b87ccc7aa1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245312108 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.4245312108
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.651196914
Short name T178
Test name
Test status
Simulation time 1328547425 ps
CPU time 3.32 seconds
Started Apr 16 12:50:11 PM PDT 24
Finished Apr 16 12:50:16 PM PDT 24
Peak memory 205328 kb
Host smart-9218358c-1c04-4e51-bbbe-0cc6588a6ff1
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=651196914 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_tl
_access.651196914
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.2946213784
Short name T204
Test name
Test status
Simulation time 626266614 ps
CPU time 2.06 seconds
Started Apr 16 12:50:00 PM PDT 24
Finished Apr 16 12:50:03 PM PDT 24
Peak memory 205376 kb
Host smart-03b6840d-6cdf-44e2-8f17-f10f2418b790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946213784 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.2946213784
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.274529780
Short name T159
Test name
Test status
Simulation time 20033370 ps
CPU time 0.67 seconds
Started Apr 16 12:50:02 PM PDT 24
Finished Apr 16 12:50:04 PM PDT 24
Peak memory 205076 kb
Host smart-8b60efdc-3d39-48ad-bc54-08b327b86f06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274529780 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.274529780
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.928527459
Short name T201
Test name
Test status
Simulation time 1830086033 ps
CPU time 3.83 seconds
Started Apr 16 12:49:59 PM PDT 24
Finished Apr 16 12:50:04 PM PDT 24
Peak memory 205380 kb
Host smart-1a4743dd-6f8d-4b3b-993c-ae94e56728ab
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=928527459 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_tl
_access.928527459
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.2530891617
Short name T202
Test name
Test status
Simulation time 4693534992 ps
CPU time 12.89 seconds
Started Apr 16 12:50:01 PM PDT 24
Finished Apr 16 12:50:14 PM PDT 24
Peak memory 205496 kb
Host smart-1fad01bc-ddf2-40a1-9420-4952c8d92cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530891617 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.2530891617
Directory /workspace/9.rv_dm_sba_tl_access/latest
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