Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
79.72 93.86 81.18 87.69 73.08 82.50 98.52 41.19


Total test records in report: 307
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html
T255 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.1031168936 Apr 23 02:12:04 PM PDT 24 Apr 23 02:12:07 PM PDT 24 56277061 ps
T256 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.3035465968 Apr 23 02:12:00 PM PDT 24 Apr 23 02:12:02 PM PDT 24 54392509 ps
T257 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.576801283 Apr 23 02:12:00 PM PDT 24 Apr 23 02:12:03 PM PDT 24 100051164 ps
T258 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.20165825 Apr 23 02:11:56 PM PDT 24 Apr 23 02:11:58 PM PDT 24 134881924 ps
T259 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.4001284769 Apr 23 02:11:50 PM PDT 24 Apr 23 02:12:08 PM PDT 24 12584576878 ps
T260 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.2864330041 Apr 23 02:12:03 PM PDT 24 Apr 23 02:12:08 PM PDT 24 1324253893 ps
T261 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3451561193 Apr 23 02:11:47 PM PDT 24 Apr 23 02:12:15 PM PDT 24 579083604 ps
T262 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2773094235 Apr 23 02:11:55 PM PDT 24 Apr 23 02:11:57 PM PDT 24 53248335 ps
T263 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.3658951189 Apr 23 02:11:54 PM PDT 24 Apr 23 02:11:57 PM PDT 24 538629999 ps
T264 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.192793063 Apr 23 02:11:50 PM PDT 24 Apr 23 02:11:54 PM PDT 24 2234947514 ps
T265 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.1849357958 Apr 23 02:11:57 PM PDT 24 Apr 23 02:11:58 PM PDT 24 107832202 ps
T266 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.1153163751 Apr 23 02:11:50 PM PDT 24 Apr 23 02:11:52 PM PDT 24 70534705 ps
T267 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1435364461 Apr 23 02:11:47 PM PDT 24 Apr 23 02:11:52 PM PDT 24 1107417767 ps
T268 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1958705131 Apr 23 02:11:50 PM PDT 24 Apr 23 02:11:52 PM PDT 24 521769261 ps
T269 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2496193256 Apr 23 02:12:19 PM PDT 24 Apr 23 02:12:27 PM PDT 24 2991671448 ps
T270 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.1778293135 Apr 23 02:12:17 PM PDT 24 Apr 23 02:12:19 PM PDT 24 98910843 ps
T271 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.854914288 Apr 23 02:12:09 PM PDT 24 Apr 23 02:12:18 PM PDT 24 3379039285 ps
T272 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2772785392 Apr 23 02:12:13 PM PDT 24 Apr 23 02:12:16 PM PDT 24 155597482 ps
T273 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.1809316719 Apr 23 02:11:44 PM PDT 24 Apr 23 02:11:45 PM PDT 24 62032625 ps
T274 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2799703004 Apr 23 02:12:11 PM PDT 24 Apr 23 02:12:22 PM PDT 24 1151443662 ps
T275 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.1278906135 Apr 23 02:11:49 PM PDT 24 Apr 23 02:13:03 PM PDT 24 15175622079 ps
T276 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1090689067 Apr 23 02:11:51 PM PDT 24 Apr 23 02:12:25 PM PDT 24 8111486685 ps
T101 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.1740317291 Apr 23 02:12:11 PM PDT 24 Apr 23 02:12:14 PM PDT 24 86978770 ps
T277 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.744305147 Apr 23 02:11:50 PM PDT 24 Apr 23 02:11:52 PM PDT 24 523201303 ps
T278 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.3905230586 Apr 23 02:11:54 PM PDT 24 Apr 23 02:11:55 PM PDT 24 28380624 ps
T279 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.3404630611 Apr 23 02:11:52 PM PDT 24 Apr 23 02:11:54 PM PDT 24 606490751 ps
T280 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.1572339032 Apr 23 02:12:14 PM PDT 24 Apr 23 02:12:20 PM PDT 24 1389332586 ps
T281 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2327859537 Apr 23 02:11:57 PM PDT 24 Apr 23 02:11:59 PM PDT 24 47874909 ps
T282 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.929339679 Apr 23 02:12:13 PM PDT 24 Apr 23 02:12:17 PM PDT 24 133731560 ps
T102 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.4021876932 Apr 23 02:12:01 PM PDT 24 Apr 23 02:12:04 PM PDT 24 43400361 ps
T283 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.9590678 Apr 23 02:12:08 PM PDT 24 Apr 23 02:12:11 PM PDT 24 104389338 ps
T103 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.1446507455 Apr 23 02:12:07 PM PDT 24 Apr 23 02:12:15 PM PDT 24 410559612 ps
T284 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.2648559846 Apr 23 02:11:57 PM PDT 24 Apr 23 02:11:59 PM PDT 24 18210280 ps
T285 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2309159938 Apr 23 02:12:08 PM PDT 24 Apr 23 02:12:17 PM PDT 24 565394170 ps
T286 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.264372871 Apr 23 02:11:48 PM PDT 24 Apr 23 02:12:59 PM PDT 24 11829467101 ps
T287 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.2000531389 Apr 23 02:11:48 PM PDT 24 Apr 23 02:11:50 PM PDT 24 156830626 ps
T288 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.630045812 Apr 23 02:11:57 PM PDT 24 Apr 23 02:12:06 PM PDT 24 583213279 ps
T95 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.1654235820 Apr 23 02:11:49 PM PDT 24 Apr 23 02:11:53 PM PDT 24 773526089 ps
T289 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.995041142 Apr 23 02:12:12 PM PDT 24 Apr 23 02:12:15 PM PDT 24 48371911 ps
T290 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.141470293 Apr 23 02:12:13 PM PDT 24 Apr 23 02:12:17 PM PDT 24 1062551783 ps
T291 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.209799323 Apr 23 02:11:54 PM PDT 24 Apr 23 02:11:57 PM PDT 24 182896079 ps
T292 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.545595106 Apr 23 02:11:56 PM PDT 24 Apr 23 02:11:59 PM PDT 24 951087409 ps
T293 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3612112515 Apr 23 02:12:00 PM PDT 24 Apr 23 02:12:08 PM PDT 24 5408503122 ps
T294 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.3052158068 Apr 23 02:11:54 PM PDT 24 Apr 23 02:11:57 PM PDT 24 51886148 ps
T295 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.4087534179 Apr 23 02:11:49 PM PDT 24 Apr 23 02:11:54 PM PDT 24 1047456958 ps
T296 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.1692195040 Apr 23 02:11:51 PM PDT 24 Apr 23 02:12:00 PM PDT 24 873755457 ps
T297 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2325833792 Apr 23 02:11:57 PM PDT 24 Apr 23 02:12:03 PM PDT 24 409459495 ps
T298 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.438846158 Apr 23 02:11:51 PM PDT 24 Apr 23 02:11:53 PM PDT 24 273733984 ps
T299 /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.2148937752 Apr 23 02:12:21 PM PDT 24 Apr 23 02:12:26 PM PDT 24 726580779 ps
T300 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.793290942 Apr 23 02:11:59 PM PDT 24 Apr 23 02:12:00 PM PDT 24 131216792 ps
T301 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.2836335025 Apr 23 02:11:57 PM PDT 24 Apr 23 02:11:59 PM PDT 24 37265087 ps
T302 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.989812268 Apr 23 02:11:57 PM PDT 24 Apr 23 02:12:31 PM PDT 24 2536570274 ps
T303 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.352526323 Apr 23 02:11:48 PM PDT 24 Apr 23 02:12:19 PM PDT 24 19118926890 ps
T304 /workspace/coverage/cover_reg_top/35.rv_dm_tap_fsm_rand_reset.3601868026 Apr 23 02:12:23 PM PDT 24 Apr 23 02:12:37 PM PDT 24 14795558128 ps
T305 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.304107593 Apr 23 02:12:16 PM PDT 24 Apr 23 02:12:21 PM PDT 24 815337199 ps
T306 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.2760553446 Apr 23 02:12:13 PM PDT 24 Apr 23 02:12:18 PM PDT 24 111379788 ps
T307 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2521630787 Apr 23 02:11:57 PM PDT 24 Apr 23 02:12:02 PM PDT 24 506226940 ps

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.614248683
Short name T4
Test name
Test status
Simulation time 56655321 ps
CPU time 0.88 seconds
Started Apr 23 01:06:43 PM PDT 24
Finished Apr 23 01:06:44 PM PDT 24
Peak memory 204912 kb
Host smart-a7d2bdd1-a16f-46a1-8f73-28bb141b20b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614248683 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.614248683
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.2336400586
Short name T32
Test name
Test status
Simulation time 12254552506 ps
CPU time 27.44 seconds
Started Apr 23 01:08:05 PM PDT 24
Finished Apr 23 01:08:33 PM PDT 24
Peak memory 213524 kb
Host smart-4268df07-8b3e-477f-bbe7-8b556993e3e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336400586 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.2336400586
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/30.rv_dm_tap_fsm_rand_reset.775558604
Short name T42
Test name
Test status
Simulation time 12947265505 ps
CPU time 43.5 seconds
Started Apr 23 02:12:23 PM PDT 24
Finished Apr 23 02:13:08 PM PDT 24
Peak memory 228992 kb
Host smart-f102c748-f5f9-4806-b914-fe0fa86295d5
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775558604 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 30.rv_dm_tap_fsm_rand_reset.775558604
Directory /workspace/30.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.613587614
Short name T40
Test name
Test status
Simulation time 59180360 ps
CPU time 0.71 seconds
Started Apr 23 01:07:44 PM PDT 24
Finished Apr 23 01:07:45 PM PDT 24
Peak memory 204936 kb
Host smart-bfb804ae-d836-4da3-8bb6-8f3a262e3f15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613587614 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.613587614
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_stress_all.2195274648
Short name T10
Test name
Test status
Simulation time 5129163782 ps
CPU time 17.37 seconds
Started Apr 23 01:08:26 PM PDT 24
Finished Apr 23 01:08:44 PM PDT 24
Peak memory 205368 kb
Host smart-9be2ac20-d6ff-43b2-95fa-6eed8b0bd1eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195274648 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.2195274648
Directory /workspace/34.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3260189917
Short name T77
Test name
Test status
Simulation time 1012263755 ps
CPU time 10.08 seconds
Started Apr 23 02:11:59 PM PDT 24
Finished Apr 23 02:12:10 PM PDT 24
Peak memory 213032 kb
Host smart-5e49f08f-061a-4456-8a65-0bb6776bdf7e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260189917 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.3260189917
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.1755051131
Short name T23
Test name
Test status
Simulation time 1845065887 ps
CPU time 4.32 seconds
Started Apr 23 01:06:37 PM PDT 24
Finished Apr 23 01:06:42 PM PDT 24
Peak memory 205164 kb
Host smart-a7ef9512-b8e6-44ad-9af3-cae918479b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755051131 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.1755051131
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/24.rv_dm_stress_all.1320841334
Short name T36
Test name
Test status
Simulation time 1630945580 ps
CPU time 5.47 seconds
Started Apr 23 01:08:16 PM PDT 24
Finished Apr 23 01:08:22 PM PDT 24
Peak memory 205144 kb
Host smart-357074ae-a752-46d5-bbb9-9c0998d68874
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320841334 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.1320841334
Directory /workspace/24.rv_dm_stress_all/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.1231312211
Short name T15
Test name
Test status
Simulation time 363909488 ps
CPU time 1.53 seconds
Started Apr 23 01:07:05 PM PDT 24
Finished Apr 23 01:07:07 PM PDT 24
Peak memory 205120 kb
Host smart-1f8c361a-3871-45db-a285-8018e7581c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231312211 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.1231312211
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.2886986581
Short name T83
Test name
Test status
Simulation time 2268651254 ps
CPU time 4.03 seconds
Started Apr 23 02:12:00 PM PDT 24
Finished Apr 23 02:12:04 PM PDT 24
Peak memory 204912 kb
Host smart-5391f57e-15e6-4b13-91ed-f8530792802e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886986581 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.2886986581
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.3313008222
Short name T37
Test name
Test status
Simulation time 175517393 ps
CPU time 1 seconds
Started Apr 23 01:07:22 PM PDT 24
Finished Apr 23 01:07:24 PM PDT 24
Peak memory 237436 kb
Host smart-309f1d1d-276b-42a0-bb89-5928d2a44a0b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313008222 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.3313008222
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.2456636018
Short name T61
Test name
Test status
Simulation time 2285771933 ps
CPU time 2.88 seconds
Started Apr 23 01:06:35 PM PDT 24
Finished Apr 23 01:06:39 PM PDT 24
Peak memory 205244 kb
Host smart-16bf5db7-953f-45a2-b438-31331163b834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456636018 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.2456636018
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1088251891
Short name T121
Test name
Test status
Simulation time 1940147406 ps
CPU time 19.8 seconds
Started Apr 23 02:11:54 PM PDT 24
Finished Apr 23 02:12:14 PM PDT 24
Peak memory 221144 kb
Host smart-8b0ccde9-5d56-45d5-9868-779f553371a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088251891 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.1088251891
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.2720606954
Short name T98
Test name
Test status
Simulation time 5608794066 ps
CPU time 55.18 seconds
Started Apr 23 02:11:56 PM PDT 24
Finished Apr 23 02:12:52 PM PDT 24
Peak memory 205008 kb
Host smart-85ee2f4e-db4b-4fc1-96ab-a08911f7ec8c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720606954 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.2720606954
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.4071817694
Short name T28
Test name
Test status
Simulation time 27117820 ps
CPU time 0.81 seconds
Started Apr 23 01:06:57 PM PDT 24
Finished Apr 23 01:06:59 PM PDT 24
Peak memory 204972 kb
Host smart-cbb4363b-3b1c-4475-9bbe-6bdc1876a44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071817694 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.4071817694
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3187578013
Short name T64
Test name
Test status
Simulation time 110887892 ps
CPU time 0.79 seconds
Started Apr 23 02:11:43 PM PDT 24
Finished Apr 23 02:11:44 PM PDT 24
Peak memory 204532 kb
Host smart-8beec27c-39ef-4f1e-973c-c5ee52a49141
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187578013 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.3187578013
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.109048023
Short name T18
Test name
Test status
Simulation time 99221303 ps
CPU time 0.81 seconds
Started Apr 23 01:06:56 PM PDT 24
Finished Apr 23 01:06:57 PM PDT 24
Peak memory 213176 kb
Host smart-6fb83224-aaf3-485b-ad1b-fbd8e0991933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109048023 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.109048023
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.2798300761
Short name T13
Test name
Test status
Simulation time 194955404 ps
CPU time 0.81 seconds
Started Apr 23 01:06:40 PM PDT 24
Finished Apr 23 01:06:42 PM PDT 24
Peak memory 204940 kb
Host smart-2e2b297f-ff80-486c-8257-4b112d9e443a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798300761 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.2798300761
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.1740317291
Short name T101
Test name
Test status
Simulation time 86978770 ps
CPU time 1.49 seconds
Started Apr 23 02:12:11 PM PDT 24
Finished Apr 23 02:12:14 PM PDT 24
Peak memory 212984 kb
Host smart-0964fee4-ceb9-4e52-89f7-9ef660e87519
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740317291 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.1740317291
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.3386798400
Short name T22
Test name
Test status
Simulation time 198598983 ps
CPU time 1.49 seconds
Started Apr 23 01:06:52 PM PDT 24
Finished Apr 23 01:06:54 PM PDT 24
Peak memory 205120 kb
Host smart-b57fc8fd-d26e-4e62-93de-ff19792e9e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386798400 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.3386798400
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.4242029700
Short name T7
Test name
Test status
Simulation time 54561643 ps
CPU time 0.87 seconds
Started Apr 23 01:06:55 PM PDT 24
Finished Apr 23 01:06:57 PM PDT 24
Peak memory 204960 kb
Host smart-cbb9a9a7-ad45-4ab5-b339-b154bdf5eb29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242029700 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.4242029700
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1700303086
Short name T125
Test name
Test status
Simulation time 264407784 ps
CPU time 8.2 seconds
Started Apr 23 02:12:10 PM PDT 24
Finished Apr 23 02:12:19 PM PDT 24
Peak memory 221048 kb
Host smart-03773d49-de3a-4224-8dfc-54faa096e8a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700303086 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.1
700303086
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.4014556950
Short name T78
Test name
Test status
Simulation time 2045408719 ps
CPU time 3.73 seconds
Started Apr 23 02:11:55 PM PDT 24
Finished Apr 23 02:12:00 PM PDT 24
Peak memory 217340 kb
Host smart-1a4a0a1d-9e24-49e4-bf02-8e0a4ac222eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014556950 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.4014556950
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.3662783278
Short name T19
Test name
Test status
Simulation time 26554815 ps
CPU time 0.72 seconds
Started Apr 23 01:07:51 PM PDT 24
Finished Apr 23 01:07:53 PM PDT 24
Peak memory 204924 kb
Host smart-edc06250-fe18-483d-a91c-b46315e6c552
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662783278 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.3662783278
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2807200960
Short name T92
Test name
Test status
Simulation time 2316817308 ps
CPU time 3.22 seconds
Started Apr 23 02:11:43 PM PDT 24
Finished Apr 23 02:11:47 PM PDT 24
Peak memory 204936 kb
Host smart-c27c4576-c298-4405-9d74-a08bdb9cf6f0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807200960 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.2807200960
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3297019200
Short name T126
Test name
Test status
Simulation time 1209922685 ps
CPU time 18.7 seconds
Started Apr 23 02:12:13 PM PDT 24
Finished Apr 23 02:12:34 PM PDT 24
Peak memory 213012 kb
Host smart-03ed0b2a-ca58-42cd-bde3-f8b59a97dddb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297019200 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.3
297019200
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.2555086666
Short name T9
Test name
Test status
Simulation time 948684537 ps
CPU time 1.34 seconds
Started Apr 23 01:06:46 PM PDT 24
Finished Apr 23 01:06:48 PM PDT 24
Peak memory 204848 kb
Host smart-66888ba5-c7b3-4adc-b5f4-adfd91d8e9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555086666 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.2555086666
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.3367587110
Short name T14
Test name
Test status
Simulation time 2883574614 ps
CPU time 3.57 seconds
Started Apr 23 01:07:05 PM PDT 24
Finished Apr 23 01:07:09 PM PDT 24
Peak memory 205252 kb
Host smart-f91c992c-2f0b-4daf-a67f-96d4393868b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367587110 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.3367587110
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.4021876932
Short name T102
Test name
Test status
Simulation time 43400361 ps
CPU time 2.17 seconds
Started Apr 23 02:12:01 PM PDT 24
Finished Apr 23 02:12:04 PM PDT 24
Peak memory 212988 kb
Host smart-2abd4063-c3fb-4ebd-85bc-06115c4d52d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021876932 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.4021876932
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.929339679
Short name T282
Test name
Test status
Simulation time 133731560 ps
CPU time 2.45 seconds
Started Apr 23 02:12:13 PM PDT 24
Finished Apr 23 02:12:17 PM PDT 24
Peak memory 213084 kb
Host smart-a83c224d-8940-40ea-b51b-8b53974282b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929339679 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.929339679
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3451561193
Short name T261
Test name
Test status
Simulation time 579083604 ps
CPU time 28.05 seconds
Started Apr 23 02:11:47 PM PDT 24
Finished Apr 23 02:12:15 PM PDT 24
Peak memory 204836 kb
Host smart-cd3f991b-3bc4-4428-8ee7-98b414c09631
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451561193 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.3451561193
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.1278906135
Short name T275
Test name
Test status
Simulation time 15175622079 ps
CPU time 72.43 seconds
Started Apr 23 02:11:49 PM PDT 24
Finished Apr 23 02:13:03 PM PDT 24
Peak memory 213124 kb
Host smart-dd985f5d-0378-46a9-9373-fd41d1612b49
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278906135 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.1278906135
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.1153163751
Short name T266
Test name
Test status
Simulation time 70534705 ps
CPU time 1.57 seconds
Started Apr 23 02:11:50 PM PDT 24
Finished Apr 23 02:11:52 PM PDT 24
Peak memory 212948 kb
Host smart-2960e4ec-85af-4d70-b45f-254d74feb3b2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153163751 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.1153163751
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3191075567
Short name T116
Test name
Test status
Simulation time 1172901299 ps
CPU time 5.17 seconds
Started Apr 23 02:11:54 PM PDT 24
Finished Apr 23 02:12:00 PM PDT 24
Peak memory 218852 kb
Host smart-babbe474-82ee-4716-8129-6a96a7475251
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191075567 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.3191075567
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2773094235
Short name T262
Test name
Test status
Simulation time 53248335 ps
CPU time 1.48 seconds
Started Apr 23 02:11:55 PM PDT 24
Finished Apr 23 02:11:57 PM PDT 24
Peak memory 212940 kb
Host smart-847e5521-5594-4ae8-8a23-23ff2d68a951
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773094235 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.2773094235
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1840433630
Short name T179
Test name
Test status
Simulation time 22849827632 ps
CPU time 28.36 seconds
Started Apr 23 02:11:47 PM PDT 24
Finished Apr 23 02:12:16 PM PDT 24
Peak memory 204776 kb
Host smart-ee51b725-1af9-4d78-badf-ed63c1753262
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840433630 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.1840433630
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1678674517
Short name T201
Test name
Test status
Simulation time 20657835394 ps
CPU time 29.45 seconds
Started Apr 23 02:11:46 PM PDT 24
Finished Apr 23 02:12:16 PM PDT 24
Peak memory 204872 kb
Host smart-e46866a7-7105-4b28-9ca7-3d83c2a2c0c4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678674517 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_bit_bash.1678674517
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.1521178285
Short name T169
Test name
Test status
Simulation time 766283596 ps
CPU time 2.36 seconds
Started Apr 23 02:11:44 PM PDT 24
Finished Apr 23 02:11:47 PM PDT 24
Peak memory 204684 kb
Host smart-23b8e09e-d8c8-4ae4-978f-180951760f7d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521178285 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.1
521178285
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.1809316719
Short name T273
Test name
Test status
Simulation time 62032625 ps
CPU time 0.82 seconds
Started Apr 23 02:11:44 PM PDT 24
Finished Apr 23 02:11:45 PM PDT 24
Peak memory 204492 kb
Host smart-f59c2e8d-6b6b-4ce4-8146-742aff5ac9bb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809316719 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.1809316719
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1435364461
Short name T267
Test name
Test status
Simulation time 1107417767 ps
CPU time 4.22 seconds
Started Apr 23 02:11:47 PM PDT 24
Finished Apr 23 02:11:52 PM PDT 24
Peak memory 204680 kb
Host smart-8bda05b8-60a7-41ae-a152-011c0d6bbe73
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435364461 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.1435364461
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3731328948
Short name T244
Test name
Test status
Simulation time 141095320 ps
CPU time 0.71 seconds
Started Apr 23 02:11:42 PM PDT 24
Finished Apr 23 02:11:44 PM PDT 24
Peak memory 204428 kb
Host smart-e9821a5a-9c3c-4aee-95ac-9acaeda1dc33
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731328948 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.3
731328948
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.3745884042
Short name T174
Test name
Test status
Simulation time 35485941 ps
CPU time 0.67 seconds
Started Apr 23 02:11:45 PM PDT 24
Finished Apr 23 02:11:46 PM PDT 24
Peak memory 203860 kb
Host smart-3be96ef8-8818-4555-ba4a-4402f8f35353
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745884042 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.3745884042
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.1683401523
Short name T222
Test name
Test status
Simulation time 48524158 ps
CPU time 0.66 seconds
Started Apr 23 02:11:51 PM PDT 24
Finished Apr 23 02:11:52 PM PDT 24
Peak memory 204292 kb
Host smart-eb7ef846-b83b-4a1d-8a4f-5ae8e95f04a1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683401523 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.1683401523
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.843123421
Short name T235
Test name
Test status
Simulation time 81196933 ps
CPU time 3.38 seconds
Started Apr 23 02:11:47 PM PDT 24
Finished Apr 23 02:11:50 PM PDT 24
Peak memory 204788 kb
Host smart-e615f31e-ee0a-4382-8013-7813d8931474
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843123421 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_c
sr_outstanding.843123421
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.3593322585
Short name T211
Test name
Test status
Simulation time 237808237 ps
CPU time 5.03 seconds
Started Apr 23 02:11:48 PM PDT 24
Finished Apr 23 02:11:54 PM PDT 24
Peak memory 213124 kb
Host smart-f899f181-25d3-4739-83f3-e3283c19b026
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593322585 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.3593322585
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.1385196827
Short name T123
Test name
Test status
Simulation time 897767283 ps
CPU time 8.38 seconds
Started Apr 23 02:11:48 PM PDT 24
Finished Apr 23 02:11:57 PM PDT 24
Peak memory 221040 kb
Host smart-6a76e3c7-5322-453a-8bf2-64b58b323ffd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385196827 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.1385196827
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.2085752400
Short name T239
Test name
Test status
Simulation time 31065484534 ps
CPU time 76.94 seconds
Started Apr 23 02:11:54 PM PDT 24
Finished Apr 23 02:13:12 PM PDT 24
Peak memory 213196 kb
Host smart-97f26499-fec8-4de2-a313-f70a19be4967
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085752400 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.2085752400
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.989812268
Short name T302
Test name
Test status
Simulation time 2536570274 ps
CPU time 33.2 seconds
Started Apr 23 02:11:57 PM PDT 24
Finished Apr 23 02:12:31 PM PDT 24
Peak memory 204876 kb
Host smart-68a8dc03-f1b7-49f7-ba09-c2abc12410c5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989812268 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.989812268
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.3681696062
Short name T196
Test name
Test status
Simulation time 518765448 ps
CPU time 1.55 seconds
Started Apr 23 02:11:48 PM PDT 24
Finished Apr 23 02:11:50 PM PDT 24
Peak memory 212944 kb
Host smart-8b7f79c9-ec33-4568-859a-0378fdaf1aaf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681696062 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.3681696062
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2994723668
Short name T105
Test name
Test status
Simulation time 329955218 ps
CPU time 2.38 seconds
Started Apr 23 02:11:51 PM PDT 24
Finished Apr 23 02:11:54 PM PDT 24
Peak memory 212852 kb
Host smart-2b4a89dc-2adf-430e-b3d1-cf0239f6e4c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994723668 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.2994723668
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2001926992
Short name T202
Test name
Test status
Simulation time 3807317396 ps
CPU time 7.23 seconds
Started Apr 23 02:11:55 PM PDT 24
Finished Apr 23 02:12:02 PM PDT 24
Peak memory 204780 kb
Host smart-d52dd282-9e45-47c1-adb5-5b79d0451b3c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001926992 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.2001926992
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.352526323
Short name T303
Test name
Test status
Simulation time 19118926890 ps
CPU time 30.06 seconds
Started Apr 23 02:11:48 PM PDT 24
Finished Apr 23 02:12:19 PM PDT 24
Peak memory 204824 kb
Host smart-f96385c0-4b3c-4943-8ee9-857ddccd86a2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352526323 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr
_bit_bash.352526323
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1676663693
Short name T171
Test name
Test status
Simulation time 1605984442 ps
CPU time 1.43 seconds
Started Apr 23 02:11:47 PM PDT 24
Finished Apr 23 02:11:49 PM PDT 24
Peak memory 204744 kb
Host smart-f191e688-8b52-4834-8019-6bb658265804
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676663693 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.1676663693
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.3514670839
Short name T175
Test name
Test status
Simulation time 416662645 ps
CPU time 0.96 seconds
Started Apr 23 02:11:49 PM PDT 24
Finished Apr 23 02:11:51 PM PDT 24
Peak memory 204620 kb
Host smart-b45a63ff-6c2e-496a-910e-489b84c4d3ce
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514670839 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.3
514670839
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.973388339
Short name T67
Test name
Test status
Simulation time 102687609 ps
CPU time 0.74 seconds
Started Apr 23 02:11:51 PM PDT 24
Finished Apr 23 02:11:52 PM PDT 24
Peak memory 204540 kb
Host smart-a4caa618-b8fd-43b8-92bb-ec7f0205c917
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973388339 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_aliasing.973388339
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.4087534179
Short name T295
Test name
Test status
Simulation time 1047456958 ps
CPU time 4.52 seconds
Started Apr 23 02:11:49 PM PDT 24
Finished Apr 23 02:11:54 PM PDT 24
Peak memory 204608 kb
Host smart-49504742-9b9d-4053-95fc-13b20daec075
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087534179 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.4087534179
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.3315048732
Short name T227
Test name
Test status
Simulation time 90687940 ps
CPU time 0.8 seconds
Started Apr 23 02:11:47 PM PDT 24
Finished Apr 23 02:11:49 PM PDT 24
Peak memory 204488 kb
Host smart-7c17855d-9bde-4b8a-b2d7-6893d9cebd27
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315048732 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.3315048732
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.2000531389
Short name T287
Test name
Test status
Simulation time 156830626 ps
CPU time 0.88 seconds
Started Apr 23 02:11:48 PM PDT 24
Finished Apr 23 02:11:50 PM PDT 24
Peak memory 204440 kb
Host smart-9c44e21b-e89a-467c-90c5-40bfb95579b1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000531389 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.2
000531389
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.192894551
Short name T212
Test name
Test status
Simulation time 43299267 ps
CPU time 0.67 seconds
Started Apr 23 02:11:47 PM PDT 24
Finished Apr 23 02:11:49 PM PDT 24
Peak memory 204388 kb
Host smart-448a00fb-f083-4b4e-a486-282474a61075
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192894551 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_part
ial_access.192894551
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.2083890439
Short name T214
Test name
Test status
Simulation time 46786842 ps
CPU time 0.68 seconds
Started Apr 23 02:11:49 PM PDT 24
Finished Apr 23 02:11:50 PM PDT 24
Peak memory 204472 kb
Host smart-8e51bb48-baf2-41ed-ae7a-bbde751889fd
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083890439 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.2083890439
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.1181658482
Short name T86
Test name
Test status
Simulation time 3317028796 ps
CPU time 8.45 seconds
Started Apr 23 02:11:50 PM PDT 24
Finished Apr 23 02:12:00 PM PDT 24
Peak memory 204872 kb
Host smart-ab876437-f2bf-4378-b919-dffedaef4ac6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181658482 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_
csr_outstanding.1181658482
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1009534187
Short name T206
Test name
Test status
Simulation time 421748018 ps
CPU time 4.79 seconds
Started Apr 23 02:11:47 PM PDT 24
Finished Apr 23 02:11:52 PM PDT 24
Peak memory 212456 kb
Host smart-1844fa10-3ed1-4625-b711-637dd20941ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009534187 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.1009534187
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.1692195040
Short name T296
Test name
Test status
Simulation time 873755457 ps
CPU time 8.65 seconds
Started Apr 23 02:11:51 PM PDT 24
Finished Apr 23 02:12:00 PM PDT 24
Peak memory 221048 kb
Host smart-97451f9a-b0cb-45fb-8e15-1801c166b31d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692195040 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.1692195040
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.2864330041
Short name T260
Test name
Test status
Simulation time 1324253893 ps
CPU time 5.3 seconds
Started Apr 23 02:12:03 PM PDT 24
Finished Apr 23 02:12:08 PM PDT 24
Peak memory 221092 kb
Host smart-cb68b6aa-c5ea-4d3a-9b64-c5734fa3b8f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864330041 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.2864330041
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.3035465968
Short name T256
Test name
Test status
Simulation time 54392509 ps
CPU time 1.58 seconds
Started Apr 23 02:12:00 PM PDT 24
Finished Apr 23 02:12:02 PM PDT 24
Peak memory 212924 kb
Host smart-baaff49f-26ad-461e-96b4-cd29c3673ee5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035465968 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.3035465968
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3744767494
Short name T205
Test name
Test status
Simulation time 741921692 ps
CPU time 2.95 seconds
Started Apr 23 02:12:03 PM PDT 24
Finished Apr 23 02:12:06 PM PDT 24
Peak memory 204668 kb
Host smart-55c3b490-07d0-489a-9b94-97b3e6d911b1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744767494 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
3744767494
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1532754632
Short name T253
Test name
Test status
Simulation time 85890468 ps
CPU time 0.68 seconds
Started Apr 23 02:12:01 PM PDT 24
Finished Apr 23 02:12:02 PM PDT 24
Peak memory 204448 kb
Host smart-68f9f527-93a0-486d-8c9f-b59153574bfa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532754632 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
1532754632
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.1446507455
Short name T103
Test name
Test status
Simulation time 410559612 ps
CPU time 7.34 seconds
Started Apr 23 02:12:07 PM PDT 24
Finished Apr 23 02:12:15 PM PDT 24
Peak memory 204864 kb
Host smart-08bbcbc4-408e-49b6-8e9a-53002831159a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446507455 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same
_csr_outstanding.1446507455
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3586639342
Short name T224
Test name
Test status
Simulation time 95160613 ps
CPU time 2.83 seconds
Started Apr 23 02:12:02 PM PDT 24
Finished Apr 23 02:12:06 PM PDT 24
Peak memory 213084 kb
Host smart-6c1a032a-7dfc-4f25-bfcb-d04181d7c822
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586639342 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.3586639342
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1251635820
Short name T127
Test name
Test status
Simulation time 2608906920 ps
CPU time 18.73 seconds
Started Apr 23 02:12:01 PM PDT 24
Finished Apr 23 02:12:20 PM PDT 24
Peak memory 221208 kb
Host smart-eac31f32-74a7-4bf0-a5e7-9a8e017d04ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251635820 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.1
251635820
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.240249427
Short name T43
Test name
Test status
Simulation time 87091553 ps
CPU time 2.43 seconds
Started Apr 23 02:12:08 PM PDT 24
Finished Apr 23 02:12:11 PM PDT 24
Peak memory 216620 kb
Host smart-eaf2f74a-c539-4dbf-83de-b02c32269cff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240249427 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.240249427
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.1031168936
Short name T255
Test name
Test status
Simulation time 56277061 ps
CPU time 2.29 seconds
Started Apr 23 02:12:04 PM PDT 24
Finished Apr 23 02:12:07 PM PDT 24
Peak memory 218896 kb
Host smart-8154f85a-6c5b-4248-845b-9634d539f5ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031168936 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.1031168936
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.840584068
Short name T166
Test name
Test status
Simulation time 355762637 ps
CPU time 1.39 seconds
Started Apr 23 02:12:00 PM PDT 24
Finished Apr 23 02:12:02 PM PDT 24
Peak memory 204660 kb
Host smart-ed734ae0-a9ee-40da-ab95-aa38f93bc114
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840584068 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.840584068
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.2001889571
Short name T195
Test name
Test status
Simulation time 40881776 ps
CPU time 0.73 seconds
Started Apr 23 02:12:02 PM PDT 24
Finished Apr 23 02:12:04 PM PDT 24
Peak memory 204428 kb
Host smart-dfb26e25-5fda-4f18-988d-f2cb7fef572e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001889571 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.
2001889571
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.260523292
Short name T96
Test name
Test status
Simulation time 314785215 ps
CPU time 6.6 seconds
Started Apr 23 02:12:05 PM PDT 24
Finished Apr 23 02:12:12 PM PDT 24
Peak memory 204816 kb
Host smart-7c425ec3-3251-4c1d-ab24-7467a056cb1d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260523292 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same_
csr_outstanding.260523292
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.3697499912
Short name T69
Test name
Test status
Simulation time 138757811 ps
CPU time 4.13 seconds
Started Apr 23 02:12:10 PM PDT 24
Finished Apr 23 02:12:15 PM PDT 24
Peak memory 213120 kb
Host smart-af4ae41c-b71b-4d94-8aa1-0d599655c9c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697499912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.3697499912
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.4249471331
Short name T230
Test name
Test status
Simulation time 667987727 ps
CPU time 8.28 seconds
Started Apr 23 02:12:06 PM PDT 24
Finished Apr 23 02:12:15 PM PDT 24
Peak memory 221124 kb
Host smart-4a103fd4-4379-4840-b983-bb60ed8900d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249471331 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.4
249471331
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.854914288
Short name T271
Test name
Test status
Simulation time 3379039285 ps
CPU time 9.18 seconds
Started Apr 23 02:12:09 PM PDT 24
Finished Apr 23 02:12:18 PM PDT 24
Peak memory 216496 kb
Host smart-4092b5db-dd79-4ab0-b1f7-7a710ae614f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854914288 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.854914288
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.1902284621
Short name T89
Test name
Test status
Simulation time 50582474 ps
CPU time 1.43 seconds
Started Apr 23 02:12:07 PM PDT 24
Finished Apr 23 02:12:09 PM PDT 24
Peak memory 212868 kb
Host smart-77b55016-37f6-4370-962c-911577542f99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902284621 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.1902284621
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1704775542
Short name T185
Test name
Test status
Simulation time 289802068 ps
CPU time 1.63 seconds
Started Apr 23 02:12:04 PM PDT 24
Finished Apr 23 02:12:06 PM PDT 24
Peak memory 204632 kb
Host smart-47de9b15-432e-466b-b3d4-8f5fb61abe62
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704775542 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
1704775542
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.2209141474
Short name T180
Test name
Test status
Simulation time 79796115 ps
CPU time 0.69 seconds
Started Apr 23 02:12:04 PM PDT 24
Finished Apr 23 02:12:05 PM PDT 24
Peak memory 204476 kb
Host smart-4af6652f-b2d7-4dde-85ab-0394568eed8d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209141474 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
2209141474
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1823654866
Short name T85
Test name
Test status
Simulation time 392411301 ps
CPU time 6.31 seconds
Started Apr 23 02:12:07 PM PDT 24
Finished Apr 23 02:12:14 PM PDT 24
Peak memory 204784 kb
Host smart-89755c65-0279-4b03-9aee-fb5689768740
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823654866 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.1823654866
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tap_fsm_rand_reset.3966192384
Short name T187
Test name
Test status
Simulation time 18656675902 ps
CPU time 11.81 seconds
Started Apr 23 02:12:04 PM PDT 24
Finished Apr 23 02:12:16 PM PDT 24
Peak memory 220604 kb
Host smart-0127d80e-e948-4e84-a865-a4331203476c
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966192384 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rv_dm_tap_fsm_rand_reset.3966192384
Directory /workspace/12.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.969501433
Short name T190
Test name
Test status
Simulation time 206530502 ps
CPU time 2.31 seconds
Started Apr 23 02:12:09 PM PDT 24
Finished Apr 23 02:12:12 PM PDT 24
Peak memory 217852 kb
Host smart-69b0eff2-071a-496e-9da1-ea7e1a51fbf9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969501433 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.969501433
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.995041142
Short name T289
Test name
Test status
Simulation time 48371911 ps
CPU time 1.44 seconds
Started Apr 23 02:12:12 PM PDT 24
Finished Apr 23 02:12:15 PM PDT 24
Peak memory 212916 kb
Host smart-42c40f97-454f-4b1e-9638-b751790b0fb5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995041142 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.995041142
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.807375320
Short name T173
Test name
Test status
Simulation time 455228059 ps
CPU time 1.9 seconds
Started Apr 23 02:12:12 PM PDT 24
Finished Apr 23 02:12:15 PM PDT 24
Peak memory 204668 kb
Host smart-6047e99c-04c3-4d6c-84b2-53bca8778eaa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807375320 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.807375320
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3589805181
Short name T231
Test name
Test status
Simulation time 50728271 ps
CPU time 0.73 seconds
Started Apr 23 02:12:07 PM PDT 24
Finished Apr 23 02:12:09 PM PDT 24
Peak memory 204508 kb
Host smart-0ecef014-ebea-4b17-9cc1-de2f481b7ee6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589805181 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
3589805181
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2309159938
Short name T285
Test name
Test status
Simulation time 565394170 ps
CPU time 7.71 seconds
Started Apr 23 02:12:08 PM PDT 24
Finished Apr 23 02:12:17 PM PDT 24
Peak memory 204836 kb
Host smart-44bdc651-7512-4d2b-a469-252c1f2108c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309159938 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.2309159938
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.9590678
Short name T283
Test name
Test status
Simulation time 104389338 ps
CPU time 2.21 seconds
Started Apr 23 02:12:08 PM PDT 24
Finished Apr 23 02:12:11 PM PDT 24
Peak memory 213104 kb
Host smart-89526fe7-f72b-4fe1-af3e-a464bd889421
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9590678 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.9590678
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1985388974
Short name T128
Test name
Test status
Simulation time 1509077660 ps
CPU time 9.79 seconds
Started Apr 23 02:12:10 PM PDT 24
Finished Apr 23 02:12:21 PM PDT 24
Peak memory 212956 kb
Host smart-31bb8e00-6567-4b3a-a1e0-5cf452e8ef4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985388974 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.1
985388974
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.652594350
Short name T80
Test name
Test status
Simulation time 4135406608 ps
CPU time 7.14 seconds
Started Apr 23 02:12:11 PM PDT 24
Finished Apr 23 02:12:19 PM PDT 24
Peak memory 219028 kb
Host smart-1661b86d-f898-4d42-a658-a228349cc540
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652594350 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.652594350
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.290865196
Short name T221
Test name
Test status
Simulation time 633322500 ps
CPU time 2.44 seconds
Started Apr 23 02:12:09 PM PDT 24
Finished Apr 23 02:12:13 PM PDT 24
Peak memory 213128 kb
Host smart-b4c36f7a-581d-4af9-b201-52fb2d295aee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290865196 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.290865196
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2292348390
Short name T238
Test name
Test status
Simulation time 321220556 ps
CPU time 1.59 seconds
Started Apr 23 02:12:06 PM PDT 24
Finished Apr 23 02:12:08 PM PDT 24
Peak memory 204624 kb
Host smart-b8b592bd-1018-41e0-86f8-72e2135f5f0b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292348390 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
2292348390
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.853284855
Short name T68
Test name
Test status
Simulation time 195464045 ps
CPU time 0.69 seconds
Started Apr 23 02:12:07 PM PDT 24
Finished Apr 23 02:12:09 PM PDT 24
Peak memory 204488 kb
Host smart-00bab909-28ea-41e5-a311-b61b6e912cc4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853284855 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.853284855
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3751741472
Short name T82
Test name
Test status
Simulation time 320275681 ps
CPU time 3.67 seconds
Started Apr 23 02:12:12 PM PDT 24
Finished Apr 23 02:12:17 PM PDT 24
Peak memory 204828 kb
Host smart-77bcc7b1-185e-42d3-94a4-d80a42352597
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751741472 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.3751741472
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tap_fsm_rand_reset.2459543473
Short name T115
Test name
Test status
Simulation time 11451573381 ps
CPU time 19.21 seconds
Started Apr 23 02:12:13 PM PDT 24
Finished Apr 23 02:12:34 PM PDT 24
Peak memory 215040 kb
Host smart-ae4872c1-9a12-49f6-bf19-8cdd8ebf1664
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459543473 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rv_dm_tap_fsm_rand_reset.2459543473
Directory /workspace/14.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.2027756366
Short name T234
Test name
Test status
Simulation time 81946544 ps
CPU time 3.22 seconds
Started Apr 23 02:12:11 PM PDT 24
Finished Apr 23 02:12:15 PM PDT 24
Peak memory 213056 kb
Host smart-d71f1d76-ae0b-485a-ae43-93ab1978dfb9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027756366 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.2027756366
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.2131940807
Short name T197
Test name
Test status
Simulation time 169319543 ps
CPU time 3.97 seconds
Started Apr 23 02:12:12 PM PDT 24
Finished Apr 23 02:12:17 PM PDT 24
Peak memory 218336 kb
Host smart-bd298771-c882-4bcb-8d73-e26b6fc3566d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131940807 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.2131940807
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.431751794
Short name T192
Test name
Test status
Simulation time 2435115964 ps
CPU time 8.27 seconds
Started Apr 23 02:12:10 PM PDT 24
Finished Apr 23 02:12:19 PM PDT 24
Peak memory 204748 kb
Host smart-8ecdf147-73e1-4f9f-b2bb-83133ad47dda
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431751794 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.431751794
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.2365814667
Short name T188
Test name
Test status
Simulation time 57700408 ps
CPU time 0.75 seconds
Started Apr 23 02:12:11 PM PDT 24
Finished Apr 23 02:12:13 PM PDT 24
Peak memory 204448 kb
Host smart-cb9e0586-28c3-4e52-b92c-91e80c00cf50
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365814667 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
2365814667
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.1784877980
Short name T217
Test name
Test status
Simulation time 86962562 ps
CPU time 3.53 seconds
Started Apr 23 02:12:11 PM PDT 24
Finished Apr 23 02:12:16 PM PDT 24
Peak memory 204824 kb
Host smart-56d2c6a0-1749-446d-a5d1-da5a503a1f32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784877980 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.1784877980
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tap_fsm_rand_reset.2234691161
Short name T237
Test name
Test status
Simulation time 11774280109 ps
CPU time 14.77 seconds
Started Apr 23 02:12:11 PM PDT 24
Finished Apr 23 02:12:26 PM PDT 24
Peak memory 220360 kb
Host smart-083e18fb-f2ed-43f3-9f26-bc01dd296469
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234691161 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rv_dm_tap_fsm_rand_reset.2234691161
Directory /workspace/15.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.2760553446
Short name T306
Test name
Test status
Simulation time 111379788 ps
CPU time 4.03 seconds
Started Apr 23 02:12:13 PM PDT 24
Finished Apr 23 02:12:18 PM PDT 24
Peak memory 213052 kb
Host smart-5f7d08fd-aa10-438e-a2a2-c9316c246218
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760553446 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.2760553446
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2799703004
Short name T274
Test name
Test status
Simulation time 1151443662 ps
CPU time 9.72 seconds
Started Apr 23 02:12:11 PM PDT 24
Finished Apr 23 02:12:22 PM PDT 24
Peak memory 213024 kb
Host smart-3536e188-660c-4891-b952-5ae9e0b5a1cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799703004 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.2
799703004
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2772785392
Short name T272
Test name
Test status
Simulation time 155597482 ps
CPU time 2.17 seconds
Started Apr 23 02:12:13 PM PDT 24
Finished Apr 23 02:12:16 PM PDT 24
Peak memory 215336 kb
Host smart-374128aa-0395-4c2d-8e6e-d6f291a47458
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772785392 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.2772785392
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.1778293135
Short name T270
Test name
Test status
Simulation time 98910843 ps
CPU time 1.5 seconds
Started Apr 23 02:12:17 PM PDT 24
Finished Apr 23 02:12:19 PM PDT 24
Peak memory 218548 kb
Host smart-0caae102-47cf-4b1b-bd43-d75325ca175f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778293135 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.1778293135
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2418329737
Short name T210
Test name
Test status
Simulation time 1763174962 ps
CPU time 3.47 seconds
Started Apr 23 02:12:17 PM PDT 24
Finished Apr 23 02:12:21 PM PDT 24
Peak memory 204656 kb
Host smart-44346d90-0884-4be6-9f41-db63126a0db0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418329737 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
2418329737
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.703118590
Short name T228
Test name
Test status
Simulation time 77300549 ps
CPU time 0.7 seconds
Started Apr 23 02:12:11 PM PDT 24
Finished Apr 23 02:12:13 PM PDT 24
Peak memory 204468 kb
Host smart-78a85967-dac6-4539-9eda-e182c6e6daf4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703118590 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.703118590
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.47525416
Short name T90
Test name
Test status
Simulation time 1609403073 ps
CPU time 4.58 seconds
Started Apr 23 02:12:12 PM PDT 24
Finished Apr 23 02:12:18 PM PDT 24
Peak memory 204768 kb
Host smart-b2b605d6-cb1e-4f0e-8150-bf912f3aa936
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47525416 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same_c
sr_outstanding.47525416
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.2673263523
Short name T114
Test name
Test status
Simulation time 1538230848 ps
CPU time 4.51 seconds
Started Apr 23 02:12:14 PM PDT 24
Finished Apr 23 02:12:20 PM PDT 24
Peak memory 213092 kb
Host smart-d0f9082c-c26d-49e5-a26f-f4e5d39538e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673263523 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.2673263523
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.4150005684
Short name T124
Test name
Test status
Simulation time 514004608 ps
CPU time 8.34 seconds
Started Apr 23 02:12:16 PM PDT 24
Finished Apr 23 02:12:25 PM PDT 24
Peak memory 213068 kb
Host smart-b78d5fd7-7a76-40eb-9792-c0d67cb14c37
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150005684 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.4
150005684
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.141470293
Short name T290
Test name
Test status
Simulation time 1062551783 ps
CPU time 2.32 seconds
Started Apr 23 02:12:13 PM PDT 24
Finished Apr 23 02:12:17 PM PDT 24
Peak memory 216624 kb
Host smart-3225e3a5-d539-4a75-96eb-9ce8532ad720
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141470293 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.141470293
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.111029861
Short name T107
Test name
Test status
Simulation time 177935684 ps
CPU time 2.4 seconds
Started Apr 23 02:12:15 PM PDT 24
Finished Apr 23 02:12:19 PM PDT 24
Peak memory 212884 kb
Host smart-e816dfdc-b902-4610-ba22-bd43046dc4c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111029861 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.111029861
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.1572339032
Short name T280
Test name
Test status
Simulation time 1389332586 ps
CPU time 5.34 seconds
Started Apr 23 02:12:14 PM PDT 24
Finished Apr 23 02:12:20 PM PDT 24
Peak memory 204632 kb
Host smart-3e1ec29a-fe30-4e66-8747-f8724228f6dc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572339032 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
1572339032
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.4193477433
Short name T232
Test name
Test status
Simulation time 84306207 ps
CPU time 0.75 seconds
Started Apr 23 02:12:14 PM PDT 24
Finished Apr 23 02:12:16 PM PDT 24
Peak memory 204460 kb
Host smart-a5423f90-420d-4722-b088-dd1b75bcb2c4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193477433 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
4193477433
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.962913654
Short name T111
Test name
Test status
Simulation time 635361032 ps
CPU time 4.02 seconds
Started Apr 23 02:12:13 PM PDT 24
Finished Apr 23 02:12:18 PM PDT 24
Peak memory 204752 kb
Host smart-0474d3c4-db1a-483c-a343-68bb9810029b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962913654 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same_
csr_outstanding.962913654
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tap_fsm_rand_reset.1222463565
Short name T118
Test name
Test status
Simulation time 9490574050 ps
CPU time 16.63 seconds
Started Apr 23 02:12:14 PM PDT 24
Finished Apr 23 02:12:31 PM PDT 24
Peak memory 219012 kb
Host smart-b9391588-4643-4fdc-bceb-c5c237978478
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222463565 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rv_dm_tap_fsm_rand_reset.1222463565
Directory /workspace/17.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.3351106252
Short name T44
Test name
Test status
Simulation time 68381393 ps
CPU time 2.12 seconds
Started Apr 23 02:12:17 PM PDT 24
Finished Apr 23 02:12:20 PM PDT 24
Peak memory 213068 kb
Host smart-22ed92d9-f57c-4a35-ab10-0a95335e1d90
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351106252 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.3351106252
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2594655006
Short name T215
Test name
Test status
Simulation time 641024219 ps
CPU time 9.71 seconds
Started Apr 23 02:12:17 PM PDT 24
Finished Apr 23 02:12:28 PM PDT 24
Peak memory 221112 kb
Host smart-1736f33c-a877-4d22-840c-f3badc5cdd86
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594655006 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.2
594655006
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2496193256
Short name T269
Test name
Test status
Simulation time 2991671448 ps
CPU time 7.68 seconds
Started Apr 23 02:12:19 PM PDT 24
Finished Apr 23 02:12:27 PM PDT 24
Peak memory 221308 kb
Host smart-25035f61-8ed1-421b-bf33-0e583f0746b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496193256 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.2496193256
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2663150371
Short name T207
Test name
Test status
Simulation time 52314443 ps
CPU time 1.45 seconds
Started Apr 23 02:12:16 PM PDT 24
Finished Apr 23 02:12:18 PM PDT 24
Peak memory 213072 kb
Host smart-6ded0aaf-7acd-4c61-92e0-bb4724c4877b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663150371 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.2663150371
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1681880263
Short name T184
Test name
Test status
Simulation time 899797323 ps
CPU time 3.52 seconds
Started Apr 23 02:12:15 PM PDT 24
Finished Apr 23 02:12:19 PM PDT 24
Peak memory 204788 kb
Host smart-63836abb-ebae-4e15-af10-80f57b411782
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681880263 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
1681880263
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2912735459
Short name T182
Test name
Test status
Simulation time 44082176 ps
CPU time 0.79 seconds
Started Apr 23 02:12:15 PM PDT 24
Finished Apr 23 02:12:17 PM PDT 24
Peak memory 204468 kb
Host smart-b5ec63eb-3043-41d8-b503-69f31989dbea
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912735459 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
2912735459
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3261571356
Short name T100
Test name
Test status
Simulation time 1967599333 ps
CPU time 4.22 seconds
Started Apr 23 02:12:17 PM PDT 24
Finished Apr 23 02:12:22 PM PDT 24
Peak memory 204828 kb
Host smart-60550a8f-2d11-481c-b313-082b9c0df9c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261571356 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.3261571356
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.1681310806
Short name T147
Test name
Test status
Simulation time 75769667 ps
CPU time 2.65 seconds
Started Apr 23 02:12:11 PM PDT 24
Finished Apr 23 02:12:15 PM PDT 24
Peak memory 213000 kb
Host smart-8ef01079-7de3-4759-8e3f-03a8b3aa9fe9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681310806 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.1681310806
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.196393367
Short name T129
Test name
Test status
Simulation time 755963605 ps
CPU time 8.14 seconds
Started Apr 23 02:12:17 PM PDT 24
Finished Apr 23 02:12:25 PM PDT 24
Peak memory 221164 kb
Host smart-9900db0f-bf31-46f3-b54f-7be21ad04420
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196393367 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.196393367
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.18075149
Short name T178
Test name
Test status
Simulation time 119040619 ps
CPU time 2.23 seconds
Started Apr 23 02:12:21 PM PDT 24
Finished Apr 23 02:12:23 PM PDT 24
Peak memory 218192 kb
Host smart-c461209c-dee5-47f9-a9d8-0c78b372a5cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18075149 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.18075149
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3935543848
Short name T104
Test name
Test status
Simulation time 58522450 ps
CPU time 1.54 seconds
Started Apr 23 02:12:15 PM PDT 24
Finished Apr 23 02:12:17 PM PDT 24
Peak memory 212928 kb
Host smart-26508970-01c4-4e6c-a0a2-1336329b9226
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935543848 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.3935543848
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.304107593
Short name T305
Test name
Test status
Simulation time 815337199 ps
CPU time 3.47 seconds
Started Apr 23 02:12:16 PM PDT 24
Finished Apr 23 02:12:21 PM PDT 24
Peak memory 204656 kb
Host smart-3241f280-0789-42c7-84e6-f8f578005e57
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304107593 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.304107593
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.140198790
Short name T193
Test name
Test status
Simulation time 88516568 ps
CPU time 0.73 seconds
Started Apr 23 02:12:17 PM PDT 24
Finished Apr 23 02:12:18 PM PDT 24
Peak memory 204484 kb
Host smart-361f0fec-5433-4802-8d06-fa6481759d4d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140198790 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.140198790
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.2148937752
Short name T299
Test name
Test status
Simulation time 726580779 ps
CPU time 4.29 seconds
Started Apr 23 02:12:21 PM PDT 24
Finished Apr 23 02:12:26 PM PDT 24
Peak memory 204736 kb
Host smart-8b0bfd2d-b9be-4408-90e6-375d16485912
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148937752 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.2148937752
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tap_fsm_rand_reset.1437173947
Short name T209
Test name
Test status
Simulation time 11503911530 ps
CPU time 13.01 seconds
Started Apr 23 02:12:16 PM PDT 24
Finished Apr 23 02:12:30 PM PDT 24
Peak memory 220168 kb
Host smart-219acf76-fc30-4855-a9cc-c1f3c96ea91d
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437173947 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rv_dm_tap_fsm_rand_reset.1437173947
Directory /workspace/19.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3549145
Short name T144
Test name
Test status
Simulation time 277171753 ps
CPU time 5.97 seconds
Started Apr 23 02:12:16 PM PDT 24
Finished Apr 23 02:12:23 PM PDT 24
Peak memory 213100 kb
Host smart-1c007f4b-5cbc-4dd5-bc9c-18247196913b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549145 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.3549145
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.601898987
Short name T91
Test name
Test status
Simulation time 1730082783 ps
CPU time 9.77 seconds
Started Apr 23 02:12:17 PM PDT 24
Finished Apr 23 02:12:28 PM PDT 24
Peak memory 221188 kb
Host smart-1753e1f3-5b1c-4a61-b423-70f683698b3f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601898987 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.601898987
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.264372871
Short name T286
Test name
Test status
Simulation time 11829467101 ps
CPU time 71.15 seconds
Started Apr 23 02:11:48 PM PDT 24
Finished Apr 23 02:12:59 PM PDT 24
Peak memory 213164 kb
Host smart-f428b86c-1d56-4108-9e03-f1dc2ba8e041
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264372871 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.rv_dm_csr_aliasing.264372871
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2093410521
Short name T106
Test name
Test status
Simulation time 5195892308 ps
CPU time 65.57 seconds
Started Apr 23 02:11:48 PM PDT 24
Finished Apr 23 02:12:55 PM PDT 24
Peak memory 205008 kb
Host smart-4e664a7a-3687-4dc9-88ab-35dc45954c46
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093410521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.2093410521
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3928266656
Short name T112
Test name
Test status
Simulation time 106209718 ps
CPU time 2.38 seconds
Started Apr 23 02:11:48 PM PDT 24
Finished Apr 23 02:11:51 PM PDT 24
Peak memory 212996 kb
Host smart-891eb918-2f6c-4cae-960f-798b6ae1411e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928266656 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.3928266656
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.1252002806
Short name T183
Test name
Test status
Simulation time 68481587 ps
CPU time 2.6 seconds
Started Apr 23 02:11:47 PM PDT 24
Finished Apr 23 02:11:51 PM PDT 24
Peak memory 218432 kb
Host smart-1d64703e-6ec7-4169-872f-5a9c896694fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252002806 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.1252002806
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.3052158068
Short name T294
Test name
Test status
Simulation time 51886148 ps
CPU time 1.5 seconds
Started Apr 23 02:11:54 PM PDT 24
Finished Apr 23 02:11:57 PM PDT 24
Peak memory 218464 kb
Host smart-b06662dc-9a38-4c90-95dd-a2ae3ff4be8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052158068 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.3052158068
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.3594454109
Short name T189
Test name
Test status
Simulation time 3790174701 ps
CPU time 8.57 seconds
Started Apr 23 02:11:57 PM PDT 24
Finished Apr 23 02:12:06 PM PDT 24
Peak memory 204820 kb
Host smart-a36d60fd-920e-4ee7-b995-015fda84b13e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594454109 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.3594454109
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.3729948608
Short name T170
Test name
Test status
Simulation time 40726702798 ps
CPU time 20.14 seconds
Started Apr 23 02:11:51 PM PDT 24
Finished Apr 23 02:12:12 PM PDT 24
Peak memory 204740 kb
Host smart-311c6bf9-f476-4015-8596-538709d69f72
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729948608 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_bit_bash.3729948608
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.1614062658
Short name T94
Test name
Test status
Simulation time 780280182 ps
CPU time 2.12 seconds
Started Apr 23 02:11:52 PM PDT 24
Finished Apr 23 02:11:54 PM PDT 24
Peak memory 204764 kb
Host smart-9f89dd8f-d5c1-4d52-94b9-872b74b1d47e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614062658 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.1614062658
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1958705131
Short name T268
Test name
Test status
Simulation time 521769261 ps
CPU time 1.23 seconds
Started Apr 23 02:11:50 PM PDT 24
Finished Apr 23 02:11:52 PM PDT 24
Peak memory 204628 kb
Host smart-721a97df-eaba-4c42-bc77-6ae672f0c973
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958705131 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.1
958705131
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.1849357958
Short name T265
Test name
Test status
Simulation time 107832202 ps
CPU time 0.82 seconds
Started Apr 23 02:11:57 PM PDT 24
Finished Apr 23 02:11:58 PM PDT 24
Peak memory 204520 kb
Host smart-5437f881-c55e-4b80-b5f0-5d3e0b3ba46b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849357958 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_aliasing.1849357958
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.3658951189
Short name T263
Test name
Test status
Simulation time 538629999 ps
CPU time 1.58 seconds
Started Apr 23 02:11:54 PM PDT 24
Finished Apr 23 02:11:57 PM PDT 24
Peak memory 204712 kb
Host smart-c407f34d-c06d-4013-8195-6f16d686306d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658951189 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.3658951189
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.4093209979
Short name T198
Test name
Test status
Simulation time 80222786 ps
CPU time 0.76 seconds
Started Apr 23 02:11:49 PM PDT 24
Finished Apr 23 02:11:50 PM PDT 24
Peak memory 204504 kb
Host smart-20187f7b-c018-4496-b802-235b35b3561f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093209979 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.4
093209979
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2299889823
Short name T250
Test name
Test status
Simulation time 47716870 ps
CPU time 0.63 seconds
Started Apr 23 02:11:51 PM PDT 24
Finished Apr 23 02:11:52 PM PDT 24
Peak memory 204368 kb
Host smart-4e0156c3-1e76-4104-92bf-15ed3591c938
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299889823 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.2299889823
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.3723083365
Short name T199
Test name
Test status
Simulation time 28758168 ps
CPU time 0.73 seconds
Started Apr 23 02:11:54 PM PDT 24
Finished Apr 23 02:11:56 PM PDT 24
Peak memory 204488 kb
Host smart-de04e615-80fe-45fd-826b-137d801cfd66
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723083365 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.3723083365
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3637364863
Short name T110
Test name
Test status
Simulation time 145564878 ps
CPU time 3.35 seconds
Started Apr 23 02:11:52 PM PDT 24
Finished Apr 23 02:11:56 PM PDT 24
Peak memory 204704 kb
Host smart-3c7728c2-b688-4fe5-be66-3d91f0428fd0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637364863 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.3637364863
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.3370059909
Short name T113
Test name
Test status
Simulation time 14680010824 ps
CPU time 29.41 seconds
Started Apr 23 02:11:57 PM PDT 24
Finished Apr 23 02:12:27 PM PDT 24
Peak memory 229420 kb
Host smart-b555e95f-9784-4c8a-bc0e-42fce00a5e62
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370059909 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.3370059909
Directory /workspace/2.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.1513452945
Short name T226
Test name
Test status
Simulation time 118238319 ps
CPU time 2.86 seconds
Started Apr 23 02:11:48 PM PDT 24
Finished Apr 23 02:11:52 PM PDT 24
Peak memory 213120 kb
Host smart-1624aa5c-0fb8-4e91-ac84-e60cb30d1c6d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513452945 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.1513452945
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.2313827500
Short name T122
Test name
Test status
Simulation time 3467527839 ps
CPU time 20.26 seconds
Started Apr 23 02:11:47 PM PDT 24
Finished Apr 23 02:12:08 PM PDT 24
Peak memory 221300 kb
Host smart-6cf7df6a-cbaa-4193-8115-60077bf77963
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313827500 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.2313827500
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/21.rv_dm_tap_fsm_rand_reset.2239751209
Short name T186
Test name
Test status
Simulation time 8251411800 ps
CPU time 22.97 seconds
Started Apr 23 02:12:21 PM PDT 24
Finished Apr 23 02:12:45 PM PDT 24
Peak memory 213824 kb
Host smart-99cf1de5-566e-4e1b-b294-d7ee6093d35e
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239751209 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 21.rv_dm_tap_fsm_rand_reset.2239751209
Directory /workspace/21.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/22.rv_dm_tap_fsm_rand_reset.2966630826
Short name T225
Test name
Test status
Simulation time 7583680356 ps
CPU time 19.42 seconds
Started Apr 23 02:12:19 PM PDT 24
Finished Apr 23 02:12:39 PM PDT 24
Peak memory 221192 kb
Host smart-51e607f4-2511-466c-9b1f-508582e0ff7d
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966630826 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 22.rv_dm_tap_fsm_rand_reset.2966630826
Directory /workspace/22.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/23.rv_dm_tap_fsm_rand_reset.2309819992
Short name T245
Test name
Test status
Simulation time 9486573105 ps
CPU time 17.48 seconds
Started Apr 23 02:12:19 PM PDT 24
Finished Apr 23 02:12:37 PM PDT 24
Peak memory 214944 kb
Host smart-575c92ad-a9cd-4764-8aee-fa8993ae5985
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309819992 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 23.rv_dm_tap_fsm_rand_reset.2309819992
Directory /workspace/23.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/24.rv_dm_tap_fsm_rand_reset.1622006405
Short name T216
Test name
Test status
Simulation time 17144572582 ps
CPU time 31.36 seconds
Started Apr 23 02:12:20 PM PDT 24
Finished Apr 23 02:12:51 PM PDT 24
Peak memory 221308 kb
Host smart-ffea1d40-f79a-41c1-b8be-d0166af78f23
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622006405 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 24.rv_dm_tap_fsm_rand_reset.1622006405
Directory /workspace/24.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/27.rv_dm_tap_fsm_rand_reset.97959576
Short name T240
Test name
Test status
Simulation time 26739819346 ps
CPU time 25.29 seconds
Started Apr 23 02:12:25 PM PDT 24
Finished Apr 23 02:12:51 PM PDT 24
Peak memory 221372 kb
Host smart-3093f4bf-8ec8-41e1-b2eb-2a310fe673ae
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97959576 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 27.rv_dm_tap_fsm_rand_reset.97959576
Directory /workspace/27.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/29.rv_dm_tap_fsm_rand_reset.528219259
Short name T119
Test name
Test status
Simulation time 9126313621 ps
CPU time 17.92 seconds
Started Apr 23 02:12:25 PM PDT 24
Finished Apr 23 02:12:44 PM PDT 24
Peak memory 212988 kb
Host smart-e2b8707a-9b53-4da7-b8f7-aa332d8e8eee
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528219259 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 29.rv_dm_tap_fsm_rand_reset.528219259
Directory /workspace/29.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.3766899545
Short name T109
Test name
Test status
Simulation time 4544676547 ps
CPU time 75.51 seconds
Started Apr 23 02:11:49 PM PDT 24
Finished Apr 23 02:13:06 PM PDT 24
Peak memory 213172 kb
Host smart-e6e9a048-8f65-485b-a075-43fdc546ae96
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766899545 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.3766899545
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.209799323
Short name T291
Test name
Test status
Simulation time 182896079 ps
CPU time 2.26 seconds
Started Apr 23 02:11:54 PM PDT 24
Finished Apr 23 02:11:57 PM PDT 24
Peak memory 212960 kb
Host smart-a0757f59-3e62-4d50-80ab-636a5fb4613b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209799323 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.209799323
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.687250413
Short name T223
Test name
Test status
Simulation time 3444869646 ps
CPU time 4.75 seconds
Started Apr 23 02:11:53 PM PDT 24
Finished Apr 23 02:11:58 PM PDT 24
Peak memory 221236 kb
Host smart-9d83f4a5-fb4b-4d21-8462-9c832022e72e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687250413 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.687250413
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.4244206083
Short name T87
Test name
Test status
Simulation time 112975681 ps
CPU time 1.62 seconds
Started Apr 23 02:11:53 PM PDT 24
Finished Apr 23 02:11:55 PM PDT 24
Peak memory 218452 kb
Host smart-bd555123-3e89-48cc-be90-c1ec5191172d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244206083 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.4244206083
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.4001284769
Short name T259
Test name
Test status
Simulation time 12584576878 ps
CPU time 17.37 seconds
Started Apr 23 02:11:50 PM PDT 24
Finished Apr 23 02:12:08 PM PDT 24
Peak memory 204732 kb
Host smart-9bedd738-ba85-4976-a5da-48f23318bcb9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001284769 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.4001284769
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1090689067
Short name T276
Test name
Test status
Simulation time 8111486685 ps
CPU time 33.13 seconds
Started Apr 23 02:11:51 PM PDT 24
Finished Apr 23 02:12:25 PM PDT 24
Peak memory 204800 kb
Host smart-8117b53a-9a44-43ec-99d4-b0a9a97ad967
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090689067 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_bit_bash.1090689067
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.1654235820
Short name T95
Test name
Test status
Simulation time 773526089 ps
CPU time 3.51 seconds
Started Apr 23 02:11:49 PM PDT 24
Finished Apr 23 02:11:53 PM PDT 24
Peak memory 204792 kb
Host smart-34e93e4a-30d2-4b30-8ffa-d0e807ba17ad
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654235820 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.1654235820
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.744305147
Short name T277
Test name
Test status
Simulation time 523201303 ps
CPU time 1.27 seconds
Started Apr 23 02:11:50 PM PDT 24
Finished Apr 23 02:11:52 PM PDT 24
Peak memory 204756 kb
Host smart-4b426726-e4d9-4c67-afa7-1685c380ac95
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744305147 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.744305147
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.1923074888
Short name T191
Test name
Test status
Simulation time 62110652 ps
CPU time 0.7 seconds
Started Apr 23 02:11:48 PM PDT 24
Finished Apr 23 02:11:49 PM PDT 24
Peak memory 204476 kb
Host smart-97037266-5fcd-4310-a834-8a6ace984d22
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923074888 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.1923074888
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.192793063
Short name T264
Test name
Test status
Simulation time 2234947514 ps
CPU time 3.65 seconds
Started Apr 23 02:11:50 PM PDT 24
Finished Apr 23 02:11:54 PM PDT 24
Peak memory 204780 kb
Host smart-2094c527-2c08-4c42-8cea-ef7af470371c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192793063 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr
_bit_bash.192793063
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.41478115
Short name T243
Test name
Test status
Simulation time 141617043 ps
CPU time 0.83 seconds
Started Apr 23 02:11:53 PM PDT 24
Finished Apr 23 02:11:54 PM PDT 24
Peak memory 204592 kb
Host smart-d1281abb-74dd-4830-b3ed-6e54fa464e4a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41478115 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_
hw_reset.41478115
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2948721053
Short name T203
Test name
Test status
Simulation time 42861835 ps
CPU time 0.72 seconds
Started Apr 23 02:11:49 PM PDT 24
Finished Apr 23 02:11:50 PM PDT 24
Peak memory 204512 kb
Host smart-a2c6390a-e66f-4fbb-b8d5-8baf32cb66d3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948721053 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.2
948721053
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.1026323197
Short name T247
Test name
Test status
Simulation time 54733551 ps
CPU time 0.66 seconds
Started Apr 23 02:11:53 PM PDT 24
Finished Apr 23 02:11:54 PM PDT 24
Peak memory 204464 kb
Host smart-8303fbfa-d968-4d89-91bf-191e68bc61cf
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026323197 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.1026323197
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.583003896
Short name T172
Test name
Test status
Simulation time 22419299 ps
CPU time 0.73 seconds
Started Apr 23 02:11:49 PM PDT 24
Finished Apr 23 02:11:50 PM PDT 24
Peak memory 204500 kb
Host smart-69a50563-aa62-47d9-bb13-e5af6ba2dd9e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583003896 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.583003896
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2407740280
Short name T248
Test name
Test status
Simulation time 866544782 ps
CPU time 7.24 seconds
Started Apr 23 02:11:51 PM PDT 24
Finished Apr 23 02:11:59 PM PDT 24
Peak memory 204884 kb
Host smart-5ca2e37f-6746-47dd-bf55-51ac37acd228
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407740280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_
csr_outstanding.2407740280
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.1063926738
Short name T75
Test name
Test status
Simulation time 452053906 ps
CPU time 3.8 seconds
Started Apr 23 02:11:48 PM PDT 24
Finished Apr 23 02:11:53 PM PDT 24
Peak memory 213012 kb
Host smart-f1cfcc5f-fa8d-43fd-90fc-77b510a7439d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063926738 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.1063926738
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3588733790
Short name T76
Test name
Test status
Simulation time 465040309 ps
CPU time 8.84 seconds
Started Apr 23 02:11:48 PM PDT 24
Finished Apr 23 02:11:57 PM PDT 24
Peak memory 221076 kb
Host smart-6641c09c-0be9-4fe8-9f61-1399f3043805
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588733790 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.3588733790
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/35.rv_dm_tap_fsm_rand_reset.3601868026
Short name T304
Test name
Test status
Simulation time 14795558128 ps
CPU time 14.47 seconds
Started Apr 23 02:12:23 PM PDT 24
Finished Apr 23 02:12:37 PM PDT 24
Peak memory 216180 kb
Host smart-0286175f-d245-473c-898a-5ec641b5319c
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601868026 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 35.rv_dm_tap_fsm_rand_reset.3601868026
Directory /workspace/35.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.591169906
Short name T242
Test name
Test status
Simulation time 3356199206 ps
CPU time 75.54 seconds
Started Apr 23 02:11:56 PM PDT 24
Finished Apr 23 02:13:12 PM PDT 24
Peak memory 205016 kb
Host smart-cc3ee1cc-f36c-4a40-a91c-30131a2c223e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591169906 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.rv_dm_csr_aliasing.591169906
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.4007926321
Short name T81
Test name
Test status
Simulation time 950895852 ps
CPU time 2.52 seconds
Started Apr 23 02:11:55 PM PDT 24
Finished Apr 23 02:11:58 PM PDT 24
Peak memory 212992 kb
Host smart-984b6624-3869-40eb-b27d-e64552df4932
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007926321 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.4007926321
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2325833792
Short name T297
Test name
Test status
Simulation time 409459495 ps
CPU time 4.71 seconds
Started Apr 23 02:11:57 PM PDT 24
Finished Apr 23 02:12:03 PM PDT 24
Peak memory 219420 kb
Host smart-7e931caa-2e1a-4d53-8707-af203c1c1d57
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325833792 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.2325833792
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.3501203929
Short name T99
Test name
Test status
Simulation time 93898001 ps
CPU time 1.46 seconds
Started Apr 23 02:11:54 PM PDT 24
Finished Apr 23 02:11:57 PM PDT 24
Peak memory 213028 kb
Host smart-9730cf46-dbe8-4449-95f0-969d4269cf0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501203929 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.3501203929
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.513145349
Short name T168
Test name
Test status
Simulation time 7749911503 ps
CPU time 14.14 seconds
Started Apr 23 02:11:51 PM PDT 24
Finished Apr 23 02:12:06 PM PDT 24
Peak memory 204752 kb
Host smart-2da5c171-4fd8-4f86-bdf3-72a706452bd9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513145349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr
_aliasing.513145349
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.369738863
Short name T167
Test name
Test status
Simulation time 27714198012 ps
CPU time 92.36 seconds
Started Apr 23 02:11:55 PM PDT 24
Finished Apr 23 02:13:28 PM PDT 24
Peak memory 204900 kb
Host smart-0804407e-ba37-429e-bc5f-89cf63131cc0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369738863 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr
_bit_bash.369738863
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.548681903
Short name T93
Test name
Test status
Simulation time 1733038561 ps
CPU time 1.9 seconds
Started Apr 23 02:11:52 PM PDT 24
Finished Apr 23 02:11:54 PM PDT 24
Peak memory 204796 kb
Host smart-c39056d7-e1cc-49ca-bc68-06ad4411c757
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548681903 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr
_hw_reset.548681903
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3317241668
Short name T254
Test name
Test status
Simulation time 425427949 ps
CPU time 1.29 seconds
Started Apr 23 02:11:52 PM PDT 24
Finished Apr 23 02:11:54 PM PDT 24
Peak memory 204724 kb
Host smart-611c9d40-2ba6-463e-90cb-798bad549840
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317241668 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.3
317241668
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.2677918661
Short name T176
Test name
Test status
Simulation time 77934484 ps
CPU time 0.82 seconds
Started Apr 23 02:11:53 PM PDT 24
Finished Apr 23 02:11:55 PM PDT 24
Peak memory 204496 kb
Host smart-d1839689-bc16-4be1-b838-c81abc4212eb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677918661 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.2677918661
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.3404630611
Short name T279
Test name
Test status
Simulation time 606490751 ps
CPU time 1.49 seconds
Started Apr 23 02:11:52 PM PDT 24
Finished Apr 23 02:11:54 PM PDT 24
Peak memory 204680 kb
Host smart-7f7591e2-91d9-43f5-908c-afbd467d7982
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404630611 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.3404630611
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.438846158
Short name T298
Test name
Test status
Simulation time 273733984 ps
CPU time 0.75 seconds
Started Apr 23 02:11:51 PM PDT 24
Finished Apr 23 02:11:53 PM PDT 24
Peak memory 204588 kb
Host smart-a93e35da-4828-4867-a181-ef99053e1bbc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438846158 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr
_hw_reset.438846158
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.3905230586
Short name T278
Test name
Test status
Simulation time 28380624 ps
CPU time 0.74 seconds
Started Apr 23 02:11:54 PM PDT 24
Finished Apr 23 02:11:55 PM PDT 24
Peak memory 204444 kb
Host smart-73e69689-0275-4f65-9c3e-7d5b778ccd7c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905230586 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.3
905230586
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.2648559846
Short name T284
Test name
Test status
Simulation time 18210280 ps
CPU time 0.68 seconds
Started Apr 23 02:11:57 PM PDT 24
Finished Apr 23 02:11:59 PM PDT 24
Peak memory 204532 kb
Host smart-84887e96-e0ce-4344-984e-76a1f870ebf9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648559846 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.2648559846
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.3088324489
Short name T181
Test name
Test status
Simulation time 30107907 ps
CPU time 0.72 seconds
Started Apr 23 02:11:58 PM PDT 24
Finished Apr 23 02:12:00 PM PDT 24
Peak memory 204456 kb
Host smart-29ae40bb-78c0-4769-ae6e-1ede92448273
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088324489 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.3088324489
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2421055233
Short name T117
Test name
Test status
Simulation time 4328156596 ps
CPU time 18.61 seconds
Started Apr 23 02:11:52 PM PDT 24
Finished Apr 23 02:12:12 PM PDT 24
Peak memory 221284 kb
Host smart-6f910e68-1adf-4ad4-97b9-e891e8c013b4
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421055233 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.2421055233
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.1300766370
Short name T241
Test name
Test status
Simulation time 210835659 ps
CPU time 3.74 seconds
Started Apr 23 02:11:53 PM PDT 24
Finished Apr 23 02:11:57 PM PDT 24
Peak memory 213048 kb
Host smart-66d7eef1-d33a-43ca-adf2-b86df6f1a09a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300766370 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.1300766370
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.2529335060
Short name T200
Test name
Test status
Simulation time 6141527177 ps
CPU time 13.46 seconds
Started Apr 23 02:11:56 PM PDT 24
Finished Apr 23 02:12:10 PM PDT 24
Peak memory 213164 kb
Host smart-ac1bd1a2-be58-419b-a54e-6aeef9e72a22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529335060 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.2529335060
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.1591129039
Short name T108
Test name
Test status
Simulation time 30264557 ps
CPU time 1.35 seconds
Started Apr 23 02:11:58 PM PDT 24
Finished Apr 23 02:12:00 PM PDT 24
Peak memory 212952 kb
Host smart-af0d7335-c0da-4a9f-bb91-8caf47cd4758
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591129039 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.1591129039
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3935190613
Short name T236
Test name
Test status
Simulation time 254300506 ps
CPU time 1.06 seconds
Started Apr 23 02:11:57 PM PDT 24
Finished Apr 23 02:11:58 PM PDT 24
Peak memory 204688 kb
Host smart-b89ecb50-d510-461e-b839-c3fb283faef7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935190613 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.3
935190613
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.2792492428
Short name T229
Test name
Test status
Simulation time 32049987 ps
CPU time 0.74 seconds
Started Apr 23 02:11:58 PM PDT 24
Finished Apr 23 02:12:00 PM PDT 24
Peak memory 204468 kb
Host smart-716ecd36-4f5a-452b-a8f9-43288fb69a69
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792492428 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.2
792492428
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1119201838
Short name T84
Test name
Test status
Simulation time 823195198 ps
CPU time 4.19 seconds
Started Apr 23 02:11:58 PM PDT 24
Finished Apr 23 02:12:03 PM PDT 24
Peak memory 204736 kb
Host smart-3b4085eb-5601-4540-b302-3cb351bd5fc1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119201838 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.1119201838
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.309867182
Short name T79
Test name
Test status
Simulation time 711461816 ps
CPU time 4.89 seconds
Started Apr 23 02:11:59 PM PDT 24
Finished Apr 23 02:12:04 PM PDT 24
Peak memory 213044 kb
Host smart-90a30189-ebbd-4135-b12a-c4efffdab4d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309867182 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.309867182
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2733318171
Short name T130
Test name
Test status
Simulation time 536927257 ps
CPU time 9.74 seconds
Started Apr 23 02:11:55 PM PDT 24
Finished Apr 23 02:12:05 PM PDT 24
Peak memory 213004 kb
Host smart-99e8faa8-4e3f-41ff-915a-1217df33ae98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733318171 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.2733318171
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2521630787
Short name T307
Test name
Test status
Simulation time 506226940 ps
CPU time 3.78 seconds
Started Apr 23 02:11:57 PM PDT 24
Finished Apr 23 02:12:02 PM PDT 24
Peak memory 218032 kb
Host smart-fbff39d7-11f2-4566-9996-dfd34c3f3af7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521630787 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.2521630787
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.20165825
Short name T258
Test name
Test status
Simulation time 134881924 ps
CPU time 1.5 seconds
Started Apr 23 02:11:56 PM PDT 24
Finished Apr 23 02:11:58 PM PDT 24
Peak memory 217724 kb
Host smart-7a36e203-12dd-473a-80af-6f4337f40153
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20165825 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.20165825
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.3309632164
Short name T219
Test name
Test status
Simulation time 949953526 ps
CPU time 1.78 seconds
Started Apr 23 02:11:57 PM PDT 24
Finished Apr 23 02:11:59 PM PDT 24
Peak memory 204624 kb
Host smart-75d4b4a7-417c-4ebe-aafa-cffdbdbebe00
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309632164 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.3
309632164
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2327859537
Short name T281
Test name
Test status
Simulation time 47874909 ps
CPU time 0.73 seconds
Started Apr 23 02:11:57 PM PDT 24
Finished Apr 23 02:11:59 PM PDT 24
Peak memory 204472 kb
Host smart-431d476a-c812-49dc-b2ae-5c0e032bcfb4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327859537 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.2
327859537
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.1001524989
Short name T246
Test name
Test status
Simulation time 823169299 ps
CPU time 6.57 seconds
Started Apr 23 02:12:00 PM PDT 24
Finished Apr 23 02:12:07 PM PDT 24
Peak memory 204764 kb
Host smart-7d1de849-66b4-4e9d-bc0a-4c72b61abe36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001524989 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.1001524989
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.545595106
Short name T292
Test name
Test status
Simulation time 951087409 ps
CPU time 2.91 seconds
Started Apr 23 02:11:56 PM PDT 24
Finished Apr 23 02:11:59 PM PDT 24
Peak memory 213040 kb
Host smart-8b1a5af9-4bb8-4352-9684-84b1a5f35ac6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545595106 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.545595106
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2549509006
Short name T204
Test name
Test status
Simulation time 588158228 ps
CPU time 10.13 seconds
Started Apr 23 02:11:59 PM PDT 24
Finished Apr 23 02:12:10 PM PDT 24
Peak memory 221044 kb
Host smart-b8181340-1456-46ef-8c6b-9d0fc2968b5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549509006 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.2549509006
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3612112515
Short name T293
Test name
Test status
Simulation time 5408503122 ps
CPU time 7.71 seconds
Started Apr 23 02:12:00 PM PDT 24
Finished Apr 23 02:12:08 PM PDT 24
Peak memory 221076 kb
Host smart-2684f6fc-36b4-48f5-8b1f-430127f724e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612112515 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.3612112515
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.2363719441
Short name T97
Test name
Test status
Simulation time 43120250 ps
CPU time 1.43 seconds
Started Apr 23 02:12:00 PM PDT 24
Finished Apr 23 02:12:02 PM PDT 24
Peak memory 221100 kb
Host smart-dc5367b8-6a64-4ad5-9076-451a5c1ac7fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363719441 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.2363719441
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.1702763545
Short name T233
Test name
Test status
Simulation time 441443500 ps
CPU time 1.47 seconds
Started Apr 23 02:11:55 PM PDT 24
Finished Apr 23 02:11:57 PM PDT 24
Peak memory 204680 kb
Host smart-7c00ecef-1ea4-4eae-95b4-452763083176
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702763545 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.1
702763545
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.2836335025
Short name T301
Test name
Test status
Simulation time 37265087 ps
CPU time 0.75 seconds
Started Apr 23 02:11:57 PM PDT 24
Finished Apr 23 02:11:59 PM PDT 24
Peak memory 204448 kb
Host smart-a5ee7ad6-b1de-47f4-97fa-b24465da5d99
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836335025 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.2
836335025
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3518427721
Short name T208
Test name
Test status
Simulation time 390805524 ps
CPU time 3.83 seconds
Started Apr 23 02:12:07 PM PDT 24
Finished Apr 23 02:12:11 PM PDT 24
Peak memory 204820 kb
Host smart-f22cfbc8-0d8c-4414-bb08-40ee25c53336
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518427721 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.3518427721
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.3072602596
Short name T251
Test name
Test status
Simulation time 448727849 ps
CPU time 5.97 seconds
Started Apr 23 02:11:57 PM PDT 24
Finished Apr 23 02:12:03 PM PDT 24
Peak memory 213116 kb
Host smart-e72d5e8d-15c4-4728-bc95-0d7e83321808
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072602596 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.3072602596
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2414236470
Short name T41
Test name
Test status
Simulation time 560943297 ps
CPU time 9.3 seconds
Started Apr 23 02:11:58 PM PDT 24
Finished Apr 23 02:12:08 PM PDT 24
Peak memory 212972 kb
Host smart-d89a4a87-6ee7-4236-a7fc-15e117cb0023
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414236470 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.2414236470
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.454119558
Short name T177
Test name
Test status
Simulation time 38385386 ps
CPU time 1.97 seconds
Started Apr 23 02:12:02 PM PDT 24
Finished Apr 23 02:12:04 PM PDT 24
Peak memory 215708 kb
Host smart-54a662d5-164c-4295-b149-a039b13580c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454119558 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.454119558
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.576801283
Short name T257
Test name
Test status
Simulation time 100051164 ps
CPU time 2.33 seconds
Started Apr 23 02:12:00 PM PDT 24
Finished Apr 23 02:12:03 PM PDT 24
Peak memory 218432 kb
Host smart-086adbdc-df25-4427-bd14-8d12c655b058
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576801283 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.576801283
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.227989462
Short name T218
Test name
Test status
Simulation time 564473330 ps
CPU time 1.41 seconds
Started Apr 23 02:11:59 PM PDT 24
Finished Apr 23 02:12:01 PM PDT 24
Peak memory 204684 kb
Host smart-1d369717-9c3d-4e23-b9fa-d0fd6a4211a5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227989462 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.227989462
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.793290942
Short name T300
Test name
Test status
Simulation time 131216792 ps
CPU time 0.83 seconds
Started Apr 23 02:11:59 PM PDT 24
Finished Apr 23 02:12:00 PM PDT 24
Peak memory 204480 kb
Host smart-dd7d98a6-dd30-4277-bb29-06b668147be2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793290942 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.793290942
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.315879854
Short name T252
Test name
Test status
Simulation time 1574861269 ps
CPU time 7.81 seconds
Started Apr 23 02:11:57 PM PDT 24
Finished Apr 23 02:12:06 PM PDT 24
Peak memory 204828 kb
Host smart-265cc896-2151-421e-8097-d0eadca160d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315879854 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_c
sr_outstanding.315879854
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.415406665
Short name T120
Test name
Test status
Simulation time 65489152 ps
CPU time 2.71 seconds
Started Apr 23 02:11:58 PM PDT 24
Finished Apr 23 02:12:02 PM PDT 24
Peak memory 213056 kb
Host smart-4c146d23-5433-4d04-a1f8-6349a64dedfd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415406665 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.415406665
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.644325200
Short name T220
Test name
Test status
Simulation time 3474410452 ps
CPU time 8.42 seconds
Started Apr 23 02:12:00 PM PDT 24
Finished Apr 23 02:12:09 PM PDT 24
Peak memory 221368 kb
Host smart-37abb9f7-154e-48bd-aaa4-3e833f5d4b86
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644325200 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.644325200
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.2452212671
Short name T249
Test name
Test status
Simulation time 197816154 ps
CPU time 1.43 seconds
Started Apr 23 02:11:58 PM PDT 24
Finished Apr 23 02:12:01 PM PDT 24
Peak memory 204668 kb
Host smart-a01e71f2-d9e5-4e03-9f67-2e9a55023554
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452212671 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.2
452212671
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1363168243
Short name T194
Test name
Test status
Simulation time 138657249 ps
CPU time 0.87 seconds
Started Apr 23 02:11:59 PM PDT 24
Finished Apr 23 02:12:01 PM PDT 24
Peak memory 204516 kb
Host smart-5fb63617-a0b5-4214-a9e4-406a1a691580
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363168243 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.1
363168243
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.1833225866
Short name T88
Test name
Test status
Simulation time 1031541918 ps
CPU time 3.98 seconds
Started Apr 23 02:12:05 PM PDT 24
Finished Apr 23 02:12:09 PM PDT 24
Peak memory 204820 kb
Host smart-0968dc9c-a267-4fa5-ad32-9adfb869a09a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833225866 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.1833225866
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.4128630177
Short name T65
Test name
Test status
Simulation time 20105762070 ps
CPU time 10.78 seconds
Started Apr 23 02:12:00 PM PDT 24
Finished Apr 23 02:12:11 PM PDT 24
Peak memory 219568 kb
Host smart-91b56034-93f3-449a-b783-8a76eac54485
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128630177 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.4128630177
Directory /workspace/9.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.3982741503
Short name T213
Test name
Test status
Simulation time 249309873 ps
CPU time 4.17 seconds
Started Apr 23 02:12:00 PM PDT 24
Finished Apr 23 02:12:05 PM PDT 24
Peak memory 213088 kb
Host smart-bf9f01bd-4089-4a92-9668-5c21eedb5e33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982741503 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.3982741503
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.630045812
Short name T288
Test name
Test status
Simulation time 583213279 ps
CPU time 8.7 seconds
Started Apr 23 02:11:57 PM PDT 24
Finished Apr 23 02:12:06 PM PDT 24
Peak memory 213036 kb
Host smart-793b15ce-9402-4668-b58f-4cb0e85f2b0e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630045812 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.630045812
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.1747154874
Short name T139
Test name
Test status
Simulation time 61340085 ps
CPU time 0.74 seconds
Started Apr 23 01:07:03 PM PDT 24
Finished Apr 23 01:07:04 PM PDT 24
Peak memory 204920 kb
Host smart-12273267-2449-408c-95f2-b4640e9de7b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747154874 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.1747154874
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.1918820478
Short name T12
Test name
Test status
Simulation time 3170334011 ps
CPU time 9.78 seconds
Started Apr 23 01:06:37 PM PDT 24
Finished Apr 23 01:06:48 PM PDT 24
Peak memory 205308 kb
Host smart-f8fdbc6c-552c-4161-9e12-8d76c34c2693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918820478 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.1918820478
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.2492178843
Short name T2
Test name
Test status
Simulation time 38782571 ps
CPU time 0.8 seconds
Started Apr 23 01:06:46 PM PDT 24
Finished Apr 23 01:06:48 PM PDT 24
Peak memory 205008 kb
Host smart-0ccbdea2-4fa7-4a67-a1a6-d357f4d658e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492178843 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.2492178843
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.873022387
Short name T163
Test name
Test status
Simulation time 79579757 ps
CPU time 0.78 seconds
Started Apr 23 01:06:47 PM PDT 24
Finished Apr 23 01:06:48 PM PDT 24
Peak memory 204764 kb
Host smart-dbde6f1d-1d77-409f-9b00-49807a304ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873022387 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.873022387
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.2135882436
Short name T165
Test name
Test status
Simulation time 379906790 ps
CPU time 0.96 seconds
Started Apr 23 01:06:52 PM PDT 24
Finished Apr 23 01:06:54 PM PDT 24
Peak memory 204864 kb
Host smart-ddeab617-e6c8-4fb8-abe5-23523cc1d53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135882436 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.2135882436
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.968779934
Short name T30
Test name
Test status
Simulation time 941496173 ps
CPU time 1.88 seconds
Started Apr 23 01:06:52 PM PDT 24
Finished Apr 23 01:06:54 PM PDT 24
Peak memory 204996 kb
Host smart-d8f9274b-d21b-468c-8740-8293da79b454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968779934 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.968779934
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.4154636720
Short name T16
Test name
Test status
Simulation time 362279849 ps
CPU time 2.01 seconds
Started Apr 23 01:06:47 PM PDT 24
Finished Apr 23 01:06:50 PM PDT 24
Peak memory 205168 kb
Host smart-61fdac66-8b15-421c-9794-fe5eafcf3cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154636720 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.4154636720
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.3089360552
Short name T20
Test name
Test status
Simulation time 477988761 ps
CPU time 1.64 seconds
Started Apr 23 01:06:53 PM PDT 24
Finished Apr 23 01:06:55 PM PDT 24
Peak memory 205112 kb
Host smart-5d8f407e-0960-477c-8638-0e54a181eacf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089360552 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.3089360552
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.3059497098
Short name T39
Test name
Test status
Simulation time 373499933 ps
CPU time 1.34 seconds
Started Apr 23 01:07:01 PM PDT 24
Finished Apr 23 01:07:03 PM PDT 24
Peak memory 229124 kb
Host smart-ec023b09-d398-4512-9233-4a6dc45921b6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059497098 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.3059497098
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.1921442804
Short name T66
Test name
Test status
Simulation time 474753596 ps
CPU time 2.19 seconds
Started Apr 23 01:06:36 PM PDT 24
Finished Apr 23 01:06:39 PM PDT 24
Peak memory 205016 kb
Host smart-7875af3f-7996-41cf-b80e-1031ba726fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921442804 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.1921442804
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.2456792382
Short name T6
Test name
Test status
Simulation time 182028118 ps
CPU time 0.7 seconds
Started Apr 23 01:07:15 PM PDT 24
Finished Apr 23 01:07:16 PM PDT 24
Peak memory 204984 kb
Host smart-1f5557bf-61e4-4888-8f4b-c11c91dec665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456792382 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.2456792382
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.1469601344
Short name T155
Test name
Test status
Simulation time 91760923 ps
CPU time 0.7 seconds
Started Apr 23 01:07:16 PM PDT 24
Finished Apr 23 01:07:17 PM PDT 24
Peak memory 204960 kb
Host smart-d78c2da2-d43d-44d7-986b-bba9dd157108
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469601344 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.1469601344
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.4103178277
Short name T24
Test name
Test status
Simulation time 548607432 ps
CPU time 1.09 seconds
Started Apr 23 01:07:04 PM PDT 24
Finished Apr 23 01:07:06 PM PDT 24
Peak memory 204956 kb
Host smart-dbdee17d-746f-44e7-b596-13be267c73ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103178277 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.4103178277
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.3307531629
Short name T8
Test name
Test status
Simulation time 382200967 ps
CPU time 0.99 seconds
Started Apr 23 01:07:11 PM PDT 24
Finished Apr 23 01:07:12 PM PDT 24
Peak memory 204896 kb
Host smart-d3272f80-deb5-4d60-84a1-d2aa45f9600a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307531629 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.3307531629
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.1979266063
Short name T11
Test name
Test status
Simulation time 5193985999 ps
CPU time 5.32 seconds
Started Apr 23 01:07:04 PM PDT 24
Finished Apr 23 01:07:10 PM PDT 24
Peak memory 205256 kb
Host smart-c6f2a65f-1b70-48f2-aef4-c522c2a97891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979266063 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.1979266063
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.544073782
Short name T131
Test name
Test status
Simulation time 27067873 ps
CPU time 0.74 seconds
Started Apr 23 01:07:14 PM PDT 24
Finished Apr 23 01:07:15 PM PDT 24
Peak memory 204776 kb
Host smart-a811b23a-3922-404f-8b97-438413a1ab10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544073782 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.544073782
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.2627720671
Short name T159
Test name
Test status
Simulation time 94658571 ps
CPU time 0.76 seconds
Started Apr 23 01:07:14 PM PDT 24
Finished Apr 23 01:07:15 PM PDT 24
Peak memory 204832 kb
Host smart-f43e032c-14e0-4b5a-9f59-bafdda11e9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627720671 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.2627720671
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.263248388
Short name T35
Test name
Test status
Simulation time 72094486 ps
CPU time 0.88 seconds
Started Apr 23 01:07:11 PM PDT 24
Finished Apr 23 01:07:12 PM PDT 24
Peak memory 204796 kb
Host smart-10d98e37-7fec-4fe8-8225-32bfc5572fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263248388 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.263248388
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.3255305238
Short name T63
Test name
Test status
Simulation time 129701170 ps
CPU time 1.07 seconds
Started Apr 23 01:07:10 PM PDT 24
Finished Apr 23 01:07:12 PM PDT 24
Peak memory 204816 kb
Host smart-23515826-417c-45d5-994a-cf3401ed1b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255305238 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.3255305238
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.1596055588
Short name T60
Test name
Test status
Simulation time 108030410 ps
CPU time 0.76 seconds
Started Apr 23 01:07:05 PM PDT 24
Finished Apr 23 01:07:07 PM PDT 24
Peak memory 204940 kb
Host smart-b7e9abb5-0e61-4b69-94fd-9935ab2cdf9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596055588 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.1596055588
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.2928536550
Short name T26
Test name
Test status
Simulation time 334716483 ps
CPU time 1.88 seconds
Started Apr 23 01:07:10 PM PDT 24
Finished Apr 23 01:07:12 PM PDT 24
Peak memory 205152 kb
Host smart-be44cbe1-cc05-4a45-85c4-7b8a99dcda08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928536550 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.2928536550
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.100586306
Short name T21
Test name
Test status
Simulation time 77276863 ps
CPU time 0.91 seconds
Started Apr 23 01:07:17 PM PDT 24
Finished Apr 23 01:07:18 PM PDT 24
Peak memory 204916 kb
Host smart-57882f18-482c-43b8-981f-9d37f02ae7da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100586306 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.100586306
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.6920808
Short name T27
Test name
Test status
Simulation time 97856789 ps
CPU time 0.74 seconds
Started Apr 23 01:07:15 PM PDT 24
Finished Apr 23 01:07:17 PM PDT 24
Peak memory 204968 kb
Host smart-08bdd9e3-445f-46cc-90d7-17b4d136144d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6920808 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.6920808
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.2836831252
Short name T17
Test name
Test status
Simulation time 19389253 ps
CPU time 0.79 seconds
Started Apr 23 01:07:17 PM PDT 24
Finished Apr 23 01:07:18 PM PDT 24
Peak memory 213116 kb
Host smart-14cdd790-f035-4662-b5d6-60201a94293f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836831252 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.2836831252
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.3781386887
Short name T38
Test name
Test status
Simulation time 152050761 ps
CPU time 1.33 seconds
Started Apr 23 01:07:18 PM PDT 24
Finished Apr 23 01:07:20 PM PDT 24
Peak memory 237280 kb
Host smart-431a4f92-97a5-4cc9-a7d4-32a0a0b4a7eb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781386887 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.3781386887
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.756204450
Short name T25
Test name
Test status
Simulation time 707056604 ps
CPU time 1.26 seconds
Started Apr 23 01:07:00 PM PDT 24
Finished Apr 23 01:07:01 PM PDT 24
Peak memory 204988 kb
Host smart-006a993d-7328-4103-a186-78d7b42aa323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756204450 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.756204450
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.1574064347
Short name T145
Test name
Test status
Simulation time 34702702 ps
CPU time 0.71 seconds
Started Apr 23 01:07:48 PM PDT 24
Finished Apr 23 01:07:50 PM PDT 24
Peak memory 204944 kb
Host smart-88f6eb08-8299-4f71-aa89-7b19613d8cc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574064347 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.1574064347
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.2991661760
Short name T160
Test name
Test status
Simulation time 40615098 ps
CPU time 0.82 seconds
Started Apr 23 01:07:52 PM PDT 24
Finished Apr 23 01:07:53 PM PDT 24
Peak memory 204992 kb
Host smart-61a8efaa-1b30-491b-a60c-a30d13ebd275
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991661760 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.2991661760
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.428319277
Short name T33
Test name
Test status
Simulation time 2245948372 ps
CPU time 7.12 seconds
Started Apr 23 01:07:56 PM PDT 24
Finished Apr 23 01:08:04 PM PDT 24
Peak memory 205376 kb
Host smart-a22dea6e-5311-48ad-9f95-b4b0e3e203b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428319277 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.428319277
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.3245026804
Short name T73
Test name
Test status
Simulation time 39452358 ps
CPU time 0.74 seconds
Started Apr 23 01:07:59 PM PDT 24
Finished Apr 23 01:08:00 PM PDT 24
Peak memory 204964 kb
Host smart-10964eac-671f-4ea1-8a46-938a5a538cb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245026804 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.3245026804
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.535211692
Short name T31
Test name
Test status
Simulation time 326734699 ps
CPU time 1.52 seconds
Started Apr 23 01:07:51 PM PDT 24
Finished Apr 23 01:07:53 PM PDT 24
Peak memory 205292 kb
Host smart-d5d56962-0dd8-4256-9f24-3ca93aca2d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535211692 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.535211692
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.3075560502
Short name T153
Test name
Test status
Simulation time 132742470 ps
CPU time 0.68 seconds
Started Apr 23 01:07:55 PM PDT 24
Finished Apr 23 01:07:56 PM PDT 24
Peak memory 204972 kb
Host smart-10de2424-af0a-4755-80a6-662e8a35b63d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075560502 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.3075560502
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.19064865
Short name T34
Test name
Test status
Simulation time 44753870275 ps
CPU time 54.22 seconds
Started Apr 23 01:07:55 PM PDT 24
Finished Apr 23 01:08:50 PM PDT 24
Peak memory 213584 kb
Host smart-e7211ba8-8bb4-49b8-92d3-41f4a7888cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19064865 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.19064865
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.3174771333
Short name T135
Test name
Test status
Simulation time 19821885 ps
CPU time 0.74 seconds
Started Apr 23 01:07:59 PM PDT 24
Finished Apr 23 01:08:00 PM PDT 24
Peak memory 204956 kb
Host smart-82345035-e45e-4aea-84c3-d82a43b37989
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174771333 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.3174771333
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.1028866351
Short name T161
Test name
Test status
Simulation time 15996835 ps
CPU time 0.72 seconds
Started Apr 23 01:08:04 PM PDT 24
Finished Apr 23 01:08:05 PM PDT 24
Peak memory 205008 kb
Host smart-1f01a49d-a9a3-465e-8793-6b6f3aa4ec5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028866351 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.1028866351
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.2025045453
Short name T71
Test name
Test status
Simulation time 59414358 ps
CPU time 0.71 seconds
Started Apr 23 01:08:04 PM PDT 24
Finished Apr 23 01:08:05 PM PDT 24
Peak memory 204896 kb
Host smart-4e5581ff-33da-4b52-b20e-ed4fc6963cc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025045453 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.2025045453
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.3196220126
Short name T146
Test name
Test status
Simulation time 49335128 ps
CPU time 0.71 seconds
Started Apr 23 01:08:12 PM PDT 24
Finished Apr 23 01:08:13 PM PDT 24
Peak memory 204944 kb
Host smart-922e65b7-e465-4746-99e1-2993db5346a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196220126 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.3196220126
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.1036579606
Short name T134
Test name
Test status
Simulation time 20804724 ps
CPU time 0.77 seconds
Started Apr 23 01:08:11 PM PDT 24
Finished Apr 23 01:08:12 PM PDT 24
Peak memory 204944 kb
Host smart-8a664cd2-9e6a-42d0-b590-bfd91daa50c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036579606 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.1036579606
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.2233571908
Short name T132
Test name
Test status
Simulation time 41854494 ps
CPU time 0.76 seconds
Started Apr 23 01:07:21 PM PDT 24
Finished Apr 23 01:07:22 PM PDT 24
Peak memory 204920 kb
Host smart-90d2cff8-a327-4043-a597-dcf4d677ed70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233571908 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.2233571908
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.1477281648
Short name T3
Test name
Test status
Simulation time 26100382 ps
CPU time 0.73 seconds
Started Apr 23 01:07:15 PM PDT 24
Finished Apr 23 01:07:16 PM PDT 24
Peak memory 204748 kb
Host smart-a500dd74-8881-447b-a934-16064a442402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477281648 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.1477281648
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.3710082871
Short name T46
Test name
Test status
Simulation time 41301963 ps
CPU time 0.71 seconds
Started Apr 23 01:08:14 PM PDT 24
Finished Apr 23 01:08:16 PM PDT 24
Peak memory 205024 kb
Host smart-37f8e18c-ca6c-4fb7-86a1-f795266e7a61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710082871 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.3710082871
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.236561172
Short name T54
Test name
Test status
Simulation time 16639215 ps
CPU time 0.7 seconds
Started Apr 23 01:08:14 PM PDT 24
Finished Apr 23 01:08:15 PM PDT 24
Peak memory 204948 kb
Host smart-3fb6f1f9-6125-4448-ac13-a58eaf025bc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236561172 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.236561172
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.3238829787
Short name T45
Test name
Test status
Simulation time 30917168 ps
CPU time 0.7 seconds
Started Apr 23 01:08:13 PM PDT 24
Finished Apr 23 01:08:14 PM PDT 24
Peak memory 204936 kb
Host smart-a1ce4bb9-5e3d-40f9-827e-6d78dd9c3c1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238829787 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.3238829787
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.345284522
Short name T74
Test name
Test status
Simulation time 22261469 ps
CPU time 0.7 seconds
Started Apr 23 01:08:17 PM PDT 24
Finished Apr 23 01:08:18 PM PDT 24
Peak memory 204964 kb
Host smart-7aa91c6e-a0a4-47f7-b663-ba65e4b51d04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345284522 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.345284522
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.3721864618
Short name T1
Test name
Test status
Simulation time 46295424 ps
CPU time 0.71 seconds
Started Apr 23 01:08:17 PM PDT 24
Finished Apr 23 01:08:18 PM PDT 24
Peak memory 204920 kb
Host smart-7f86ebe5-55ca-4e06-9a66-ce0af3c14d17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721864618 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.3721864618
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.261317849
Short name T149
Test name
Test status
Simulation time 17170976 ps
CPU time 0.7 seconds
Started Apr 23 01:08:18 PM PDT 24
Finished Apr 23 01:08:19 PM PDT 24
Peak memory 204936 kb
Host smart-d93507f8-cc64-4723-b6c3-833016592e68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261317849 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.261317849
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.164689442
Short name T59
Test name
Test status
Simulation time 48499763 ps
CPU time 0.71 seconds
Started Apr 23 01:08:21 PM PDT 24
Finished Apr 23 01:08:23 PM PDT 24
Peak memory 205020 kb
Host smart-6bf71d9a-d154-4cf5-871a-dfc63a179113
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164689442 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.164689442
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.4254041145
Short name T133
Test name
Test status
Simulation time 24848573 ps
CPU time 0.69 seconds
Started Apr 23 01:08:17 PM PDT 24
Finished Apr 23 01:08:19 PM PDT 24
Peak memory 204888 kb
Host smart-33acd866-c506-4786-bf60-4c22756d83d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254041145 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.4254041145
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.367777045
Short name T157
Test name
Test status
Simulation time 15150074 ps
CPU time 0.74 seconds
Started Apr 23 01:08:21 PM PDT 24
Finished Apr 23 01:08:22 PM PDT 24
Peak memory 204944 kb
Host smart-9bd0f21f-20d7-45b3-a89e-b702538ad5a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367777045 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.367777045
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.3741413624
Short name T154
Test name
Test status
Simulation time 33360303 ps
CPU time 0.68 seconds
Started Apr 23 01:08:21 PM PDT 24
Finished Apr 23 01:08:23 PM PDT 24
Peak memory 204884 kb
Host smart-4ec3f9eb-ffaf-4b91-874f-03ed56388773
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741413624 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.3741413624
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.3243365940
Short name T143
Test name
Test status
Simulation time 36383922 ps
CPU time 0.72 seconds
Started Apr 23 01:07:25 PM PDT 24
Finished Apr 23 01:07:26 PM PDT 24
Peak memory 204900 kb
Host smart-5307fb1c-47e8-4fe7-9d02-1308fd5431a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243365940 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.3243365940
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.464215084
Short name T158
Test name
Test status
Simulation time 213038816 ps
CPU time 1.28 seconds
Started Apr 23 01:07:20 PM PDT 24
Finished Apr 23 01:07:21 PM PDT 24
Peak memory 204864 kb
Host smart-c74b6c4a-14c3-4f80-ab9f-268def4c23b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464215084 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.464215084
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.1456936434
Short name T56
Test name
Test status
Simulation time 236664275 ps
CPU time 1.4 seconds
Started Apr 23 01:07:21 PM PDT 24
Finished Apr 23 01:07:23 PM PDT 24
Peak memory 229360 kb
Host smart-9ca42367-8e96-4da3-a4d6-79d33b43ba7a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456936434 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.1456936434
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.2808545672
Short name T5
Test name
Test status
Simulation time 26510945 ps
CPU time 0.74 seconds
Started Apr 23 01:08:22 PM PDT 24
Finished Apr 23 01:08:24 PM PDT 24
Peak memory 204956 kb
Host smart-41a800b7-3586-47e9-95a6-074f4e29e18c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808545672 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.2808545672
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.13674769
Short name T136
Test name
Test status
Simulation time 44612666 ps
CPU time 0.73 seconds
Started Apr 23 01:08:22 PM PDT 24
Finished Apr 23 01:08:24 PM PDT 24
Peak memory 204932 kb
Host smart-100ff4de-eda9-44a5-b332-6412b0912de6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13674769 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.13674769
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.922459156
Short name T151
Test name
Test status
Simulation time 44719100 ps
CPU time 0.73 seconds
Started Apr 23 01:08:26 PM PDT 24
Finished Apr 23 01:08:28 PM PDT 24
Peak memory 204980 kb
Host smart-2ed486cd-e44b-4472-8ae5-6e891af22b31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922459156 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.922459156
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.309993982
Short name T162
Test name
Test status
Simulation time 41576814 ps
CPU time 0.71 seconds
Started Apr 23 01:08:25 PM PDT 24
Finished Apr 23 01:08:27 PM PDT 24
Peak memory 204900 kb
Host smart-ded06686-e5e8-4596-9abc-f20436525ed1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309993982 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.309993982
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.283119202
Short name T150
Test name
Test status
Simulation time 54357982 ps
CPU time 0.67 seconds
Started Apr 23 01:08:25 PM PDT 24
Finished Apr 23 01:08:27 PM PDT 24
Peak memory 204936 kb
Host smart-32885479-bbb0-41c4-8ca9-cb0176e81eaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283119202 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.283119202
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.272246766
Short name T47
Test name
Test status
Simulation time 110402991 ps
CPU time 0.71 seconds
Started Apr 23 01:08:26 PM PDT 24
Finished Apr 23 01:08:27 PM PDT 24
Peak memory 204956 kb
Host smart-d177b86f-245e-465d-9a1b-02324746a67a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272246766 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.272246766
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.1317452804
Short name T50
Test name
Test status
Simulation time 32466734 ps
CPU time 0.73 seconds
Started Apr 23 01:08:26 PM PDT 24
Finished Apr 23 01:08:28 PM PDT 24
Peak memory 204940 kb
Host smart-a5d9e1a0-ad3c-4dc9-84bb-a05a09607c33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317452804 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.1317452804
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.1476530990
Short name T137
Test name
Test status
Simulation time 22250761 ps
CPU time 0.71 seconds
Started Apr 23 01:08:30 PM PDT 24
Finished Apr 23 01:08:31 PM PDT 24
Peak memory 204940 kb
Host smart-b9da0346-41be-4d68-a235-db5dda3e9183
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476530990 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.1476530990
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.1561622755
Short name T57
Test name
Test status
Simulation time 34219066 ps
CPU time 0.76 seconds
Started Apr 23 01:08:30 PM PDT 24
Finished Apr 23 01:08:32 PM PDT 24
Peak memory 204976 kb
Host smart-6f5c8be6-c624-4f3f-9309-28d27cf67cad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561622755 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.1561622755
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.1125876526
Short name T152
Test name
Test status
Simulation time 18739461 ps
CPU time 0.7 seconds
Started Apr 23 01:08:30 PM PDT 24
Finished Apr 23 01:08:32 PM PDT 24
Peak memory 204888 kb
Host smart-3a05008f-7c10-488d-9f90-d046a81b97df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125876526 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.1125876526
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.247745445
Short name T29
Test name
Test status
Simulation time 79358343 ps
CPU time 0.73 seconds
Started Apr 23 01:07:28 PM PDT 24
Finished Apr 23 01:07:29 PM PDT 24
Peak memory 204896 kb
Host smart-32887e9e-4968-4299-b1da-9ad18f0d1a47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247745445 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.247745445
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.2305449523
Short name T156
Test name
Test status
Simulation time 70202279 ps
CPU time 0.85 seconds
Started Apr 23 01:07:28 PM PDT 24
Finished Apr 23 01:07:29 PM PDT 24
Peak memory 204776 kb
Host smart-ad452abc-f8b8-4819-8952-89a028256692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305449523 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.2305449523
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.330580631
Short name T55
Test name
Test status
Simulation time 300516033 ps
CPU time 1.98 seconds
Started Apr 23 01:07:28 PM PDT 24
Finished Apr 23 01:07:31 PM PDT 24
Peak memory 229104 kb
Host smart-69264b32-b3cc-44e2-a126-cdf9fbe983a0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330580631 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.330580631
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.2666897158
Short name T138
Test name
Test status
Simulation time 17436502 ps
CPU time 0.73 seconds
Started Apr 23 01:08:30 PM PDT 24
Finished Apr 23 01:08:32 PM PDT 24
Peak memory 204960 kb
Host smart-96f563c5-c1e4-45c5-9416-571944c2a389
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666897158 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.2666897158
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.838099803
Short name T141
Test name
Test status
Simulation time 51751191 ps
CPU time 0.7 seconds
Started Apr 23 01:08:32 PM PDT 24
Finished Apr 23 01:08:33 PM PDT 24
Peak memory 204948 kb
Host smart-e547443d-bcdf-4e23-8396-13ed4241c66e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838099803 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.838099803
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.3758390514
Short name T58
Test name
Test status
Simulation time 27898108 ps
CPU time 0.7 seconds
Started Apr 23 01:08:30 PM PDT 24
Finished Apr 23 01:08:31 PM PDT 24
Peak memory 205000 kb
Host smart-352dcb48-5fbd-4f68-b36c-18a63bc7c091
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758390514 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.3758390514
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.1596525193
Short name T52
Test name
Test status
Simulation time 97767709 ps
CPU time 0.69 seconds
Started Apr 23 01:08:35 PM PDT 24
Finished Apr 23 01:08:37 PM PDT 24
Peak memory 204896 kb
Host smart-dfbc2536-d4da-4139-bb68-ca35a1119851
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596525193 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.1596525193
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.2017063898
Short name T140
Test name
Test status
Simulation time 50977302 ps
CPU time 0.69 seconds
Started Apr 23 01:08:34 PM PDT 24
Finished Apr 23 01:08:35 PM PDT 24
Peak memory 204972 kb
Host smart-aacbf48a-132a-4045-8750-3a5ee95be09f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017063898 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.2017063898
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.1107017976
Short name T49
Test name
Test status
Simulation time 16493146 ps
CPU time 0.73 seconds
Started Apr 23 01:08:35 PM PDT 24
Finished Apr 23 01:08:37 PM PDT 24
Peak memory 204920 kb
Host smart-236a20f8-1764-4595-8f6d-3d8da8e5a76d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107017976 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.1107017976
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.3721481898
Short name T164
Test name
Test status
Simulation time 32682801 ps
CPU time 0.78 seconds
Started Apr 23 01:08:35 PM PDT 24
Finished Apr 23 01:08:36 PM PDT 24
Peak memory 204956 kb
Host smart-6dfc22c4-9fdb-4ba2-8b38-1aef70fceb54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721481898 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.3721481898
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.4204238882
Short name T142
Test name
Test status
Simulation time 193486724 ps
CPU time 0.68 seconds
Started Apr 23 01:08:37 PM PDT 24
Finished Apr 23 01:08:39 PM PDT 24
Peak memory 205024 kb
Host smart-34af97ca-d3a4-4b16-afc1-11d5beb9141f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204238882 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.4204238882
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.1049838774
Short name T48
Test name
Test status
Simulation time 32767934 ps
CPU time 0.74 seconds
Started Apr 23 01:08:38 PM PDT 24
Finished Apr 23 01:08:39 PM PDT 24
Peak memory 204928 kb
Host smart-5593c074-b28e-4b36-af11-52fb4656308c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049838774 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.1049838774
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.1736372911
Short name T70
Test name
Test status
Simulation time 51102055 ps
CPU time 0.71 seconds
Started Apr 23 01:08:38 PM PDT 24
Finished Apr 23 01:08:39 PM PDT 24
Peak memory 204948 kb
Host smart-f57a9893-41a4-4664-84e0-b28ee927f10c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736372911 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.1736372911
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.393104055
Short name T53
Test name
Test status
Simulation time 21105223 ps
CPU time 0.74 seconds
Started Apr 23 01:07:32 PM PDT 24
Finished Apr 23 01:07:33 PM PDT 24
Peak memory 204956 kb
Host smart-acbacf59-f213-4b5c-88b7-51beab8755bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393104055 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.393104055
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.1727465343
Short name T62
Test name
Test status
Simulation time 572935697 ps
CPU time 1.56 seconds
Started Apr 23 01:07:29 PM PDT 24
Finished Apr 23 01:07:31 PM PDT 24
Peak memory 205280 kb
Host smart-4f6fa48b-a0af-4e36-9fc7-38a0e42cf4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727465343 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.1727465343
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.3939569061
Short name T148
Test name
Test status
Simulation time 24631463 ps
CPU time 0.73 seconds
Started Apr 23 01:07:36 PM PDT 24
Finished Apr 23 01:07:37 PM PDT 24
Peak memory 204920 kb
Host smart-57b7991d-5478-4943-9bdc-b1a6337101ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939569061 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.3939569061
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.327700273
Short name T72
Test name
Test status
Simulation time 20930018 ps
CPU time 0.72 seconds
Started Apr 23 01:07:41 PM PDT 24
Finished Apr 23 01:07:42 PM PDT 24
Peak memory 204952 kb
Host smart-787a8638-8b88-48fa-8b17-6c09e5913bfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327700273 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.327700273
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.1748475939
Short name T51
Test name
Test status
Simulation time 26334589 ps
CPU time 0.72 seconds
Started Apr 23 01:07:48 PM PDT 24
Finished Apr 23 01:07:50 PM PDT 24
Peak memory 204920 kb
Host smart-3667db35-997c-43f5-975d-5a2fe58a45fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748475939 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.1748475939
Directory /workspace/9.rv_dm_alert_test/latest
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