Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
79.72 93.86 81.18 87.69 73.08 82.50 98.52 41.19


Total tests in report: 307
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
49.95 49.95 79.25 79.25 46.15 46.15 32.50 32.50 39.74 39.74 59.33 59.33 91.45 91.45 1.19 1.19 /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.614248683
59.88 9.94 82.83 3.58 53.85 7.69 69.19 36.69 51.28 11.54 66.50 7.17 93.35 1.90 2.19 1.00 /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.2336400586
65.99 6.11 83.23 0.40 58.52 4.67 71.80 2.61 58.97 7.69 68.17 1.67 94.40 1.06 26.87 24.68 /workspace/coverage/cover_reg_top/30.rv_dm_tap_fsm_rand_reset.775558604
69.98 3.98 87.46 4.23 67.31 8.79 81.66 9.86 58.97 0.00 70.50 2.33 95.88 1.48 28.06 1.19 /workspace/coverage/default/8.rv_dm_alert_test.613587614
72.47 2.49 89.98 2.52 70.74 3.43 82.58 0.93 64.10 5.13 74.83 4.33 95.99 0.11 29.05 1.00 /workspace/coverage/default/34.rv_dm_stress_all.2195274648
74.26 1.79 90.23 0.25 73.21 2.47 82.90 0.32 64.10 0.00 75.83 1.00 95.99 0.00 37.51 8.46 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3260189917
75.54 1.29 91.94 1.71 75.69 2.47 83.91 1.01 65.38 1.28 78.17 2.33 95.99 0.00 37.71 0.20 /workspace/coverage/default/0.rv_dm_cmderr_busy.1755051131
76.76 1.22 92.40 0.45 78.02 2.34 85.12 1.21 69.23 3.85 78.83 0.67 95.99 0.00 37.71 0.00 /workspace/coverage/default/24.rv_dm_stress_all.1320841334
77.63 0.87 93.05 0.65 79.40 1.37 85.28 0.16 71.79 2.56 80.17 1.33 95.99 0.00 37.71 0.00 /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.1231312211
78.02 0.40 93.05 0.00 79.40 0.00 85.92 0.64 71.79 0.00 80.17 0.00 96.62 0.63 39.20 1.49 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.2886986581
78.32 0.30 93.05 0.00 79.81 0.41 87.29 1.37 71.79 0.00 80.17 0.00 96.73 0.11 39.40 0.20 /workspace/coverage/default/2.rv_dm_sec_cm.3313008222
78.50 0.18 93.05 0.00 79.81 0.00 87.29 0.00 73.08 1.28 80.17 0.00 96.73 0.00 39.40 0.00 /workspace/coverage/default/0.rv_dm_tap_fsm.2456636018
78.67 0.17 93.05 0.00 79.95 0.14 87.61 0.32 73.08 0.00 80.17 0.00 96.73 0.00 40.10 0.70 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1088251891
78.80 0.13 93.05 0.00 79.95 0.00 87.61 0.00 73.08 0.00 80.17 0.00 97.36 0.63 40.40 0.30 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.2720606954
78.92 0.11 93.35 0.30 79.95 0.00 87.61 0.00 73.08 0.00 80.67 0.50 97.36 0.00 40.40 0.00 /workspace/coverage/default/0.rv_dm_abstractcmd_status.4071817694
79.03 0.11 93.40 0.05 80.49 0.55 87.61 0.00 73.08 0.00 80.83 0.17 97.36 0.00 40.40 0.00 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3187578013
79.13 0.11 93.50 0.10 80.63 0.14 87.61 0.00 73.08 0.00 81.33 0.50 97.36 0.00 40.40 0.00 /workspace/coverage/default/0.rv_dm_rom_read_access.109048023
79.23 0.10 93.71 0.20 80.63 0.00 87.61 0.00 73.08 0.00 81.83 0.50 97.36 0.00 40.40 0.00 /workspace/coverage/default/0.rv_dm_cmderr_exception.2798300761
79.32 0.09 93.71 0.00 80.63 0.00 87.61 0.00 73.08 0.00 81.83 0.00 97.99 0.63 40.40 0.00 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.1740317291
79.39 0.07 93.76 0.05 80.91 0.27 87.61 0.00 73.08 0.00 82.00 0.17 97.99 0.00 40.40 0.00 /workspace/coverage/default/0.rv_dm_progbuf_busy.3386798400
79.45 0.06 93.86 0.10 80.91 0.00 87.61 0.00 73.08 0.00 82.33 0.33 97.99 0.00 40.40 0.00 /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.4242029700
79.51 0.06 93.86 0.00 80.91 0.00 87.61 0.00 73.08 0.00 82.33 0.00 97.99 0.00 40.80 0.40 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1700303086
79.55 0.04 93.86 0.00 80.91 0.00 87.61 0.00 73.08 0.00 82.33 0.00 98.20 0.21 40.90 0.10 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.4014556950
79.59 0.04 93.86 0.00 80.91 0.00 87.61 0.00 73.08 0.00 82.50 0.17 98.20 0.00 41.00 0.10 /workspace/coverage/default/11.rv_dm_alert_test.3662783278
79.62 0.03 93.86 0.00 80.91 0.00 87.61 0.00 73.08 0.00 82.50 0.00 98.42 0.21 41.00 0.00 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2807200960
79.65 0.03 93.86 0.00 80.91 0.00 87.69 0.08 73.08 0.00 82.50 0.00 98.42 0.00 41.09 0.10 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3297019200
79.67 0.02 93.86 0.00 81.04 0.14 87.69 0.00 73.08 0.00 82.50 0.00 98.42 0.00 41.09 0.00 /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.2555086666
79.69 0.02 93.86 0.00 81.18 0.14 87.69 0.00 73.08 0.00 82.50 0.00 98.42 0.00 41.09 0.00 /workspace/coverage/default/1.rv_dm_cmderr_busy.3367587110
79.70 0.02 93.86 0.00 81.18 0.00 87.69 0.00 73.08 0.00 82.50 0.00 98.52 0.11 41.09 0.00 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.4021876932
79.72 0.01 93.86 0.00 81.18 0.00 87.69 0.00 73.08 0.00 82.50 0.00 98.52 0.00 41.19 0.10 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.929339679

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3451561193
/workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.1278906135
/workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.1153163751
/workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3191075567
/workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2773094235
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1840433630
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1678674517
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.1521178285
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.1809316719
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1435364461
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3731328948
/workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.3745884042
/workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.1683401523
/workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.843123421
/workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.3593322585
/workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.1385196827
/workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.2085752400
/workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.989812268
/workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.3681696062
/workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2994723668
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2001926992
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.352526323
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1676663693
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.3514670839
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.973388339
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.4087534179
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.3315048732
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.2000531389
/workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.192894551
/workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.2083890439
/workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.1181658482
/workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1009534187
/workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.1692195040
/workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.2864330041
/workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.3035465968
/workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3744767494
/workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1532754632
/workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.1446507455
/workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3586639342
/workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1251635820
/workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.240249427
/workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.1031168936
/workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.840584068
/workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.2001889571
/workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.260523292
/workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.3697499912
/workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.4249471331
/workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.854914288
/workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.1902284621
/workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1704775542
/workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.2209141474
/workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1823654866
/workspace/coverage/cover_reg_top/12.rv_dm_tap_fsm_rand_reset.3966192384
/workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.969501433
/workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.995041142
/workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.807375320
/workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3589805181
/workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2309159938
/workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.9590678
/workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1985388974
/workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.652594350
/workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.290865196
/workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2292348390
/workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.853284855
/workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3751741472
/workspace/coverage/cover_reg_top/14.rv_dm_tap_fsm_rand_reset.2459543473
/workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.2027756366
/workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.2131940807
/workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.431751794
/workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.2365814667
/workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.1784877980
/workspace/coverage/cover_reg_top/15.rv_dm_tap_fsm_rand_reset.2234691161
/workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.2760553446
/workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2799703004
/workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2772785392
/workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.1778293135
/workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2418329737
/workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.703118590
/workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.47525416
/workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.2673263523
/workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.4150005684
/workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.141470293
/workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.111029861
/workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.1572339032
/workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.4193477433
/workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.962913654
/workspace/coverage/cover_reg_top/17.rv_dm_tap_fsm_rand_reset.1222463565
/workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.3351106252
/workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2594655006
/workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2496193256
/workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2663150371
/workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1681880263
/workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2912735459
/workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3261571356
/workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.1681310806
/workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.196393367
/workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.18075149
/workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3935543848
/workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.304107593
/workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.140198790
/workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.2148937752
/workspace/coverage/cover_reg_top/19.rv_dm_tap_fsm_rand_reset.1437173947
/workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3549145
/workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.601898987
/workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.264372871
/workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2093410521
/workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3928266656
/workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.1252002806
/workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.3052158068
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.3594454109
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.3729948608
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.1614062658
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1958705131
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.1849357958
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.3658951189
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.4093209979
/workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2299889823
/workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.3723083365
/workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3637364863
/workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.3370059909
/workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.1513452945
/workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.2313827500
/workspace/coverage/cover_reg_top/21.rv_dm_tap_fsm_rand_reset.2239751209
/workspace/coverage/cover_reg_top/22.rv_dm_tap_fsm_rand_reset.2966630826
/workspace/coverage/cover_reg_top/23.rv_dm_tap_fsm_rand_reset.2309819992
/workspace/coverage/cover_reg_top/24.rv_dm_tap_fsm_rand_reset.1622006405
/workspace/coverage/cover_reg_top/27.rv_dm_tap_fsm_rand_reset.97959576
/workspace/coverage/cover_reg_top/29.rv_dm_tap_fsm_rand_reset.528219259
/workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.3766899545
/workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.209799323
/workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.687250413
/workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.4244206083
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.4001284769
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1090689067
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.1654235820
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.744305147
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.1923074888
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.192793063
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.41478115
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2948721053
/workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.1026323197
/workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.583003896
/workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2407740280
/workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.1063926738
/workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3588733790
/workspace/coverage/cover_reg_top/35.rv_dm_tap_fsm_rand_reset.3601868026
/workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.591169906
/workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.4007926321
/workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2325833792
/workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.3501203929
/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.513145349
/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.369738863
/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.548681903
/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3317241668
/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.2677918661
/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.3404630611
/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.438846158
/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.3905230586
/workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.2648559846
/workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.3088324489
/workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2421055233
/workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.1300766370
/workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.2529335060
/workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.1591129039
/workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3935190613
/workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.2792492428
/workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1119201838
/workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.309867182
/workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2733318171
/workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2521630787
/workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.20165825
/workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.3309632164
/workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2327859537
/workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.1001524989
/workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.545595106
/workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2549509006
/workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3612112515
/workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.2363719441
/workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.1702763545
/workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.2836335025
/workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3518427721
/workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.3072602596
/workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2414236470
/workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.454119558
/workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.576801283
/workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.227989462
/workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.793290942
/workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.315879854
/workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.415406665
/workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.644325200
/workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.2452212671
/workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1363168243
/workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.1833225866
/workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.4128630177
/workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.3982741503
/workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.630045812
/workspace/coverage/default/0.rv_dm_alert_test.1747154874
/workspace/coverage/default/0.rv_dm_cmderr_not_supported.1918820478
/workspace/coverage/default/0.rv_dm_dataaddr_rw_access.2492178843
/workspace/coverage/default/0.rv_dm_hart_unavail.873022387
/workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.2135882436
/workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.968779934
/workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.4154636720
/workspace/coverage/default/0.rv_dm_ndmreset_req.3089360552
/workspace/coverage/default/0.rv_dm_sec_cm.3059497098
/workspace/coverage/default/0.rv_dm_smoke.1921442804
/workspace/coverage/default/1.rv_dm_abstractcmd_status.2456792382
/workspace/coverage/default/1.rv_dm_alert_test.1469601344
/workspace/coverage/default/1.rv_dm_cmderr_exception.4103178277
/workspace/coverage/default/1.rv_dm_cmderr_halt_resume.3307531629
/workspace/coverage/default/1.rv_dm_cmderr_not_supported.1979266063
/workspace/coverage/default/1.rv_dm_dataaddr_rw_access.544073782
/workspace/coverage/default/1.rv_dm_hart_unavail.2627720671
/workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.263248388
/workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.3255305238
/workspace/coverage/default/1.rv_dm_mem_tl_access_halted.1596055588
/workspace/coverage/default/1.rv_dm_ndmreset_req.2928536550
/workspace/coverage/default/1.rv_dm_progbuf_busy.100586306
/workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.6920808
/workspace/coverage/default/1.rv_dm_rom_read_access.2836831252
/workspace/coverage/default/1.rv_dm_sec_cm.3781386887
/workspace/coverage/default/1.rv_dm_smoke.756204450
/workspace/coverage/default/10.rv_dm_alert_test.1574064347
/workspace/coverage/default/12.rv_dm_alert_test.2991661760
/workspace/coverage/default/12.rv_dm_sba_tl_access.428319277
/workspace/coverage/default/13.rv_dm_alert_test.3245026804
/workspace/coverage/default/13.rv_dm_sba_tl_access.535211692
/workspace/coverage/default/14.rv_dm_alert_test.3075560502
/workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.19064865
/workspace/coverage/default/15.rv_dm_alert_test.3174771333
/workspace/coverage/default/16.rv_dm_alert_test.1028866351
/workspace/coverage/default/17.rv_dm_alert_test.2025045453
/workspace/coverage/default/18.rv_dm_alert_test.3196220126
/workspace/coverage/default/19.rv_dm_alert_test.1036579606
/workspace/coverage/default/2.rv_dm_alert_test.2233571908
/workspace/coverage/default/2.rv_dm_hart_unavail.1477281648
/workspace/coverage/default/20.rv_dm_alert_test.3710082871
/workspace/coverage/default/21.rv_dm_alert_test.236561172
/workspace/coverage/default/22.rv_dm_alert_test.3238829787
/workspace/coverage/default/23.rv_dm_alert_test.345284522
/workspace/coverage/default/24.rv_dm_alert_test.3721864618
/workspace/coverage/default/25.rv_dm_alert_test.261317849
/workspace/coverage/default/26.rv_dm_alert_test.164689442
/workspace/coverage/default/27.rv_dm_alert_test.4254041145
/workspace/coverage/default/28.rv_dm_alert_test.367777045
/workspace/coverage/default/29.rv_dm_alert_test.3741413624
/workspace/coverage/default/3.rv_dm_alert_test.3243365940
/workspace/coverage/default/3.rv_dm_hart_unavail.464215084
/workspace/coverage/default/3.rv_dm_sec_cm.1456936434
/workspace/coverage/default/30.rv_dm_alert_test.2808545672
/workspace/coverage/default/31.rv_dm_alert_test.13674769
/workspace/coverage/default/32.rv_dm_alert_test.922459156
/workspace/coverage/default/33.rv_dm_alert_test.309993982
/workspace/coverage/default/34.rv_dm_alert_test.283119202
/workspace/coverage/default/35.rv_dm_alert_test.272246766
/workspace/coverage/default/36.rv_dm_alert_test.1317452804
/workspace/coverage/default/37.rv_dm_alert_test.1476530990
/workspace/coverage/default/38.rv_dm_alert_test.1561622755
/workspace/coverage/default/39.rv_dm_alert_test.1125876526
/workspace/coverage/default/4.rv_dm_alert_test.247745445
/workspace/coverage/default/4.rv_dm_hart_unavail.2305449523
/workspace/coverage/default/4.rv_dm_sec_cm.330580631
/workspace/coverage/default/40.rv_dm_alert_test.2666897158
/workspace/coverage/default/41.rv_dm_alert_test.838099803
/workspace/coverage/default/42.rv_dm_alert_test.3758390514
/workspace/coverage/default/43.rv_dm_alert_test.1596525193
/workspace/coverage/default/44.rv_dm_alert_test.2017063898
/workspace/coverage/default/45.rv_dm_alert_test.1107017976
/workspace/coverage/default/46.rv_dm_alert_test.3721481898
/workspace/coverage/default/47.rv_dm_alert_test.4204238882
/workspace/coverage/default/48.rv_dm_alert_test.1049838774
/workspace/coverage/default/49.rv_dm_alert_test.1736372911
/workspace/coverage/default/5.rv_dm_alert_test.393104055
/workspace/coverage/default/5.rv_dm_sba_tl_access.1727465343
/workspace/coverage/default/6.rv_dm_alert_test.3939569061
/workspace/coverage/default/7.rv_dm_alert_test.327700273
/workspace/coverage/default/9.rv_dm_alert_test.1748475939



Total test records in report: 307
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/24.rv_dm_alert_test.3721864618 Apr 23 01:08:17 PM PDT 24 Apr 23 01:08:18 PM PDT 24 46295424 ps
T2 /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.2492178843 Apr 23 01:06:46 PM PDT 24 Apr 23 01:06:48 PM PDT 24 38782571 ps
T3 /workspace/coverage/default/2.rv_dm_hart_unavail.1477281648 Apr 23 01:07:15 PM PDT 24 Apr 23 01:07:16 PM PDT 24 26100382 ps
T29 /workspace/coverage/default/4.rv_dm_alert_test.247745445 Apr 23 01:07:28 PM PDT 24 Apr 23 01:07:29 PM PDT 24 79358343 ps
T40 /workspace/coverage/default/8.rv_dm_alert_test.613587614 Apr 23 01:07:44 PM PDT 24 Apr 23 01:07:45 PM PDT 24 59180360 ps
T4 /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.614248683 Apr 23 01:06:43 PM PDT 24 Apr 23 01:06:44 PM PDT 24 56655321 ps
T5 /workspace/coverage/default/30.rv_dm_alert_test.2808545672 Apr 23 01:08:22 PM PDT 24 Apr 23 01:08:24 PM PDT 24 26510945 ps
T19 /workspace/coverage/default/11.rv_dm_alert_test.3662783278 Apr 23 01:07:51 PM PDT 24 Apr 23 01:07:53 PM PDT 24 26554815 ps
T54 /workspace/coverage/default/21.rv_dm_alert_test.236561172 Apr 23 01:08:14 PM PDT 24 Apr 23 01:08:15 PM PDT 24 16639215 ps
T6 /workspace/coverage/default/1.rv_dm_abstractcmd_status.2456792382 Apr 23 01:07:15 PM PDT 24 Apr 23 01:07:16 PM PDT 24 182028118 ps
T45 /workspace/coverage/default/22.rv_dm_alert_test.3238829787 Apr 23 01:08:13 PM PDT 24 Apr 23 01:08:14 PM PDT 24 30917168 ps
T49 /workspace/coverage/default/45.rv_dm_alert_test.1107017976 Apr 23 01:08:35 PM PDT 24 Apr 23 01:08:37 PM PDT 24 16493146 ps
T30 /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.968779934 Apr 23 01:06:52 PM PDT 24 Apr 23 01:06:54 PM PDT 24 941496173 ps
T46 /workspace/coverage/default/20.rv_dm_alert_test.3710082871 Apr 23 01:08:14 PM PDT 24 Apr 23 01:08:16 PM PDT 24 41301963 ps
T37 /workspace/coverage/default/2.rv_dm_sec_cm.3313008222 Apr 23 01:07:22 PM PDT 24 Apr 23 01:07:24 PM PDT 24 175517393 ps
T53 /workspace/coverage/default/5.rv_dm_alert_test.393104055 Apr 23 01:07:32 PM PDT 24 Apr 23 01:07:33 PM PDT 24 21105223 ps
T47 /workspace/coverage/default/35.rv_dm_alert_test.272246766 Apr 23 01:08:26 PM PDT 24 Apr 23 01:08:27 PM PDT 24 110402991 ps
T38 /workspace/coverage/default/1.rv_dm_sec_cm.3781386887 Apr 23 01:07:18 PM PDT 24 Apr 23 01:07:20 PM PDT 24 152050761 ps
T57 /workspace/coverage/default/38.rv_dm_alert_test.1561622755 Apr 23 01:08:30 PM PDT 24 Apr 23 01:08:32 PM PDT 24 34219066 ps
T58 /workspace/coverage/default/42.rv_dm_alert_test.3758390514 Apr 23 01:08:30 PM PDT 24 Apr 23 01:08:31 PM PDT 24 27898108 ps
T59 /workspace/coverage/default/26.rv_dm_alert_test.164689442 Apr 23 01:08:21 PM PDT 24 Apr 23 01:08:23 PM PDT 24 48499763 ps
T25 /workspace/coverage/default/1.rv_dm_smoke.756204450 Apr 23 01:07:00 PM PDT 24 Apr 23 01:07:01 PM PDT 24 707056604 ps
T7 /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.4242029700 Apr 23 01:06:55 PM PDT 24 Apr 23 01:06:57 PM PDT 24 54561643 ps
T60 /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.1596055588 Apr 23 01:07:05 PM PDT 24 Apr 23 01:07:07 PM PDT 24 108030410 ps
T50 /workspace/coverage/default/36.rv_dm_alert_test.1317452804 Apr 23 01:08:26 PM PDT 24 Apr 23 01:08:28 PM PDT 24 32466734 ps
T13 /workspace/coverage/default/0.rv_dm_cmderr_exception.2798300761 Apr 23 01:06:40 PM PDT 24 Apr 23 01:06:42 PM PDT 24 194955404 ps
T48 /workspace/coverage/default/48.rv_dm_alert_test.1049838774 Apr 23 01:08:38 PM PDT 24 Apr 23 01:08:39 PM PDT 24 32767934 ps
T134 /workspace/coverage/default/19.rv_dm_alert_test.1036579606 Apr 23 01:08:11 PM PDT 24 Apr 23 01:08:12 PM PDT 24 20804724 ps
T14 /workspace/coverage/default/1.rv_dm_cmderr_busy.3367587110 Apr 23 01:07:05 PM PDT 24 Apr 23 01:07:09 PM PDT 24 2883574614 ps
T21 /workspace/coverage/default/1.rv_dm_progbuf_busy.100586306 Apr 23 01:07:17 PM PDT 24 Apr 23 01:07:18 PM PDT 24 77276863 ps
T138 /workspace/coverage/default/40.rv_dm_alert_test.2666897158 Apr 23 01:08:30 PM PDT 24 Apr 23 01:08:32 PM PDT 24 17436502 ps
T20 /workspace/coverage/default/0.rv_dm_ndmreset_req.3089360552 Apr 23 01:06:53 PM PDT 24 Apr 23 01:06:55 PM PDT 24 477988761 ps
T133 /workspace/coverage/default/27.rv_dm_alert_test.4254041145 Apr 23 01:08:17 PM PDT 24 Apr 23 01:08:19 PM PDT 24 24848573 ps
T155 /workspace/coverage/default/1.rv_dm_alert_test.1469601344 Apr 23 01:07:16 PM PDT 24 Apr 23 01:07:17 PM PDT 24 91760923 ps
T10 /workspace/coverage/default/34.rv_dm_stress_all.2195274648 Apr 23 01:08:26 PM PDT 24 Apr 23 01:08:44 PM PDT 24 5129163782 ps
T151 /workspace/coverage/default/32.rv_dm_alert_test.922459156 Apr 23 01:08:26 PM PDT 24 Apr 23 01:08:28 PM PDT 24 44719100 ps
T51 /workspace/coverage/default/9.rv_dm_alert_test.1748475939 Apr 23 01:07:48 PM PDT 24 Apr 23 01:07:50 PM PDT 24 26334589 ps
T23 /workspace/coverage/default/0.rv_dm_cmderr_busy.1755051131 Apr 23 01:06:37 PM PDT 24 Apr 23 01:06:42 PM PDT 24 1845065887 ps
T39 /workspace/coverage/default/0.rv_dm_sec_cm.3059497098 Apr 23 01:07:01 PM PDT 24 Apr 23 01:07:03 PM PDT 24 373499933 ps
T11 /workspace/coverage/default/1.rv_dm_cmderr_not_supported.1979266063 Apr 23 01:07:04 PM PDT 24 Apr 23 01:07:10 PM PDT 24 5193985999 ps
T52 /workspace/coverage/default/43.rv_dm_alert_test.1596525193 Apr 23 01:08:35 PM PDT 24 Apr 23 01:08:37 PM PDT 24 97767709 ps
T150 /workspace/coverage/default/34.rv_dm_alert_test.283119202 Apr 23 01:08:25 PM PDT 24 Apr 23 01:08:27 PM PDT 24 54357982 ps
T139 /workspace/coverage/default/0.rv_dm_alert_test.1747154874 Apr 23 01:07:03 PM PDT 24 Apr 23 01:07:04 PM PDT 24 61340085 ps
T31 /workspace/coverage/default/13.rv_dm_sba_tl_access.535211692 Apr 23 01:07:51 PM PDT 24 Apr 23 01:07:53 PM PDT 24 326734699 ps
T70 /workspace/coverage/default/49.rv_dm_alert_test.1736372911 Apr 23 01:08:38 PM PDT 24 Apr 23 01:08:39 PM PDT 24 51102055 ps
T15 /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.1231312211 Apr 23 01:07:05 PM PDT 24 Apr 23 01:07:07 PM PDT 24 363909488 ps
T17 /workspace/coverage/default/1.rv_dm_rom_read_access.2836831252 Apr 23 01:07:17 PM PDT 24 Apr 23 01:07:18 PM PDT 24 19389253 ps
T71 /workspace/coverage/default/17.rv_dm_alert_test.2025045453 Apr 23 01:08:04 PM PDT 24 Apr 23 01:08:05 PM PDT 24 59414358 ps
T22 /workspace/coverage/default/0.rv_dm_progbuf_busy.3386798400 Apr 23 01:06:52 PM PDT 24 Apr 23 01:06:54 PM PDT 24 198598983 ps
T72 /workspace/coverage/default/7.rv_dm_alert_test.327700273 Apr 23 01:07:41 PM PDT 24 Apr 23 01:07:42 PM PDT 24 20930018 ps
T73 /workspace/coverage/default/13.rv_dm_alert_test.3245026804 Apr 23 01:07:59 PM PDT 24 Apr 23 01:08:00 PM PDT 24 39452358 ps
T24 /workspace/coverage/default/1.rv_dm_cmderr_exception.4103178277 Apr 23 01:07:04 PM PDT 24 Apr 23 01:07:06 PM PDT 24 548607432 ps
T74 /workspace/coverage/default/23.rv_dm_alert_test.345284522 Apr 23 01:08:17 PM PDT 24 Apr 23 01:08:18 PM PDT 24 22261469 ps
T156 /workspace/coverage/default/4.rv_dm_hart_unavail.2305449523 Apr 23 01:07:28 PM PDT 24 Apr 23 01:07:29 PM PDT 24 70202279 ps
T140 /workspace/coverage/default/44.rv_dm_alert_test.2017063898 Apr 23 01:08:34 PM PDT 24 Apr 23 01:08:35 PM PDT 24 50977302 ps
T32 /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.2336400586 Apr 23 01:08:05 PM PDT 24 Apr 23 01:08:33 PM PDT 24 12254552506 ps
T12 /workspace/coverage/default/0.rv_dm_cmderr_not_supported.1918820478 Apr 23 01:06:37 PM PDT 24 Apr 23 01:06:48 PM PDT 24 3170334011 ps
T148 /workspace/coverage/default/6.rv_dm_alert_test.3939569061 Apr 23 01:07:36 PM PDT 24 Apr 23 01:07:37 PM PDT 24 24631463 ps
T8 /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.3307531629 Apr 23 01:07:11 PM PDT 24 Apr 23 01:07:12 PM PDT 24 382200967 ps
T18 /workspace/coverage/default/0.rv_dm_rom_read_access.109048023 Apr 23 01:06:56 PM PDT 24 Apr 23 01:06:57 PM PDT 24 99221303 ps
T157 /workspace/coverage/default/28.rv_dm_alert_test.367777045 Apr 23 01:08:21 PM PDT 24 Apr 23 01:08:22 PM PDT 24 15150074 ps
T33 /workspace/coverage/default/12.rv_dm_sba_tl_access.428319277 Apr 23 01:07:56 PM PDT 24 Apr 23 01:08:04 PM PDT 24 2245948372 ps
T136 /workspace/coverage/default/31.rv_dm_alert_test.13674769 Apr 23 01:08:22 PM PDT 24 Apr 23 01:08:24 PM PDT 24 44612666 ps
T158 /workspace/coverage/default/3.rv_dm_hart_unavail.464215084 Apr 23 01:07:20 PM PDT 24 Apr 23 01:07:21 PM PDT 24 213038816 ps
T35 /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.263248388 Apr 23 01:07:11 PM PDT 24 Apr 23 01:07:12 PM PDT 24 72094486 ps
T66 /workspace/coverage/default/0.rv_dm_smoke.1921442804 Apr 23 01:06:36 PM PDT 24 Apr 23 01:06:39 PM PDT 24 474753596 ps
T55 /workspace/coverage/default/4.rv_dm_sec_cm.330580631 Apr 23 01:07:28 PM PDT 24 Apr 23 01:07:31 PM PDT 24 300516033 ps
T159 /workspace/coverage/default/1.rv_dm_hart_unavail.2627720671 Apr 23 01:07:14 PM PDT 24 Apr 23 01:07:15 PM PDT 24 94658571 ps
T160 /workspace/coverage/default/12.rv_dm_alert_test.2991661760 Apr 23 01:07:52 PM PDT 24 Apr 23 01:07:53 PM PDT 24 40615098 ps
T154 /workspace/coverage/default/29.rv_dm_alert_test.3741413624 Apr 23 01:08:21 PM PDT 24 Apr 23 01:08:23 PM PDT 24 33360303 ps
T36 /workspace/coverage/default/24.rv_dm_stress_all.1320841334 Apr 23 01:08:16 PM PDT 24 Apr 23 01:08:22 PM PDT 24 1630945580 ps
T27 /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.6920808 Apr 23 01:07:15 PM PDT 24 Apr 23 01:07:17 PM PDT 24 97856789 ps
T143 /workspace/coverage/default/3.rv_dm_alert_test.3243365940 Apr 23 01:07:25 PM PDT 24 Apr 23 01:07:26 PM PDT 24 36383922 ps
T132 /workspace/coverage/default/2.rv_dm_alert_test.2233571908 Apr 23 01:07:21 PM PDT 24 Apr 23 01:07:22 PM PDT 24 41854494 ps
T26 /workspace/coverage/default/1.rv_dm_ndmreset_req.2928536550 Apr 23 01:07:10 PM PDT 24 Apr 23 01:07:12 PM PDT 24 334716483 ps
T161 /workspace/coverage/default/16.rv_dm_alert_test.1028866351 Apr 23 01:08:04 PM PDT 24 Apr 23 01:08:05 PM PDT 24 15996835 ps
T34 /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.19064865 Apr 23 01:07:55 PM PDT 24 Apr 23 01:08:50 PM PDT 24 44753870275 ps
T135 /workspace/coverage/default/15.rv_dm_alert_test.3174771333 Apr 23 01:07:59 PM PDT 24 Apr 23 01:08:00 PM PDT 24 19821885 ps
T141 /workspace/coverage/default/41.rv_dm_alert_test.838099803 Apr 23 01:08:32 PM PDT 24 Apr 23 01:08:33 PM PDT 24 51751191 ps
T131 /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.544073782 Apr 23 01:07:14 PM PDT 24 Apr 23 01:07:15 PM PDT 24 27067873 ps
T152 /workspace/coverage/default/39.rv_dm_alert_test.1125876526 Apr 23 01:08:30 PM PDT 24 Apr 23 01:08:32 PM PDT 24 18739461 ps
T162 /workspace/coverage/default/33.rv_dm_alert_test.309993982 Apr 23 01:08:25 PM PDT 24 Apr 23 01:08:27 PM PDT 24 41576814 ps
T146 /workspace/coverage/default/18.rv_dm_alert_test.3196220126 Apr 23 01:08:12 PM PDT 24 Apr 23 01:08:13 PM PDT 24 49335128 ps
T163 /workspace/coverage/default/0.rv_dm_hart_unavail.873022387 Apr 23 01:06:47 PM PDT 24 Apr 23 01:06:48 PM PDT 24 79579757 ps
T28 /workspace/coverage/default/0.rv_dm_abstractcmd_status.4071817694 Apr 23 01:06:57 PM PDT 24 Apr 23 01:06:59 PM PDT 24 27117820 ps
T149 /workspace/coverage/default/25.rv_dm_alert_test.261317849 Apr 23 01:08:18 PM PDT 24 Apr 23 01:08:19 PM PDT 24 17170976 ps
T56 /workspace/coverage/default/3.rv_dm_sec_cm.1456936434 Apr 23 01:07:21 PM PDT 24 Apr 23 01:07:23 PM PDT 24 236664275 ps
T164 /workspace/coverage/default/46.rv_dm_alert_test.3721481898 Apr 23 01:08:35 PM PDT 24 Apr 23 01:08:36 PM PDT 24 32682801 ps
T9 /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.2555086666 Apr 23 01:06:46 PM PDT 24 Apr 23 01:06:48 PM PDT 24 948684537 ps
T62 /workspace/coverage/default/5.rv_dm_sba_tl_access.1727465343 Apr 23 01:07:29 PM PDT 24 Apr 23 01:07:31 PM PDT 24 572935697 ps
T142 /workspace/coverage/default/47.rv_dm_alert_test.4204238882 Apr 23 01:08:37 PM PDT 24 Apr 23 01:08:39 PM PDT 24 193486724 ps
T153 /workspace/coverage/default/14.rv_dm_alert_test.3075560502 Apr 23 01:07:55 PM PDT 24 Apr 23 01:07:56 PM PDT 24 132742470 ps
T16 /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.4154636720 Apr 23 01:06:47 PM PDT 24 Apr 23 01:06:50 PM PDT 24 362279849 ps
T137 /workspace/coverage/default/37.rv_dm_alert_test.1476530990 Apr 23 01:08:30 PM PDT 24 Apr 23 01:08:31 PM PDT 24 22250761 ps
T165 /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.2135882436 Apr 23 01:06:52 PM PDT 24 Apr 23 01:06:54 PM PDT 24 379906790 ps
T63 /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.3255305238 Apr 23 01:07:10 PM PDT 24 Apr 23 01:07:12 PM PDT 24 129701170 ps
T145 /workspace/coverage/default/10.rv_dm_alert_test.1574064347 Apr 23 01:07:48 PM PDT 24 Apr 23 01:07:50 PM PDT 24 34702702 ps
T61 /workspace/coverage/default/0.rv_dm_tap_fsm.2456636018 Apr 23 01:06:35 PM PDT 24 Apr 23 01:06:39 PM PDT 24 2285771933 ps
T41 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2414236470 Apr 23 02:11:58 PM PDT 24 Apr 23 02:12:08 PM PDT 24 560943297 ps
T166 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.840584068 Apr 23 02:12:00 PM PDT 24 Apr 23 02:12:02 PM PDT 24 355762637 ps
T44 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.3351106252 Apr 23 02:12:17 PM PDT 24 Apr 23 02:12:20 PM PDT 24 68381393 ps
T42 /workspace/coverage/cover_reg_top/30.rv_dm_tap_fsm_rand_reset.775558604 Apr 23 02:12:23 PM PDT 24 Apr 23 02:13:08 PM PDT 24 12947265505 ps
T69 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.3697499912 Apr 23 02:12:10 PM PDT 24 Apr 23 02:12:15 PM PDT 24 138757811 ps
T67 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.973388339 Apr 23 02:11:51 PM PDT 24 Apr 23 02:11:52 PM PDT 24 102687609 ps
T167 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.369738863 Apr 23 02:11:55 PM PDT 24 Apr 23 02:13:28 PM PDT 24 27714198012 ps
T168 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.513145349 Apr 23 02:11:51 PM PDT 24 Apr 23 02:12:06 PM PDT 24 7749911503 ps
T169 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.1521178285 Apr 23 02:11:44 PM PDT 24 Apr 23 02:11:47 PM PDT 24 766283596 ps
T170 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.3729948608 Apr 23 02:11:51 PM PDT 24 Apr 23 02:12:12 PM PDT 24 40726702798 ps
T171 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1676663693 Apr 23 02:11:47 PM PDT 24 Apr 23 02:11:49 PM PDT 24 1605984442 ps
T64 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3187578013 Apr 23 02:11:43 PM PDT 24 Apr 23 02:11:44 PM PDT 24 110887892 ps
T75 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.1063926738 Apr 23 02:11:48 PM PDT 24 Apr 23 02:11:53 PM PDT 24 452053906 ps
T43 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.240249427 Apr 23 02:12:08 PM PDT 24 Apr 23 02:12:11 PM PDT 24 87091553 ps
T172 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.583003896 Apr 23 02:11:49 PM PDT 24 Apr 23 02:11:50 PM PDT 24 22419299 ps
T81 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.4007926321 Apr 23 02:11:55 PM PDT 24 Apr 23 02:11:58 PM PDT 24 950895852 ps
T173 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.807375320 Apr 23 02:12:12 PM PDT 24 Apr 23 02:12:15 PM PDT 24 455228059 ps
T68 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.853284855 Apr 23 02:12:07 PM PDT 24 Apr 23 02:12:09 PM PDT 24 195464045 ps
T76 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3588733790 Apr 23 02:11:48 PM PDT 24 Apr 23 02:11:57 PM PDT 24 465040309 ps
T174 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.3745884042 Apr 23 02:11:45 PM PDT 24 Apr 23 02:11:46 PM PDT 24 35485941 ps
T77 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3260189917 Apr 23 02:11:59 PM PDT 24 Apr 23 02:12:10 PM PDT 24 1012263755 ps
T65 /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.4128630177 Apr 23 02:12:00 PM PDT 24 Apr 23 02:12:11 PM PDT 24 20105762070 ps
T175 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.3514670839 Apr 23 02:11:49 PM PDT 24 Apr 23 02:11:51 PM PDT 24 416662645 ps
T78 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.4014556950 Apr 23 02:11:55 PM PDT 24 Apr 23 02:12:00 PM PDT 24 2045408719 ps
T82 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3751741472 Apr 23 02:12:12 PM PDT 24 Apr 23 02:12:17 PM PDT 24 320275681 ps
T83 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.2886986581 Apr 23 02:12:00 PM PDT 24 Apr 23 02:12:04 PM PDT 24 2268651254 ps
T176 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.2677918661 Apr 23 02:11:53 PM PDT 24 Apr 23 02:11:55 PM PDT 24 77934484 ps
T79 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.309867182 Apr 23 02:11:59 PM PDT 24 Apr 23 02:12:04 PM PDT 24 711461816 ps
T80 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.652594350 Apr 23 02:12:11 PM PDT 24 Apr 23 02:12:19 PM PDT 24 4135406608 ps
T84 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1119201838 Apr 23 02:11:58 PM PDT 24 Apr 23 02:12:03 PM PDT 24 823195198 ps
T91 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.601898987 Apr 23 02:12:17 PM PDT 24 Apr 23 02:12:28 PM PDT 24 1730082783 ps
T129 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.196393367 Apr 23 02:12:17 PM PDT 24 Apr 23 02:12:25 PM PDT 24 755963605 ps
T113 /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.3370059909 Apr 23 02:11:57 PM PDT 24 Apr 23 02:12:27 PM PDT 24 14680010824 ps
T85 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1823654866 Apr 23 02:12:07 PM PDT 24 Apr 23 02:12:14 PM PDT 24 392411301 ps
T114 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.2673263523 Apr 23 02:12:14 PM PDT 24 Apr 23 02:12:20 PM PDT 24 1538230848 ps
T86 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.1181658482 Apr 23 02:11:50 PM PDT 24 Apr 23 02:12:00 PM PDT 24 3317028796 ps
T147 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.1681310806 Apr 23 02:12:11 PM PDT 24 Apr 23 02:12:15 PM PDT 24 75769667 ps
T177 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.454119558 Apr 23 02:12:02 PM PDT 24 Apr 23 02:12:04 PM PDT 24 38385386 ps
T178 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.18075149 Apr 23 02:12:21 PM PDT 24 Apr 23 02:12:23 PM PDT 24 119040619 ps
T179 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1840433630 Apr 23 02:11:47 PM PDT 24 Apr 23 02:12:16 PM PDT 24 22849827632 ps
T180 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.2209141474 Apr 23 02:12:04 PM PDT 24 Apr 23 02:12:05 PM PDT 24 79796115 ps
T87 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.4244206083 Apr 23 02:11:53 PM PDT 24 Apr 23 02:11:55 PM PDT 24 112975681 ps
T88 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.1833225866 Apr 23 02:12:05 PM PDT 24 Apr 23 02:12:09 PM PDT 24 1031541918 ps
T89 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.1902284621 Apr 23 02:12:07 PM PDT 24 Apr 23 02:12:09 PM PDT 24 50582474 ps
T90 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.47525416 Apr 23 02:12:12 PM PDT 24 Apr 23 02:12:18 PM PDT 24 1609403073 ps
T115 /workspace/coverage/cover_reg_top/14.rv_dm_tap_fsm_rand_reset.2459543473 Apr 23 02:12:13 PM PDT 24 Apr 23 02:12:34 PM PDT 24 11451573381 ps
T116 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3191075567 Apr 23 02:11:54 PM PDT 24 Apr 23 02:12:00 PM PDT 24 1172901299 ps
T181 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.3088324489 Apr 23 02:11:58 PM PDT 24 Apr 23 02:12:00 PM PDT 24 30107907 ps
T96 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.260523292 Apr 23 02:12:05 PM PDT 24 Apr 23 02:12:12 PM PDT 24 314785215 ps
T182 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2912735459 Apr 23 02:12:15 PM PDT 24 Apr 23 02:12:17 PM PDT 24 44082176 ps
T121 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1088251891 Apr 23 02:11:54 PM PDT 24 Apr 23 02:12:14 PM PDT 24 1940147406 ps
T110 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3637364863 Apr 23 02:11:52 PM PDT 24 Apr 23 02:11:56 PM PDT 24 145564878 ps
T183 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.1252002806 Apr 23 02:11:47 PM PDT 24 Apr 23 02:11:51 PM PDT 24 68481587 ps
T112 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3928266656 Apr 23 02:11:48 PM PDT 24 Apr 23 02:11:51 PM PDT 24 106209718 ps
T125 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1700303086 Apr 23 02:12:10 PM PDT 24 Apr 23 02:12:19 PM PDT 24 264407784 ps
T184 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1681880263 Apr 23 02:12:15 PM PDT 24 Apr 23 02:12:19 PM PDT 24 899797323 ps
T117 /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2421055233 Apr 23 02:11:52 PM PDT 24 Apr 23 02:12:12 PM PDT 24 4328156596 ps
T144 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3549145 Apr 23 02:12:16 PM PDT 24 Apr 23 02:12:23 PM PDT 24 277171753 ps
T185 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1704775542 Apr 23 02:12:04 PM PDT 24 Apr 23 02:12:06 PM PDT 24 289802068 ps
T97 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.2363719441 Apr 23 02:12:00 PM PDT 24 Apr 23 02:12:02 PM PDT 24 43120250 ps
T122 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.2313827500 Apr 23 02:11:47 PM PDT 24 Apr 23 02:12:08 PM PDT 24 3467527839 ps
T111 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.962913654 Apr 23 02:12:13 PM PDT 24 Apr 23 02:12:18 PM PDT 24 635361032 ps
T98 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.2720606954 Apr 23 02:11:56 PM PDT 24 Apr 23 02:12:52 PM PDT 24 5608794066 ps
T186 /workspace/coverage/cover_reg_top/21.rv_dm_tap_fsm_rand_reset.2239751209 Apr 23 02:12:21 PM PDT 24 Apr 23 02:12:45 PM PDT 24 8251411800 ps
T187 /workspace/coverage/cover_reg_top/12.rv_dm_tap_fsm_rand_reset.3966192384 Apr 23 02:12:04 PM PDT 24 Apr 23 02:12:16 PM PDT 24 18656675902 ps
T99 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.3501203929 Apr 23 02:11:54 PM PDT 24 Apr 23 02:11:57 PM PDT 24 93898001 ps
T188 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.2365814667 Apr 23 02:12:11 PM PDT 24 Apr 23 02:12:13 PM PDT 24 57700408 ps
T189 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.3594454109 Apr 23 02:11:57 PM PDT 24 Apr 23 02:12:06 PM PDT 24 3790174701 ps
T190 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.969501433 Apr 23 02:12:09 PM PDT 24 Apr 23 02:12:12 PM PDT 24 206530502 ps
T100 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3261571356 Apr 23 02:12:17 PM PDT 24 Apr 23 02:12:22 PM PDT 24 1967599333 ps
T191 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.1923074888 Apr 23 02:11:48 PM PDT 24 Apr 23 02:11:49 PM PDT 24 62110652 ps
T119 /workspace/coverage/cover_reg_top/29.rv_dm_tap_fsm_rand_reset.528219259 Apr 23 02:12:25 PM PDT 24 Apr 23 02:12:44 PM PDT 24 9126313621 ps
T192 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.431751794 Apr 23 02:12:10 PM PDT 24 Apr 23 02:12:19 PM PDT 24 2435115964 ps
T193 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.140198790 Apr 23 02:12:17 PM PDT 24 Apr 23 02:12:18 PM PDT 24 88516568 ps
T194 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1363168243 Apr 23 02:11:59 PM PDT 24 Apr 23 02:12:01 PM PDT 24 138657249 ps
T195 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.2001889571 Apr 23 02:12:02 PM PDT 24 Apr 23 02:12:04 PM PDT 24 40881776 ps
T104 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3935543848 Apr 23 02:12:15 PM PDT 24 Apr 23 02:12:17 PM PDT 24 58522450 ps
T118 /workspace/coverage/cover_reg_top/17.rv_dm_tap_fsm_rand_reset.1222463565 Apr 23 02:12:14 PM PDT 24 Apr 23 02:12:31 PM PDT 24 9490574050 ps
T196 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.3681696062 Apr 23 02:11:48 PM PDT 24 Apr 23 02:11:50 PM PDT 24 518765448 ps
T197 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.2131940807 Apr 23 02:12:12 PM PDT 24 Apr 23 02:12:17 PM PDT 24 169319543 ps
T198 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.4093209979 Apr 23 02:11:49 PM PDT 24 Apr 23 02:11:50 PM PDT 24 80222786 ps
T120 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.415406665 Apr 23 02:11:58 PM PDT 24 Apr 23 02:12:02 PM PDT 24 65489152 ps
T199 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.3723083365 Apr 23 02:11:54 PM PDT 24 Apr 23 02:11:56 PM PDT 24 28758168 ps
T200 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.2529335060 Apr 23 02:11:56 PM PDT 24 Apr 23 02:12:10 PM PDT 24 6141527177 ps
T201 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1678674517 Apr 23 02:11:46 PM PDT 24 Apr 23 02:12:16 PM PDT 24 20657835394 ps
T202 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2001926992 Apr 23 02:11:55 PM PDT 24 Apr 23 02:12:02 PM PDT 24 3807317396 ps
T203 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2948721053 Apr 23 02:11:49 PM PDT 24 Apr 23 02:11:50 PM PDT 24 42861835 ps
T204 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2549509006 Apr 23 02:11:59 PM PDT 24 Apr 23 02:12:10 PM PDT 24 588158228 ps
T205 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3744767494 Apr 23 02:12:03 PM PDT 24 Apr 23 02:12:06 PM PDT 24 741921692 ps
T206 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1009534187 Apr 23 02:11:47 PM PDT 24 Apr 23 02:11:52 PM PDT 24 421748018 ps
T207 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2663150371 Apr 23 02:12:16 PM PDT 24 Apr 23 02:12:18 PM PDT 24 52314443 ps
T208 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3518427721 Apr 23 02:12:07 PM PDT 24 Apr 23 02:12:11 PM PDT 24 390805524 ps
T105 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2994723668 Apr 23 02:11:51 PM PDT 24 Apr 23 02:11:54 PM PDT 24 329955218 ps
T123 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.1385196827 Apr 23 02:11:48 PM PDT 24 Apr 23 02:11:57 PM PDT 24 897767283 ps
T209 /workspace/coverage/cover_reg_top/19.rv_dm_tap_fsm_rand_reset.1437173947 Apr 23 02:12:16 PM PDT 24 Apr 23 02:12:30 PM PDT 24 11503911530 ps
T106 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2093410521 Apr 23 02:11:48 PM PDT 24 Apr 23 02:12:55 PM PDT 24 5195892308 ps
T210 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2418329737 Apr 23 02:12:17 PM PDT 24 Apr 23 02:12:21 PM PDT 24 1763174962 ps
T107 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.111029861 Apr 23 02:12:15 PM PDT 24 Apr 23 02:12:19 PM PDT 24 177935684 ps
T128 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1985388974 Apr 23 02:12:10 PM PDT 24 Apr 23 02:12:21 PM PDT 24 1509077660 ps
T92 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2807200960 Apr 23 02:11:43 PM PDT 24 Apr 23 02:11:47 PM PDT 24 2316817308 ps
T211 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.3593322585 Apr 23 02:11:48 PM PDT 24 Apr 23 02:11:54 PM PDT 24 237808237 ps
T124 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.4150005684 Apr 23 02:12:16 PM PDT 24 Apr 23 02:12:25 PM PDT 24 514004608 ps
T212 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.192894551 Apr 23 02:11:47 PM PDT 24 Apr 23 02:11:49 PM PDT 24 43299267 ps
T213 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.3982741503 Apr 23 02:12:00 PM PDT 24 Apr 23 02:12:05 PM PDT 24 249309873 ps
T214 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.2083890439 Apr 23 02:11:49 PM PDT 24 Apr 23 02:11:50 PM PDT 24 46786842 ps
T215 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2594655006 Apr 23 02:12:17 PM PDT 24 Apr 23 02:12:28 PM PDT 24 641024219 ps
T130 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2733318171 Apr 23 02:11:55 PM PDT 24 Apr 23 02:12:05 PM PDT 24 536927257 ps
T216 /workspace/coverage/cover_reg_top/24.rv_dm_tap_fsm_rand_reset.1622006405 Apr 23 02:12:20 PM PDT 24 Apr 23 02:12:51 PM PDT 24 17144572582 ps
T217 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.1784877980 Apr 23 02:12:11 PM PDT 24 Apr 23 02:12:16 PM PDT 24 86962562 ps
T218 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.227989462 Apr 23 02:11:59 PM PDT 24 Apr 23 02:12:01 PM PDT 24 564473330 ps
T219 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.3309632164 Apr 23 02:11:57 PM PDT 24 Apr 23 02:11:59 PM PDT 24 949953526 ps
T126 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3297019200 Apr 23 02:12:13 PM PDT 24 Apr 23 02:12:34 PM PDT 24 1209922685 ps
T220 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.644325200 Apr 23 02:12:00 PM PDT 24 Apr 23 02:12:09 PM PDT 24 3474410452 ps
T221 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.290865196 Apr 23 02:12:09 PM PDT 24 Apr 23 02:12:13 PM PDT 24 633322500 ps
T93 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.548681903 Apr 23 02:11:52 PM PDT 24 Apr 23 02:11:54 PM PDT 24 1733038561 ps
T222 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.1683401523 Apr 23 02:11:51 PM PDT 24 Apr 23 02:11:52 PM PDT 24 48524158 ps
T223 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.687250413 Apr 23 02:11:53 PM PDT 24 Apr 23 02:11:58 PM PDT 24 3444869646 ps
T108 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.1591129039 Apr 23 02:11:58 PM PDT 24 Apr 23 02:12:00 PM PDT 24 30264557 ps
T224 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3586639342 Apr 23 02:12:02 PM PDT 24 Apr 23 02:12:06 PM PDT 24 95160613 ps
T225 /workspace/coverage/cover_reg_top/22.rv_dm_tap_fsm_rand_reset.2966630826 Apr 23 02:12:19 PM PDT 24 Apr 23 02:12:39 PM PDT 24 7583680356 ps
T226 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.1513452945 Apr 23 02:11:48 PM PDT 24 Apr 23 02:11:52 PM PDT 24 118238319 ps
T227 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.3315048732 Apr 23 02:11:47 PM PDT 24 Apr 23 02:11:49 PM PDT 24 90687940 ps
T94 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.1614062658 Apr 23 02:11:52 PM PDT 24 Apr 23 02:11:54 PM PDT 24 780280182 ps
T228 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.703118590 Apr 23 02:12:11 PM PDT 24 Apr 23 02:12:13 PM PDT 24 77300549 ps
T127 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1251635820 Apr 23 02:12:01 PM PDT 24 Apr 23 02:12:20 PM PDT 24 2608906920 ps
T229 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.2792492428 Apr 23 02:11:58 PM PDT 24 Apr 23 02:12:00 PM PDT 24 32049987 ps
T230 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.4249471331 Apr 23 02:12:06 PM PDT 24 Apr 23 02:12:15 PM PDT 24 667987727 ps
T231 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3589805181 Apr 23 02:12:07 PM PDT 24 Apr 23 02:12:09 PM PDT 24 50728271 ps
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T235 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.843123421 Apr 23 02:11:47 PM PDT 24 Apr 23 02:11:50 PM PDT 24 81196933 ps
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T237 /workspace/coverage/cover_reg_top/15.rv_dm_tap_fsm_rand_reset.2234691161 Apr 23 02:12:11 PM PDT 24 Apr 23 02:12:26 PM PDT 24 11774280109 ps
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T239 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.2085752400 Apr 23 02:11:54 PM PDT 24 Apr 23 02:13:12 PM PDT 24 31065484534 ps
T240 /workspace/coverage/cover_reg_top/27.rv_dm_tap_fsm_rand_reset.97959576 Apr 23 02:12:25 PM PDT 24 Apr 23 02:12:51 PM PDT 24 26739819346 ps
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T243 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.41478115 Apr 23 02:11:53 PM PDT 24 Apr 23 02:11:54 PM PDT 24 141617043 ps
T244 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3731328948 Apr 23 02:11:42 PM PDT 24 Apr 23 02:11:44 PM PDT 24 141095320 ps
T245 /workspace/coverage/cover_reg_top/23.rv_dm_tap_fsm_rand_reset.2309819992 Apr 23 02:12:19 PM PDT 24 Apr 23 02:12:37 PM PDT 24 9486573105 ps
T246 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.1001524989 Apr 23 02:12:00 PM PDT 24 Apr 23 02:12:07 PM PDT 24 823169299 ps
T247 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.1026323197 Apr 23 02:11:53 PM PDT 24 Apr 23 02:11:54 PM PDT 24 54733551 ps
T248 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2407740280 Apr 23 02:11:51 PM PDT 24 Apr 23 02:11:59 PM PDT 24 866544782 ps
T249 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.2452212671 Apr 23 02:11:58 PM PDT 24 Apr 23 02:12:01 PM PDT 24 197816154 ps
T250 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2299889823 Apr 23 02:11:51 PM PDT 24 Apr 23 02:11:52 PM PDT 24 47716870 ps
T251 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.3072602596 Apr 23 02:11:57 PM PDT 24 Apr 23 02:12:03 PM PDT 24 448727849 ps
T252 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.315879854 Apr 23 02:11:57 PM PDT 24 Apr 23 02:12:06 PM PDT 24 1574861269 ps
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T254 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3317241668 Apr 23 02:11:52 PM PDT 24 Apr 23 02:11:54 PM PDT 24 425427949 ps
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