Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
75.74 90.33 76.92 86.93 64.10 76.17 98.42 37.33


Total test records in report: 304
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html
T258 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.1691047233 Apr 25 12:48:11 PM PDT 24 Apr 25 12:48:17 PM PDT 24 77878037 ps
T259 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.1372168796 Apr 25 12:48:08 PM PDT 24 Apr 25 12:48:11 PM PDT 24 598418168 ps
T260 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.3910330190 Apr 25 12:48:38 PM PDT 24 Apr 25 12:48:42 PM PDT 24 116709323 ps
T261 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.1074027027 Apr 25 12:47:53 PM PDT 24 Apr 25 12:48:01 PM PDT 24 389709408 ps
T262 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.681742788 Apr 25 12:47:58 PM PDT 24 Apr 25 12:49:59 PM PDT 24 34379063121 ps
T263 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.2358135711 Apr 25 12:48:04 PM PDT 24 Apr 25 12:48:07 PM PDT 24 154116556 ps
T264 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.751999537 Apr 25 12:48:11 PM PDT 24 Apr 25 12:48:13 PM PDT 24 21656512 ps
T265 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.1461590051 Apr 25 12:48:05 PM PDT 24 Apr 25 12:48:10 PM PDT 24 95396309 ps
T266 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3119041620 Apr 25 12:48:25 PM PDT 24 Apr 25 12:48:27 PM PDT 24 84029332 ps
T267 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.873075966 Apr 25 12:48:30 PM PDT 24 Apr 25 12:48:32 PM PDT 24 48358826 ps
T136 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.2317903690 Apr 25 12:48:31 PM PDT 24 Apr 25 12:48:47 PM PDT 24 432234271 ps
T268 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.2633976183 Apr 25 12:48:31 PM PDT 24 Apr 25 12:48:33 PM PDT 24 111159991 ps
T77 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.382202042 Apr 25 12:47:48 PM PDT 24 Apr 25 12:48:11 PM PDT 24 986400913 ps
T269 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1827049214 Apr 25 12:48:08 PM PDT 24 Apr 25 12:48:10 PM PDT 24 64643034 ps
T270 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.3417803888 Apr 25 12:48:28 PM PDT 24 Apr 25 12:48:31 PM PDT 24 69175364 ps
T271 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.4040588355 Apr 25 12:48:29 PM PDT 24 Apr 25 12:48:32 PM PDT 24 789673738 ps
T272 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2618883274 Apr 25 12:48:26 PM PDT 24 Apr 25 12:48:33 PM PDT 24 106943373 ps
T273 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.367068401 Apr 25 12:48:23 PM PDT 24 Apr 25 12:48:32 PM PDT 24 825202054 ps
T274 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.3777618372 Apr 25 12:48:39 PM PDT 24 Apr 25 12:48:44 PM PDT 24 364286134 ps
T85 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.2488686973 Apr 25 12:48:10 PM PDT 24 Apr 25 12:48:12 PM PDT 24 63802803 ps
T275 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2974395873 Apr 25 12:48:15 PM PDT 24 Apr 25 12:48:17 PM PDT 24 88032215 ps
T276 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.3883567004 Apr 25 12:48:15 PM PDT 24 Apr 25 12:49:16 PM PDT 24 16153808463 ps
T277 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2947781528 Apr 25 12:48:36 PM PDT 24 Apr 25 12:48:48 PM PDT 24 1330359861 ps
T278 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.381476969 Apr 25 12:48:01 PM PDT 24 Apr 25 12:48:03 PM PDT 24 54339805 ps
T84 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2938344539 Apr 25 12:49:12 PM PDT 24 Apr 25 12:49:33 PM PDT 24 3754171679 ps
T279 /workspace/coverage/cover_reg_top/25.rv_dm_tap_fsm_rand_reset.1618617559 Apr 25 12:48:48 PM PDT 24 Apr 25 12:49:17 PM PDT 24 29264626312 ps
T280 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.3458328175 Apr 25 12:48:38 PM PDT 24 Apr 25 12:48:42 PM PDT 24 1255593770 ps
T281 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3092542121 Apr 25 12:48:08 PM PDT 24 Apr 25 12:48:14 PM PDT 24 2276083291 ps
T282 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.3926676532 Apr 25 12:48:37 PM PDT 24 Apr 25 12:48:41 PM PDT 24 401889328 ps
T283 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.2000960996 Apr 25 12:48:11 PM PDT 24 Apr 25 12:48:35 PM PDT 24 23810072857 ps
T284 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3639682607 Apr 25 12:48:29 PM PDT 24 Apr 25 12:48:38 PM PDT 24 294507019 ps
T285 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.1325159270 Apr 25 12:48:40 PM PDT 24 Apr 25 12:48:43 PM PDT 24 90196781 ps
T86 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.2445918862 Apr 25 12:48:05 PM PDT 24 Apr 25 12:48:17 PM PDT 24 1248000216 ps
T286 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2961146444 Apr 25 12:48:10 PM PDT 24 Apr 25 12:48:44 PM PDT 24 3965405076 ps
T287 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.872574086 Apr 25 12:48:26 PM PDT 24 Apr 25 12:48:30 PM PDT 24 118836983 ps
T288 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.868336576 Apr 25 12:48:03 PM PDT 24 Apr 25 12:48:14 PM PDT 24 9791814545 ps
T289 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.2075673437 Apr 25 12:48:26 PM PDT 24 Apr 25 12:48:27 PM PDT 24 50079358 ps
T290 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.3518963378 Apr 25 12:48:20 PM PDT 24 Apr 25 12:48:48 PM PDT 24 729416313 ps
T291 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.2978165050 Apr 25 12:48:11 PM PDT 24 Apr 25 12:48:41 PM PDT 24 1205309526 ps
T139 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.902210592 Apr 25 12:48:28 PM PDT 24 Apr 25 12:48:41 PM PDT 24 4416691002 ps
T292 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.595470114 Apr 25 12:48:31 PM PDT 24 Apr 25 12:48:36 PM PDT 24 535872152 ps
T293 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.1482980937 Apr 25 12:48:07 PM PDT 24 Apr 25 12:48:16 PM PDT 24 1398804079 ps
T122 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.1444205634 Apr 25 12:48:36 PM PDT 24 Apr 25 12:48:40 PM PDT 24 210352571 ps
T294 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.3212060474 Apr 25 12:48:12 PM PDT 24 Apr 25 12:48:52 PM PDT 24 9632749270 ps
T295 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.534350118 Apr 25 12:48:01 PM PDT 24 Apr 25 12:48:03 PM PDT 24 186063727 ps
T296 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.1165751653 Apr 25 12:48:22 PM PDT 24 Apr 25 12:48:42 PM PDT 24 1119378257 ps
T297 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.4279162334 Apr 25 12:48:03 PM PDT 24 Apr 25 12:48:05 PM PDT 24 124883297 ps
T298 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.4184343003 Apr 25 12:48:00 PM PDT 24 Apr 25 12:48:02 PM PDT 24 72660049 ps
T299 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.3787342497 Apr 25 12:48:13 PM PDT 24 Apr 25 12:48:17 PM PDT 24 105079242 ps
T300 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.2016023997 Apr 25 12:48:18 PM PDT 24 Apr 25 12:48:20 PM PDT 24 183507594 ps
T301 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.2868812045 Apr 25 12:48:11 PM PDT 24 Apr 25 12:48:16 PM PDT 24 112013675 ps
T302 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.3244201 Apr 25 12:48:24 PM PDT 24 Apr 25 12:48:25 PM PDT 24 379618992 ps
T303 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.3666522356 Apr 25 12:48:26 PM PDT 24 Apr 25 12:48:30 PM PDT 24 760890303 ps
T304 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1031134166 Apr 25 12:48:13 PM PDT 24 Apr 25 12:48:25 PM PDT 24 3073211616 ps

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.3253036955
Short name T7
Test name
Test status
Simulation time 3054780803 ps
CPU time 4.38 seconds
Started Apr 25 12:49:51 PM PDT 24
Finished Apr 25 12:50:02 PM PDT 24
Peak memory 205500 kb
Host smart-f8db8076-5b7b-45e3-9708-8fe055112e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253036955 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.3253036955
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.2844871225
Short name T38
Test name
Test status
Simulation time 40961081 ps
CPU time 0.74 seconds
Started Apr 25 12:49:56 PM PDT 24
Finished Apr 25 12:49:59 PM PDT 24
Peak memory 205084 kb
Host smart-f72539a4-e277-4b5b-abba-13f35d9c005f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844871225 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.2844871225
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_stress_all.772511348
Short name T14
Test name
Test status
Simulation time 7218816469 ps
CPU time 15.76 seconds
Started Apr 25 12:49:54 PM PDT 24
Finished Apr 25 12:50:12 PM PDT 24
Peak memory 213676 kb
Host smart-773a4600-b204-4870-8788-0e83956e3b7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772511348 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.772511348
Directory /workspace/41.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2426322902
Short name T40
Test name
Test status
Simulation time 4472515895 ps
CPU time 20.2 seconds
Started Apr 25 12:48:29 PM PDT 24
Finished Apr 25 12:48:51 PM PDT 24
Peak memory 213236 kb
Host smart-3e429496-206a-40f2-a91e-fa29f8dff219
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426322902 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.2
426322902
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.3496656505
Short name T106
Test name
Test status
Simulation time 17561627079 ps
CPU time 34.11 seconds
Started Apr 25 12:48:25 PM PDT 24
Finished Apr 25 12:49:00 PM PDT 24
Peak memory 229636 kb
Host smart-ddaa076b-850c-4a36-8a65-35e723fc1627
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496656505 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.3496656505
Directory /workspace/9.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/47.rv_dm_stress_all.2969913653
Short name T6
Test name
Test status
Simulation time 1487227277 ps
CPU time 5.98 seconds
Started Apr 25 12:50:08 PM PDT 24
Finished Apr 25 12:50:17 PM PDT 24
Peak memory 205312 kb
Host smart-ff4859b0-7d0f-4add-bf05-6ec4c7976089
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969913653 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.2969913653
Directory /workspace/47.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.4224254739
Short name T50
Test name
Test status
Simulation time 957722452 ps
CPU time 1.77 seconds
Started Apr 25 12:47:55 PM PDT 24
Finished Apr 25 12:47:58 PM PDT 24
Peak memory 204768 kb
Host smart-5c1534b8-21f5-4fce-a5d6-b0a50fb91e46
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224254739 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.4224254739
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.4101615802
Short name T91
Test name
Test status
Simulation time 3861712305 ps
CPU time 7.41 seconds
Started Apr 25 12:48:12 PM PDT 24
Finished Apr 25 12:48:22 PM PDT 24
Peak memory 219440 kb
Host smart-b0dba706-2fd3-41d7-b53d-35dfc867c382
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101615802 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.4101615802
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.3570759851
Short name T108
Test name
Test status
Simulation time 2704730687 ps
CPU time 26.78 seconds
Started Apr 25 12:48:12 PM PDT 24
Finished Apr 25 12:48:42 PM PDT 24
Peak memory 204784 kb
Host smart-46a0b065-9988-45b8-8875-947c9a70bb7f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570759851 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.3570759851
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.2652507830
Short name T76
Test name
Test status
Simulation time 9078869351 ps
CPU time 19.53 seconds
Started Apr 25 12:48:26 PM PDT 24
Finished Apr 25 12:48:46 PM PDT 24
Peak memory 213100 kb
Host smart-e8825b13-9887-42f6-bfd3-a7f266af2562
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652507830 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.2
652507830
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.3176980344
Short name T52
Test name
Test status
Simulation time 16215458490 ps
CPU time 30.08 seconds
Started Apr 25 12:48:06 PM PDT 24
Finished Apr 25 12:48:38 PM PDT 24
Peak memory 204860 kb
Host smart-15017cc3-ee19-4871-b9a6-510f85f10aa1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176980344 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_bit_bash.3176980344
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.2169493442
Short name T62
Test name
Test status
Simulation time 210385388 ps
CPU time 1.01 seconds
Started Apr 25 12:49:26 PM PDT 24
Finished Apr 25 12:49:28 PM PDT 24
Peak memory 229360 kb
Host smart-fbc34508-625c-4411-9474-8f0fa55820cb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169493442 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.2169493442
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.4140334980
Short name T71
Test name
Test status
Simulation time 1487228036 ps
CPU time 4.17 seconds
Started Apr 25 12:49:29 PM PDT 24
Finished Apr 25 12:49:34 PM PDT 24
Peak memory 205236 kb
Host smart-4cd455ef-0d53-4f3b-a2a2-032f4e444a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140334980 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.4140334980
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.80864668
Short name T1
Test name
Test status
Simulation time 81739850 ps
CPU time 0.75 seconds
Started Apr 25 12:49:27 PM PDT 24
Finished Apr 25 12:49:29 PM PDT 24
Peak memory 205084 kb
Host smart-d5d966d7-10f1-477c-900b-b74d1b0b9825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80864668 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.80864668
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2938344539
Short name T84
Test name
Test status
Simulation time 3754171679 ps
CPU time 17.61 seconds
Started Apr 25 12:49:12 PM PDT 24
Finished Apr 25 12:49:33 PM PDT 24
Peak memory 220836 kb
Host smart-113c2ae6-ea4f-4660-9994-ecf393e4dc1b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938344539 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.2938344539
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.3358276031
Short name T22
Test name
Test status
Simulation time 18784752 ps
CPU time 0.8 seconds
Started Apr 25 12:49:38 PM PDT 24
Finished Apr 25 12:49:40 PM PDT 24
Peak memory 213408 kb
Host smart-8c8b9851-e003-4a50-8cc2-800e2c138b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358276031 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.3358276031
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.2646747563
Short name T24
Test name
Test status
Simulation time 187355130 ps
CPU time 0.76 seconds
Started Apr 25 12:49:25 PM PDT 24
Finished Apr 25 12:49:26 PM PDT 24
Peak memory 205176 kb
Host smart-d4833a4f-9211-4a2b-800e-5630df63a3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646747563 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.2646747563
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.933039526
Short name T88
Test name
Test status
Simulation time 955733530 ps
CPU time 16.57 seconds
Started Apr 25 12:49:07 PM PDT 24
Finished Apr 25 12:49:28 PM PDT 24
Peak memory 213076 kb
Host smart-26a8a1b6-7ccf-4eb8-839e-09338d4a9031
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933039526 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.933039526
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.4085249348
Short name T11
Test name
Test status
Simulation time 538617575 ps
CPU time 2.24 seconds
Started Apr 25 12:49:29 PM PDT 24
Finished Apr 25 12:49:32 PM PDT 24
Peak memory 205304 kb
Host smart-98c11c49-b0f8-4f82-b00f-94e16e80e314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085249348 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.4085249348
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.288298230
Short name T55
Test name
Test status
Simulation time 778857245 ps
CPU time 2.42 seconds
Started Apr 25 12:47:53 PM PDT 24
Finished Apr 25 12:47:58 PM PDT 24
Peak memory 204860 kb
Host smart-24ad017d-19f6-4bfd-acb1-cc758998e911
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288298230 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr
_hw_reset.288298230
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.107808842
Short name T43
Test name
Test status
Simulation time 1217884960 ps
CPU time 4.09 seconds
Started Apr 25 12:48:02 PM PDT 24
Finished Apr 25 12:48:08 PM PDT 24
Peak memory 204828 kb
Host smart-6bee32cb-5749-4225-8f7b-e57ee685346e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107808842 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_c
sr_outstanding.107808842
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.3218617880
Short name T27
Test name
Test status
Simulation time 38057720 ps
CPU time 0.79 seconds
Started Apr 25 12:49:31 PM PDT 24
Finished Apr 25 12:49:33 PM PDT 24
Peak memory 205112 kb
Host smart-756f19a5-bf6f-45ab-9039-bbf82db55df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218617880 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.3218617880
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.150649993
Short name T65
Test name
Test status
Simulation time 24715019 ps
CPU time 0.71 seconds
Started Apr 25 12:49:53 PM PDT 24
Finished Apr 25 12:49:56 PM PDT 24
Peak memory 205132 kb
Host smart-13942df4-2589-43a1-8620-4bd42f769ceb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150649993 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.150649993
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_dm_tap_fsm_rand_reset.1663808119
Short name T82
Test name
Test status
Simulation time 8231207961 ps
CPU time 24.38 seconds
Started Apr 25 12:49:38 PM PDT 24
Finished Apr 25 12:50:04 PM PDT 24
Peak memory 214384 kb
Host smart-d76cc617-ed12-429e-af81-cdd3b39cd015
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663808119 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 22.rv_dm_tap_fsm_rand_reset.1663808119
Directory /workspace/22.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.940882779
Short name T186
Test name
Test status
Simulation time 29214031 ps
CPU time 0.75 seconds
Started Apr 25 12:48:16 PM PDT 24
Finished Apr 25 12:48:18 PM PDT 24
Peak memory 204564 kb
Host smart-561e7d00-6b40-47cf-9502-339094e790ee
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940882779 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.940882779
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.2445918862
Short name T86
Test name
Test status
Simulation time 1248000216 ps
CPU time 10.33 seconds
Started Apr 25 12:48:05 PM PDT 24
Finished Apr 25 12:48:17 PM PDT 24
Peak memory 212976 kb
Host smart-ac36f51e-1c80-4c1c-abfb-3facdf4b84e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445918862 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.2445918862
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2323538912
Short name T49
Test name
Test status
Simulation time 1804171327 ps
CPU time 2.35 seconds
Started Apr 25 12:48:18 PM PDT 24
Finished Apr 25 12:48:22 PM PDT 24
Peak memory 204736 kb
Host smart-fc6f97e2-9f63-4420-88e4-e932bb001564
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323538912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.2323538912
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.1530930058
Short name T17
Test name
Test status
Simulation time 959205566 ps
CPU time 1.15 seconds
Started Apr 25 12:49:27 PM PDT 24
Finished Apr 25 12:49:29 PM PDT 24
Peak memory 205036 kb
Host smart-e159783e-e0be-40da-a38d-58ac32027366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530930058 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.1530930058
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/14.rv_dm_stress_all.2507993027
Short name T9
Test name
Test status
Simulation time 6930606254 ps
CPU time 6.42 seconds
Started Apr 25 12:49:52 PM PDT 24
Finished Apr 25 12:50:00 PM PDT 24
Peak memory 205380 kb
Host smart-ef9bdd8c-ded6-4364-af82-acf73faf5f3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507993027 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.2507993027
Directory /workspace/14.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.3694086736
Short name T121
Test name
Test status
Simulation time 138113938 ps
CPU time 2.18 seconds
Started Apr 25 12:48:29 PM PDT 24
Finished Apr 25 12:48:33 PM PDT 24
Peak memory 221320 kb
Host smart-fac56b76-f68a-451c-ad0c-5c4e9e8aca6c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694086736 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.3694086736
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.382202042
Short name T77
Test name
Test status
Simulation time 986400913 ps
CPU time 18.08 seconds
Started Apr 25 12:47:48 PM PDT 24
Finished Apr 25 12:48:11 PM PDT 24
Peak memory 213168 kb
Host smart-3c99b89b-c78f-459b-8272-15358b089994
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382202042 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.382202042
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.821113686
Short name T104
Test name
Test status
Simulation time 3454364420 ps
CPU time 19.76 seconds
Started Apr 25 12:48:09 PM PDT 24
Finished Apr 25 12:48:30 PM PDT 24
Peak memory 213192 kb
Host smart-bb8add8e-b663-4cb7-96ba-c192fc831b8c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821113686 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.821113686
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.3835158604
Short name T243
Test name
Test status
Simulation time 2705875834 ps
CPU time 4.42 seconds
Started Apr 25 12:48:38 PM PDT 24
Finished Apr 25 12:48:43 PM PDT 24
Peak memory 217188 kb
Host smart-3b85449e-d41c-43c8-b753-8b687e34c538
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835158604 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.3835158604
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tap_fsm_rand_reset.1425167878
Short name T83
Test name
Test status
Simulation time 10415733570 ps
CPU time 18.53 seconds
Started Apr 25 12:48:33 PM PDT 24
Finished Apr 25 12:48:53 PM PDT 24
Peak memory 214816 kb
Host smart-66a2cc06-95b9-4103-b830-a2ce8367bc04
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425167878 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rv_dm_tap_fsm_rand_reset.1425167878
Directory /workspace/18.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.3950152759
Short name T191
Test name
Test status
Simulation time 3848190124 ps
CPU time 6.27 seconds
Started Apr 25 12:48:14 PM PDT 24
Finished Apr 25 12:48:22 PM PDT 24
Peak memory 218832 kb
Host smart-3dce37bf-49f1-43bb-aa67-f7a7d7cdc677
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950152759 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.3950152759
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.4143659328
Short name T56
Test name
Test status
Simulation time 2207106846 ps
CPU time 3.08 seconds
Started Apr 25 12:48:11 PM PDT 24
Finished Apr 25 12:48:15 PM PDT 24
Peak memory 204832 kb
Host smart-da49b950-fa5e-4cc6-87a9-b15ef96fb1d5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143659328 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.4143659328
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.644907390
Short name T78
Test name
Test status
Simulation time 685762809 ps
CPU time 9.95 seconds
Started Apr 25 12:48:19 PM PDT 24
Finished Apr 25 12:48:30 PM PDT 24
Peak memory 221180 kb
Host smart-12028765-7454-47aa-87f3-1e057394f35e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644907390 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.644907390
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.521093982
Short name T46
Test name
Test status
Simulation time 58492965 ps
CPU time 0.71 seconds
Started Apr 25 12:49:35 PM PDT 24
Finished Apr 25 12:49:37 PM PDT 24
Peak memory 205144 kb
Host smart-dcd51c9f-2d1f-469a-b75c-e55ed3612bb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521093982 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.521093982
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1908500659
Short name T124
Test name
Test status
Simulation time 1772507945 ps
CPU time 32.19 seconds
Started Apr 25 12:48:05 PM PDT 24
Finished Apr 25 12:48:39 PM PDT 24
Peak memory 213084 kb
Host smart-c980bf9b-c84f-4dd1-aa81-3b14ccfb6445
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908500659 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.1908500659
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.2672079605
Short name T202
Test name
Test status
Simulation time 6308497517 ps
CPU time 31.28 seconds
Started Apr 25 12:48:06 PM PDT 24
Finished Apr 25 12:48:39 PM PDT 24
Peak memory 205052 kb
Host smart-520bdde4-81eb-42b5-abd0-e73a5461306c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672079605 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.2672079605
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.483651615
Short name T254
Test name
Test status
Simulation time 74002208 ps
CPU time 1.65 seconds
Started Apr 25 12:48:09 PM PDT 24
Finished Apr 25 12:48:12 PM PDT 24
Peak memory 213056 kb
Host smart-deb50dbe-f376-4013-80fa-417c1b6c0897
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483651615 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.483651615
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.4038750904
Short name T93
Test name
Test status
Simulation time 336474637 ps
CPU time 3.78 seconds
Started Apr 25 12:48:07 PM PDT 24
Finished Apr 25 12:48:12 PM PDT 24
Peak memory 220912 kb
Host smart-9770f5ac-94bd-4c13-9fa8-2f79131d6396
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038750904 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.4038750904
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.282766378
Short name T98
Test name
Test status
Simulation time 28489649 ps
CPU time 1.47 seconds
Started Apr 25 12:47:59 PM PDT 24
Finished Apr 25 12:48:02 PM PDT 24
Peak memory 213072 kb
Host smart-39bb42b7-79a3-4f8a-8c46-6c4c825e2ead
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282766378 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.282766378
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.450034688
Short name T229
Test name
Test status
Simulation time 17356373288 ps
CPU time 45.94 seconds
Started Apr 25 12:47:53 PM PDT 24
Finished Apr 25 12:48:41 PM PDT 24
Peak memory 204840 kb
Host smart-84ae32d2-c9f3-4625-9a15-8a6d62fd6970
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450034688 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr
_aliasing.450034688
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.681742788
Short name T262
Test name
Test status
Simulation time 34379063121 ps
CPU time 113.83 seconds
Started Apr 25 12:47:58 PM PDT 24
Finished Apr 25 12:49:59 PM PDT 24
Peak memory 204916 kb
Host smart-3e0b920e-b989-4f79-bb9b-64b8f76cb426
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681742788 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr
_bit_bash.681742788
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.33806895
Short name T215
Test name
Test status
Simulation time 481526769 ps
CPU time 2.01 seconds
Started Apr 25 12:47:59 PM PDT 24
Finished Apr 25 12:48:03 PM PDT 24
Peak memory 204792 kb
Host smart-d9219b2e-226b-49c9-82d8-fdc123ee44fe
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33806895 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.33806895
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3183904726
Short name T210
Test name
Test status
Simulation time 66232409 ps
CPU time 0.85 seconds
Started Apr 25 12:48:00 PM PDT 24
Finished Apr 25 12:48:02 PM PDT 24
Peak memory 204612 kb
Host smart-4bc1f4d7-39d3-4d91-9a90-574ea97c48ca
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183904726 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.3183904726
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.4145729998
Short name T257
Test name
Test status
Simulation time 2863728649 ps
CPU time 3.02 seconds
Started Apr 25 12:47:58 PM PDT 24
Finished Apr 25 12:48:03 PM PDT 24
Peak memory 204900 kb
Host smart-01ea2195-d715-492e-97f3-7380b1aa1a70
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145729998 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.4145729998
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.4230926619
Short name T219
Test name
Test status
Simulation time 66829738 ps
CPU time 0.69 seconds
Started Apr 25 12:48:12 PM PDT 24
Finished Apr 25 12:48:15 PM PDT 24
Peak memory 204572 kb
Host smart-ee7276d3-0931-4f6c-a914-bc8c39fa3d9a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230926619 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.4230926619
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.4184343003
Short name T298
Test name
Test status
Simulation time 72660049 ps
CPU time 0.7 seconds
Started Apr 25 12:48:00 PM PDT 24
Finished Apr 25 12:48:02 PM PDT 24
Peak memory 204580 kb
Host smart-faf6303e-5e54-4f73-8e45-a20ffd8b0deb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184343003 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.4184343003
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.3588543457
Short name T223
Test name
Test status
Simulation time 57860775 ps
CPU time 0.7 seconds
Started Apr 25 12:48:03 PM PDT 24
Finished Apr 25 12:48:05 PM PDT 24
Peak memory 204528 kb
Host smart-781cb978-b596-43cb-8a9c-eaeed3a5c98a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588543457 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.3588543457
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.470025977
Short name T44
Test name
Test status
Simulation time 411525155 ps
CPU time 3.63 seconds
Started Apr 25 12:48:05 PM PDT 24
Finished Apr 25 12:48:10 PM PDT 24
Peak memory 204976 kb
Host smart-8791699a-d103-42a2-b5b2-f5e19f9fc6f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470025977 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_c
sr_outstanding.470025977
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.1074027027
Short name T261
Test name
Test status
Simulation time 389709408 ps
CPU time 5.12 seconds
Started Apr 25 12:47:53 PM PDT 24
Finished Apr 25 12:48:01 PM PDT 24
Peak memory 213056 kb
Host smart-b7f7ac09-89db-4bc4-afd7-437f46f6298e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074027027 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.1074027027
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.2730333779
Short name T128
Test name
Test status
Simulation time 4064482378 ps
CPU time 27.42 seconds
Started Apr 25 12:48:12 PM PDT 24
Finished Apr 25 12:48:42 PM PDT 24
Peak memory 214260 kb
Host smart-296fe416-cbdc-494f-92d4-f729a4297194
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730333779 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.2730333779
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.1372637223
Short name T116
Test name
Test status
Simulation time 23247829719 ps
CPU time 68.38 seconds
Started Apr 25 12:48:04 PM PDT 24
Finished Apr 25 12:49:14 PM PDT 24
Peak memory 204980 kb
Host smart-e658ab41-fa3a-41d9-bc9e-e27f5dbed7ef
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372637223 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.1372637223
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2720716802
Short name T245
Test name
Test status
Simulation time 183105810 ps
CPU time 1.65 seconds
Started Apr 25 12:48:22 PM PDT 24
Finished Apr 25 12:48:24 PM PDT 24
Peak memory 213168 kb
Host smart-5d534991-c165-4d9b-9f47-b800c22157e4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720716802 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.2720716802
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.1632309228
Short name T205
Test name
Test status
Simulation time 3585423311 ps
CPU time 5.41 seconds
Started Apr 25 12:48:04 PM PDT 24
Finished Apr 25 12:48:11 PM PDT 24
Peak memory 218652 kb
Host smart-853adad8-4832-4cf5-9bff-e7d542de406c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632309228 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.1632309228
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.387153281
Short name T236
Test name
Test status
Simulation time 69573544 ps
CPU time 1.58 seconds
Started Apr 25 12:48:05 PM PDT 24
Finished Apr 25 12:48:08 PM PDT 24
Peak memory 213140 kb
Host smart-e187dead-3200-43ac-84d3-6538a0ae54f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387153281 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.387153281
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.3419398271
Short name T241
Test name
Test status
Simulation time 10078949034 ps
CPU time 11.61 seconds
Started Apr 25 12:48:06 PM PDT 24
Finished Apr 25 12:48:19 PM PDT 24
Peak memory 204824 kb
Host smart-6ad1ebba-b43d-4446-918e-352f445f8f25
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419398271 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.3419398271
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.4027016916
Short name T248
Test name
Test status
Simulation time 34304995264 ps
CPU time 46.26 seconds
Started Apr 25 12:48:07 PM PDT 24
Finished Apr 25 12:48:55 PM PDT 24
Peak memory 204956 kb
Host smart-bcb1c606-4f40-4a38-a4ff-92e8113ed5fa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027016916 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_bit_bash.4027016916
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.4079839250
Short name T192
Test name
Test status
Simulation time 365504564 ps
CPU time 2.06 seconds
Started Apr 25 12:48:13 PM PDT 24
Finished Apr 25 12:48:17 PM PDT 24
Peak memory 204804 kb
Host smart-dc054c1d-13d4-4fe0-99e4-022903b293dd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079839250 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.4
079839250
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2974395873
Short name T275
Test name
Test status
Simulation time 88032215 ps
CPU time 0.97 seconds
Started Apr 25 12:48:15 PM PDT 24
Finished Apr 25 12:48:17 PM PDT 24
Peak memory 204540 kb
Host smart-594585f6-cfc1-4095-8d47-78e8b97fb4bd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974395873 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.2974395873
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.3257138645
Short name T203
Test name
Test status
Simulation time 1184913339 ps
CPU time 1.94 seconds
Started Apr 25 12:47:57 PM PDT 24
Finished Apr 25 12:48:01 PM PDT 24
Peak memory 204760 kb
Host smart-d76a0976-a9a6-45d9-b8d7-1d6531d160a1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257138645 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.3257138645
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.546667844
Short name T75
Test name
Test status
Simulation time 175417591 ps
CPU time 0.93 seconds
Started Apr 25 12:47:55 PM PDT 24
Finished Apr 25 12:47:58 PM PDT 24
Peak memory 204576 kb
Host smart-d3c34eb1-bfd3-477e-bde0-dfddb69870f4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546667844 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_hw_reset.546667844
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.2804097588
Short name T256
Test name
Test status
Simulation time 33109979 ps
CPU time 0.78 seconds
Started Apr 25 12:48:11 PM PDT 24
Finished Apr 25 12:48:13 PM PDT 24
Peak memory 204560 kb
Host smart-ae7fe9cf-2d1b-41d6-88c7-b1f8d94c0728
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804097588 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.2
804097588
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2946881768
Short name T177
Test name
Test status
Simulation time 45640555 ps
CPU time 0.71 seconds
Started Apr 25 12:48:07 PM PDT 24
Finished Apr 25 12:48:09 PM PDT 24
Peak memory 204528 kb
Host smart-7ff61c2e-2811-4b69-8dbe-dca7e03a90b6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946881768 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.2946881768
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.2016023997
Short name T300
Test name
Test status
Simulation time 183507594 ps
CPU time 0.69 seconds
Started Apr 25 12:48:18 PM PDT 24
Finished Apr 25 12:48:20 PM PDT 24
Peak memory 204476 kb
Host smart-1f076c6c-47dc-4397-b2ca-59820e6e1999
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016023997 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.2016023997
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.207476277
Short name T217
Test name
Test status
Simulation time 183642994 ps
CPU time 2.54 seconds
Started Apr 25 12:48:08 PM PDT 24
Finished Apr 25 12:48:12 PM PDT 24
Peak memory 213156 kb
Host smart-a806c32c-5bf9-4c4e-9845-c71d8c0df173
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207476277 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.207476277
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.1115372998
Short name T95
Test name
Test status
Simulation time 3923319871 ps
CPU time 9.87 seconds
Started Apr 25 12:48:26 PM PDT 24
Finished Apr 25 12:48:38 PM PDT 24
Peak memory 221292 kb
Host smart-14cf781f-47d6-4fcd-85ed-84d46fe93dd3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115372998 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.1115372998
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.3458328175
Short name T280
Test name
Test status
Simulation time 1255593770 ps
CPU time 2.51 seconds
Started Apr 25 12:48:38 PM PDT 24
Finished Apr 25 12:48:42 PM PDT 24
Peak memory 213136 kb
Host smart-fdea0253-b996-4d7e-a07c-e4573b1eeb3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458328175 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.3458328175
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2313676784
Short name T189
Test name
Test status
Simulation time 690258930 ps
CPU time 3.15 seconds
Started Apr 25 12:49:11 PM PDT 24
Finished Apr 25 12:49:18 PM PDT 24
Peak memory 203488 kb
Host smart-f80e8be6-bb4d-4439-809b-b6131e6c53d3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313676784 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
2313676784
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.3835155842
Short name T237
Test name
Test status
Simulation time 155002779 ps
CPU time 0.7 seconds
Started Apr 25 12:48:18 PM PDT 24
Finished Apr 25 12:48:20 PM PDT 24
Peak memory 204592 kb
Host smart-0d18658c-6154-4960-ac5d-f48cada3eeac
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835155842 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
3835155842
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3002341353
Short name T228
Test name
Test status
Simulation time 145775162 ps
CPU time 6.29 seconds
Started Apr 25 12:48:43 PM PDT 24
Finished Apr 25 12:48:52 PM PDT 24
Peak memory 204928 kb
Host smart-4c688389-82d6-4651-b96b-797a3c9772aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002341353 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same
_csr_outstanding.3002341353
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.1934906754
Short name T105
Test name
Test status
Simulation time 30399440 ps
CPU time 1.82 seconds
Started Apr 25 12:48:28 PM PDT 24
Finished Apr 25 12:48:31 PM PDT 24
Peak memory 213216 kb
Host smart-73d3e1ed-95c1-4093-8f18-5efc4977b65e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934906754 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.1934906754
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.571758885
Short name T247
Test name
Test status
Simulation time 1554723463 ps
CPU time 19.79 seconds
Started Apr 25 12:48:18 PM PDT 24
Finished Apr 25 12:48:39 PM PDT 24
Peak memory 221168 kb
Host smart-d127e890-0ea3-446b-a6b5-25b39328e717
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571758885 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.571758885
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1381312940
Short name T240
Test name
Test status
Simulation time 35892496 ps
CPU time 2.54 seconds
Started Apr 25 12:48:36 PM PDT 24
Finished Apr 25 12:48:41 PM PDT 24
Peak memory 218268 kb
Host smart-c967f435-53de-4f06-91d3-cc8c5ead1769
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381312940 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.1381312940
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.2710364727
Short name T54
Test name
Test status
Simulation time 330556134 ps
CPU time 1.38 seconds
Started Apr 25 12:48:20 PM PDT 24
Finished Apr 25 12:48:23 PM PDT 24
Peak memory 204792 kb
Host smart-7697a03e-9c1d-482e-b8cc-1011c7341047
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710364727 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
2710364727
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.2075673437
Short name T289
Test name
Test status
Simulation time 50079358 ps
CPU time 0.79 seconds
Started Apr 25 12:48:26 PM PDT 24
Finished Apr 25 12:48:27 PM PDT 24
Peak memory 204572 kb
Host smart-7955caf7-19c4-471d-a2ba-eaf88bc83c1e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075673437 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.
2075673437
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.367068401
Short name T273
Test name
Test status
Simulation time 825202054 ps
CPU time 8.06 seconds
Started Apr 25 12:48:23 PM PDT 24
Finished Apr 25 12:48:32 PM PDT 24
Peak memory 204896 kb
Host smart-cd95664c-bc0b-448f-a62e-287a9140da80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367068401 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same_
csr_outstanding.367068401
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.1924733722
Short name T239
Test name
Test status
Simulation time 227471738 ps
CPU time 6.11 seconds
Started Apr 25 12:48:20 PM PDT 24
Finished Apr 25 12:48:28 PM PDT 24
Peak memory 213224 kb
Host smart-441be170-379f-402f-80f5-80f6515113d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924733722 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.1924733722
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.1165751653
Short name T296
Test name
Test status
Simulation time 1119378257 ps
CPU time 18.9 seconds
Started Apr 25 12:48:22 PM PDT 24
Finished Apr 25 12:48:42 PM PDT 24
Peak memory 221292 kb
Host smart-c5920a8f-40de-4b8f-98c6-37a0a523833e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165751653 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.1
165751653
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.3386649094
Short name T207
Test name
Test status
Simulation time 64076805 ps
CPU time 2.17 seconds
Started Apr 25 12:48:34 PM PDT 24
Finished Apr 25 12:48:37 PM PDT 24
Peak memory 220788 kb
Host smart-f6e3ee48-6b73-406f-861b-44ee5fa23a0c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386649094 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.3386649094
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.3253078696
Short name T112
Test name
Test status
Simulation time 313508549 ps
CPU time 1.58 seconds
Started Apr 25 12:48:31 PM PDT 24
Finished Apr 25 12:48:34 PM PDT 24
Peak memory 218308 kb
Host smart-d846b0d5-944d-4779-9297-739cc4148701
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253078696 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.3253078696
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.2880080024
Short name T250
Test name
Test status
Simulation time 921218387 ps
CPU time 3.84 seconds
Started Apr 25 12:48:39 PM PDT 24
Finished Apr 25 12:48:44 PM PDT 24
Peak memory 204780 kb
Host smart-98808a58-4727-4e46-b3c9-cf6808441949
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880080024 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
2880080024
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.2534081017
Short name T201
Test name
Test status
Simulation time 153468055 ps
CPU time 1.08 seconds
Started Apr 25 12:48:20 PM PDT 24
Finished Apr 25 12:48:22 PM PDT 24
Peak memory 204568 kb
Host smart-b0f74524-95b8-421a-9a24-32974f2e3203
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534081017 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
2534081017
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3973376725
Short name T244
Test name
Test status
Simulation time 823134859 ps
CPU time 7.35 seconds
Started Apr 25 12:48:17 PM PDT 24
Finished Apr 25 12:48:25 PM PDT 24
Peak memory 204928 kb
Host smart-a921640e-0f7e-4813-afd2-434fe35af0be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973376725 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.3973376725
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.3910330190
Short name T260
Test name
Test status
Simulation time 116709323 ps
CPU time 3.42 seconds
Started Apr 25 12:48:38 PM PDT 24
Finished Apr 25 12:48:42 PM PDT 24
Peak memory 213200 kb
Host smart-526568d7-e4e3-4554-8152-1a0053d0577c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910330190 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.3910330190
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.601294982
Short name T103
Test name
Test status
Simulation time 96803423 ps
CPU time 2.39 seconds
Started Apr 25 12:48:23 PM PDT 24
Finished Apr 25 12:48:26 PM PDT 24
Peak memory 213152 kb
Host smart-d0b63789-644f-4bd0-ae4a-5f1333f46a7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601294982 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.601294982
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.831170525
Short name T220
Test name
Test status
Simulation time 1736437445 ps
CPU time 5.74 seconds
Started Apr 25 12:48:34 PM PDT 24
Finished Apr 25 12:48:41 PM PDT 24
Peak memory 204864 kb
Host smart-75ad9db3-2dc7-45d1-8f2d-721d119947c8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831170525 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.831170525
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3119041620
Short name T266
Test name
Test status
Simulation time 84029332 ps
CPU time 0.73 seconds
Started Apr 25 12:48:25 PM PDT 24
Finished Apr 25 12:48:27 PM PDT 24
Peak memory 204616 kb
Host smart-3c45a4c1-163d-4522-a433-6a30391ecc8f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119041620 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
3119041620
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.18130367
Short name T127
Test name
Test status
Simulation time 237735914 ps
CPU time 4.23 seconds
Started Apr 25 12:48:30 PM PDT 24
Finished Apr 25 12:48:36 PM PDT 24
Peak memory 204844 kb
Host smart-55918415-6ce8-42a4-bc92-96ec461c3a26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18130367 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same_c
sr_outstanding.18130367
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.3777618372
Short name T274
Test name
Test status
Simulation time 364286134 ps
CPU time 3.51 seconds
Started Apr 25 12:48:39 PM PDT 24
Finished Apr 25 12:48:44 PM PDT 24
Peak memory 213188 kb
Host smart-dae8793a-be5d-4205-9862-f5d665b4bd65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777618372 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.3777618372
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2947781528
Short name T277
Test name
Test status
Simulation time 1330359861 ps
CPU time 9.63 seconds
Started Apr 25 12:48:36 PM PDT 24
Finished Apr 25 12:48:48 PM PDT 24
Peak memory 213080 kb
Host smart-f117d983-2f7f-435a-a7cb-dec3bb46c9d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947781528 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.2
947781528
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.4217396913
Short name T206
Test name
Test status
Simulation time 148957353 ps
CPU time 2.16 seconds
Started Apr 25 12:48:24 PM PDT 24
Finished Apr 25 12:48:27 PM PDT 24
Peak memory 213136 kb
Host smart-3f460f98-25f5-4151-94ff-64b96d7083ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217396913 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.4217396913
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.2584272620
Short name T226
Test name
Test status
Simulation time 432410509 ps
CPU time 2.31 seconds
Started Apr 25 12:48:36 PM PDT 24
Finished Apr 25 12:48:40 PM PDT 24
Peak memory 213156 kb
Host smart-3c5af16a-7512-45a5-8886-7055b226be2d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584272620 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.2584272620
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1555118248
Short name T51
Test name
Test status
Simulation time 2291926495 ps
CPU time 7.38 seconds
Started Apr 25 12:48:26 PM PDT 24
Finished Apr 25 12:48:35 PM PDT 24
Peak memory 204816 kb
Host smart-512a1891-7c04-472f-9d1a-e6d76f837aa4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555118248 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
1555118248
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2662029904
Short name T74
Test name
Test status
Simulation time 52696359 ps
CPU time 0.67 seconds
Started Apr 25 12:48:23 PM PDT 24
Finished Apr 25 12:48:25 PM PDT 24
Peak memory 204572 kb
Host smart-62373bdd-3e18-47e4-b054-6056fee412c4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662029904 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
2662029904
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3055195494
Short name T97
Test name
Test status
Simulation time 823585245 ps
CPU time 7.51 seconds
Started Apr 25 12:48:27 PM PDT 24
Finished Apr 25 12:48:36 PM PDT 24
Peak memory 204924 kb
Host smart-31081bb3-e096-4f94-bf1d-d8d26df8ca6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055195494 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.3055195494
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tap_fsm_rand_reset.3717404817
Short name T72
Test name
Test status
Simulation time 10832182095 ps
CPU time 13.48 seconds
Started Apr 25 12:48:19 PM PDT 24
Finished Apr 25 12:48:33 PM PDT 24
Peak memory 213220 kb
Host smart-bbe0ef56-be97-457a-b747-e284eb7ea215
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717404817 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rv_dm_tap_fsm_rand_reset.3717404817
Directory /workspace/14.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.120911400
Short name T89
Test name
Test status
Simulation time 165354792 ps
CPU time 4.59 seconds
Started Apr 25 12:48:34 PM PDT 24
Finished Apr 25 12:48:40 PM PDT 24
Peak memory 213200 kb
Host smart-107e59cf-653f-4596-a7b5-f11a55d1bea0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120911400 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.120911400
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3346854210
Short name T134
Test name
Test status
Simulation time 1754227789 ps
CPU time 18.77 seconds
Started Apr 25 12:48:33 PM PDT 24
Finished Apr 25 12:48:53 PM PDT 24
Peak memory 213124 kb
Host smart-5cad8a97-c5f8-4ec9-9259-12c978e07396
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346854210 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.3
346854210
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.671825018
Short name T232
Test name
Test status
Simulation time 176412260 ps
CPU time 2.34 seconds
Started Apr 25 12:48:27 PM PDT 24
Finished Apr 25 12:48:31 PM PDT 24
Peak memory 218196 kb
Host smart-c214e74b-f71e-4641-b97e-a7815bc4a89b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671825018 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.671825018
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3251014681
Short name T182
Test name
Test status
Simulation time 150552804 ps
CPU time 1.28 seconds
Started Apr 25 12:48:41 PM PDT 24
Finished Apr 25 12:48:45 PM PDT 24
Peak memory 204780 kb
Host smart-760c3b0e-c74f-4273-8f5a-5cc005a189d1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251014681 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
3251014681
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.873075966
Short name T267
Test name
Test status
Simulation time 48358826 ps
CPU time 0.7 seconds
Started Apr 25 12:48:30 PM PDT 24
Finished Apr 25 12:48:32 PM PDT 24
Peak memory 204520 kb
Host smart-1d8db4f4-7a11-46a5-aed0-df76f836f6ae
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873075966 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.873075966
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.1180217481
Short name T125
Test name
Test status
Simulation time 204823340 ps
CPU time 6.26 seconds
Started Apr 25 12:48:30 PM PDT 24
Finished Apr 25 12:48:38 PM PDT 24
Peak memory 204864 kb
Host smart-7f2d6411-3f8f-4674-88a1-d01f912c9ba5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180217481 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.1180217481
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.3926676532
Short name T282
Test name
Test status
Simulation time 401889328 ps
CPU time 2.41 seconds
Started Apr 25 12:48:37 PM PDT 24
Finished Apr 25 12:48:41 PM PDT 24
Peak memory 213168 kb
Host smart-f2871111-c20c-4956-94d6-419e56e61d12
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926676532 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.3926676532
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.48619700
Short name T81
Test name
Test status
Simulation time 741583531 ps
CPU time 10.07 seconds
Started Apr 25 12:48:24 PM PDT 24
Finished Apr 25 12:48:35 PM PDT 24
Peak memory 221156 kb
Host smart-3f92706e-e2bc-4430-9e47-971ef37cd39a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48619700 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.48619700
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.465400432
Short name T249
Test name
Test status
Simulation time 1939640774 ps
CPU time 5.32 seconds
Started Apr 25 12:48:34 PM PDT 24
Finished Apr 25 12:48:40 PM PDT 24
Peak memory 221408 kb
Host smart-ec528a3f-6e56-41c8-a129-5e92ae557a27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465400432 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.465400432
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.1525125958
Short name T188
Test name
Test status
Simulation time 184940318 ps
CPU time 1.55 seconds
Started Apr 25 12:48:35 PM PDT 24
Finished Apr 25 12:48:38 PM PDT 24
Peak memory 213132 kb
Host smart-7c23242b-5730-4fca-8947-675864cf350b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525125958 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.1525125958
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.4040588355
Short name T271
Test name
Test status
Simulation time 789673738 ps
CPU time 1.58 seconds
Started Apr 25 12:48:29 PM PDT 24
Finished Apr 25 12:48:32 PM PDT 24
Peak memory 204700 kb
Host smart-d24a6d2d-1cfa-4d27-b44b-06a2076e152c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040588355 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
4040588355
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3809278828
Short name T73
Test name
Test status
Simulation time 192741663 ps
CPU time 0.74 seconds
Started Apr 25 12:48:29 PM PDT 24
Finished Apr 25 12:48:31 PM PDT 24
Peak memory 204608 kb
Host smart-58faac68-2d2a-4f48-8659-58dbbb4bcccd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809278828 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
3809278828
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3780617804
Short name T42
Test name
Test status
Simulation time 163784482 ps
CPU time 3.48 seconds
Started Apr 25 12:48:28 PM PDT 24
Finished Apr 25 12:48:32 PM PDT 24
Peak memory 204948 kb
Host smart-28d5abcf-d69c-45f1-a968-e917cb4704fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780617804 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.3780617804
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3639682607
Short name T284
Test name
Test status
Simulation time 294507019 ps
CPU time 6.66 seconds
Started Apr 25 12:48:29 PM PDT 24
Finished Apr 25 12:48:38 PM PDT 24
Peak memory 213212 kb
Host smart-5e7a959e-dab8-4565-be5f-e8a41f01380f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639682607 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.3639682607
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.595470114
Short name T292
Test name
Test status
Simulation time 535872152 ps
CPU time 3.69 seconds
Started Apr 25 12:48:31 PM PDT 24
Finished Apr 25 12:48:36 PM PDT 24
Peak memory 217760 kb
Host smart-bbae5ea0-fb46-437b-8609-72113fdb7aa3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595470114 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.595470114
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.3383015822
Short name T222
Test name
Test status
Simulation time 123532254 ps
CPU time 1.57 seconds
Started Apr 25 12:48:24 PM PDT 24
Finished Apr 25 12:48:27 PM PDT 24
Peak memory 212996 kb
Host smart-a8487106-4f22-438c-8911-9e0dcbfc025d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383015822 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.3383015822
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.3666522356
Short name T303
Test name
Test status
Simulation time 760890303 ps
CPU time 2.01 seconds
Started Apr 25 12:48:26 PM PDT 24
Finished Apr 25 12:48:30 PM PDT 24
Peak memory 204792 kb
Host smart-efcd84d9-4447-414a-8050-1c32e75a96c0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666522356 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
3666522356
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.57813819
Short name T227
Test name
Test status
Simulation time 72505241 ps
CPU time 0.81 seconds
Started Apr 25 12:48:28 PM PDT 24
Finished Apr 25 12:48:30 PM PDT 24
Peak memory 204528 kb
Host smart-7f1678e9-9901-4696-9e63-0ab8ed8856b8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57813819 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.57813819
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3774107406
Short name T109
Test name
Test status
Simulation time 222754511 ps
CPU time 4.17 seconds
Started Apr 25 12:48:27 PM PDT 24
Finished Apr 25 12:48:33 PM PDT 24
Peak memory 204908 kb
Host smart-be3905ff-4fdd-4196-bb0e-155f6777d1f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774107406 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.3774107406
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2877090539
Short name T211
Test name
Test status
Simulation time 121214731 ps
CPU time 3.12 seconds
Started Apr 25 12:48:40 PM PDT 24
Finished Apr 25 12:48:44 PM PDT 24
Peak memory 213232 kb
Host smart-bccb4c42-63eb-4c33-9c05-51b587b23862
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877090539 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.2877090539
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.1092440177
Short name T137
Test name
Test status
Simulation time 2690566080 ps
CPU time 10.82 seconds
Started Apr 25 12:48:32 PM PDT 24
Finished Apr 25 12:48:44 PM PDT 24
Peak memory 213192 kb
Host smart-148e0ebd-b866-4304-bea0-46c3a09794ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092440177 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.1
092440177
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.3359030436
Short name T255
Test name
Test status
Simulation time 1136407290 ps
CPU time 2.86 seconds
Started Apr 25 12:48:43 PM PDT 24
Finished Apr 25 12:48:48 PM PDT 24
Peak memory 216068 kb
Host smart-cc772b05-9d20-41df-8d6e-a43aee64b0fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359030436 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.3359030436
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2732358634
Short name T123
Test name
Test status
Simulation time 867623009 ps
CPU time 2.42 seconds
Started Apr 25 12:48:34 PM PDT 24
Finished Apr 25 12:48:37 PM PDT 24
Peak memory 218296 kb
Host smart-17d6c954-72cd-4111-8097-4f641e0756a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732358634 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.2732358634
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.3583651777
Short name T53
Test name
Test status
Simulation time 541156863 ps
CPU time 1.99 seconds
Started Apr 25 12:48:34 PM PDT 24
Finished Apr 25 12:48:37 PM PDT 24
Peak memory 204716 kb
Host smart-29c5ac8b-332c-4182-b45d-a5adf909652e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583651777 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
3583651777
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.1325159270
Short name T285
Test name
Test status
Simulation time 90196781 ps
CPU time 0.72 seconds
Started Apr 25 12:48:40 PM PDT 24
Finished Apr 25 12:48:43 PM PDT 24
Peak memory 204536 kb
Host smart-2d468cc7-b89b-4c63-8389-f7ad11bbd35e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325159270 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
1325159270
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1650023436
Short name T101
Test name
Test status
Simulation time 1541902773 ps
CPU time 7.32 seconds
Started Apr 25 12:48:35 PM PDT 24
Finished Apr 25 12:48:44 PM PDT 24
Peak memory 204884 kb
Host smart-5996baf6-0cfb-439a-a3b8-29e68689bf9d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650023436 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.1650023436
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.872574086
Short name T287
Test name
Test status
Simulation time 118836983 ps
CPU time 2.7 seconds
Started Apr 25 12:48:26 PM PDT 24
Finished Apr 25 12:48:30 PM PDT 24
Peak memory 213152 kb
Host smart-352db23c-29ec-47c1-bab1-2b5bbaca2490
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872574086 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.872574086
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.2317903690
Short name T136
Test name
Test status
Simulation time 432234271 ps
CPU time 15.34 seconds
Started Apr 25 12:48:31 PM PDT 24
Finished Apr 25 12:48:47 PM PDT 24
Peak memory 213008 kb
Host smart-82ad1007-7796-4cf2-8495-6d11d74b6c92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317903690 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.2
317903690
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1319089405
Short name T218
Test name
Test status
Simulation time 3347627771 ps
CPU time 8.96 seconds
Started Apr 25 12:48:33 PM PDT 24
Finished Apr 25 12:48:44 PM PDT 24
Peak memory 221336 kb
Host smart-0c6b607f-eecf-466f-ae9a-c35053c514fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319089405 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.1319089405
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.1444205634
Short name T122
Test name
Test status
Simulation time 210352571 ps
CPU time 2.47 seconds
Started Apr 25 12:48:36 PM PDT 24
Finished Apr 25 12:48:40 PM PDT 24
Peak memory 213096 kb
Host smart-bb6b6731-97ab-4183-856d-ed914680fb27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444205634 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.1444205634
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.172796453
Short name T221
Test name
Test status
Simulation time 1011575170 ps
CPU time 4.1 seconds
Started Apr 25 12:48:26 PM PDT 24
Finished Apr 25 12:48:31 PM PDT 24
Peak memory 204668 kb
Host smart-9fddc4e8-6283-4294-9ba4-03ed291bce56
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172796453 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.172796453
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.3009473432
Short name T204
Test name
Test status
Simulation time 84254950 ps
CPU time 0.69 seconds
Started Apr 25 12:48:42 PM PDT 24
Finished Apr 25 12:48:45 PM PDT 24
Peak memory 204516 kb
Host smart-fb17e414-d26a-447d-8e46-58579751133e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009473432 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
3009473432
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1625766940
Short name T230
Test name
Test status
Simulation time 820477853 ps
CPU time 4.23 seconds
Started Apr 25 12:48:44 PM PDT 24
Finished Apr 25 12:48:50 PM PDT 24
Peak memory 204844 kb
Host smart-2bd9d359-7826-4760-92d3-f738c0dfadab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625766940 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.1625766940
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.681841940
Short name T235
Test name
Test status
Simulation time 209257528 ps
CPU time 2.46 seconds
Started Apr 25 12:48:35 PM PDT 24
Finished Apr 25 12:48:39 PM PDT 24
Peak memory 213208 kb
Host smart-291006b4-622a-46da-a9cf-675e381a0ed8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681841940 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.681841940
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2080913577
Short name T120
Test name
Test status
Simulation time 4550156067 ps
CPU time 63.27 seconds
Started Apr 25 12:48:05 PM PDT 24
Finished Apr 25 12:49:10 PM PDT 24
Peak memory 217804 kb
Host smart-83b81204-ea1b-4d83-a690-3207c62faad1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080913577 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.2080913577
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2961146444
Short name T286
Test name
Test status
Simulation time 3965405076 ps
CPU time 32.89 seconds
Started Apr 25 12:48:10 PM PDT 24
Finished Apr 25 12:48:44 PM PDT 24
Peak memory 204984 kb
Host smart-f7b9e394-9b71-496d-a5e6-f0972c550716
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961146444 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.2961146444
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3177974401
Short name T180
Test name
Test status
Simulation time 116986771 ps
CPU time 1.64 seconds
Started Apr 25 12:48:13 PM PDT 24
Finished Apr 25 12:48:17 PM PDT 24
Peak memory 213116 kb
Host smart-3830f090-b0cc-4cc4-a9fd-1b8fb7f5f90d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177974401 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.3177974401
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.1711728077
Short name T92
Test name
Test status
Simulation time 698613973 ps
CPU time 3.97 seconds
Started Apr 25 12:48:08 PM PDT 24
Finished Apr 25 12:48:14 PM PDT 24
Peak memory 218904 kb
Host smart-8bbccfbb-5fb2-4663-8a45-439359296e87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711728077 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.1711728077
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1105223988
Short name T107
Test name
Test status
Simulation time 433743893 ps
CPU time 2.41 seconds
Started Apr 25 12:48:06 PM PDT 24
Finished Apr 25 12:48:10 PM PDT 24
Peak memory 213112 kb
Host smart-69afd776-de2f-42fe-a51b-e3ce76a1c801
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105223988 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.1105223988
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.868336576
Short name T288
Test name
Test status
Simulation time 9791814545 ps
CPU time 9.8 seconds
Started Apr 25 12:48:03 PM PDT 24
Finished Apr 25 12:48:14 PM PDT 24
Peak memory 204896 kb
Host smart-1218df00-9055-45e3-966a-d49a93af1b22
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868336576 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr
_aliasing.868336576
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1246851304
Short name T251
Test name
Test status
Simulation time 525221974 ps
CPU time 1.46 seconds
Started Apr 25 12:48:01 PM PDT 24
Finished Apr 25 12:48:03 PM PDT 24
Peak memory 204764 kb
Host smart-3e17a9d3-217d-4c45-9095-56f163b4726a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246851304 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.1
246851304
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.381476969
Short name T278
Test name
Test status
Simulation time 54339805 ps
CPU time 0.85 seconds
Started Apr 25 12:48:01 PM PDT 24
Finished Apr 25 12:48:03 PM PDT 24
Peak memory 204536 kb
Host smart-22a2e29c-9494-4a69-8745-e98b3058bdb1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381476969 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_aliasing.381476969
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.3723994871
Short name T213
Test name
Test status
Simulation time 6153615304 ps
CPU time 6.72 seconds
Started Apr 25 12:48:14 PM PDT 24
Finished Apr 25 12:48:23 PM PDT 24
Peak memory 204848 kb
Host smart-906c67a8-1e33-48dc-8494-5331f63357e6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723994871 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.3723994871
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.534350118
Short name T295
Test name
Test status
Simulation time 186063727 ps
CPU time 0.99 seconds
Started Apr 25 12:48:01 PM PDT 24
Finished Apr 25 12:48:03 PM PDT 24
Peak memory 204668 kb
Host smart-a5c52da7-6611-4b5f-b8be-1cdb30cc4496
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534350118 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_hw_reset.534350118
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.1946750701
Short name T252
Test name
Test status
Simulation time 45191942 ps
CPU time 0.78 seconds
Started Apr 25 12:48:03 PM PDT 24
Finished Apr 25 12:48:05 PM PDT 24
Peak memory 204508 kb
Host smart-246b5cb1-eabf-40a9-8fcb-088f3a7d9813
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946750701 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.1
946750701
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2990098556
Short name T231
Test name
Test status
Simulation time 41100461 ps
CPU time 0.7 seconds
Started Apr 25 12:48:09 PM PDT 24
Finished Apr 25 12:48:11 PM PDT 24
Peak memory 204604 kb
Host smart-20fa3499-d8a7-43fa-a8e4-cda79e6592da
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990098556 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.2990098556
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.751999537
Short name T264
Test name
Test status
Simulation time 21656512 ps
CPU time 0.68 seconds
Started Apr 25 12:48:11 PM PDT 24
Finished Apr 25 12:48:13 PM PDT 24
Peak memory 204604 kb
Host smart-5c8ea810-55e5-47ce-a6df-d8932f30e31d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751999537 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.751999537
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.1482980937
Short name T293
Test name
Test status
Simulation time 1398804079 ps
CPU time 7.68 seconds
Started Apr 25 12:48:07 PM PDT 24
Finished Apr 25 12:48:16 PM PDT 24
Peak memory 204780 kb
Host smart-e0ed9da1-4af6-43f2-8780-a08f29304d70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482980937 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.1482980937
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.615166965
Short name T208
Test name
Test status
Simulation time 11030329666 ps
CPU time 36.87 seconds
Started Apr 25 12:48:12 PM PDT 24
Finished Apr 25 12:48:52 PM PDT 24
Peak memory 221372 kb
Host smart-962ad186-695b-4fb8-9280-c87d1c91cb2e
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615166965 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.615166965
Directory /workspace/2.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.4066096733
Short name T90
Test name
Test status
Simulation time 82469283 ps
CPU time 4.97 seconds
Started Apr 25 12:48:02 PM PDT 24
Finished Apr 25 12:48:08 PM PDT 24
Peak memory 213232 kb
Host smart-e716c852-ef96-4a3c-b0ad-f336b220a324
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066096733 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.4066096733
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.rv_dm_tap_fsm_rand_reset.3383153286
Short name T193
Test name
Test status
Simulation time 10879784458 ps
CPU time 23.38 seconds
Started Apr 25 12:48:36 PM PDT 24
Finished Apr 25 12:49:01 PM PDT 24
Peak memory 220404 kb
Host smart-00e09ed0-159b-4170-8c0c-1db600bb374f
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383153286 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 20.rv_dm_tap_fsm_rand_reset.3383153286
Directory /workspace/20.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/23.rv_dm_tap_fsm_rand_reset.260856320
Short name T80
Test name
Test status
Simulation time 6060997758 ps
CPU time 15.88 seconds
Started Apr 25 12:48:35 PM PDT 24
Finished Apr 25 12:48:52 PM PDT 24
Peak memory 221368 kb
Host smart-6e6cc257-e099-4772-a951-f3352cb69fc6
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260856320 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 23.rv_dm_tap_fsm_rand_reset.260856320
Directory /workspace/23.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/25.rv_dm_tap_fsm_rand_reset.1618617559
Short name T279
Test name
Test status
Simulation time 29264626312 ps
CPU time 26.81 seconds
Started Apr 25 12:48:48 PM PDT 24
Finished Apr 25 12:49:17 PM PDT 24
Peak memory 229600 kb
Host smart-602536d4-704d-4ebd-90e4-175873399499
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618617559 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 25.rv_dm_tap_fsm_rand_reset.1618617559
Directory /workspace/25.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/26.rv_dm_tap_fsm_rand_reset.1168749814
Short name T225
Test name
Test status
Simulation time 9835556027 ps
CPU time 18.43 seconds
Started Apr 25 12:48:25 PM PDT 24
Finished Apr 25 12:48:44 PM PDT 24
Peak memory 221296 kb
Host smart-0a4e6556-95b2-4471-8be8-fcad3c41963c
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168749814 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 26.rv_dm_tap_fsm_rand_reset.1168749814
Directory /workspace/26.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.2978165050
Short name T291
Test name
Test status
Simulation time 1205309526 ps
CPU time 27.29 seconds
Started Apr 25 12:48:11 PM PDT 24
Finished Apr 25 12:48:41 PM PDT 24
Peak memory 204944 kb
Host smart-9451f890-4055-4bc5-9333-7116c621805b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978165050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.2978165050
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.3099339847
Short name T118
Test name
Test status
Simulation time 256056195 ps
CPU time 2.42 seconds
Started Apr 25 12:48:05 PM PDT 24
Finished Apr 25 12:48:09 PM PDT 24
Peak memory 213044 kb
Host smart-73eb8ecc-d2f9-4136-a0ca-0d603ce835c8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099339847 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.3099339847
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.1706169068
Short name T224
Test name
Test status
Simulation time 49844265 ps
CPU time 2.22 seconds
Started Apr 25 12:48:06 PM PDT 24
Finished Apr 25 12:48:10 PM PDT 24
Peak memory 213184 kb
Host smart-588a5f49-ab65-4b00-9b30-90880211290e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706169068 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.1706169068
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.2000960996
Short name T283
Test name
Test status
Simulation time 23810072857 ps
CPU time 21.83 seconds
Started Apr 25 12:48:11 PM PDT 24
Finished Apr 25 12:48:35 PM PDT 24
Peak memory 204896 kb
Host smart-0ca02bdd-77da-42ca-8eca-1fd777573b26
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000960996 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.2000960996
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.3212060474
Short name T294
Test name
Test status
Simulation time 9632749270 ps
CPU time 37.74 seconds
Started Apr 25 12:48:12 PM PDT 24
Finished Apr 25 12:48:52 PM PDT 24
Peak memory 204924 kb
Host smart-c2d76d69-dfe5-4b25-ade4-bb0056711504
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212060474 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_bit_bash.3212060474
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.2443468513
Short name T176
Test name
Test status
Simulation time 220286940 ps
CPU time 1.46 seconds
Started Apr 25 12:48:10 PM PDT 24
Finished Apr 25 12:48:13 PM PDT 24
Peak memory 204756 kb
Host smart-bc3a86cf-9420-430b-869d-1b645a1872a9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443468513 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.2
443468513
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.4279162334
Short name T297
Test name
Test status
Simulation time 124883297 ps
CPU time 0.79 seconds
Started Apr 25 12:48:03 PM PDT 24
Finished Apr 25 12:48:05 PM PDT 24
Peak memory 204536 kb
Host smart-bad22610-c748-428c-a283-dfb101f2a103
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279162334 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.4279162334
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2901253361
Short name T214
Test name
Test status
Simulation time 1958960815 ps
CPU time 1.63 seconds
Started Apr 25 12:48:12 PM PDT 24
Finished Apr 25 12:48:17 PM PDT 24
Peak memory 204796 kb
Host smart-c8cf2a6c-488b-4013-92d6-03819603142d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901253361 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.2901253361
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3653668048
Short name T187
Test name
Test status
Simulation time 30583393 ps
CPU time 0.75 seconds
Started Apr 25 12:48:14 PM PDT 24
Finished Apr 25 12:48:17 PM PDT 24
Peak memory 204552 kb
Host smart-2c126e49-9a9f-486c-ad58-aee4d1a1dd3a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653668048 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.3653668048
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1827049214
Short name T269
Test name
Test status
Simulation time 64643034 ps
CPU time 0.73 seconds
Started Apr 25 12:48:08 PM PDT 24
Finished Apr 25 12:48:10 PM PDT 24
Peak memory 204604 kb
Host smart-c6f6f883-e652-41d5-b5d2-b43b23b66227
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827049214 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.1
827049214
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.1676893547
Short name T242
Test name
Test status
Simulation time 52221801 ps
CPU time 0.71 seconds
Started Apr 25 12:48:07 PM PDT 24
Finished Apr 25 12:48:09 PM PDT 24
Peak memory 204484 kb
Host smart-a8c2febb-42fa-401f-ab10-868ffb2076f1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676893547 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.1676893547
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.2488686973
Short name T85
Test name
Test status
Simulation time 63802803 ps
CPU time 0.69 seconds
Started Apr 25 12:48:10 PM PDT 24
Finished Apr 25 12:48:12 PM PDT 24
Peak memory 204624 kb
Host smart-f4c506fe-f175-48bd-ba6b-331c5c01ebd5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488686973 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.2488686973
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.3600715899
Short name T253
Test name
Test status
Simulation time 327443715 ps
CPU time 3.88 seconds
Started Apr 25 12:48:15 PM PDT 24
Finished Apr 25 12:48:20 PM PDT 24
Peak memory 204848 kb
Host smart-7af86e8f-e102-4563-a331-b5a1d7fee24d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600715899 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_
csr_outstanding.3600715899
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.3166309853
Short name T200
Test name
Test status
Simulation time 130390567 ps
CPU time 4.39 seconds
Started Apr 25 12:48:12 PM PDT 24
Finished Apr 25 12:48:19 PM PDT 24
Peak memory 213232 kb
Host smart-b1c984ee-df39-4f94-a8b2-380f59fbb711
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166309853 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.3166309853
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/31.rv_dm_tap_fsm_rand_reset.3978630558
Short name T212
Test name
Test status
Simulation time 14273712049 ps
CPU time 14.64 seconds
Started Apr 25 12:48:29 PM PDT 24
Finished Apr 25 12:48:45 PM PDT 24
Peak memory 213248 kb
Host smart-faa1b4f3-a5f1-4394-847d-bc1b8320b88a
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978630558 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 31.rv_dm_tap_fsm_rand_reset.3978630558
Directory /workspace/31.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/35.rv_dm_tap_fsm_rand_reset.59521300
Short name T39
Test name
Test status
Simulation time 16351308199 ps
CPU time 11.21 seconds
Started Apr 25 12:48:47 PM PDT 24
Finished Apr 25 12:49:00 PM PDT 24
Peak memory 214164 kb
Host smart-fc8eac31-56ae-40b1-ba46-950e9b1af0cb
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59521300 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 35.rv_dm_tap_fsm_rand_reset.59521300
Directory /workspace/35.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/39.rv_dm_tap_fsm_rand_reset.1465530390
Short name T233
Test name
Test status
Simulation time 17620781851 ps
CPU time 12.67 seconds
Started Apr 25 12:48:26 PM PDT 24
Finished Apr 25 12:48:40 PM PDT 24
Peak memory 217688 kb
Host smart-d9394507-effd-46db-a03b-2f89435b2453
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465530390 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 39.rv_dm_tap_fsm_rand_reset.1465530390
Directory /workspace/39.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.3071336713
Short name T100
Test name
Test status
Simulation time 1174259985 ps
CPU time 67.7 seconds
Started Apr 25 12:47:59 PM PDT 24
Finished Apr 25 12:49:08 PM PDT 24
Peak memory 204896 kb
Host smart-df5fbca1-4179-4968-9010-fb37748a5908
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071336713 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.3071336713
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.3518963378
Short name T290
Test name
Test status
Simulation time 729416313 ps
CPU time 27.24 seconds
Started Apr 25 12:48:20 PM PDT 24
Finished Apr 25 12:48:48 PM PDT 24
Peak memory 204876 kb
Host smart-5c0f9f52-7b3d-44e3-9489-f5eed52f64c6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518963378 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.3518963378
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.287880972
Short name T115
Test name
Test status
Simulation time 113412259 ps
CPU time 2.51 seconds
Started Apr 25 12:48:20 PM PDT 24
Finished Apr 25 12:48:24 PM PDT 24
Peak memory 213028 kb
Host smart-50a04b1b-9bc0-492a-bb9d-d61512a12711
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287880972 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.287880972
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.1715435658
Short name T87
Test name
Test status
Simulation time 71511850 ps
CPU time 1.98 seconds
Started Apr 25 12:48:11 PM PDT 24
Finished Apr 25 12:48:15 PM PDT 24
Peak memory 214232 kb
Host smart-1fa661bb-977c-40d6-98e3-bf3619a9aff0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715435658 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.1715435658
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.2289926642
Short name T99
Test name
Test status
Simulation time 774540760 ps
CPU time 1.56 seconds
Started Apr 25 12:48:17 PM PDT 24
Finished Apr 25 12:48:19 PM PDT 24
Peak memory 213060 kb
Host smart-519511aa-0182-4cb7-8aa5-8837c2ab9bef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289926642 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.2289926642
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.3883567004
Short name T276
Test name
Test status
Simulation time 16153808463 ps
CPU time 59.77 seconds
Started Apr 25 12:48:15 PM PDT 24
Finished Apr 25 12:49:16 PM PDT 24
Peak memory 204800 kb
Host smart-7eff70e8-06b4-4137-b3bc-90ec4a9df532
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883567004 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.3883567004
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.146901294
Short name T48
Test name
Test status
Simulation time 544805677 ps
CPU time 2.23 seconds
Started Apr 25 12:48:06 PM PDT 24
Finished Apr 25 12:48:10 PM PDT 24
Peak memory 204908 kb
Host smart-95ee7ab4-dfa5-47ea-bdd9-34b53e6d627b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146901294 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr
_hw_reset.146901294
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.4094928048
Short name T238
Test name
Test status
Simulation time 773380545 ps
CPU time 3.22 seconds
Started Apr 25 12:48:08 PM PDT 24
Finished Apr 25 12:48:13 PM PDT 24
Peak memory 204768 kb
Host smart-17d642fe-6679-4de1-a093-d24cf3071f89
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094928048 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.4
094928048
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.2358135711
Short name T263
Test name
Test status
Simulation time 154116556 ps
CPU time 1.13 seconds
Started Apr 25 12:48:04 PM PDT 24
Finished Apr 25 12:48:07 PM PDT 24
Peak memory 204564 kb
Host smart-b97c01bc-dc9b-40e4-b349-cf75b42db994
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358135711 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.2358135711
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.3941592664
Short name T183
Test name
Test status
Simulation time 2492340951 ps
CPU time 3.88 seconds
Started Apr 25 12:48:08 PM PDT 24
Finished Apr 25 12:48:14 PM PDT 24
Peak memory 204832 kb
Host smart-cf0012b8-cfd2-47c4-9503-d3f8f844d560
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941592664 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.3941592664
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.1784559596
Short name T195
Test name
Test status
Simulation time 152763066 ps
CPU time 0.74 seconds
Started Apr 25 12:48:12 PM PDT 24
Finished Apr 25 12:48:15 PM PDT 24
Peak memory 204644 kb
Host smart-21c847af-7914-4a9b-b66f-39cd07af7fc9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784559596 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.1784559596
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.3917598265
Short name T190
Test name
Test status
Simulation time 51000494 ps
CPU time 0.73 seconds
Started Apr 25 12:48:07 PM PDT 24
Finished Apr 25 12:48:09 PM PDT 24
Peak memory 204544 kb
Host smart-d2f6a173-cfa8-4d9a-8e16-82de4ce42dee
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917598265 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.3
917598265
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.2475555449
Short name T181
Test name
Test status
Simulation time 49856492 ps
CPU time 0.73 seconds
Started Apr 25 12:48:10 PM PDT 24
Finished Apr 25 12:48:12 PM PDT 24
Peak memory 204572 kb
Host smart-9063d4ea-8cb0-4677-bfb4-bf3cc4c08b8e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475555449 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.2475555449
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.2458384014
Short name T196
Test name
Test status
Simulation time 118365570 ps
CPU time 0.68 seconds
Started Apr 25 12:49:11 PM PDT 24
Finished Apr 25 12:49:16 PM PDT 24
Peak memory 203312 kb
Host smart-b082fea4-8baa-44fb-9c38-eb73527f377d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458384014 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.2458384014
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1788471735
Short name T114
Test name
Test status
Simulation time 416770989 ps
CPU time 8.17 seconds
Started Apr 25 12:48:06 PM PDT 24
Finished Apr 25 12:48:16 PM PDT 24
Peak memory 204912 kb
Host smart-ce5c6e89-ce74-487d-9485-d9aed5847cdf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788471735 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.1788471735
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.1038348581
Short name T132
Test name
Test status
Simulation time 142843562 ps
CPU time 3.88 seconds
Started Apr 25 12:48:09 PM PDT 24
Finished Apr 25 12:48:15 PM PDT 24
Peak memory 213224 kb
Host smart-1cf1c0e8-dc18-428f-97a0-e3a2abf6ab7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038348581 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.1038348581
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1031134166
Short name T304
Test name
Test status
Simulation time 3073211616 ps
CPU time 9.88 seconds
Started Apr 25 12:48:13 PM PDT 24
Finished Apr 25 12:48:25 PM PDT 24
Peak memory 221244 kb
Host smart-6a3c0d4b-3f54-42ad-bc83-eef2ec199406
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031134166 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.1031134166
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3092542121
Short name T281
Test name
Test status
Simulation time 2276083291 ps
CPU time 5.42 seconds
Started Apr 25 12:48:08 PM PDT 24
Finished Apr 25 12:48:14 PM PDT 24
Peak memory 218416 kb
Host smart-fd5afcd9-4592-4be5-b30b-ac18d776e306
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092542121 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.3092542121
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.655866595
Short name T119
Test name
Test status
Simulation time 183439442 ps
CPU time 1.55 seconds
Started Apr 25 12:48:27 PM PDT 24
Finished Apr 25 12:48:30 PM PDT 24
Peak memory 218308 kb
Host smart-783f21fb-d973-42d7-bbd8-10ac050a46da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655866595 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.655866595
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.2432745973
Short name T179
Test name
Test status
Simulation time 1871308007 ps
CPU time 3.65 seconds
Started Apr 25 12:48:04 PM PDT 24
Finished Apr 25 12:48:09 PM PDT 24
Peak memory 204632 kb
Host smart-93b06d4f-6955-41c8-8688-133277727133
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432745973 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.2
432745973
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3224058688
Short name T184
Test name
Test status
Simulation time 40290374 ps
CPU time 0.7 seconds
Started Apr 25 12:49:06 PM PDT 24
Finished Apr 25 12:49:16 PM PDT 24
Peak memory 203908 kb
Host smart-c694a351-4078-441b-992d-1be23d570e19
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224058688 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.3
224058688
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1201126884
Short name T110
Test name
Test status
Simulation time 840685700 ps
CPU time 4.15 seconds
Started Apr 25 12:48:24 PM PDT 24
Finished Apr 25 12:48:29 PM PDT 24
Peak memory 204820 kb
Host smart-03e1cecd-767f-42f3-9789-1217502f06b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201126884 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.1201126884
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.2488438715
Short name T216
Test name
Test status
Simulation time 132423581 ps
CPU time 2.35 seconds
Started Apr 25 12:48:21 PM PDT 24
Finished Apr 25 12:48:24 PM PDT 24
Peak memory 213208 kb
Host smart-350138bd-e6f6-4f3c-82b7-66808cc71d18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488438715 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.2488438715
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2420524414
Short name T135
Test name
Test status
Simulation time 1540194337 ps
CPU time 16.07 seconds
Started Apr 25 12:48:37 PM PDT 24
Finished Apr 25 12:48:54 PM PDT 24
Peak memory 221228 kb
Host smart-b0dfa929-fc18-4027-87d1-d1a80c3709ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420524414 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.2420524414
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.3715145818
Short name T199
Test name
Test status
Simulation time 3545845473 ps
CPU time 6.9 seconds
Started Apr 25 12:48:06 PM PDT 24
Finished Apr 25 12:48:15 PM PDT 24
Peak memory 221384 kb
Host smart-b2124416-cff8-489f-8f07-8c55f4f19b45
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715145818 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.3715145818
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1480677179
Short name T117
Test name
Test status
Simulation time 30610096 ps
CPU time 1.43 seconds
Started Apr 25 12:48:20 PM PDT 24
Finished Apr 25 12:48:23 PM PDT 24
Peak memory 221236 kb
Host smart-a5e9ad86-0d59-496b-836e-58f79febc898
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480677179 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.1480677179
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.3244201
Short name T302
Test name
Test status
Simulation time 379618992 ps
CPU time 1.05 seconds
Started Apr 25 12:48:24 PM PDT 24
Finished Apr 25 12:48:25 PM PDT 24
Peak memory 204836 kb
Host smart-6e92766f-ac02-45bc-be31-b86d0967ec35
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244201 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.3244201
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2423815875
Short name T198
Test name
Test status
Simulation time 92985530 ps
CPU time 0.96 seconds
Started Apr 25 12:48:15 PM PDT 24
Finished Apr 25 12:48:17 PM PDT 24
Peak memory 204572 kb
Host smart-2088a2f1-5e25-44df-8ffd-25dfe4ddac48
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423815875 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.2
423815875
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.1691047233
Short name T258
Test name
Test status
Simulation time 77878037 ps
CPU time 3.54 seconds
Started Apr 25 12:48:11 PM PDT 24
Finished Apr 25 12:48:17 PM PDT 24
Peak memory 204896 kb
Host smart-afa14419-8e0a-412e-aae7-b9f04a28516f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691047233 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.1691047233
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.1461590051
Short name T265
Test name
Test status
Simulation time 95396309 ps
CPU time 3.21 seconds
Started Apr 25 12:48:05 PM PDT 24
Finished Apr 25 12:48:10 PM PDT 24
Peak memory 213232 kb
Host smart-721acac3-9fcd-49a4-9961-356ab286fabe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461590051 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.1461590051
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3246180608
Short name T197
Test name
Test status
Simulation time 2032601637 ps
CPU time 3.93 seconds
Started Apr 25 12:48:18 PM PDT 24
Finished Apr 25 12:48:23 PM PDT 24
Peak memory 217552 kb
Host smart-f323a0c0-4ef4-456c-b492-08f82b62a512
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246180608 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.3246180608
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.3417803888
Short name T270
Test name
Test status
Simulation time 69175364 ps
CPU time 2.11 seconds
Started Apr 25 12:48:28 PM PDT 24
Finished Apr 25 12:48:31 PM PDT 24
Peak memory 213084 kb
Host smart-e525b3a8-bb96-49f0-89f8-acc059e23d59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417803888 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.3417803888
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.1372168796
Short name T259
Test name
Test status
Simulation time 598418168 ps
CPU time 1.35 seconds
Started Apr 25 12:48:08 PM PDT 24
Finished Apr 25 12:48:11 PM PDT 24
Peak memory 204696 kb
Host smart-c472c28d-419c-4993-a828-e10e9496ad02
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372168796 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.1
372168796
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.2633976183
Short name T268
Test name
Test status
Simulation time 111159991 ps
CPU time 0.69 seconds
Started Apr 25 12:48:31 PM PDT 24
Finished Apr 25 12:48:33 PM PDT 24
Peak memory 204540 kb
Host smart-a67973f4-00c0-4e6d-8f8a-d9e803959194
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633976183 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.2
633976183
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.2517156379
Short name T126
Test name
Test status
Simulation time 1691501982 ps
CPU time 7.78 seconds
Started Apr 25 12:48:33 PM PDT 24
Finished Apr 25 12:48:42 PM PDT 24
Peak memory 204888 kb
Host smart-64c08528-5b1c-4d95-be66-aaafbf3feddf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517156379 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.2517156379
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.2611643212
Short name T133
Test name
Test status
Simulation time 163594318 ps
CPU time 4.83 seconds
Started Apr 25 12:48:07 PM PDT 24
Finished Apr 25 12:48:13 PM PDT 24
Peak memory 213196 kb
Host smart-289ee800-5303-4143-a8a0-d40a155a726e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611643212 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.2611643212
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.1973597386
Short name T138
Test name
Test status
Simulation time 815068582 ps
CPU time 8.26 seconds
Started Apr 25 12:48:05 PM PDT 24
Finished Apr 25 12:48:15 PM PDT 24
Peak memory 213044 kb
Host smart-59b98926-48a2-48a7-a14b-a27ccc6cf438
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973597386 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.1973597386
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.3482760291
Short name T194
Test name
Test status
Simulation time 168436370 ps
CPU time 2.29 seconds
Started Apr 25 12:48:29 PM PDT 24
Finished Apr 25 12:48:34 PM PDT 24
Peak memory 217004 kb
Host smart-99687331-7bfd-4668-a8e9-ed8449ed8bf8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482760291 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.3482760291
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.2598089484
Short name T102
Test name
Test status
Simulation time 61985146 ps
CPU time 1.53 seconds
Started Apr 25 12:48:15 PM PDT 24
Finished Apr 25 12:48:18 PM PDT 24
Peak memory 221224 kb
Host smart-17067849-f3a5-49a9-8aca-533f29eec88b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598089484 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.2598089484
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1861893199
Short name T234
Test name
Test status
Simulation time 1129988711 ps
CPU time 4.21 seconds
Started Apr 25 12:48:14 PM PDT 24
Finished Apr 25 12:48:20 PM PDT 24
Peak memory 204764 kb
Host smart-1812f487-2852-4333-904a-ffe29b63db2b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861893199 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.1
861893199
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2618883274
Short name T272
Test name
Test status
Simulation time 106943373 ps
CPU time 0.73 seconds
Started Apr 25 12:48:26 PM PDT 24
Finished Apr 25 12:48:33 PM PDT 24
Peak memory 204620 kb
Host smart-bf709f04-8cff-41a0-a393-72298437d29f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618883274 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.2
618883274
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.3322290401
Short name T111
Test name
Test status
Simulation time 548696804 ps
CPU time 8.14 seconds
Started Apr 25 12:48:11 PM PDT 24
Finished Apr 25 12:48:22 PM PDT 24
Peak memory 204944 kb
Host smart-945a64f2-4472-457a-a371-35919d78599c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322290401 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_
csr_outstanding.3322290401
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.3679120308
Short name T209
Test name
Test status
Simulation time 7132389470 ps
CPU time 24.21 seconds
Started Apr 25 12:48:24 PM PDT 24
Finished Apr 25 12:48:49 PM PDT 24
Peak memory 220028 kb
Host smart-0feb5e82-f6b7-4b72-a1cc-23ef33b4d0f0
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679120308 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.3679120308
Directory /workspace/8.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.1454773381
Short name T246
Test name
Test status
Simulation time 809422790 ps
CPU time 5.77 seconds
Started Apr 25 12:48:25 PM PDT 24
Finished Apr 25 12:48:31 PM PDT 24
Peak memory 213248 kb
Host smart-6015fef4-5fe3-4846-8eae-4612ce9b1d4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454773381 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.1454773381
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.453700621
Short name T94
Test name
Test status
Simulation time 204813942 ps
CPU time 8.28 seconds
Started Apr 25 12:48:18 PM PDT 24
Finished Apr 25 12:48:28 PM PDT 24
Peak memory 213128 kb
Host smart-c228a518-8925-43b4-83d7-5823e4b10987
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453700621 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.453700621
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.135191560
Short name T41
Test name
Test status
Simulation time 37559154 ps
CPU time 2.35 seconds
Started Apr 25 12:48:17 PM PDT 24
Finished Apr 25 12:48:21 PM PDT 24
Peak memory 220836 kb
Host smart-17051a31-e637-413c-a0b9-564da1bf050f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135191560 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.135191560
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.3787342497
Short name T299
Test name
Test status
Simulation time 105079242 ps
CPU time 1.55 seconds
Started Apr 25 12:48:13 PM PDT 24
Finished Apr 25 12:48:17 PM PDT 24
Peak memory 218568 kb
Host smart-1e04984d-615c-4bae-a3b2-56deccaf38de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787342497 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.3787342497
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3831693283
Short name T178
Test name
Test status
Simulation time 158247014 ps
CPU time 1.17 seconds
Started Apr 25 12:48:15 PM PDT 24
Finished Apr 25 12:48:17 PM PDT 24
Peak memory 204748 kb
Host smart-1d3abd04-67a3-428a-b4f7-2013ddd0ac87
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831693283 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.3
831693283
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.3581862838
Short name T185
Test name
Test status
Simulation time 115258229 ps
CPU time 0.73 seconds
Started Apr 25 12:48:10 PM PDT 24
Finished Apr 25 12:48:12 PM PDT 24
Peak memory 204524 kb
Host smart-7413aee5-8183-4077-9e7d-1c97207d68b2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581862838 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.3
581862838
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.3293788446
Short name T113
Test name
Test status
Simulation time 1272316332 ps
CPU time 6.24 seconds
Started Apr 25 12:48:26 PM PDT 24
Finished Apr 25 12:48:33 PM PDT 24
Peak memory 204948 kb
Host smart-cf560a5d-ae16-432f-b36b-89fd171d2120
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293788446 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.3293788446
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.2868812045
Short name T301
Test name
Test status
Simulation time 112013675 ps
CPU time 2.82 seconds
Started Apr 25 12:48:11 PM PDT 24
Finished Apr 25 12:48:16 PM PDT 24
Peak memory 213168 kb
Host smart-bb100c0d-8857-4229-972d-4dd265c3a240
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868812045 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.2868812045
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.902210592
Short name T139
Test name
Test status
Simulation time 4416691002 ps
CPU time 10.72 seconds
Started Apr 25 12:48:28 PM PDT 24
Finished Apr 25 12:48:41 PM PDT 24
Peak memory 213300 kb
Host smart-f40fb310-8ef3-4208-8415-f80080ab5b59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902210592 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.902210592
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.873919053
Short name T29
Test name
Test status
Simulation time 74444263 ps
CPU time 0.72 seconds
Started Apr 25 12:49:32 PM PDT 24
Finished Apr 25 12:49:34 PM PDT 24
Peak memory 205052 kb
Host smart-3662bbb6-5a08-43fb-89d4-9b5b3112047a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873919053 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.873919053
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.1750557948
Short name T167
Test name
Test status
Simulation time 24582122 ps
CPU time 0.76 seconds
Started Apr 25 12:49:29 PM PDT 24
Finished Apr 25 12:49:31 PM PDT 24
Peak memory 205164 kb
Host smart-2bd7eb23-030e-4556-9d34-7b93253ca209
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750557948 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.1750557948
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.1821161718
Short name T10
Test name
Test status
Simulation time 1970909484 ps
CPU time 7 seconds
Started Apr 25 12:49:19 PM PDT 24
Finished Apr 25 12:49:28 PM PDT 24
Peak memory 205340 kb
Host smart-f36de025-23ed-4d06-8e92-fe4842d5e560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821161718 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.1821161718
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.2317995458
Short name T19
Test name
Test status
Simulation time 2688570439 ps
CPU time 5.07 seconds
Started Apr 25 12:49:35 PM PDT 24
Finished Apr 25 12:49:42 PM PDT 24
Peak memory 205504 kb
Host smart-b5cdc642-8468-420a-8a1a-9ba0a021651c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317995458 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.2317995458
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.3312075066
Short name T174
Test name
Test status
Simulation time 56533051 ps
CPU time 0.78 seconds
Started Apr 25 12:49:18 PM PDT 24
Finished Apr 25 12:49:20 PM PDT 24
Peak memory 205052 kb
Host smart-5d785d37-d3d3-46b4-af1e-b263c163dd58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312075066 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.3312075066
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.750542107
Short name T171
Test name
Test status
Simulation time 58944128 ps
CPU time 0.85 seconds
Started Apr 25 12:49:22 PM PDT 24
Finished Apr 25 12:49:24 PM PDT 24
Peak memory 204976 kb
Host smart-9d1f2a2d-63e2-40c1-ad28-df5cfa8a70ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750542107 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.750542107
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.1752980208
Short name T172
Test name
Test status
Simulation time 99370922 ps
CPU time 0.99 seconds
Started Apr 25 12:49:13 PM PDT 24
Finished Apr 25 12:49:17 PM PDT 24
Peak memory 205064 kb
Host smart-3a263da4-b086-4dca-9c8d-23152ddbc566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752980208 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.1752980208
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.3557265474
Short name T18
Test name
Test status
Simulation time 229097491 ps
CPU time 1.08 seconds
Started Apr 25 12:49:35 PM PDT 24
Finished Apr 25 12:49:38 PM PDT 24
Peak memory 204984 kb
Host smart-529b7b25-8828-435c-aee8-29c94f19d82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557265474 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.3557265474
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.3310152319
Short name T140
Test name
Test status
Simulation time 58412276 ps
CPU time 0.72 seconds
Started Apr 25 12:49:25 PM PDT 24
Finished Apr 25 12:49:27 PM PDT 24
Peak memory 205104 kb
Host smart-cf6a6dbb-0b09-45af-bfb9-03ba3d3c7dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310152319 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.3310152319
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.1222869042
Short name T3
Test name
Test status
Simulation time 495044848 ps
CPU time 2.1 seconds
Started Apr 25 12:49:22 PM PDT 24
Finished Apr 25 12:49:25 PM PDT 24
Peak memory 205328 kb
Host smart-4a947802-1efe-4124-9f47-1c6cbf74a016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222869042 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.1222869042
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.3857959662
Short name T16
Test name
Test status
Simulation time 147578957 ps
CPU time 1.1 seconds
Started Apr 25 12:49:23 PM PDT 24
Finished Apr 25 12:49:30 PM PDT 24
Peak memory 205156 kb
Host smart-aa649da9-ebff-4687-9b50-30832a029df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857959662 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.3857959662
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.2732591473
Short name T12
Test name
Test status
Simulation time 144952271 ps
CPU time 0.96 seconds
Started Apr 25 12:49:19 PM PDT 24
Finished Apr 25 12:49:21 PM PDT 24
Peak memory 205192 kb
Host smart-e05ef82b-5456-4b50-8ca3-0717e4a24119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732591473 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.2732591473
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.4052068623
Short name T23
Test name
Test status
Simulation time 77310539 ps
CPU time 0.79 seconds
Started Apr 25 12:49:31 PM PDT 24
Finished Apr 25 12:49:33 PM PDT 24
Peak memory 213352 kb
Host smart-835f9805-2205-4f94-a9c3-7f1772b76934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052068623 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.4052068623
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.2636240767
Short name T32
Test name
Test status
Simulation time 161114755 ps
CPU time 1.58 seconds
Started Apr 25 12:49:23 PM PDT 24
Finished Apr 25 12:49:26 PM PDT 24
Peak memory 229272 kb
Host smart-07270244-6636-4ecc-9f06-c7fc0a4988ad
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636240767 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.2636240767
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.748062907
Short name T59
Test name
Test status
Simulation time 490046986 ps
CPU time 1.64 seconds
Started Apr 25 12:49:33 PM PDT 24
Finished Apr 25 12:49:36 PM PDT 24
Peak memory 205216 kb
Host smart-7314d732-bcec-4cc2-beea-57666d8879f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748062907 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.748062907
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.727367678
Short name T158
Test name
Test status
Simulation time 20149827 ps
CPU time 0.71 seconds
Started Apr 25 12:49:25 PM PDT 24
Finished Apr 25 12:49:26 PM PDT 24
Peak memory 205144 kb
Host smart-1864d6d1-959e-48d8-9418-27f64026648d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727367678 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.727367678
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.975452727
Short name T25
Test name
Test status
Simulation time 292577023 ps
CPU time 1.51 seconds
Started Apr 25 12:49:22 PM PDT 24
Finished Apr 25 12:49:24 PM PDT 24
Peak memory 205264 kb
Host smart-15728796-15e6-400a-af77-b9dc084fffea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975452727 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.975452727
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.2661405790
Short name T21
Test name
Test status
Simulation time 120201443 ps
CPU time 0.99 seconds
Started Apr 25 12:49:32 PM PDT 24
Finished Apr 25 12:49:35 PM PDT 24
Peak memory 205028 kb
Host smart-b5de28b5-4139-430a-a483-b37c8bd08fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661405790 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.2661405790
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.103567670
Short name T79
Test name
Test status
Simulation time 2717743003 ps
CPU time 5.73 seconds
Started Apr 25 12:49:19 PM PDT 24
Finished Apr 25 12:49:31 PM PDT 24
Peak memory 205420 kb
Host smart-40ef1306-a92e-4215-bd21-e55a2330b614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103567670 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.103567670
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.2799840559
Short name T15
Test name
Test status
Simulation time 124045915 ps
CPU time 0.75 seconds
Started Apr 25 12:49:50 PM PDT 24
Finished Apr 25 12:49:53 PM PDT 24
Peak memory 205120 kb
Host smart-8f8255b0-8ba0-4406-ae8d-e3b93626138d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799840559 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.2799840559
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.3254701411
Short name T67
Test name
Test status
Simulation time 90092180 ps
CPU time 0.72 seconds
Started Apr 25 12:49:36 PM PDT 24
Finished Apr 25 12:49:39 PM PDT 24
Peak memory 205036 kb
Host smart-415794cf-b047-4b86-ae46-94c03369289c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254701411 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.3254701411
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.3087744407
Short name T58
Test name
Test status
Simulation time 102556852 ps
CPU time 0.9 seconds
Started Apr 25 12:49:30 PM PDT 24
Finished Apr 25 12:49:33 PM PDT 24
Peak memory 204980 kb
Host smart-d03de837-9a73-4a5d-8223-81378212f0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087744407 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.3087744407
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.3414419534
Short name T131
Test name
Test status
Simulation time 99841965 ps
CPU time 0.95 seconds
Started Apr 25 12:49:37 PM PDT 24
Finished Apr 25 12:49:39 PM PDT 24
Peak memory 205056 kb
Host smart-d4fe6de2-7e7f-4dbd-8c19-31b7878f7bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414419534 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.3414419534
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.2061591903
Short name T8
Test name
Test status
Simulation time 64228201 ps
CPU time 0.8 seconds
Started Apr 25 12:49:24 PM PDT 24
Finished Apr 25 12:49:25 PM PDT 24
Peak memory 205140 kb
Host smart-6f1ac2a2-d0d6-4e72-a5a4-7e7d0ae65ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061591903 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.2061591903
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.2902296066
Short name T13
Test name
Test status
Simulation time 100340055 ps
CPU time 0.9 seconds
Started Apr 25 12:49:36 PM PDT 24
Finished Apr 25 12:49:39 PM PDT 24
Peak memory 205048 kb
Host smart-dc8aeb8d-c78f-4b3c-9d67-0eb25ac312c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902296066 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.2902296066
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.4058726629
Short name T96
Test name
Test status
Simulation time 409945569 ps
CPU time 1.39 seconds
Started Apr 25 12:49:38 PM PDT 24
Finished Apr 25 12:49:41 PM PDT 24
Peak memory 205328 kb
Host smart-6f6bec1e-48ed-4b92-b4de-0f0d2b7ef55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058726629 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.4058726629
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.2734640531
Short name T28
Test name
Test status
Simulation time 95695530 ps
CPU time 0.88 seconds
Started Apr 25 12:49:25 PM PDT 24
Finished Apr 25 12:49:27 PM PDT 24
Peak memory 205164 kb
Host smart-d706f2dd-9067-4704-8895-81d3cf900262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734640531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.2734640531
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.1345485976
Short name T26
Test name
Test status
Simulation time 1169513651 ps
CPU time 1.13 seconds
Started Apr 25 12:49:25 PM PDT 24
Finished Apr 25 12:49:27 PM PDT 24
Peak memory 205024 kb
Host smart-826acccc-8ae0-49f5-ac3a-043b97602d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345485976 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.1345485976
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.243579911
Short name T68
Test name
Test status
Simulation time 31669316 ps
CPU time 0.75 seconds
Started Apr 25 12:49:34 PM PDT 24
Finished Apr 25 12:49:36 PM PDT 24
Peak memory 205100 kb
Host smart-20bf9692-ea46-4a73-a798-7b62744cb624
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243579911 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.243579911
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.29423139
Short name T159
Test name
Test status
Simulation time 59547533 ps
CPU time 0.74 seconds
Started Apr 25 12:49:35 PM PDT 24
Finished Apr 25 12:49:37 PM PDT 24
Peak memory 205108 kb
Host smart-1959dc31-7623-45f9-9b03-d0cd7eefca34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29423139 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.29423139
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.3185270259
Short name T170
Test name
Test status
Simulation time 21859107 ps
CPU time 0.71 seconds
Started Apr 25 12:49:35 PM PDT 24
Finished Apr 25 12:49:37 PM PDT 24
Peak memory 205124 kb
Host smart-4a4effe9-a6a0-4a8b-9cb1-8d6b927ff8b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185270259 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.3185270259
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.4150304714
Short name T149
Test name
Test status
Simulation time 152259383 ps
CPU time 0.73 seconds
Started Apr 25 12:49:41 PM PDT 24
Finished Apr 25 12:49:43 PM PDT 24
Peak memory 205144 kb
Host smart-5e09b7cb-2087-45a1-85bf-0137b7153fbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150304714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.4150304714
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.587513185
Short name T169
Test name
Test status
Simulation time 29174140 ps
CPU time 0.76 seconds
Started Apr 25 12:49:52 PM PDT 24
Finished Apr 25 12:49:55 PM PDT 24
Peak memory 205068 kb
Host smart-613d9def-f49e-4617-9d9d-10c78fff806c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587513185 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.587513185
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.1909859291
Short name T161
Test name
Test status
Simulation time 33739198 ps
CPU time 0.71 seconds
Started Apr 25 12:49:48 PM PDT 24
Finished Apr 25 12:49:51 PM PDT 24
Peak memory 205032 kb
Host smart-0ebe9416-e5b5-4e3b-9610-dcc9e8ea83a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909859291 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.1909859291
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.1708380999
Short name T175
Test name
Test status
Simulation time 30029951 ps
CPU time 0.71 seconds
Started Apr 25 12:49:41 PM PDT 24
Finished Apr 25 12:49:42 PM PDT 24
Peak memory 205060 kb
Host smart-acc6963c-fcdc-4db8-9984-ba2c53f64995
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708380999 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.1708380999
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.3707160080
Short name T60
Test name
Test status
Simulation time 63052819 ps
CPU time 0.74 seconds
Started Apr 25 12:49:49 PM PDT 24
Finished Apr 25 12:49:52 PM PDT 24
Peak memory 205052 kb
Host smart-1120d75b-83c0-422f-afa6-5560cd675d03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707160080 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.3707160080
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.844959033
Short name T70
Test name
Test status
Simulation time 61392510 ps
CPU time 0.75 seconds
Started Apr 25 12:49:50 PM PDT 24
Finished Apr 25 12:49:52 PM PDT 24
Peak memory 205048 kb
Host smart-3d5229cf-5151-4778-a98b-4045e5a6e5c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844959033 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.844959033
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.1911127814
Short name T130
Test name
Test status
Simulation time 36825304 ps
CPU time 0.74 seconds
Started Apr 25 12:49:51 PM PDT 24
Finished Apr 25 12:49:53 PM PDT 24
Peak memory 205088 kb
Host smart-4d741d32-6238-4398-8e6c-4575a40e7cbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911127814 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.1911127814
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.1782055690
Short name T157
Test name
Test status
Simulation time 18885483 ps
CPU time 0.76 seconds
Started Apr 25 12:49:36 PM PDT 24
Finished Apr 25 12:49:39 PM PDT 24
Peak memory 205148 kb
Host smart-92301ef6-83f0-4d16-b269-7b568985c18d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782055690 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.1782055690
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.671934825
Short name T37
Test name
Test status
Simulation time 89495822 ps
CPU time 0.81 seconds
Started Apr 25 12:49:29 PM PDT 24
Finished Apr 25 12:49:31 PM PDT 24
Peak memory 204972 kb
Host smart-588b2f51-78cc-4036-b918-42e6e88ce3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671934825 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.671934825
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.1581596306
Short name T66
Test name
Test status
Simulation time 227476281 ps
CPU time 1.45 seconds
Started Apr 25 12:49:30 PM PDT 24
Finished Apr 25 12:49:33 PM PDT 24
Peak memory 229468 kb
Host smart-fc3ffe1e-05e8-4b07-b1bb-4cdacad3c23b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581596306 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.1581596306
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.3267884580
Short name T154
Test name
Test status
Simulation time 22738011 ps
CPU time 0.69 seconds
Started Apr 25 12:50:00 PM PDT 24
Finished Apr 25 12:50:03 PM PDT 24
Peak memory 205160 kb
Host smart-b78dc3e0-c64f-4246-b0ac-8b8628a3e280
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267884580 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.3267884580
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.757976005
Short name T151
Test name
Test status
Simulation time 44788498 ps
CPU time 0.7 seconds
Started Apr 25 12:50:01 PM PDT 24
Finished Apr 25 12:50:04 PM PDT 24
Peak memory 205176 kb
Host smart-bec08b7f-2efb-42f1-ac02-8cb1dfdeaaaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757976005 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.757976005
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.3810375367
Short name T34
Test name
Test status
Simulation time 33319167 ps
CPU time 0.71 seconds
Started Apr 25 12:49:59 PM PDT 24
Finished Apr 25 12:50:02 PM PDT 24
Peak memory 204356 kb
Host smart-dc3dc71d-1d71-4b75-935e-ae12eb050d6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810375367 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.3810375367
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.194745978
Short name T61
Test name
Test status
Simulation time 44412543 ps
CPU time 0.69 seconds
Started Apr 25 12:49:52 PM PDT 24
Finished Apr 25 12:49:54 PM PDT 24
Peak memory 205096 kb
Host smart-a8cad6e9-33d9-4cc4-a4e2-0dd5791d561a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194745978 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.194745978
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.3657930829
Short name T148
Test name
Test status
Simulation time 17059866 ps
CPU time 0.7 seconds
Started Apr 25 12:49:48 PM PDT 24
Finished Apr 25 12:49:51 PM PDT 24
Peak memory 204360 kb
Host smart-9343970c-c9aa-4b69-b31a-1eaf61a9089a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657930829 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.3657930829
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.2678654027
Short name T64
Test name
Test status
Simulation time 25305702 ps
CPU time 0.73 seconds
Started Apr 25 12:49:52 PM PDT 24
Finished Apr 25 12:49:54 PM PDT 24
Peak memory 205164 kb
Host smart-a443e8a3-fbc9-4fe8-826c-48b46f91c03e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678654027 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.2678654027
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.3215599818
Short name T45
Test name
Test status
Simulation time 16762453 ps
CPU time 0.71 seconds
Started Apr 25 12:49:55 PM PDT 24
Finished Apr 25 12:49:58 PM PDT 24
Peak memory 205084 kb
Host smart-e2dffcf3-b236-43b4-84d4-cafeb61005da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215599818 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.3215599818
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.2278479409
Short name T166
Test name
Test status
Simulation time 29241873 ps
CPU time 0.73 seconds
Started Apr 25 12:50:03 PM PDT 24
Finished Apr 25 12:50:07 PM PDT 24
Peak memory 205136 kb
Host smart-0a5183e7-35b7-4be6-9eb0-e1bc4a69130c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278479409 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.2278479409
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.652091046
Short name T153
Test name
Test status
Simulation time 21732590 ps
CPU time 0.76 seconds
Started Apr 25 12:49:54 PM PDT 24
Finished Apr 25 12:49:58 PM PDT 24
Peak memory 205092 kb
Host smart-7b62c2bc-8c0b-4462-8bd0-fe81f18ba0b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652091046 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.652091046
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.3799861875
Short name T57
Test name
Test status
Simulation time 41078494 ps
CPU time 0.81 seconds
Started Apr 25 12:49:36 PM PDT 24
Finished Apr 25 12:49:39 PM PDT 24
Peak memory 205036 kb
Host smart-f60f615a-9337-4111-8f15-8f98af4b54c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799861875 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.3799861875
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.2377781804
Short name T31
Test name
Test status
Simulation time 853713203 ps
CPU time 1.47 seconds
Started Apr 25 12:49:50 PM PDT 24
Finished Apr 25 12:49:53 PM PDT 24
Peak memory 229124 kb
Host smart-55b56f10-176c-4443-95ee-860d9e504e6d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377781804 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.2377781804
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all.3017110319
Short name T5
Test name
Test status
Simulation time 1602933230 ps
CPU time 3.64 seconds
Started Apr 25 12:49:28 PM PDT 24
Finished Apr 25 12:49:33 PM PDT 24
Peak memory 205384 kb
Host smart-933f8206-46a0-4578-8a34-721591c129b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017110319 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.3017110319
Directory /workspace/3.rv_dm_stress_all/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.3471666677
Short name T156
Test name
Test status
Simulation time 85108383 ps
CPU time 0.69 seconds
Started Apr 25 12:50:01 PM PDT 24
Finished Apr 25 12:50:04 PM PDT 24
Peak memory 204364 kb
Host smart-c62ffd6c-df6e-48c8-a310-4c762ba6d4d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471666677 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.3471666677
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.2624579840
Short name T147
Test name
Test status
Simulation time 29587929 ps
CPU time 0.72 seconds
Started Apr 25 12:49:57 PM PDT 24
Finished Apr 25 12:50:00 PM PDT 24
Peak memory 205136 kb
Host smart-9f7ce75f-5d65-4773-bed4-63e83b3b9d1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624579840 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.2624579840
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.4034321089
Short name T141
Test name
Test status
Simulation time 66343343 ps
CPU time 0.76 seconds
Started Apr 25 12:49:56 PM PDT 24
Finished Apr 25 12:49:59 PM PDT 24
Peak memory 205064 kb
Host smart-0604d729-8f44-44a6-b486-aed61b527191
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034321089 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.4034321089
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.2529176096
Short name T162
Test name
Test status
Simulation time 46786526 ps
CPU time 0.73 seconds
Started Apr 25 12:49:59 PM PDT 24
Finished Apr 25 12:50:02 PM PDT 24
Peak memory 205136 kb
Host smart-253a4a73-6d5f-4db7-864f-f9f24f369dfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529176096 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.2529176096
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.41468558
Short name T142
Test name
Test status
Simulation time 40561534 ps
CPU time 0.68 seconds
Started Apr 25 12:49:58 PM PDT 24
Finished Apr 25 12:50:01 PM PDT 24
Peak memory 205072 kb
Host smart-8b955e3a-b001-495c-9d3d-5f1243a31cb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41468558 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.41468558
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.1187650600
Short name T63
Test name
Test status
Simulation time 40292889 ps
CPU time 0.68 seconds
Started Apr 25 12:49:55 PM PDT 24
Finished Apr 25 12:50:03 PM PDT 24
Peak memory 205160 kb
Host smart-a2434114-090d-4f00-8503-d0169aaf18ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187650600 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.1187650600
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.91645962
Short name T146
Test name
Test status
Simulation time 123446319 ps
CPU time 0.72 seconds
Started Apr 25 12:49:58 PM PDT 24
Finished Apr 25 12:50:00 PM PDT 24
Peak memory 205084 kb
Host smart-4f7c11c1-b822-495d-8c55-be00ddbee3b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91645962 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.91645962
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.1122174661
Short name T35
Test name
Test status
Simulation time 25076010 ps
CPU time 0.75 seconds
Started Apr 25 12:50:29 PM PDT 24
Finished Apr 25 12:50:32 PM PDT 24
Peak memory 205060 kb
Host smart-e45ff87c-275e-4e3e-9d8c-37a82229c1de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122174661 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.1122174661
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.2843673848
Short name T145
Test name
Test status
Simulation time 72696151 ps
CPU time 0.69 seconds
Started Apr 25 12:49:59 PM PDT 24
Finished Apr 25 12:50:02 PM PDT 24
Peak memory 205072 kb
Host smart-56812900-a007-428c-b624-cfda60fdc834
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843673848 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.2843673848
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.1421499118
Short name T129
Test name
Test status
Simulation time 18683535 ps
CPU time 0.78 seconds
Started Apr 25 12:50:01 PM PDT 24
Finished Apr 25 12:50:04 PM PDT 24
Peak memory 205184 kb
Host smart-8d1e8ce1-7902-4b70-a713-0df206828ffe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421499118 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.1421499118
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_stress_all.286763912
Short name T36
Test name
Test status
Simulation time 2108167581 ps
CPU time 3.71 seconds
Started Apr 25 12:49:53 PM PDT 24
Finished Apr 25 12:49:58 PM PDT 24
Peak memory 205300 kb
Host smart-e9a58ecc-7c9b-437d-87a1-f0b02f1941ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286763912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.286763912
Directory /workspace/39.rv_dm_stress_all/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.1405724911
Short name T163
Test name
Test status
Simulation time 32592156 ps
CPU time 0.74 seconds
Started Apr 25 12:49:30 PM PDT 24
Finished Apr 25 12:49:32 PM PDT 24
Peak memory 205156 kb
Host smart-2d9b44b0-5818-4f0b-bc6b-6c50d528ab5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405724911 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.1405724911
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.411187126
Short name T4
Test name
Test status
Simulation time 30267073 ps
CPU time 0.69 seconds
Started Apr 25 12:49:40 PM PDT 24
Finished Apr 25 12:49:42 PM PDT 24
Peak memory 204992 kb
Host smart-ff3b98e8-d35e-4526-882c-cea1cf1ba7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411187126 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.411187126
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.2066874214
Short name T30
Test name
Test status
Simulation time 160210487 ps
CPU time 1.47 seconds
Started Apr 25 12:49:35 PM PDT 24
Finished Apr 25 12:49:38 PM PDT 24
Peak memory 229132 kb
Host smart-01bf43a6-2cf4-488a-ace3-786e70e45750
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066874214 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.2066874214
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.3866581352
Short name T33
Test name
Test status
Simulation time 18336314 ps
CPU time 0.69 seconds
Started Apr 25 12:49:53 PM PDT 24
Finished Apr 25 12:49:56 PM PDT 24
Peak memory 205092 kb
Host smart-9455ef93-9e7f-4357-b1b0-a4f5c51183a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866581352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.3866581352
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.2364234315
Short name T144
Test name
Test status
Simulation time 66881671 ps
CPU time 0.7 seconds
Started Apr 25 12:49:58 PM PDT 24
Finished Apr 25 12:50:01 PM PDT 24
Peak memory 205148 kb
Host smart-fb040559-d5ec-4640-bfe5-6076245f4d32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364234315 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.2364234315
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.147890366
Short name T173
Test name
Test status
Simulation time 39938904 ps
CPU time 0.76 seconds
Started Apr 25 12:50:13 PM PDT 24
Finished Apr 25 12:50:23 PM PDT 24
Peak memory 205140 kb
Host smart-04af508b-784c-467c-868b-57633946d6eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147890366 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.147890366
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.2314287086
Short name T2
Test name
Test status
Simulation time 155684547 ps
CPU time 0.77 seconds
Started Apr 25 12:49:58 PM PDT 24
Finished Apr 25 12:50:01 PM PDT 24
Peak memory 205148 kb
Host smart-f768c18d-7989-4746-807b-b00dbf01ac9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314287086 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.2314287086
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.350678407
Short name T168
Test name
Test status
Simulation time 47608033 ps
CPU time 0.66 seconds
Started Apr 25 12:50:14 PM PDT 24
Finished Apr 25 12:50:19 PM PDT 24
Peak memory 204972 kb
Host smart-da3a7097-fd4a-440f-8a4e-33b1554758a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350678407 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.350678407
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_stress_all.2552153818
Short name T20
Test name
Test status
Simulation time 2667377750 ps
CPU time 3.15 seconds
Started Apr 25 12:49:59 PM PDT 24
Finished Apr 25 12:50:04 PM PDT 24
Peak memory 205444 kb
Host smart-bf4c1727-072c-42f6-abba-554377e617ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552153818 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.2552153818
Directory /workspace/44.rv_dm_stress_all/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.831314171
Short name T164
Test name
Test status
Simulation time 25483033 ps
CPU time 0.71 seconds
Started Apr 25 12:50:12 PM PDT 24
Finished Apr 25 12:50:18 PM PDT 24
Peak memory 204972 kb
Host smart-616dc36f-744d-4a32-b135-6439a4cbfa14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831314171 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.831314171
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.1597792688
Short name T47
Test name
Test status
Simulation time 23602222 ps
CPU time 0.74 seconds
Started Apr 25 12:50:04 PM PDT 24
Finished Apr 25 12:50:08 PM PDT 24
Peak memory 205064 kb
Host smart-163d3eff-e2b2-400e-bc0d-a0f5fcb74a3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597792688 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.1597792688
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.2123812152
Short name T155
Test name
Test status
Simulation time 41305585 ps
CPU time 0.69 seconds
Started Apr 25 12:49:57 PM PDT 24
Finished Apr 25 12:49:59 PM PDT 24
Peak memory 205156 kb
Host smart-2d365e2a-d323-4efe-916c-f3217df9569a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123812152 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.2123812152
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.800122811
Short name T69
Test name
Test status
Simulation time 70962806 ps
CPU time 0.7 seconds
Started Apr 25 12:50:03 PM PDT 24
Finished Apr 25 12:50:07 PM PDT 24
Peak memory 205052 kb
Host smart-750b4970-c17c-493e-a31a-4ba9268c511b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800122811 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.800122811
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.1388404665
Short name T165
Test name
Test status
Simulation time 55290834 ps
CPU time 0.68 seconds
Started Apr 25 12:50:03 PM PDT 24
Finished Apr 25 12:50:07 PM PDT 24
Peak memory 205080 kb
Host smart-50821564-2ed6-41bf-a917-87e497ce54f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388404665 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.1388404665
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.1213125080
Short name T152
Test name
Test status
Simulation time 28440363 ps
CPU time 0.69 seconds
Started Apr 25 12:49:39 PM PDT 24
Finished Apr 25 12:49:41 PM PDT 24
Peak memory 205140 kb
Host smart-cb7348b2-b868-484e-bdda-b052b0d344c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213125080 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.1213125080
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.260085899
Short name T150
Test name
Test status
Simulation time 21817602 ps
CPU time 0.73 seconds
Started Apr 25 12:49:46 PM PDT 24
Finished Apr 25 12:49:48 PM PDT 24
Peak memory 205124 kb
Host smart-64ac0a23-eaf8-4c2c-8a18-99e5051a61f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260085899 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.260085899
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.1277272554
Short name T160
Test name
Test status
Simulation time 54663287 ps
CPU time 0.7 seconds
Started Apr 25 12:49:36 PM PDT 24
Finished Apr 25 12:49:39 PM PDT 24
Peak memory 205152 kb
Host smart-fd683b47-f1ca-47ae-abca-e28ce4a3aeaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277272554 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.1277272554
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.1417416418
Short name T143
Test name
Test status
Simulation time 44732648 ps
CPU time 0.7 seconds
Started Apr 25 12:49:44 PM PDT 24
Finished Apr 25 12:49:47 PM PDT 24
Peak memory 205048 kb
Host smart-b75ed710-d32d-4443-a34b-30c1f575f74f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417416418 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.1417416418
Directory /workspace/8.rv_dm_alert_test/latest
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