Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
75.74 90.33 76.92 86.93 64.10 76.17 98.42 37.33


Total tests in report: 304
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
51.49 51.49 81.47 81.47 48.49 48.49 32.82 32.82 42.31 42.31 61.83 61.83 91.45 91.45 2.09 2.09 /workspace/coverage/default/1.rv_dm_cmderr_busy.3253036955
58.03 6.53 85.70 4.23 58.79 10.30 58.93 26.11 42.31 0.00 64.17 2.33 92.93 1.48 3.36 1.27 /workspace/coverage/default/3.rv_dm_alert_test.2844871225
63.79 5.76 87.92 2.22 65.66 6.87 71.40 12.47 52.56 10.26 69.17 5.00 93.35 0.42 6.45 3.09 /workspace/coverage/default/41.rv_dm_stress_all.772511348
68.09 4.30 88.27 0.35 71.29 5.63 73.89 2.49 52.56 0.00 70.83 1.67 93.98 0.63 25.79 19.35 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2426322902
70.26 2.17 88.52 0.25 72.12 0.82 74.05 0.16 58.97 6.41 71.67 0.83 94.09 0.11 32.43 6.63 /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.3496656505
71.57 1.31 89.48 0.96 73.35 1.24 75.22 1.17 62.82 3.85 73.50 1.83 94.19 0.11 32.43 0.00 /workspace/coverage/default/47.rv_dm_stress_all.2969913653
72.47 0.90 89.48 0.00 73.90 0.55 78.84 3.62 62.82 0.00 73.67 0.17 95.78 1.58 32.79 0.36 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.4224254739
73.14 0.67 89.48 0.00 74.59 0.69 79.44 0.60 62.82 0.00 73.67 0.00 96.09 0.32 35.88 3.09 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.4101615802
73.51 0.38 89.48 0.00 74.59 0.00 80.33 0.88 62.82 0.00 73.67 0.00 97.57 1.48 36.15 0.27 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.3570759851
73.77 0.26 89.48 0.00 74.86 0.27 81.50 1.17 62.82 0.00 73.67 0.00 97.57 0.00 36.51 0.36 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.2652507830
73.98 0.21 89.48 0.00 74.86 0.00 82.94 1.45 62.82 0.00 73.67 0.00 97.57 0.00 36.51 0.00 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.3176980344
74.17 0.19 89.48 0.00 75.27 0.41 83.55 0.60 62.82 0.00 73.67 0.00 97.68 0.11 36.69 0.18 /workspace/coverage/default/1.rv_dm_sec_cm.2169493442
74.35 0.18 89.48 0.00 75.27 0.00 83.55 0.00 64.10 1.28 73.67 0.00 97.68 0.00 36.69 0.00 /workspace/coverage/default/0.rv_dm_tap_fsm.4140334980
74.50 0.15 89.78 0.30 75.55 0.27 83.55 0.00 64.10 0.00 74.17 0.50 97.68 0.00 36.69 0.00 /workspace/coverage/default/1.rv_dm_abstractcmd_status.80864668
74.65 0.15 89.78 0.00 75.55 0.00 84.39 0.84 64.10 0.00 74.17 0.00 97.68 0.00 36.88 0.18 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2938344539
74.79 0.14 89.88 0.10 75.96 0.41 84.39 0.00 64.10 0.00 74.67 0.50 97.68 0.00 36.88 0.00 /workspace/coverage/default/1.rv_dm_rom_read_access.3358276031
74.93 0.14 89.98 0.10 76.51 0.55 84.39 0.00 64.10 0.00 75.00 0.33 97.68 0.00 36.88 0.00 /workspace/coverage/default/1.rv_dm_progbuf_busy.2646747563
75.04 0.10 89.98 0.00 76.51 0.00 84.84 0.44 64.10 0.00 75.00 0.00 97.68 0.00 37.15 0.27 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.933039526
75.14 0.10 90.18 0.20 76.51 0.00 84.84 0.00 64.10 0.00 75.50 0.50 97.68 0.00 37.15 0.00 /workspace/coverage/default/0.rv_dm_cmderr_exception.4085249348
75.24 0.10 90.18 0.00 76.65 0.14 85.40 0.56 64.10 0.00 75.50 0.00 97.68 0.00 37.15 0.00 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.288298230
75.33 0.09 90.18 0.00 76.65 0.00 85.40 0.00 64.10 0.00 75.50 0.00 98.31 0.63 37.15 0.00 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.107808842
75.39 0.06 90.28 0.10 76.65 0.00 85.40 0.00 64.10 0.00 75.83 0.33 98.31 0.00 37.15 0.00 /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.3218617880
75.44 0.05 90.28 0.00 76.65 0.00 85.60 0.20 64.10 0.00 76.00 0.17 98.31 0.00 37.15 0.00 /workspace/coverage/default/20.rv_dm_alert_test.150649993
75.49 0.05 90.28 0.00 76.65 0.00 85.96 0.36 64.10 0.00 76.00 0.00 98.31 0.00 37.15 0.00 /workspace/coverage/cover_reg_top/22.rv_dm_tap_fsm_rand_reset.1663808119
75.54 0.05 90.33 0.05 76.79 0.14 85.96 0.00 64.10 0.00 76.17 0.17 98.31 0.00 37.15 0.00 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.940882779
75.58 0.03 90.33 0.00 76.79 0.00 86.20 0.24 64.10 0.00 76.17 0.00 98.31 0.00 37.15 0.00 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.2445918862
75.60 0.02 90.33 0.00 76.79 0.00 86.36 0.16 64.10 0.00 76.17 0.00 98.31 0.00 37.15 0.00 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2323538912
75.62 0.02 90.33 0.00 76.92 0.14 86.36 0.00 64.10 0.00 76.17 0.00 98.31 0.00 37.15 0.00 /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.1530930058
75.64 0.02 90.33 0.00 76.92 0.00 86.48 0.12 64.10 0.00 76.17 0.00 98.31 0.00 37.15 0.00 /workspace/coverage/default/14.rv_dm_stress_all.2507993027
75.65 0.02 90.33 0.00 76.92 0.00 86.48 0.00 64.10 0.00 76.17 0.00 98.42 0.11 37.15 0.00 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.3694086736
75.67 0.01 90.33 0.00 76.92 0.00 86.48 0.00 64.10 0.00 76.17 0.00 98.42 0.00 37.24 0.09 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.382202042
75.68 0.01 90.33 0.00 76.92 0.00 86.48 0.00 64.10 0.00 76.17 0.00 98.42 0.00 37.33 0.09 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.821113686
75.69 0.01 90.33 0.00 76.92 0.00 86.56 0.08 64.10 0.00 76.17 0.00 98.42 0.00 37.33 0.00 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.3835158604
75.70 0.01 90.33 0.00 76.92 0.00 86.65 0.08 64.10 0.00 76.17 0.00 98.42 0.00 37.33 0.00 /workspace/coverage/cover_reg_top/18.rv_dm_tap_fsm_rand_reset.1425167878
75.71 0.01 90.33 0.00 76.92 0.00 86.73 0.08 64.10 0.00 76.17 0.00 98.42 0.00 37.33 0.00 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.3950152759
75.73 0.01 90.33 0.00 76.92 0.00 86.81 0.08 64.10 0.00 76.17 0.00 98.42 0.00 37.33 0.00 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.4143659328
75.74 0.01 90.33 0.00 76.92 0.00 86.89 0.08 64.10 0.00 76.17 0.00 98.42 0.00 37.33 0.00 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.644907390
75.74 0.01 90.33 0.00 76.92 0.00 86.93 0.04 64.10 0.00 76.17 0.00 98.42 0.00 37.33 0.00 /workspace/coverage/default/9.rv_dm_alert_test.521093982

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1908500659
/workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.2672079605
/workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.483651615
/workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.4038750904
/workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.282766378
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.450034688
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.681742788
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.33806895
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3183904726
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.4145729998
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.4230926619
/workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.4184343003
/workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.3588543457
/workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.470025977
/workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.1074027027
/workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.2730333779
/workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.1372637223
/workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2720716802
/workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.1632309228
/workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.387153281
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.3419398271
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.4027016916
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.4079839250
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2974395873
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.3257138645
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.546667844
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.2804097588
/workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2946881768
/workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.2016023997
/workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.207476277
/workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.1115372998
/workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.3458328175
/workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2313676784
/workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.3835155842
/workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3002341353
/workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.1934906754
/workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.571758885
/workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1381312940
/workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.2710364727
/workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.2075673437
/workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.367068401
/workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.1924733722
/workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.1165751653
/workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.3386649094
/workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.3253078696
/workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.2880080024
/workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.2534081017
/workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3973376725
/workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.3910330190
/workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.601294982
/workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.831170525
/workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3119041620
/workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.18130367
/workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.3777618372
/workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2947781528
/workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.4217396913
/workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.2584272620
/workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1555118248
/workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2662029904
/workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3055195494
/workspace/coverage/cover_reg_top/14.rv_dm_tap_fsm_rand_reset.3717404817
/workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.120911400
/workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3346854210
/workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.671825018
/workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3251014681
/workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.873075966
/workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.1180217481
/workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.3926676532
/workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.48619700
/workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.465400432
/workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.1525125958
/workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.4040588355
/workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3809278828
/workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3780617804
/workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3639682607
/workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.595470114
/workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.3383015822
/workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.3666522356
/workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.57813819
/workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3774107406
/workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2877090539
/workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.1092440177
/workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.3359030436
/workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2732358634
/workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.3583651777
/workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.1325159270
/workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1650023436
/workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.872574086
/workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.2317903690
/workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1319089405
/workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.1444205634
/workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.172796453
/workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.3009473432
/workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1625766940
/workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.681841940
/workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2080913577
/workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2961146444
/workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3177974401
/workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.1711728077
/workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1105223988
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.868336576
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1246851304
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.381476969
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.3723994871
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.534350118
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.1946750701
/workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2990098556
/workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.751999537
/workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.1482980937
/workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.615166965
/workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.4066096733
/workspace/coverage/cover_reg_top/20.rv_dm_tap_fsm_rand_reset.3383153286
/workspace/coverage/cover_reg_top/23.rv_dm_tap_fsm_rand_reset.260856320
/workspace/coverage/cover_reg_top/25.rv_dm_tap_fsm_rand_reset.1618617559
/workspace/coverage/cover_reg_top/26.rv_dm_tap_fsm_rand_reset.1168749814
/workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.2978165050
/workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.3099339847
/workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.1706169068
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.2000960996
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.3212060474
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.2443468513
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.4279162334
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2901253361
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3653668048
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1827049214
/workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.1676893547
/workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.2488686973
/workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.3600715899
/workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.3166309853
/workspace/coverage/cover_reg_top/31.rv_dm_tap_fsm_rand_reset.3978630558
/workspace/coverage/cover_reg_top/35.rv_dm_tap_fsm_rand_reset.59521300
/workspace/coverage/cover_reg_top/39.rv_dm_tap_fsm_rand_reset.1465530390
/workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.3071336713
/workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.3518963378
/workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.287880972
/workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.1715435658
/workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.2289926642
/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.3883567004
/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.146901294
/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.4094928048
/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.2358135711
/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.3941592664
/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.1784559596
/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.3917598265
/workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.2475555449
/workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.2458384014
/workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1788471735
/workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.1038348581
/workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1031134166
/workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3092542121
/workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.655866595
/workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.2432745973
/workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3224058688
/workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1201126884
/workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.2488438715
/workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2420524414
/workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.3715145818
/workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1480677179
/workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.3244201
/workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2423815875
/workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.1691047233
/workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.1461590051
/workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3246180608
/workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.3417803888
/workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.1372168796
/workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.2633976183
/workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.2517156379
/workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.2611643212
/workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.1973597386
/workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.3482760291
/workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.2598089484
/workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1861893199
/workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2618883274
/workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.3322290401
/workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.3679120308
/workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.1454773381
/workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.453700621
/workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.135191560
/workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.3787342497
/workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3831693283
/workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.3581862838
/workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.3293788446
/workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.2868812045
/workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.902210592
/workspace/coverage/default/0.rv_dm_abstractcmd_status.873919053
/workspace/coverage/default/0.rv_dm_alert_test.1750557948
/workspace/coverage/default/0.rv_dm_cmderr_busy.1821161718
/workspace/coverage/default/0.rv_dm_cmderr_not_supported.2317995458
/workspace/coverage/default/0.rv_dm_dataaddr_rw_access.3312075066
/workspace/coverage/default/0.rv_dm_hart_unavail.750542107
/workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.1752980208
/workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.3557265474
/workspace/coverage/default/0.rv_dm_mem_tl_access_halted.3310152319
/workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.1222869042
/workspace/coverage/default/0.rv_dm_ndmreset_req.3857959662
/workspace/coverage/default/0.rv_dm_progbuf_busy.2732591473
/workspace/coverage/default/0.rv_dm_rom_read_access.4052068623
/workspace/coverage/default/0.rv_dm_sec_cm.2636240767
/workspace/coverage/default/0.rv_dm_smoke.748062907
/workspace/coverage/default/1.rv_dm_alert_test.727367678
/workspace/coverage/default/1.rv_dm_cmderr_exception.975452727
/workspace/coverage/default/1.rv_dm_cmderr_halt_resume.2661405790
/workspace/coverage/default/1.rv_dm_cmderr_not_supported.103567670
/workspace/coverage/default/1.rv_dm_dataaddr_rw_access.2799840559
/workspace/coverage/default/1.rv_dm_hart_unavail.3254701411
/workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.3087744407
/workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.3414419534
/workspace/coverage/default/1.rv_dm_mem_tl_access_halted.2061591903
/workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.2902296066
/workspace/coverage/default/1.rv_dm_ndmreset_req.4058726629
/workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.2734640531
/workspace/coverage/default/1.rv_dm_smoke.1345485976
/workspace/coverage/default/10.rv_dm_alert_test.243579911
/workspace/coverage/default/11.rv_dm_alert_test.29423139
/workspace/coverage/default/12.rv_dm_alert_test.3185270259
/workspace/coverage/default/13.rv_dm_alert_test.4150304714
/workspace/coverage/default/14.rv_dm_alert_test.587513185
/workspace/coverage/default/15.rv_dm_alert_test.1909859291
/workspace/coverage/default/16.rv_dm_alert_test.1708380999
/workspace/coverage/default/17.rv_dm_alert_test.3707160080
/workspace/coverage/default/18.rv_dm_alert_test.844959033
/workspace/coverage/default/19.rv_dm_alert_test.1911127814
/workspace/coverage/default/2.rv_dm_alert_test.1782055690
/workspace/coverage/default/2.rv_dm_hart_unavail.671934825
/workspace/coverage/default/2.rv_dm_sec_cm.1581596306
/workspace/coverage/default/21.rv_dm_alert_test.3267884580
/workspace/coverage/default/22.rv_dm_alert_test.757976005
/workspace/coverage/default/23.rv_dm_alert_test.3810375367
/workspace/coverage/default/24.rv_dm_alert_test.194745978
/workspace/coverage/default/25.rv_dm_alert_test.3657930829
/workspace/coverage/default/26.rv_dm_alert_test.2678654027
/workspace/coverage/default/27.rv_dm_alert_test.3215599818
/workspace/coverage/default/28.rv_dm_alert_test.2278479409
/workspace/coverage/default/29.rv_dm_alert_test.652091046
/workspace/coverage/default/3.rv_dm_hart_unavail.3799861875
/workspace/coverage/default/3.rv_dm_sec_cm.2377781804
/workspace/coverage/default/3.rv_dm_stress_all.3017110319
/workspace/coverage/default/30.rv_dm_alert_test.3471666677
/workspace/coverage/default/31.rv_dm_alert_test.2624579840
/workspace/coverage/default/32.rv_dm_alert_test.4034321089
/workspace/coverage/default/33.rv_dm_alert_test.2529176096
/workspace/coverage/default/34.rv_dm_alert_test.41468558
/workspace/coverage/default/35.rv_dm_alert_test.1187650600
/workspace/coverage/default/36.rv_dm_alert_test.91645962
/workspace/coverage/default/37.rv_dm_alert_test.1122174661
/workspace/coverage/default/38.rv_dm_alert_test.2843673848
/workspace/coverage/default/39.rv_dm_alert_test.1421499118
/workspace/coverage/default/39.rv_dm_stress_all.286763912
/workspace/coverage/default/4.rv_dm_alert_test.1405724911
/workspace/coverage/default/4.rv_dm_hart_unavail.411187126
/workspace/coverage/default/4.rv_dm_sec_cm.2066874214
/workspace/coverage/default/40.rv_dm_alert_test.3866581352
/workspace/coverage/default/41.rv_dm_alert_test.2364234315
/workspace/coverage/default/42.rv_dm_alert_test.147890366
/workspace/coverage/default/43.rv_dm_alert_test.2314287086
/workspace/coverage/default/44.rv_dm_alert_test.350678407
/workspace/coverage/default/44.rv_dm_stress_all.2552153818
/workspace/coverage/default/45.rv_dm_alert_test.831314171
/workspace/coverage/default/46.rv_dm_alert_test.1597792688
/workspace/coverage/default/47.rv_dm_alert_test.2123812152
/workspace/coverage/default/48.rv_dm_alert_test.800122811
/workspace/coverage/default/49.rv_dm_alert_test.1388404665
/workspace/coverage/default/5.rv_dm_alert_test.1213125080
/workspace/coverage/default/6.rv_dm_alert_test.260085899
/workspace/coverage/default/7.rv_dm_alert_test.1277272554
/workspace/coverage/default/8.rv_dm_alert_test.1417416418



Total test records in report: 304
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/1.rv_dm_abstractcmd_status.80864668 Apr 25 12:49:27 PM PDT 24 Apr 25 12:49:29 PM PDT 24 81739850 ps
T2 /workspace/coverage/default/43.rv_dm_alert_test.2314287086 Apr 25 12:49:58 PM PDT 24 Apr 25 12:50:01 PM PDT 24 155684547 ps
T3 /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.1222869042 Apr 25 12:49:22 PM PDT 24 Apr 25 12:49:25 PM PDT 24 495044848 ps
T4 /workspace/coverage/default/4.rv_dm_hart_unavail.411187126 Apr 25 12:49:40 PM PDT 24 Apr 25 12:49:42 PM PDT 24 30267073 ps
T17 /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.1530930058 Apr 25 12:49:27 PM PDT 24 Apr 25 12:49:29 PM PDT 24 959205566 ps
T7 /workspace/coverage/default/1.rv_dm_cmderr_busy.3253036955 Apr 25 12:49:51 PM PDT 24 Apr 25 12:50:02 PM PDT 24 3054780803 ps
T33 /workspace/coverage/default/40.rv_dm_alert_test.3866581352 Apr 25 12:49:53 PM PDT 24 Apr 25 12:49:56 PM PDT 24 18336314 ps
T34 /workspace/coverage/default/23.rv_dm_alert_test.3810375367 Apr 25 12:49:59 PM PDT 24 Apr 25 12:50:02 PM PDT 24 33319167 ps
T35 /workspace/coverage/default/37.rv_dm_alert_test.1122174661 Apr 25 12:50:29 PM PDT 24 Apr 25 12:50:32 PM PDT 24 25076010 ps
T45 /workspace/coverage/default/27.rv_dm_alert_test.3215599818 Apr 25 12:49:55 PM PDT 24 Apr 25 12:49:58 PM PDT 24 16762453 ps
T47 /workspace/coverage/default/46.rv_dm_alert_test.1597792688 Apr 25 12:50:04 PM PDT 24 Apr 25 12:50:08 PM PDT 24 23602222 ps
T8 /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.2061591903 Apr 25 12:49:24 PM PDT 24 Apr 25 12:49:25 PM PDT 24 64228201 ps
T37 /workspace/coverage/default/2.rv_dm_hart_unavail.671934825 Apr 25 12:49:29 PM PDT 24 Apr 25 12:49:31 PM PDT 24 89495822 ps
T46 /workspace/coverage/default/9.rv_dm_alert_test.521093982 Apr 25 12:49:35 PM PDT 24 Apr 25 12:49:37 PM PDT 24 58492965 ps
T5 /workspace/coverage/default/3.rv_dm_stress_all.3017110319 Apr 25 12:49:28 PM PDT 24 Apr 25 12:49:33 PM PDT 24 1602933230 ps
T30 /workspace/coverage/default/4.rv_dm_sec_cm.2066874214 Apr 25 12:49:35 PM PDT 24 Apr 25 12:49:38 PM PDT 24 160210487 ps
T67 /workspace/coverage/default/1.rv_dm_hart_unavail.3254701411 Apr 25 12:49:36 PM PDT 24 Apr 25 12:49:39 PM PDT 24 90092180 ps
T38 /workspace/coverage/default/3.rv_dm_alert_test.2844871225 Apr 25 12:49:56 PM PDT 24 Apr 25 12:49:59 PM PDT 24 40961081 ps
T68 /workspace/coverage/default/10.rv_dm_alert_test.243579911 Apr 25 12:49:34 PM PDT 24 Apr 25 12:49:36 PM PDT 24 31669316 ps
T57 /workspace/coverage/default/3.rv_dm_hart_unavail.3799861875 Apr 25 12:49:36 PM PDT 24 Apr 25 12:49:39 PM PDT 24 41078494 ps
T69 /workspace/coverage/default/48.rv_dm_alert_test.800122811 Apr 25 12:50:03 PM PDT 24 Apr 25 12:50:07 PM PDT 24 70962806 ps
T70 /workspace/coverage/default/18.rv_dm_alert_test.844959033 Apr 25 12:49:50 PM PDT 24 Apr 25 12:49:52 PM PDT 24 61392510 ps
T15 /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.2799840559 Apr 25 12:49:50 PM PDT 24 Apr 25 12:49:53 PM PDT 24 124045915 ps
T19 /workspace/coverage/default/0.rv_dm_cmderr_not_supported.2317995458 Apr 25 12:49:35 PM PDT 24 Apr 25 12:49:42 PM PDT 24 2688570439 ps
T6 /workspace/coverage/default/47.rv_dm_stress_all.2969913653 Apr 25 12:50:08 PM PDT 24 Apr 25 12:50:17 PM PDT 24 1487227277 ps
T21 /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.2661405790 Apr 25 12:49:32 PM PDT 24 Apr 25 12:49:35 PM PDT 24 120201443 ps
T18 /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.3557265474 Apr 25 12:49:35 PM PDT 24 Apr 25 12:49:38 PM PDT 24 229097491 ps
T129 /workspace/coverage/default/39.rv_dm_alert_test.1421499118 Apr 25 12:50:01 PM PDT 24 Apr 25 12:50:04 PM PDT 24 18683535 ps
T9 /workspace/coverage/default/14.rv_dm_stress_all.2507993027 Apr 25 12:49:52 PM PDT 24 Apr 25 12:50:00 PM PDT 24 6930606254 ps
T27 /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.3218617880 Apr 25 12:49:31 PM PDT 24 Apr 25 12:49:33 PM PDT 24 38057720 ps
T130 /workspace/coverage/default/19.rv_dm_alert_test.1911127814 Apr 25 12:49:51 PM PDT 24 Apr 25 12:49:53 PM PDT 24 36825304 ps
T61 /workspace/coverage/default/24.rv_dm_alert_test.194745978 Apr 25 12:49:52 PM PDT 24 Apr 25 12:49:54 PM PDT 24 44412543 ps
T26 /workspace/coverage/default/1.rv_dm_smoke.1345485976 Apr 25 12:49:25 PM PDT 24 Apr 25 12:49:27 PM PDT 24 1169513651 ps
T11 /workspace/coverage/default/0.rv_dm_cmderr_exception.4085249348 Apr 25 12:49:29 PM PDT 24 Apr 25 12:49:32 PM PDT 24 538617575 ps
T16 /workspace/coverage/default/0.rv_dm_ndmreset_req.3857959662 Apr 25 12:49:23 PM PDT 24 Apr 25 12:49:30 PM PDT 24 147578957 ps
T64 /workspace/coverage/default/26.rv_dm_alert_test.2678654027 Apr 25 12:49:52 PM PDT 24 Apr 25 12:49:54 PM PDT 24 25305702 ps
T59 /workspace/coverage/default/0.rv_dm_smoke.748062907 Apr 25 12:49:33 PM PDT 24 Apr 25 12:49:36 PM PDT 24 490046986 ps
T65 /workspace/coverage/default/20.rv_dm_alert_test.150649993 Apr 25 12:49:53 PM PDT 24 Apr 25 12:49:56 PM PDT 24 24715019 ps
T143 /workspace/coverage/default/8.rv_dm_alert_test.1417416418 Apr 25 12:49:44 PM PDT 24 Apr 25 12:49:47 PM PDT 24 44732648 ps
T146 /workspace/coverage/default/36.rv_dm_alert_test.91645962 Apr 25 12:49:58 PM PDT 24 Apr 25 12:50:00 PM PDT 24 123446319 ps
T31 /workspace/coverage/default/3.rv_dm_sec_cm.2377781804 Apr 25 12:49:50 PM PDT 24 Apr 25 12:49:53 PM PDT 24 853713203 ps
T165 /workspace/coverage/default/49.rv_dm_alert_test.1388404665 Apr 25 12:50:03 PM PDT 24 Apr 25 12:50:07 PM PDT 24 55290834 ps
T163 /workspace/coverage/default/4.rv_dm_alert_test.1405724911 Apr 25 12:49:30 PM PDT 24 Apr 25 12:49:32 PM PDT 24 32592156 ps
T25 /workspace/coverage/default/1.rv_dm_cmderr_exception.975452727 Apr 25 12:49:22 PM PDT 24 Apr 25 12:49:24 PM PDT 24 292577023 ps
T151 /workspace/coverage/default/22.rv_dm_alert_test.757976005 Apr 25 12:50:01 PM PDT 24 Apr 25 12:50:04 PM PDT 24 44788498 ps
T58 /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.3087744407 Apr 25 12:49:30 PM PDT 24 Apr 25 12:49:33 PM PDT 24 102556852 ps
T153 /workspace/coverage/default/29.rv_dm_alert_test.652091046 Apr 25 12:49:54 PM PDT 24 Apr 25 12:49:58 PM PDT 24 21732590 ps
T166 /workspace/coverage/default/28.rv_dm_alert_test.2278479409 Apr 25 12:50:03 PM PDT 24 Apr 25 12:50:07 PM PDT 24 29241873 ps
T22 /workspace/coverage/default/1.rv_dm_rom_read_access.3358276031 Apr 25 12:49:38 PM PDT 24 Apr 25 12:49:40 PM PDT 24 18784752 ps
T29 /workspace/coverage/default/0.rv_dm_abstractcmd_status.873919053 Apr 25 12:49:32 PM PDT 24 Apr 25 12:49:34 PM PDT 24 74444263 ps
T159 /workspace/coverage/default/11.rv_dm_alert_test.29423139 Apr 25 12:49:35 PM PDT 24 Apr 25 12:49:37 PM PDT 24 59547533 ps
T131 /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.3414419534 Apr 25 12:49:37 PM PDT 24 Apr 25 12:49:39 PM PDT 24 99841965 ps
T167 /workspace/coverage/default/0.rv_dm_alert_test.1750557948 Apr 25 12:49:29 PM PDT 24 Apr 25 12:49:31 PM PDT 24 24582122 ps
T32 /workspace/coverage/default/0.rv_dm_sec_cm.2636240767 Apr 25 12:49:23 PM PDT 24 Apr 25 12:49:26 PM PDT 24 161114755 ps
T66 /workspace/coverage/default/2.rv_dm_sec_cm.1581596306 Apr 25 12:49:30 PM PDT 24 Apr 25 12:49:33 PM PDT 24 227476281 ps
T28 /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.2734640531 Apr 25 12:49:25 PM PDT 24 Apr 25 12:49:27 PM PDT 24 95695530 ps
T168 /workspace/coverage/default/44.rv_dm_alert_test.350678407 Apr 25 12:50:14 PM PDT 24 Apr 25 12:50:19 PM PDT 24 47608033 ps
T144 /workspace/coverage/default/41.rv_dm_alert_test.2364234315 Apr 25 12:49:58 PM PDT 24 Apr 25 12:50:01 PM PDT 24 66881671 ps
T157 /workspace/coverage/default/2.rv_dm_alert_test.1782055690 Apr 25 12:49:36 PM PDT 24 Apr 25 12:49:39 PM PDT 24 18885483 ps
T169 /workspace/coverage/default/14.rv_dm_alert_test.587513185 Apr 25 12:49:52 PM PDT 24 Apr 25 12:49:55 PM PDT 24 29174140 ps
T170 /workspace/coverage/default/12.rv_dm_alert_test.3185270259 Apr 25 12:49:35 PM PDT 24 Apr 25 12:49:37 PM PDT 24 21859107 ps
T148 /workspace/coverage/default/25.rv_dm_alert_test.3657930829 Apr 25 12:49:48 PM PDT 24 Apr 25 12:49:51 PM PDT 24 17059866 ps
T20 /workspace/coverage/default/44.rv_dm_stress_all.2552153818 Apr 25 12:49:59 PM PDT 24 Apr 25 12:50:04 PM PDT 24 2667377750 ps
T145 /workspace/coverage/default/38.rv_dm_alert_test.2843673848 Apr 25 12:49:59 PM PDT 24 Apr 25 12:50:02 PM PDT 24 72696151 ps
T12 /workspace/coverage/default/0.rv_dm_progbuf_busy.2732591473 Apr 25 12:49:19 PM PDT 24 Apr 25 12:49:21 PM PDT 24 144952271 ps
T60 /workspace/coverage/default/17.rv_dm_alert_test.3707160080 Apr 25 12:49:49 PM PDT 24 Apr 25 12:49:52 PM PDT 24 63052819 ps
T63 /workspace/coverage/default/35.rv_dm_alert_test.1187650600 Apr 25 12:49:55 PM PDT 24 Apr 25 12:50:03 PM PDT 24 40292889 ps
T23 /workspace/coverage/default/0.rv_dm_rom_read_access.4052068623 Apr 25 12:49:31 PM PDT 24 Apr 25 12:49:33 PM PDT 24 77310539 ps
T154 /workspace/coverage/default/21.rv_dm_alert_test.3267884580 Apr 25 12:50:00 PM PDT 24 Apr 25 12:50:03 PM PDT 24 22738011 ps
T171 /workspace/coverage/default/0.rv_dm_hart_unavail.750542107 Apr 25 12:49:22 PM PDT 24 Apr 25 12:49:24 PM PDT 24 58944128 ps
T10 /workspace/coverage/default/0.rv_dm_cmderr_busy.1821161718 Apr 25 12:49:19 PM PDT 24 Apr 25 12:49:28 PM PDT 24 1970909484 ps
T156 /workspace/coverage/default/30.rv_dm_alert_test.3471666677 Apr 25 12:50:01 PM PDT 24 Apr 25 12:50:04 PM PDT 24 85108383 ps
T13 /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.2902296066 Apr 25 12:49:36 PM PDT 24 Apr 25 12:49:39 PM PDT 24 100340055 ps
T141 /workspace/coverage/default/32.rv_dm_alert_test.4034321089 Apr 25 12:49:56 PM PDT 24 Apr 25 12:49:59 PM PDT 24 66343343 ps
T62 /workspace/coverage/default/1.rv_dm_sec_cm.2169493442 Apr 25 12:49:26 PM PDT 24 Apr 25 12:49:28 PM PDT 24 210385388 ps
T14 /workspace/coverage/default/41.rv_dm_stress_all.772511348 Apr 25 12:49:54 PM PDT 24 Apr 25 12:50:12 PM PDT 24 7218816469 ps
T24 /workspace/coverage/default/1.rv_dm_progbuf_busy.2646747563 Apr 25 12:49:25 PM PDT 24 Apr 25 12:49:26 PM PDT 24 187355130 ps
T142 /workspace/coverage/default/34.rv_dm_alert_test.41468558 Apr 25 12:49:58 PM PDT 24 Apr 25 12:50:01 PM PDT 24 40561534 ps
T161 /workspace/coverage/default/15.rv_dm_alert_test.1909859291 Apr 25 12:49:48 PM PDT 24 Apr 25 12:49:51 PM PDT 24 33739198 ps
T172 /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.1752980208 Apr 25 12:49:13 PM PDT 24 Apr 25 12:49:17 PM PDT 24 99370922 ps
T79 /workspace/coverage/default/1.rv_dm_cmderr_not_supported.103567670 Apr 25 12:49:19 PM PDT 24 Apr 25 12:49:31 PM PDT 24 2717743003 ps
T96 /workspace/coverage/default/1.rv_dm_ndmreset_req.4058726629 Apr 25 12:49:38 PM PDT 24 Apr 25 12:49:41 PM PDT 24 409945569 ps
T152 /workspace/coverage/default/5.rv_dm_alert_test.1213125080 Apr 25 12:49:39 PM PDT 24 Apr 25 12:49:41 PM PDT 24 28440363 ps
T160 /workspace/coverage/default/7.rv_dm_alert_test.1277272554 Apr 25 12:49:36 PM PDT 24 Apr 25 12:49:39 PM PDT 24 54663287 ps
T155 /workspace/coverage/default/47.rv_dm_alert_test.2123812152 Apr 25 12:49:57 PM PDT 24 Apr 25 12:49:59 PM PDT 24 41305585 ps
T149 /workspace/coverage/default/13.rv_dm_alert_test.4150304714 Apr 25 12:49:41 PM PDT 24 Apr 25 12:49:43 PM PDT 24 152259383 ps
T164 /workspace/coverage/default/45.rv_dm_alert_test.831314171 Apr 25 12:50:12 PM PDT 24 Apr 25 12:50:18 PM PDT 24 25483033 ps
T173 /workspace/coverage/default/42.rv_dm_alert_test.147890366 Apr 25 12:50:13 PM PDT 24 Apr 25 12:50:23 PM PDT 24 39938904 ps
T162 /workspace/coverage/default/33.rv_dm_alert_test.2529176096 Apr 25 12:49:59 PM PDT 24 Apr 25 12:50:02 PM PDT 24 46786526 ps
T174 /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.3312075066 Apr 25 12:49:18 PM PDT 24 Apr 25 12:49:20 PM PDT 24 56533051 ps
T36 /workspace/coverage/default/39.rv_dm_stress_all.286763912 Apr 25 12:49:53 PM PDT 24 Apr 25 12:49:58 PM PDT 24 2108167581 ps
T150 /workspace/coverage/default/6.rv_dm_alert_test.260085899 Apr 25 12:49:46 PM PDT 24 Apr 25 12:49:48 PM PDT 24 21817602 ps
T147 /workspace/coverage/default/31.rv_dm_alert_test.2624579840 Apr 25 12:49:57 PM PDT 24 Apr 25 12:50:00 PM PDT 24 29587929 ps
T140 /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.3310152319 Apr 25 12:49:25 PM PDT 24 Apr 25 12:49:27 PM PDT 24 58412276 ps
T71 /workspace/coverage/default/0.rv_dm_tap_fsm.4140334980 Apr 25 12:49:29 PM PDT 24 Apr 25 12:49:34 PM PDT 24 1487228036 ps
T175 /workspace/coverage/default/16.rv_dm_alert_test.1708380999 Apr 25 12:49:41 PM PDT 24 Apr 25 12:49:42 PM PDT 24 30029951 ps
T158 /workspace/coverage/default/1.rv_dm_alert_test.727367678 Apr 25 12:49:25 PM PDT 24 Apr 25 12:49:26 PM PDT 24 20149827 ps
T44 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.470025977 Apr 25 12:48:05 PM PDT 24 Apr 25 12:48:10 PM PDT 24 411525155 ps
T39 /workspace/coverage/cover_reg_top/35.rv_dm_tap_fsm_rand_reset.59521300 Apr 25 12:48:47 PM PDT 24 Apr 25 12:49:00 PM PDT 24 16351308199 ps
T42 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3780617804 Apr 25 12:48:28 PM PDT 24 Apr 25 12:48:32 PM PDT 24 163784482 ps
T40 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2426322902 Apr 25 12:48:29 PM PDT 24 Apr 25 12:48:51 PM PDT 24 4472515895 ps
T43 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.107808842 Apr 25 12:48:02 PM PDT 24 Apr 25 12:48:08 PM PDT 24 1217884960 ps
T41 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.135191560 Apr 25 12:48:17 PM PDT 24 Apr 25 12:48:21 PM PDT 24 37559154 ps
T78 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.644907390 Apr 25 12:48:19 PM PDT 24 Apr 25 12:48:30 PM PDT 24 685762809 ps
T97 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3055195494 Apr 25 12:48:27 PM PDT 24 Apr 25 12:48:36 PM PDT 24 823585245 ps
T89 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.120911400 Apr 25 12:48:34 PM PDT 24 Apr 25 12:48:40 PM PDT 24 165354792 ps
T98 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.282766378 Apr 25 12:47:59 PM PDT 24 Apr 25 12:48:02 PM PDT 24 28489649 ps
T99 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.2289926642 Apr 25 12:48:17 PM PDT 24 Apr 25 12:48:19 PM PDT 24 774540760 ps
T90 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.4066096733 Apr 25 12:48:02 PM PDT 24 Apr 25 12:48:08 PM PDT 24 82469283 ps
T176 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.2443468513 Apr 25 12:48:10 PM PDT 24 Apr 25 12:48:13 PM PDT 24 220286940 ps
T100 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.3071336713 Apr 25 12:47:59 PM PDT 24 Apr 25 12:49:08 PM PDT 24 1174259985 ps
T54 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.2710364727 Apr 25 12:48:20 PM PDT 24 Apr 25 12:48:23 PM PDT 24 330556134 ps
T177 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2946881768 Apr 25 12:48:07 PM PDT 24 Apr 25 12:48:09 PM PDT 24 45640555 ps
T73 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3809278828 Apr 25 12:48:29 PM PDT 24 Apr 25 12:48:31 PM PDT 24 192741663 ps
T101 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1650023436 Apr 25 12:48:35 PM PDT 24 Apr 25 12:48:44 PM PDT 24 1541902773 ps
T102 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.2598089484 Apr 25 12:48:15 PM PDT 24 Apr 25 12:48:18 PM PDT 24 61985146 ps
T91 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.4101615802 Apr 25 12:48:12 PM PDT 24 Apr 25 12:48:22 PM PDT 24 3861712305 ps
T103 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.601294982 Apr 25 12:48:23 PM PDT 24 Apr 25 12:48:26 PM PDT 24 96803423 ps
T107 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1105223988 Apr 25 12:48:06 PM PDT 24 Apr 25 12:48:10 PM PDT 24 433743893 ps
T51 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1555118248 Apr 25 12:48:26 PM PDT 24 Apr 25 12:48:35 PM PDT 24 2291926495 ps
T72 /workspace/coverage/cover_reg_top/14.rv_dm_tap_fsm_rand_reset.3717404817 Apr 25 12:48:19 PM PDT 24 Apr 25 12:48:33 PM PDT 24 10832182095 ps
T108 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.3570759851 Apr 25 12:48:12 PM PDT 24 Apr 25 12:48:42 PM PDT 24 2704730687 ps
T74 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2662029904 Apr 25 12:48:23 PM PDT 24 Apr 25 12:48:25 PM PDT 24 52696359 ps
T75 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.546667844 Apr 25 12:47:55 PM PDT 24 Apr 25 12:47:58 PM PDT 24 175417591 ps
T178 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3831693283 Apr 25 12:48:15 PM PDT 24 Apr 25 12:48:17 PM PDT 24 158247014 ps
T92 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.1711728077 Apr 25 12:48:08 PM PDT 24 Apr 25 12:48:14 PM PDT 24 698613973 ps
T179 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.2432745973 Apr 25 12:48:04 PM PDT 24 Apr 25 12:48:09 PM PDT 24 1871308007 ps
T93 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.4038750904 Apr 25 12:48:07 PM PDT 24 Apr 25 12:48:12 PM PDT 24 336474637 ps
T115 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.287880972 Apr 25 12:48:20 PM PDT 24 Apr 25 12:48:24 PM PDT 24 113412259 ps
T104 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.821113686 Apr 25 12:48:09 PM PDT 24 Apr 25 12:48:30 PM PDT 24 3454364420 ps
T48 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.146901294 Apr 25 12:48:06 PM PDT 24 Apr 25 12:48:10 PM PDT 24 544805677 ps
T128 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.2730333779 Apr 25 12:48:12 PM PDT 24 Apr 25 12:48:42 PM PDT 24 4064482378 ps
T116 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.1372637223 Apr 25 12:48:04 PM PDT 24 Apr 25 12:49:14 PM PDT 24 23247829719 ps
T180 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3177974401 Apr 25 12:48:13 PM PDT 24 Apr 25 12:48:17 PM PDT 24 116986771 ps
T181 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.2475555449 Apr 25 12:48:10 PM PDT 24 Apr 25 12:48:12 PM PDT 24 49856492 ps
T182 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3251014681 Apr 25 12:48:41 PM PDT 24 Apr 25 12:48:45 PM PDT 24 150552804 ps
T81 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.48619700 Apr 25 12:48:24 PM PDT 24 Apr 25 12:48:35 PM PDT 24 741583531 ps
T52 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.3176980344 Apr 25 12:48:06 PM PDT 24 Apr 25 12:48:38 PM PDT 24 16215458490 ps
T117 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1480677179 Apr 25 12:48:20 PM PDT 24 Apr 25 12:48:23 PM PDT 24 30610096 ps
T94 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.453700621 Apr 25 12:48:18 PM PDT 24 Apr 25 12:48:28 PM PDT 24 204813942 ps
T183 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.3941592664 Apr 25 12:48:08 PM PDT 24 Apr 25 12:48:14 PM PDT 24 2492340951 ps
T95 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.1115372998 Apr 25 12:48:26 PM PDT 24 Apr 25 12:48:38 PM PDT 24 3923319871 ps
T105 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.1934906754 Apr 25 12:48:28 PM PDT 24 Apr 25 12:48:31 PM PDT 24 30399440 ps
T184 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3224058688 Apr 25 12:49:06 PM PDT 24 Apr 25 12:49:16 PM PDT 24 40290374 ps
T87 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.1715435658 Apr 25 12:48:11 PM PDT 24 Apr 25 12:48:15 PM PDT 24 71511850 ps
T106 /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.3496656505 Apr 25 12:48:25 PM PDT 24 Apr 25 12:49:00 PM PDT 24 17561627079 ps
T185 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.3581862838 Apr 25 12:48:10 PM PDT 24 Apr 25 12:48:12 PM PDT 24 115258229 ps
T134 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3346854210 Apr 25 12:48:33 PM PDT 24 Apr 25 12:48:53 PM PDT 24 1754227789 ps
T186 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.940882779 Apr 25 12:48:16 PM PDT 24 Apr 25 12:48:18 PM PDT 24 29214031 ps
T83 /workspace/coverage/cover_reg_top/18.rv_dm_tap_fsm_rand_reset.1425167878 Apr 25 12:48:33 PM PDT 24 Apr 25 12:48:53 PM PDT 24 10415733570 ps
T118 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.3099339847 Apr 25 12:48:05 PM PDT 24 Apr 25 12:48:09 PM PDT 24 256056195 ps
T187 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3653668048 Apr 25 12:48:14 PM PDT 24 Apr 25 12:48:17 PM PDT 24 30583393 ps
T188 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.1525125958 Apr 25 12:48:35 PM PDT 24 Apr 25 12:48:38 PM PDT 24 184940318 ps
T76 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.2652507830 Apr 25 12:48:26 PM PDT 24 Apr 25 12:48:46 PM PDT 24 9078869351 ps
T109 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3774107406 Apr 25 12:48:27 PM PDT 24 Apr 25 12:48:33 PM PDT 24 222754511 ps
T125 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.1180217481 Apr 25 12:48:30 PM PDT 24 Apr 25 12:48:38 PM PDT 24 204823340 ps
T126 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.2517156379 Apr 25 12:48:33 PM PDT 24 Apr 25 12:48:42 PM PDT 24 1691501982 ps
T88 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.933039526 Apr 25 12:49:07 PM PDT 24 Apr 25 12:49:28 PM PDT 24 955733530 ps
T189 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2313676784 Apr 25 12:49:11 PM PDT 24 Apr 25 12:49:18 PM PDT 24 690258930 ps
T190 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.3917598265 Apr 25 12:48:07 PM PDT 24 Apr 25 12:48:09 PM PDT 24 51000494 ps
T191 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.3950152759 Apr 25 12:48:14 PM PDT 24 Apr 25 12:48:22 PM PDT 24 3848190124 ps
T192 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.4079839250 Apr 25 12:48:13 PM PDT 24 Apr 25 12:48:17 PM PDT 24 365504564 ps
T132 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.1038348581 Apr 25 12:48:09 PM PDT 24 Apr 25 12:48:15 PM PDT 24 142843562 ps
T193 /workspace/coverage/cover_reg_top/20.rv_dm_tap_fsm_rand_reset.3383153286 Apr 25 12:48:36 PM PDT 24 Apr 25 12:49:01 PM PDT 24 10879784458 ps
T80 /workspace/coverage/cover_reg_top/23.rv_dm_tap_fsm_rand_reset.260856320 Apr 25 12:48:35 PM PDT 24 Apr 25 12:48:52 PM PDT 24 6060997758 ps
T194 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.3482760291 Apr 25 12:48:29 PM PDT 24 Apr 25 12:48:34 PM PDT 24 168436370 ps
T195 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.1784559596 Apr 25 12:48:12 PM PDT 24 Apr 25 12:48:15 PM PDT 24 152763066 ps
T53 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.3583651777 Apr 25 12:48:34 PM PDT 24 Apr 25 12:48:37 PM PDT 24 541156863 ps
T196 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.2458384014 Apr 25 12:49:11 PM PDT 24 Apr 25 12:49:16 PM PDT 24 118365570 ps
T197 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3246180608 Apr 25 12:48:18 PM PDT 24 Apr 25 12:48:23 PM PDT 24 2032601637 ps
T133 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.2611643212 Apr 25 12:48:07 PM PDT 24 Apr 25 12:48:13 PM PDT 24 163594318 ps
T198 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2423815875 Apr 25 12:48:15 PM PDT 24 Apr 25 12:48:17 PM PDT 24 92985530 ps
T199 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.3715145818 Apr 25 12:48:06 PM PDT 24 Apr 25 12:48:15 PM PDT 24 3545845473 ps
T200 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.3166309853 Apr 25 12:48:12 PM PDT 24 Apr 25 12:48:19 PM PDT 24 130390567 ps
T201 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.2534081017 Apr 25 12:48:20 PM PDT 24 Apr 25 12:48:22 PM PDT 24 153468055 ps
T127 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.18130367 Apr 25 12:48:30 PM PDT 24 Apr 25 12:48:36 PM PDT 24 237735914 ps
T110 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1201126884 Apr 25 12:48:24 PM PDT 24 Apr 25 12:48:29 PM PDT 24 840685700 ps
T202 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.2672079605 Apr 25 12:48:06 PM PDT 24 Apr 25 12:48:39 PM PDT 24 6308497517 ps
T203 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.3257138645 Apr 25 12:47:57 PM PDT 24 Apr 25 12:48:01 PM PDT 24 1184913339 ps
T204 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.3009473432 Apr 25 12:48:42 PM PDT 24 Apr 25 12:48:45 PM PDT 24 84254950 ps
T205 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.1632309228 Apr 25 12:48:04 PM PDT 24 Apr 25 12:48:11 PM PDT 24 3585423311 ps
T119 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.655866595 Apr 25 12:48:27 PM PDT 24 Apr 25 12:48:30 PM PDT 24 183439442 ps
T111 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.3322290401 Apr 25 12:48:11 PM PDT 24 Apr 25 12:48:22 PM PDT 24 548696804 ps
T206 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.4217396913 Apr 25 12:48:24 PM PDT 24 Apr 25 12:48:27 PM PDT 24 148957353 ps
T207 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.3386649094 Apr 25 12:48:34 PM PDT 24 Apr 25 12:48:37 PM PDT 24 64076805 ps
T208 /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.615166965 Apr 25 12:48:12 PM PDT 24 Apr 25 12:48:52 PM PDT 24 11030329666 ps
T209 /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.3679120308 Apr 25 12:48:24 PM PDT 24 Apr 25 12:48:49 PM PDT 24 7132389470 ps
T210 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3183904726 Apr 25 12:48:00 PM PDT 24 Apr 25 12:48:02 PM PDT 24 66232409 ps
T211 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2877090539 Apr 25 12:48:40 PM PDT 24 Apr 25 12:48:44 PM PDT 24 121214731 ps
T135 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2420524414 Apr 25 12:48:37 PM PDT 24 Apr 25 12:48:54 PM PDT 24 1540194337 ps
T212 /workspace/coverage/cover_reg_top/31.rv_dm_tap_fsm_rand_reset.3978630558 Apr 25 12:48:29 PM PDT 24 Apr 25 12:48:45 PM PDT 24 14273712049 ps
T213 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.3723994871 Apr 25 12:48:14 PM PDT 24 Apr 25 12:48:23 PM PDT 24 6153615304 ps
T214 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2901253361 Apr 25 12:48:12 PM PDT 24 Apr 25 12:48:17 PM PDT 24 1958960815 ps
T82 /workspace/coverage/cover_reg_top/22.rv_dm_tap_fsm_rand_reset.1663808119 Apr 25 12:49:38 PM PDT 24 Apr 25 12:50:04 PM PDT 24 8231207961 ps
T215 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.33806895 Apr 25 12:47:59 PM PDT 24 Apr 25 12:48:03 PM PDT 24 481526769 ps
T216 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.2488438715 Apr 25 12:48:21 PM PDT 24 Apr 25 12:48:24 PM PDT 24 132423581 ps
T49 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2323538912 Apr 25 12:48:18 PM PDT 24 Apr 25 12:48:22 PM PDT 24 1804171327 ps
T112 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.3253078696 Apr 25 12:48:31 PM PDT 24 Apr 25 12:48:34 PM PDT 24 313508549 ps
T120 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2080913577 Apr 25 12:48:05 PM PDT 24 Apr 25 12:49:10 PM PDT 24 4550156067 ps
T217 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.207476277 Apr 25 12:48:08 PM PDT 24 Apr 25 12:48:12 PM PDT 24 183642994 ps
T113 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.3293788446 Apr 25 12:48:26 PM PDT 24 Apr 25 12:48:33 PM PDT 24 1272316332 ps
T218 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1319089405 Apr 25 12:48:33 PM PDT 24 Apr 25 12:48:44 PM PDT 24 3347627771 ps
T123 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2732358634 Apr 25 12:48:34 PM PDT 24 Apr 25 12:48:37 PM PDT 24 867623009 ps
T124 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1908500659 Apr 25 12:48:05 PM PDT 24 Apr 25 12:48:39 PM PDT 24 1772507945 ps
T219 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.4230926619 Apr 25 12:48:12 PM PDT 24 Apr 25 12:48:15 PM PDT 24 66829738 ps
T220 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.831170525 Apr 25 12:48:34 PM PDT 24 Apr 25 12:48:41 PM PDT 24 1736437445 ps
T221 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.172796453 Apr 25 12:48:26 PM PDT 24 Apr 25 12:48:31 PM PDT 24 1011575170 ps
T222 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.3383015822 Apr 25 12:48:24 PM PDT 24 Apr 25 12:48:27 PM PDT 24 123532254 ps
T223 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.3588543457 Apr 25 12:48:03 PM PDT 24 Apr 25 12:48:05 PM PDT 24 57860775 ps
T114 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1788471735 Apr 25 12:48:06 PM PDT 24 Apr 25 12:48:16 PM PDT 24 416770989 ps
T50 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.4224254739 Apr 25 12:47:55 PM PDT 24 Apr 25 12:47:58 PM PDT 24 957722452 ps
T224 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.1706169068 Apr 25 12:48:06 PM PDT 24 Apr 25 12:48:10 PM PDT 24 49844265 ps
T225 /workspace/coverage/cover_reg_top/26.rv_dm_tap_fsm_rand_reset.1168749814 Apr 25 12:48:25 PM PDT 24 Apr 25 12:48:44 PM PDT 24 9835556027 ps
T226 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.2584272620 Apr 25 12:48:36 PM PDT 24 Apr 25 12:48:40 PM PDT 24 432410509 ps
T227 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.57813819 Apr 25 12:48:28 PM PDT 24 Apr 25 12:48:30 PM PDT 24 72505241 ps
T228 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3002341353 Apr 25 12:48:43 PM PDT 24 Apr 25 12:48:52 PM PDT 24 145775162 ps
T229 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.450034688 Apr 25 12:47:53 PM PDT 24 Apr 25 12:48:41 PM PDT 24 17356373288 ps
T230 /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1625766940 Apr 25 12:48:44 PM PDT 24 Apr 25 12:48:50 PM PDT 24 820477853 ps
T231 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2990098556 Apr 25 12:48:09 PM PDT 24 Apr 25 12:48:11 PM PDT 24 41100461 ps
T232 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.671825018 Apr 25 12:48:27 PM PDT 24 Apr 25 12:48:31 PM PDT 24 176412260 ps
T233 /workspace/coverage/cover_reg_top/39.rv_dm_tap_fsm_rand_reset.1465530390 Apr 25 12:48:26 PM PDT 24 Apr 25 12:48:40 PM PDT 24 17620781851 ps
T234 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1861893199 Apr 25 12:48:14 PM PDT 24 Apr 25 12:48:20 PM PDT 24 1129988711 ps
T235 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.681841940 Apr 25 12:48:35 PM PDT 24 Apr 25 12:48:39 PM PDT 24 209257528 ps
T236 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.387153281 Apr 25 12:48:05 PM PDT 24 Apr 25 12:48:08 PM PDT 24 69573544 ps
T237 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.3835155842 Apr 25 12:48:18 PM PDT 24 Apr 25 12:48:20 PM PDT 24 155002779 ps
T238 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.4094928048 Apr 25 12:48:08 PM PDT 24 Apr 25 12:48:13 PM PDT 24 773380545 ps
T239 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.1924733722 Apr 25 12:48:20 PM PDT 24 Apr 25 12:48:28 PM PDT 24 227471738 ps
T56 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.4143659328 Apr 25 12:48:11 PM PDT 24 Apr 25 12:48:15 PM PDT 24 2207106846 ps
T240 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1381312940 Apr 25 12:48:36 PM PDT 24 Apr 25 12:48:41 PM PDT 24 35892496 ps
T121 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.3694086736 Apr 25 12:48:29 PM PDT 24 Apr 25 12:48:33 PM PDT 24 138113938 ps
T241 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.3419398271 Apr 25 12:48:06 PM PDT 24 Apr 25 12:48:19 PM PDT 24 10078949034 ps
T242 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.1676893547 Apr 25 12:48:07 PM PDT 24 Apr 25 12:48:09 PM PDT 24 52221801 ps
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T244 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3973376725 Apr 25 12:48:17 PM PDT 24 Apr 25 12:48:25 PM PDT 24 823134859 ps
T245 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2720716802 Apr 25 12:48:22 PM PDT 24 Apr 25 12:48:24 PM PDT 24 183105810 ps
T246 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.1454773381 Apr 25 12:48:25 PM PDT 24 Apr 25 12:48:31 PM PDT 24 809422790 ps
T247 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.571758885 Apr 25 12:48:18 PM PDT 24 Apr 25 12:48:39 PM PDT 24 1554723463 ps
T248 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.4027016916 Apr 25 12:48:07 PM PDT 24 Apr 25 12:48:55 PM PDT 24 34304995264 ps
T249 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.465400432 Apr 25 12:48:34 PM PDT 24 Apr 25 12:48:40 PM PDT 24 1939640774 ps
T250 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.2880080024 Apr 25 12:48:39 PM PDT 24 Apr 25 12:48:44 PM PDT 24 921218387 ps
T251 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1246851304 Apr 25 12:48:01 PM PDT 24 Apr 25 12:48:03 PM PDT 24 525221974 ps
T138 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.1973597386 Apr 25 12:48:05 PM PDT 24 Apr 25 12:48:15 PM PDT 24 815068582 ps
T252 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.1946750701 Apr 25 12:48:03 PM PDT 24 Apr 25 12:48:05 PM PDT 24 45191942 ps
T253 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.3600715899 Apr 25 12:48:15 PM PDT 24 Apr 25 12:48:20 PM PDT 24 327443715 ps
T254 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.483651615 Apr 25 12:48:09 PM PDT 24 Apr 25 12:48:12 PM PDT 24 74002208 ps
T255 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.3359030436 Apr 25 12:48:43 PM PDT 24 Apr 25 12:48:48 PM PDT 24 1136407290 ps
T256 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.2804097588 Apr 25 12:48:11 PM PDT 24 Apr 25 12:48:13 PM PDT 24 33109979 ps
T55 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.288298230 Apr 25 12:47:53 PM PDT 24 Apr 25 12:47:58 PM PDT 24 778857245 ps
T137 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.1092440177 Apr 25 12:48:32 PM PDT 24 Apr 25 12:48:44 PM PDT 24 2690566080 ps
T257 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.4145729998 Apr 25 12:47:58 PM PDT 24 Apr 25 12:48:03 PM PDT 24 2863728649 ps
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