Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
79.17 93.86 81.18 87.61 73.08 82.33 98.52 37.60


Total test records in report: 305
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html
T257 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.205050313 Apr 28 12:55:16 PM PDT 24 Apr 28 12:55:21 PM PDT 24 277275908 ps
T258 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.715648441 Apr 28 12:55:03 PM PDT 24 Apr 28 12:55:15 PM PDT 24 5555591939 ps
T259 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.3811614084 Apr 28 12:54:51 PM PDT 24 Apr 28 12:55:25 PM PDT 24 2572585671 ps
T260 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2789666548 Apr 28 12:55:10 PM PDT 24 Apr 28 12:55:26 PM PDT 24 1621056032 ps
T130 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2966972066 Apr 28 12:55:07 PM PDT 24 Apr 28 12:55:26 PM PDT 24 3417017440 ps
T261 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1500553331 Apr 28 12:54:47 PM PDT 24 Apr 28 12:54:49 PM PDT 24 40649802 ps
T262 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.2495264181 Apr 28 12:54:42 PM PDT 24 Apr 28 12:54:44 PM PDT 24 32120132 ps
T263 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.2928310062 Apr 28 12:54:50 PM PDT 24 Apr 28 12:54:51 PM PDT 24 38989421 ps
T264 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.4285034205 Apr 28 12:54:44 PM PDT 24 Apr 28 12:55:21 PM PDT 24 39048482118 ps
T265 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2035661382 Apr 28 12:54:47 PM PDT 24 Apr 28 12:54:55 PM PDT 24 2020446704 ps
T266 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.1757187911 Apr 28 12:54:53 PM PDT 24 Apr 28 12:54:54 PM PDT 24 27776885 ps
T267 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.921175584 Apr 28 12:55:08 PM PDT 24 Apr 28 12:55:13 PM PDT 24 604638139 ps
T268 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2115037741 Apr 28 12:55:07 PM PDT 24 Apr 28 12:55:09 PM PDT 24 66184161 ps
T269 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.393859635 Apr 28 12:55:04 PM PDT 24 Apr 28 12:55:10 PM PDT 24 161816880 ps
T270 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.2473604127 Apr 28 12:54:43 PM PDT 24 Apr 28 12:54:47 PM PDT 24 825117279 ps
T271 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3117915274 Apr 28 12:55:07 PM PDT 24 Apr 28 12:55:08 PM PDT 24 77571917 ps
T272 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2566264216 Apr 28 12:55:12 PM PDT 24 Apr 28 12:55:18 PM PDT 24 4409933859 ps
T273 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3421147155 Apr 28 12:55:17 PM PDT 24 Apr 28 12:55:23 PM PDT 24 250289461 ps
T112 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3522698025 Apr 28 12:54:37 PM PDT 24 Apr 28 12:55:50 PM PDT 24 6717996843 ps
T274 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.1949186114 Apr 28 12:54:48 PM PDT 24 Apr 28 12:54:49 PM PDT 24 17945179 ps
T275 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.3218315834 Apr 28 12:55:09 PM PDT 24 Apr 28 12:55:14 PM PDT 24 214717973 ps
T276 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.3468589607 Apr 28 12:54:42 PM PDT 24 Apr 28 12:54:44 PM PDT 24 129015773 ps
T277 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.4078589809 Apr 28 12:55:17 PM PDT 24 Apr 28 12:55:18 PM PDT 24 58821910 ps
T278 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.499545549 Apr 28 12:55:09 PM PDT 24 Apr 28 12:55:11 PM PDT 24 53432879 ps
T279 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.235537829 Apr 28 12:55:17 PM PDT 24 Apr 28 12:55:24 PM PDT 24 2360094411 ps
T69 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.895107879 Apr 28 12:54:42 PM PDT 24 Apr 28 12:55:50 PM PDT 24 15013009259 ps
T280 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.1568748211 Apr 28 12:55:15 PM PDT 24 Apr 28 12:55:36 PM PDT 24 1162407481 ps
T281 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2720646846 Apr 28 12:54:43 PM PDT 24 Apr 28 12:54:49 PM PDT 24 1155623673 ps
T282 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2621670500 Apr 28 12:54:59 PM PDT 24 Apr 28 12:55:02 PM PDT 24 217129327 ps
T283 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.2128305877 Apr 28 12:55:06 PM PDT 24 Apr 28 12:55:09 PM PDT 24 49646230 ps
T284 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1497890078 Apr 28 12:54:41 PM PDT 24 Apr 28 12:54:43 PM PDT 24 209111830 ps
T285 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.995422001 Apr 28 12:55:14 PM PDT 24 Apr 28 12:55:17 PM PDT 24 133965757 ps
T286 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3457279153 Apr 28 12:55:05 PM PDT 24 Apr 28 12:55:07 PM PDT 24 111925844 ps
T287 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.1944114761 Apr 28 12:54:54 PM PDT 24 Apr 28 12:54:56 PM PDT 24 758934712 ps
T288 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.2189825935 Apr 28 12:54:43 PM PDT 24 Apr 28 12:54:45 PM PDT 24 32196866 ps
T289 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.756708751 Apr 28 12:55:00 PM PDT 24 Apr 28 12:55:02 PM PDT 24 90544540 ps
T290 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.1283638240 Apr 28 12:54:58 PM PDT 24 Apr 28 12:55:03 PM PDT 24 405466521 ps
T291 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.439168885 Apr 28 12:55:10 PM PDT 24 Apr 28 12:55:18 PM PDT 24 405462835 ps
T292 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1718140996 Apr 28 12:54:50 PM PDT 24 Apr 28 12:54:53 PM PDT 24 669636036 ps
T293 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.836623817 Apr 28 12:54:58 PM PDT 24 Apr 28 12:55:07 PM PDT 24 1473860854 ps
T294 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.3772952325 Apr 28 12:54:51 PM PDT 24 Apr 28 12:54:53 PM PDT 24 593763860 ps
T295 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3152529645 Apr 28 12:54:55 PM PDT 24 Apr 28 12:55:36 PM PDT 24 11604972613 ps
T296 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.615021164 Apr 28 12:54:46 PM PDT 24 Apr 28 12:55:10 PM PDT 24 18971248829 ps
T297 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.3750192485 Apr 28 12:55:05 PM PDT 24 Apr 28 12:55:08 PM PDT 24 1299175958 ps
T135 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2186863109 Apr 28 12:54:47 PM PDT 24 Apr 28 12:55:04 PM PDT 24 704358273 ps
T133 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.1835749871 Apr 28 12:55:16 PM PDT 24 Apr 28 12:55:33 PM PDT 24 600830344 ps
T298 /workspace/coverage/cover_reg_top/33.rv_dm_tap_fsm_rand_reset.4121107794 Apr 28 12:55:19 PM PDT 24 Apr 28 12:55:39 PM PDT 24 9734241182 ps
T299 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.1586256928 Apr 28 12:54:58 PM PDT 24 Apr 28 12:55:02 PM PDT 24 130398593 ps
T300 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.798085173 Apr 28 12:55:03 PM PDT 24 Apr 28 12:55:11 PM PDT 24 281579760 ps
T301 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2121549022 Apr 28 12:54:50 PM PDT 24 Apr 28 12:54:53 PM PDT 24 177948829 ps
T302 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1653043473 Apr 28 12:54:47 PM PDT 24 Apr 28 12:54:48 PM PDT 24 38755805 ps
T303 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1411642379 Apr 28 12:54:47 PM PDT 24 Apr 28 12:55:05 PM PDT 24 18974788386 ps
T304 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.877633635 Apr 28 12:54:52 PM PDT 24 Apr 28 12:54:56 PM PDT 24 2460819603 ps
T134 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.2891863163 Apr 28 12:54:39 PM PDT 24 Apr 28 12:55:05 PM PDT 24 3819246794 ps
T305 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.1337898394 Apr 28 12:54:50 PM PDT 24 Apr 28 12:55:08 PM PDT 24 7798519125 ps

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.1051600093
Short name T30
Test name
Test status
Simulation time 3484172513 ps
CPU time 5.67 seconds
Started Apr 28 04:26:05 PM PDT 24
Finished Apr 28 04:26:11 PM PDT 24
Peak memory 213756 kb
Host smart-19b9eaf8-bdcb-4a5f-8f00-ad448f153a77
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1051600093 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.1051600093
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.3789410558
Short name T7
Test name
Test status
Simulation time 765623435 ps
CPU time 3.38 seconds
Started Apr 28 04:25:44 PM PDT 24
Finished Apr 28 04:25:48 PM PDT 24
Peak memory 205408 kb
Host smart-c778d13f-43ec-4c33-a15f-5e5db14029fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789410558 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.3789410558
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.1849434339
Short name T5
Test name
Test status
Simulation time 138654491 ps
CPU time 0.75 seconds
Started Apr 28 04:26:29 PM PDT 24
Finished Apr 28 04:26:30 PM PDT 24
Peak memory 205128 kb
Host smart-7d95e2c7-dde4-4d18-859c-82141fbc53cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849434339 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.1849434339
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1220357809
Short name T46
Test name
Test status
Simulation time 1872011680 ps
CPU time 4.37 seconds
Started Apr 28 12:54:49 PM PDT 24
Finished Apr 28 12:54:54 PM PDT 24
Peak memory 218156 kb
Host smart-f8bc96bb-70a1-4aa4-a745-d94453df4ee1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220357809 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.1220357809
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/26.rv_dm_stress_all.2777379177
Short name T11
Test name
Test status
Simulation time 7401895297 ps
CPU time 10.84 seconds
Started Apr 28 04:27:07 PM PDT 24
Finished Apr 28 04:27:18 PM PDT 24
Peak memory 205540 kb
Host smart-7d0d53f1-2217-471b-ba1c-663030289a4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777379177 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.2777379177
Directory /workspace/26.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tap_fsm_rand_reset.1370525239
Short name T138
Test name
Test status
Simulation time 5014245435 ps
CPU time 18.85 seconds
Started Apr 28 12:55:05 PM PDT 24
Finished Apr 28 12:55:24 PM PDT 24
Peak memory 221416 kb
Host smart-53c497cd-2a16-476e-924d-b4340e80fa28
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370525239 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rv_dm_tap_fsm_rand_reset.1370525239
Directory /workspace/12.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/21.rv_dm_stress_all.1454110384
Short name T15
Test name
Test status
Simulation time 4860773013 ps
CPU time 5.72 seconds
Started Apr 28 04:27:04 PM PDT 24
Finished Apr 28 04:27:10 PM PDT 24
Peak memory 205540 kb
Host smart-58bb43d7-44a4-4a7c-8bfd-b82f829a3023
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454110384 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.1454110384
Directory /workspace/21.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.1242335710
Short name T98
Test name
Test status
Simulation time 1465132992 ps
CPU time 53.3 seconds
Started Apr 28 12:54:39 PM PDT 24
Finished Apr 28 12:55:34 PM PDT 24
Peak memory 204912 kb
Host smart-729cb081-0667-491f-833c-4616b08085d5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242335710 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.1242335710
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.132231166
Short name T34
Test name
Test status
Simulation time 1336202882 ps
CPU time 3.97 seconds
Started Apr 28 04:26:35 PM PDT 24
Finished Apr 28 04:26:40 PM PDT 24
Peak memory 205460 kb
Host smart-043a486c-5ea0-4703-afbd-a0a75e8c3841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132231166 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.132231166
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1627132869
Short name T45
Test name
Test status
Simulation time 723685407 ps
CPU time 9.58 seconds
Started Apr 28 12:54:57 PM PDT 24
Finished Apr 28 12:55:07 PM PDT 24
Peak memory 221160 kb
Host smart-63d23f51-56cc-4ae4-a0a7-ee043d789f7a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627132869 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.1627132869
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.3749557451
Short name T79
Test name
Test status
Simulation time 153869498 ps
CPU time 4.41 seconds
Started Apr 28 12:55:14 PM PDT 24
Finished Apr 28 12:55:20 PM PDT 24
Peak memory 213108 kb
Host smart-1d7f2f4e-3bbf-406a-9157-c73ef9315aec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749557451 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.3749557451
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.2957500470
Short name T26
Test name
Test status
Simulation time 3605151089 ps
CPU time 3.96 seconds
Started Apr 28 04:25:12 PM PDT 24
Finished Apr 28 04:25:16 PM PDT 24
Peak memory 205508 kb
Host smart-385d8155-493d-4ebb-9435-19d8ca401239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957500470 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.2957500470
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.1203393672
Short name T61
Test name
Test status
Simulation time 364280536 ps
CPU time 1.31 seconds
Started Apr 28 04:25:35 PM PDT 24
Finished Apr 28 04:25:36 PM PDT 24
Peak memory 229672 kb
Host smart-1cc0328c-f676-4530-a25e-c2ea154cbf40
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203393672 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.1203393672
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.514965244
Short name T25
Test name
Test status
Simulation time 1313666486 ps
CPU time 1.3 seconds
Started Apr 28 04:25:45 PM PDT 24
Finished Apr 28 04:25:47 PM PDT 24
Peak memory 205188 kb
Host smart-910fa9a2-893d-4eae-97df-833dc7f4892e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514965244 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.514965244
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.3421859849
Short name T125
Test name
Test status
Simulation time 1116912809 ps
CPU time 16.3 seconds
Started Apr 28 12:54:42 PM PDT 24
Finished Apr 28 12:54:59 PM PDT 24
Peak memory 213180 kb
Host smart-c68e2f47-6e15-4a8d-9e77-f078b4832a1b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421859849 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.3421859849
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.4011937887
Short name T29
Test name
Test status
Simulation time 59021842 ps
CPU time 0.79 seconds
Started Apr 28 04:25:30 PM PDT 24
Finished Apr 28 04:25:31 PM PDT 24
Peak memory 205164 kb
Host smart-b59a8670-2dd5-4f18-a0f5-3781ee65e17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011937887 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.4011937887
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.755080345
Short name T23
Test name
Test status
Simulation time 230184247 ps
CPU time 1.4 seconds
Started Apr 28 04:25:51 PM PDT 24
Finished Apr 28 04:25:53 PM PDT 24
Peak memory 205080 kb
Host smart-27b60325-78b0-45f0-9345-fea8bff6b382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755080345 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.755080345
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.1198734923
Short name T17
Test name
Test status
Simulation time 31941037 ps
CPU time 0.82 seconds
Started Apr 28 04:25:31 PM PDT 24
Finished Apr 28 04:25:32 PM PDT 24
Peak memory 213320 kb
Host smart-028d6061-babd-4ce0-8025-cc566ae100e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198734923 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.1198734923
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1053143485
Short name T100
Test name
Test status
Simulation time 11823079607 ps
CPU time 30.9 seconds
Started Apr 28 12:54:50 PM PDT 24
Finished Apr 28 12:55:22 PM PDT 24
Peak memory 204940 kb
Host smart-965e4b07-2f41-4e67-8212-9b7830abb432
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053143485 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.1053143485
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3978255629
Short name T68
Test name
Test status
Simulation time 2252726720 ps
CPU time 8.51 seconds
Started Apr 28 12:55:09 PM PDT 24
Finished Apr 28 12:55:18 PM PDT 24
Peak memory 220700 kb
Host smart-3de7bb21-9b43-439a-8eb1-a1afe2b13ddb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978255629 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.3
978255629
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.1968357885
Short name T19
Test name
Test status
Simulation time 33561074 ps
CPU time 0.81 seconds
Started Apr 28 04:26:32 PM PDT 24
Finished Apr 28 04:26:34 PM PDT 24
Peak memory 205168 kb
Host smart-a0668c7a-a019-4591-8efd-6986344e8046
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968357885 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.1968357885
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.935758542
Short name T82
Test name
Test status
Simulation time 1890388309 ps
CPU time 7.61 seconds
Started Apr 28 12:55:05 PM PDT 24
Finished Apr 28 12:55:13 PM PDT 24
Peak memory 205020 kb
Host smart-bc828b89-d946-4016-ac7f-f4c603d8c995
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935758542 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same_
csr_outstanding.935758542
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.2595904710
Short name T27
Test name
Test status
Simulation time 226512398 ps
CPU time 0.83 seconds
Started Apr 28 04:25:34 PM PDT 24
Finished Apr 28 04:25:35 PM PDT 24
Peak memory 205168 kb
Host smart-6bc2740c-5ad6-468a-8e17-85c039c7136d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595904710 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.2595904710
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.3072701159
Short name T129
Test name
Test status
Simulation time 1239031829 ps
CPU time 19.53 seconds
Started Apr 28 12:54:58 PM PDT 24
Finished Apr 28 12:55:18 PM PDT 24
Peak memory 213140 kb
Host smart-9e8503d8-ed40-49ec-998b-2471fb11fd4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072701159 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.3072701159
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.1349084261
Short name T194
Test name
Test status
Simulation time 105330003 ps
CPU time 0.78 seconds
Started Apr 28 12:54:46 PM PDT 24
Finished Apr 28 12:54:48 PM PDT 24
Peak memory 204560 kb
Host smart-56d1d34b-297b-4369-a500-4069edb0f50b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349084261 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.1349084261
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.511811443
Short name T127
Test name
Test status
Simulation time 1822775401 ps
CPU time 18.48 seconds
Started Apr 28 12:54:54 PM PDT 24
Finished Apr 28 12:55:13 PM PDT 24
Peak memory 221336 kb
Host smart-2a771ed6-0d8f-4bd8-9d67-0f37b5513dd6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511811443 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.511811443
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.1219580296
Short name T97
Test name
Test status
Simulation time 1486386181 ps
CPU time 2.45 seconds
Started Apr 28 12:54:39 PM PDT 24
Finished Apr 28 12:54:43 PM PDT 24
Peak memory 204852 kb
Host smart-4e134183-4629-468b-ad23-097d274ef03c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219580296 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.1219580296
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.3652021756
Short name T33
Test name
Test status
Simulation time 6034848962 ps
CPU time 6.09 seconds
Started Apr 28 04:25:56 PM PDT 24
Finished Apr 28 04:26:02 PM PDT 24
Peak memory 213796 kb
Host smart-fd42569e-cfcb-42fc-bc95-219a994dfca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652021756 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.3652021756
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.3935482305
Short name T52
Test name
Test status
Simulation time 41816132 ps
CPU time 0.76 seconds
Started Apr 28 04:27:04 PM PDT 24
Finished Apr 28 04:27:05 PM PDT 24
Peak memory 205164 kb
Host smart-5d8410e9-e6df-427a-83a0-9a01bb510e0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935482305 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.3935482305
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.1062597171
Short name T9
Test name
Test status
Simulation time 214652741 ps
CPU time 1.36 seconds
Started Apr 28 04:25:24 PM PDT 24
Finished Apr 28 04:25:26 PM PDT 24
Peak memory 205056 kb
Host smart-eebaa19f-76d5-490d-8873-174ce32f2ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062597171 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.1062597171
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3522698025
Short name T112
Test name
Test status
Simulation time 6717996843 ps
CPU time 71.99 seconds
Started Apr 28 12:54:37 PM PDT 24
Finished Apr 28 12:55:50 PM PDT 24
Peak memory 216848 kb
Host smart-e8020624-502d-40e0-adf0-86ba9317ef71
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522698025 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.3522698025
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.682465789
Short name T108
Test name
Test status
Simulation time 596311077 ps
CPU time 2.48 seconds
Started Apr 28 12:54:39 PM PDT 24
Finished Apr 28 12:54:43 PM PDT 24
Peak memory 221200 kb
Host smart-7ee828f0-2523-47fe-9ab2-d6a6320cf090
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682465789 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.682465789
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.2891863163
Short name T134
Test name
Test status
Simulation time 3819246794 ps
CPU time 24.71 seconds
Started Apr 28 12:54:39 PM PDT 24
Finished Apr 28 12:55:05 PM PDT 24
Peak memory 213152 kb
Host smart-ac5cddbb-5f95-4956-a2c2-9022248eec6c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891863163 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.2891863163
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1527368374
Short name T214
Test name
Test status
Simulation time 200961297 ps
CPU time 5.65 seconds
Started Apr 28 12:54:42 PM PDT 24
Finished Apr 28 12:54:49 PM PDT 24
Peak memory 213228 kb
Host smart-af0a8ad0-7092-480f-9ef5-8acdc538cd3a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527368374 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.1527368374
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.1197376007
Short name T86
Test name
Test status
Simulation time 201414327 ps
CPU time 1.58 seconds
Started Apr 28 12:54:37 PM PDT 24
Finished Apr 28 12:54:39 PM PDT 24
Peak memory 213060 kb
Host smart-3bf9d227-5e67-4e8d-9a91-b9fa17009780
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197376007 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.1197376007
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3170845905
Short name T205
Test name
Test status
Simulation time 73207493 ps
CPU time 1.84 seconds
Started Apr 28 12:54:38 PM PDT 24
Finished Apr 28 12:54:41 PM PDT 24
Peak memory 214292 kb
Host smart-b61aa021-ff8f-4d64-892e-3dae5c9d2c48
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170845905 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.3170845905
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.2665171807
Short name T223
Test name
Test status
Simulation time 4389235507 ps
CPU time 18.06 seconds
Started Apr 28 12:54:38 PM PDT 24
Finished Apr 28 12:54:57 PM PDT 24
Peak memory 204880 kb
Host smart-5d20caad-3393-4b4f-b72e-3daa15af38e4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665171807 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.2665171807
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.615021164
Short name T296
Test name
Test status
Simulation time 18971248829 ps
CPU time 22.96 seconds
Started Apr 28 12:54:46 PM PDT 24
Finished Apr 28 12:55:10 PM PDT 24
Peak memory 204868 kb
Host smart-f9c884f9-b7f6-4db4-9073-5c28c1c2d9ca
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615021164 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr
_bit_bash.615021164
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.1718442073
Short name T248
Test name
Test status
Simulation time 267845479 ps
CPU time 1.22 seconds
Started Apr 28 12:54:46 PM PDT 24
Finished Apr 28 12:54:48 PM PDT 24
Peak memory 204692 kb
Host smart-b0be587b-3a27-41b9-ae3c-53c195e430a5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718442073 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.1
718442073
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.1595860124
Short name T213
Test name
Test status
Simulation time 60523532 ps
CPU time 0.86 seconds
Started Apr 28 12:54:38 PM PDT 24
Finished Apr 28 12:54:40 PM PDT 24
Peak memory 204496 kb
Host smart-99e87964-4570-4d6a-ac23-72dcb5abe1c3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595860124 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.1595860124
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.13514206
Short name T250
Test name
Test status
Simulation time 635626091 ps
CPU time 1.37 seconds
Started Apr 28 12:54:38 PM PDT 24
Finished Apr 28 12:54:41 PM PDT 24
Peak memory 204684 kb
Host smart-947030cb-a8a8-4e60-8fb9-0139e2b02006
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13514206 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_
bit_bash.13514206
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3086312204
Short name T231
Test name
Test status
Simulation time 101613803 ps
CPU time 0.86 seconds
Started Apr 28 12:54:40 PM PDT 24
Finished Apr 28 12:54:42 PM PDT 24
Peak memory 204604 kb
Host smart-bad991de-adbf-4582-b210-904aa87a45ab
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086312204 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.3
086312204
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.2897583454
Short name T240
Test name
Test status
Simulation time 43480632 ps
CPU time 0.67 seconds
Started Apr 28 12:54:38 PM PDT 24
Finished Apr 28 12:54:41 PM PDT 24
Peak memory 204492 kb
Host smart-2fede6bd-915c-449c-a4c1-3d3e8ba93b7a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897583454 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.2897583454
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.1522507901
Short name T180
Test name
Test status
Simulation time 36421397 ps
CPU time 0.71 seconds
Started Apr 28 12:54:38 PM PDT 24
Finished Apr 28 12:54:40 PM PDT 24
Peak memory 204556 kb
Host smart-8b54a724-ca17-4f28-9895-f38f7a627650
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522507901 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.1522507901
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.771129557
Short name T101
Test name
Test status
Simulation time 884310580 ps
CPU time 6.54 seconds
Started Apr 28 12:54:39 PM PDT 24
Finished Apr 28 12:54:47 PM PDT 24
Peak memory 204844 kb
Host smart-3646334a-c55b-4ed3-a014-c331799b45ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771129557 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_c
sr_outstanding.771129557
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.2010687708
Short name T191
Test name
Test status
Simulation time 159304563 ps
CPU time 3.73 seconds
Started Apr 28 12:54:37 PM PDT 24
Finished Apr 28 12:54:42 PM PDT 24
Peak memory 213216 kb
Host smart-38865974-f83c-4a44-804a-3a7753379113
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010687708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.2010687708
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.1407332721
Short name T245
Test name
Test status
Simulation time 14829914678 ps
CPU time 62.51 seconds
Started Apr 28 12:54:43 PM PDT 24
Finished Apr 28 12:55:47 PM PDT 24
Peak memory 205240 kb
Host smart-4593be79-2f07-4df1-82d1-41e2f4925def
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407332721 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.1407332721
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2797163201
Short name T87
Test name
Test status
Simulation time 206856421 ps
CPU time 1.64 seconds
Started Apr 28 12:54:45 PM PDT 24
Finished Apr 28 12:54:47 PM PDT 24
Peak memory 213060 kb
Host smart-31ae1390-04ba-4a27-a8aa-e4aacf1b132b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797163201 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.2797163201
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2935645218
Short name T77
Test name
Test status
Simulation time 4454423291 ps
CPU time 9.65 seconds
Started Apr 28 12:54:43 PM PDT 24
Finished Apr 28 12:54:53 PM PDT 24
Peak memory 221376 kb
Host smart-a54094f5-93ac-4615-90d5-7cf311a5429a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935645218 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.2935645218
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2274346494
Short name T236
Test name
Test status
Simulation time 97993253 ps
CPU time 1.47 seconds
Started Apr 28 12:54:43 PM PDT 24
Finished Apr 28 12:54:46 PM PDT 24
Peak memory 213080 kb
Host smart-ad54176d-8976-435e-8cc4-f57cd2c7021d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274346494 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.2274346494
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.4285034205
Short name T264
Test name
Test status
Simulation time 39048482118 ps
CPU time 35.74 seconds
Started Apr 28 12:54:44 PM PDT 24
Finished Apr 28 12:55:21 PM PDT 24
Peak memory 204848 kb
Host smart-7f335075-8688-4829-9cfd-5e2435428640
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285034205 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.4285034205
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2051280903
Short name T241
Test name
Test status
Simulation time 8083741307 ps
CPU time 31.21 seconds
Started Apr 28 12:54:41 PM PDT 24
Finished Apr 28 12:55:14 PM PDT 24
Peak memory 204904 kb
Host smart-92a572a4-e570-4fe3-85bc-4977bf2f7718
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051280903 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_bit_bash.2051280903
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.86027723
Short name T94
Test name
Test status
Simulation time 722513228 ps
CPU time 3.35 seconds
Started Apr 28 12:54:42 PM PDT 24
Finished Apr 28 12:54:47 PM PDT 24
Peak memory 204852 kb
Host smart-0d8d7eeb-f9cb-45d6-b304-c8863f7982f4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86027723 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_
hw_reset.86027723
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.2473604127
Short name T270
Test name
Test status
Simulation time 825117279 ps
CPU time 3.46 seconds
Started Apr 28 12:54:43 PM PDT 24
Finished Apr 28 12:54:47 PM PDT 24
Peak memory 204804 kb
Host smart-54ac2d5c-d45a-4f67-b0cc-6518513848c3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473604127 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.2
473604127
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3867927375
Short name T246
Test name
Test status
Simulation time 35756249 ps
CPU time 0.74 seconds
Started Apr 28 12:54:51 PM PDT 24
Finished Apr 28 12:54:52 PM PDT 24
Peak memory 204520 kb
Host smart-5f37117f-fb73-469f-9980-7f8d90e1a986
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867927375 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.3867927375
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.579623665
Short name T176
Test name
Test status
Simulation time 853752236 ps
CPU time 3.1 seconds
Started Apr 28 12:54:42 PM PDT 24
Finished Apr 28 12:54:47 PM PDT 24
Peak memory 204724 kb
Host smart-c74fe838-c6f6-4e0b-a06e-513a0af18fcb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579623665 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_bit_bash.579623665
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.3468589607
Short name T276
Test name
Test status
Simulation time 129015773 ps
CPU time 0.82 seconds
Started Apr 28 12:54:42 PM PDT 24
Finished Apr 28 12:54:44 PM PDT 24
Peak memory 204552 kb
Host smart-b97986bf-d85c-48d3-914e-def8c8a572fb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468589607 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.3468589607
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.2495264181
Short name T262
Test name
Test status
Simulation time 32120132 ps
CPU time 0.74 seconds
Started Apr 28 12:54:42 PM PDT 24
Finished Apr 28 12:54:44 PM PDT 24
Peak memory 204440 kb
Host smart-4abfeb70-1bef-45e3-9286-c907f48ac98f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495264181 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.2
495264181
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2482191698
Short name T181
Test name
Test status
Simulation time 37159232 ps
CPU time 0.66 seconds
Started Apr 28 12:54:41 PM PDT 24
Finished Apr 28 12:54:43 PM PDT 24
Peak memory 204568 kb
Host smart-711ead16-0895-46c3-be00-5dedf52b526f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482191698 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.2482191698
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.336197237
Short name T177
Test name
Test status
Simulation time 18425451 ps
CPU time 0.73 seconds
Started Apr 28 12:54:45 PM PDT 24
Finished Apr 28 12:54:47 PM PDT 24
Peak memory 204624 kb
Host smart-9b78af42-bdfa-45e2-8984-d7ced3118365
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336197237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.336197237
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2720646846
Short name T281
Test name
Test status
Simulation time 1155623673 ps
CPU time 4.34 seconds
Started Apr 28 12:54:43 PM PDT 24
Finished Apr 28 12:54:49 PM PDT 24
Peak memory 204800 kb
Host smart-c34b3783-6178-4259-908f-99278331513d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720646846 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_
csr_outstanding.2720646846
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.838911090
Short name T255
Test name
Test status
Simulation time 3735609703 ps
CPU time 5.32 seconds
Started Apr 28 12:55:03 PM PDT 24
Finished Apr 28 12:55:09 PM PDT 24
Peak memory 213176 kb
Host smart-25b83490-f562-4ed2-be73-9e9e2478919f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838911090 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.838911090
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.3918716754
Short name T84
Test name
Test status
Simulation time 57942350 ps
CPU time 1.5 seconds
Started Apr 28 12:55:06 PM PDT 24
Finished Apr 28 12:55:08 PM PDT 24
Peak memory 213020 kb
Host smart-c6b77915-0a16-4f25-bd8e-55304206339a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918716754 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.3918716754
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.982042359
Short name T190
Test name
Test status
Simulation time 332724718 ps
CPU time 1.14 seconds
Started Apr 28 12:55:04 PM PDT 24
Finished Apr 28 12:55:06 PM PDT 24
Peak memory 204792 kb
Host smart-177ff228-a3bd-4a55-85b8-e57f7bc48e41
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982042359 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.982042359
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.2592007023
Short name T183
Test name
Test status
Simulation time 167486834 ps
CPU time 0.71 seconds
Started Apr 28 12:55:00 PM PDT 24
Finished Apr 28 12:55:01 PM PDT 24
Peak memory 204576 kb
Host smart-a0e6c224-b733-4616-99a6-9675dbd8363b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592007023 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
2592007023
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.982514205
Short name T123
Test name
Test status
Simulation time 209491130 ps
CPU time 4.59 seconds
Started Apr 28 12:55:03 PM PDT 24
Finished Apr 28 12:55:09 PM PDT 24
Peak memory 213112 kb
Host smart-11804624-0ece-4689-b071-07a3fef3697c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982514205 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.982514205
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1769758618
Short name T93
Test name
Test status
Simulation time 528179727 ps
CPU time 8.91 seconds
Started Apr 28 12:55:05 PM PDT 24
Finished Apr 28 12:55:15 PM PDT 24
Peak memory 221272 kb
Host smart-65e286f6-f218-436e-bd90-4ac98b254d3c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769758618 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.1
769758618
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.715648441
Short name T258
Test name
Test status
Simulation time 5555591939 ps
CPU time 11.79 seconds
Started Apr 28 12:55:03 PM PDT 24
Finished Apr 28 12:55:15 PM PDT 24
Peak memory 221448 kb
Host smart-43619317-8657-4a26-badc-5f2d698b9bdc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715648441 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.715648441
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.4136629744
Short name T201
Test name
Test status
Simulation time 52479281 ps
CPU time 1.45 seconds
Started Apr 28 12:55:04 PM PDT 24
Finished Apr 28 12:55:06 PM PDT 24
Peak memory 218148 kb
Host smart-3a6c0723-b9f3-414e-a295-a226b03433ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136629744 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.4136629744
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3447907823
Short name T219
Test name
Test status
Simulation time 1115302645 ps
CPU time 3.09 seconds
Started Apr 28 12:55:04 PM PDT 24
Finished Apr 28 12:55:07 PM PDT 24
Peak memory 204764 kb
Host smart-f7584bd0-550d-4d59-8b14-f88c9f298628
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447907823 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
3447907823
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.680608269
Short name T71
Test name
Test status
Simulation time 64177350 ps
CPU time 0.71 seconds
Started Apr 28 12:55:05 PM PDT 24
Finished Apr 28 12:55:06 PM PDT 24
Peak memory 204536 kb
Host smart-1fb30821-7ace-47a8-8e2e-06ce2311e33a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680608269 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.680608269
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.343054846
Short name T115
Test name
Test status
Simulation time 804300129 ps
CPU time 4.1 seconds
Started Apr 28 12:55:04 PM PDT 24
Finished Apr 28 12:55:09 PM PDT 24
Peak memory 204848 kb
Host smart-c7d81360-85fa-4018-925f-5f4039e6c193
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343054846 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same_
csr_outstanding.343054846
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tap_fsm_rand_reset.2158588664
Short name T208
Test name
Test status
Simulation time 19636140808 ps
CPU time 31.48 seconds
Started Apr 28 12:55:04 PM PDT 24
Finished Apr 28 12:55:36 PM PDT 24
Peak memory 221284 kb
Host smart-34e1c1e2-5ed2-4fc0-aa22-2d954160c64a
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158588664 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rv_dm_tap_fsm_rand_reset.2158588664
Directory /workspace/11.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.977219396
Short name T199
Test name
Test status
Simulation time 307054307 ps
CPU time 3.21 seconds
Started Apr 28 12:55:05 PM PDT 24
Finished Apr 28 12:55:08 PM PDT 24
Peak memory 213212 kb
Host smart-9aecc163-31e2-42d5-a21c-3257a9464f5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977219396 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.977219396
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.798085173
Short name T300
Test name
Test status
Simulation time 281579760 ps
CPU time 8.14 seconds
Started Apr 28 12:55:03 PM PDT 24
Finished Apr 28 12:55:11 PM PDT 24
Peak memory 213144 kb
Host smart-e9cae136-0f6c-45ba-a5e6-8224d82007cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798085173 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.798085173
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.2099416401
Short name T200
Test name
Test status
Simulation time 59970763 ps
CPU time 2.76 seconds
Started Apr 28 12:55:04 PM PDT 24
Finished Apr 28 12:55:07 PM PDT 24
Peak memory 218232 kb
Host smart-4e36d97f-1d7c-4da8-8bbe-21db4ee218f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099416401 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.2099416401
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.3750192485
Short name T297
Test name
Test status
Simulation time 1299175958 ps
CPU time 2.43 seconds
Started Apr 28 12:55:05 PM PDT 24
Finished Apr 28 12:55:08 PM PDT 24
Peak memory 219020 kb
Host smart-d1f24bcb-ebf3-4b16-91e3-3d19f549ccd6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750192485 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.3750192485
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.4202877314
Short name T227
Test name
Test status
Simulation time 925866575 ps
CPU time 3.35 seconds
Started Apr 28 12:55:03 PM PDT 24
Finished Apr 28 12:55:07 PM PDT 24
Peak memory 204820 kb
Host smart-5cf28249-ddcb-4a37-bf6f-eadf2cb2777f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202877314 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
4202877314
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3457279153
Short name T286
Test name
Test status
Simulation time 111925844 ps
CPU time 0.75 seconds
Started Apr 28 12:55:05 PM PDT 24
Finished Apr 28 12:55:07 PM PDT 24
Peak memory 204552 kb
Host smart-9bb02f4b-96dc-4a6d-85f4-a72e16bb1332
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457279153 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
3457279153
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1546388060
Short name T117
Test name
Test status
Simulation time 222946771 ps
CPU time 4.16 seconds
Started Apr 28 12:55:02 PM PDT 24
Finished Apr 28 12:55:07 PM PDT 24
Peak memory 204784 kb
Host smart-8099fba9-116b-46e2-8b4e-65b94e2b3f91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546388060 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.1546388060
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.2128305877
Short name T283
Test name
Test status
Simulation time 49646230 ps
CPU time 2.71 seconds
Started Apr 28 12:55:06 PM PDT 24
Finished Apr 28 12:55:09 PM PDT 24
Peak memory 213076 kb
Host smart-4e7d5d1e-e564-4f2c-bcb7-0e28e77d7717
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128305877 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.2128305877
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2966972066
Short name T130
Test name
Test status
Simulation time 3417017440 ps
CPU time 18.38 seconds
Started Apr 28 12:55:07 PM PDT 24
Finished Apr 28 12:55:26 PM PDT 24
Peak memory 213156 kb
Host smart-58bbf7bf-0624-4e40-827c-78db025973ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966972066 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.2
966972066
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.921175584
Short name T267
Test name
Test status
Simulation time 604638139 ps
CPU time 3.7 seconds
Started Apr 28 12:55:08 PM PDT 24
Finished Apr 28 12:55:13 PM PDT 24
Peak memory 217076 kb
Host smart-3108e2c9-455f-4733-ab50-d94ac423758c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921175584 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.921175584
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.1430657957
Short name T102
Test name
Test status
Simulation time 224453009 ps
CPU time 2.39 seconds
Started Apr 28 12:55:07 PM PDT 24
Finished Apr 28 12:55:10 PM PDT 24
Peak memory 213060 kb
Host smart-3a53835d-60c3-424e-adc9-eb67439194db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430657957 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.1430657957
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.4175416897
Short name T228
Test name
Test status
Simulation time 540765160 ps
CPU time 1.7 seconds
Started Apr 28 12:55:10 PM PDT 24
Finished Apr 28 12:55:12 PM PDT 24
Peak memory 204660 kb
Host smart-3cf652a0-1e3c-4118-aa9f-5ec7aa0fff31
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175416897 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
4175416897
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3117915274
Short name T271
Test name
Test status
Simulation time 77571917 ps
CPU time 0.71 seconds
Started Apr 28 12:55:07 PM PDT 24
Finished Apr 28 12:55:08 PM PDT 24
Peak memory 204576 kb
Host smart-25d71e4a-2952-4f9b-9e2b-8d4ec060e38c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117915274 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
3117915274
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.439168885
Short name T291
Test name
Test status
Simulation time 405462835 ps
CPU time 7.34 seconds
Started Apr 28 12:55:10 PM PDT 24
Finished Apr 28 12:55:18 PM PDT 24
Peak memory 204864 kb
Host smart-1fd76068-bd3b-43ee-8d6a-fd5792e7ba42
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439168885 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same_
csr_outstanding.439168885
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tap_fsm_rand_reset.3375331168
Short name T243
Test name
Test status
Simulation time 12547735213 ps
CPU time 23.43 seconds
Started Apr 28 12:55:08 PM PDT 24
Finished Apr 28 12:55:32 PM PDT 24
Peak memory 215332 kb
Host smart-7a9827e6-a7de-4613-b9ac-13d14ef34b21
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375331168 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rv_dm_tap_fsm_rand_reset.3375331168
Directory /workspace/13.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.3218315834
Short name T275
Test name
Test status
Simulation time 214717973 ps
CPU time 4.12 seconds
Started Apr 28 12:55:09 PM PDT 24
Finished Apr 28 12:55:14 PM PDT 24
Peak memory 213220 kb
Host smart-8d9bc68c-fcdb-4418-b48c-3ee933c24e1a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218315834 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.3218315834
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3607286078
Short name T131
Test name
Test status
Simulation time 788132195 ps
CPU time 15.64 seconds
Started Apr 28 12:55:12 PM PDT 24
Finished Apr 28 12:55:29 PM PDT 24
Peak memory 221260 kb
Host smart-6a72a7c7-f4d5-40e8-936c-1e48df6e7e04
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607286078 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.3
607286078
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.2590737548
Short name T232
Test name
Test status
Simulation time 172764745 ps
CPU time 2.51 seconds
Started Apr 28 12:55:13 PM PDT 24
Finished Apr 28 12:55:17 PM PDT 24
Peak memory 218872 kb
Host smart-64c70b6d-1b19-4423-b261-4d3a504f757b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590737548 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.2590737548
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.572489849
Short name T111
Test name
Test status
Simulation time 108559700 ps
CPU time 2.52 seconds
Started Apr 28 12:55:09 PM PDT 24
Finished Apr 28 12:55:12 PM PDT 24
Peak memory 213076 kb
Host smart-0e2fa348-98a6-4758-afe2-d2d825ab8c99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572489849 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.572489849
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.578140595
Short name T224
Test name
Test status
Simulation time 538120969 ps
CPU time 2.66 seconds
Started Apr 28 12:55:08 PM PDT 24
Finished Apr 28 12:55:12 PM PDT 24
Peak memory 204716 kb
Host smart-f88803ca-1563-405a-8613-ba5d0a9243b6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578140595 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.578140595
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2115037741
Short name T268
Test name
Test status
Simulation time 66184161 ps
CPU time 0.7 seconds
Started Apr 28 12:55:07 PM PDT 24
Finished Apr 28 12:55:09 PM PDT 24
Peak memory 204488 kb
Host smart-e58db632-1bfd-4bc8-a57f-7c61959b77c8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115037741 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
2115037741
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2692107834
Short name T103
Test name
Test status
Simulation time 325179520 ps
CPU time 3.48 seconds
Started Apr 28 12:55:08 PM PDT 24
Finished Apr 28 12:55:12 PM PDT 24
Peak memory 204920 kb
Host smart-fff1f825-5947-45ae-966d-50e1793c58e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692107834 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.2692107834
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.2066631026
Short name T78
Test name
Test status
Simulation time 124040865 ps
CPU time 3.29 seconds
Started Apr 28 12:55:07 PM PDT 24
Finished Apr 28 12:55:11 PM PDT 24
Peak memory 213172 kb
Host smart-38eca239-85c8-4f3f-b5c0-6930d47be8ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066631026 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.2066631026
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.4105835715
Short name T203
Test name
Test status
Simulation time 4309151929 ps
CPU time 8.82 seconds
Started Apr 28 12:55:10 PM PDT 24
Finished Apr 28 12:55:19 PM PDT 24
Peak memory 215452 kb
Host smart-bc04da8b-20e1-4ef4-b5a5-81424de6aa2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105835715 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.4105835715
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.1040866440
Short name T110
Test name
Test status
Simulation time 220275949 ps
CPU time 1.6 seconds
Started Apr 28 12:55:13 PM PDT 24
Finished Apr 28 12:55:16 PM PDT 24
Peak memory 218284 kb
Host smart-b23fb2b5-e66e-4eab-8592-286deac39a98
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040866440 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.1040866440
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.1670139079
Short name T192
Test name
Test status
Simulation time 1083255041 ps
CPU time 1.89 seconds
Started Apr 28 12:55:10 PM PDT 24
Finished Apr 28 12:55:13 PM PDT 24
Peak memory 204780 kb
Host smart-2dbd9c01-15bf-4869-b029-7feb7c1bcd0c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670139079 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
1670139079
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3847354815
Short name T226
Test name
Test status
Simulation time 59826572 ps
CPU time 0.72 seconds
Started Apr 28 12:55:09 PM PDT 24
Finished Apr 28 12:55:11 PM PDT 24
Peak memory 204492 kb
Host smart-42fce041-d1aa-45af-9e38-f7008b805936
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847354815 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
3847354815
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.624408081
Short name T249
Test name
Test status
Simulation time 1374919749 ps
CPU time 7.64 seconds
Started Apr 28 12:55:12 PM PDT 24
Finished Apr 28 12:55:21 PM PDT 24
Peak memory 204964 kb
Host smart-3715eac4-074e-4092-be30-3ff4962fcd2a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624408081 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same_
csr_outstanding.624408081
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.1301215877
Short name T211
Test name
Test status
Simulation time 67003341 ps
CPU time 3.86 seconds
Started Apr 28 12:55:07 PM PDT 24
Finished Apr 28 12:55:12 PM PDT 24
Peak memory 213172 kb
Host smart-ab0c0f0c-f035-4681-9b70-7e5abbb2ba8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301215877 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.1301215877
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2789666548
Short name T260
Test name
Test status
Simulation time 1621056032 ps
CPU time 15.5 seconds
Started Apr 28 12:55:10 PM PDT 24
Finished Apr 28 12:55:26 PM PDT 24
Peak memory 221196 kb
Host smart-a8bcfcc5-3643-4b93-9427-43a50ef1ddce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789666548 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.2
789666548
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2566264216
Short name T272
Test name
Test status
Simulation time 4409933859 ps
CPU time 4.56 seconds
Started Apr 28 12:55:12 PM PDT 24
Finished Apr 28 12:55:18 PM PDT 24
Peak memory 216956 kb
Host smart-f2f1ac73-e903-4c82-b937-01ccde54de55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566264216 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.2566264216
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.523852185
Short name T204
Test name
Test status
Simulation time 86564663 ps
CPU time 2.32 seconds
Started Apr 28 12:55:14 PM PDT 24
Finished Apr 28 12:55:17 PM PDT 24
Peak memory 213228 kb
Host smart-33b2e9ab-93e5-4618-9762-43c71df6d670
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523852185 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.523852185
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.180361566
Short name T182
Test name
Test status
Simulation time 1525447296 ps
CPU time 2.84 seconds
Started Apr 28 12:55:15 PM PDT 24
Finished Apr 28 12:55:18 PM PDT 24
Peak memory 204720 kb
Host smart-53c510b9-13d3-4f2d-b81e-277df20ace62
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180361566 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.180361566
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3947799598
Short name T221
Test name
Test status
Simulation time 59295264 ps
CPU time 0.79 seconds
Started Apr 28 12:55:14 PM PDT 24
Finished Apr 28 12:55:15 PM PDT 24
Peak memory 204592 kb
Host smart-363ea730-0b4a-4930-8eef-d79709ab30ae
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947799598 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
3947799598
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.728431720
Short name T50
Test name
Test status
Simulation time 3386268052 ps
CPU time 4.18 seconds
Started Apr 28 12:55:14 PM PDT 24
Finished Apr 28 12:55:19 PM PDT 24
Peak memory 204888 kb
Host smart-75d8d7c8-ed2e-4a10-83bb-1afe79c9d3e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728431720 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same_
csr_outstanding.728431720
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3421147155
Short name T273
Test name
Test status
Simulation time 250289461 ps
CPU time 5.47 seconds
Started Apr 28 12:55:17 PM PDT 24
Finished Apr 28 12:55:23 PM PDT 24
Peak memory 213240 kb
Host smart-302f3f9a-638b-4b76-b1ac-10289ca32458
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421147155 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.3421147155
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.2445287400
Short name T80
Test name
Test status
Simulation time 887603622 ps
CPU time 19.8 seconds
Started Apr 28 12:55:15 PM PDT 24
Finished Apr 28 12:55:36 PM PDT 24
Peak memory 221256 kb
Host smart-96e53626-ae27-4cc4-80f3-f23405ca8d90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445287400 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.2
445287400
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.109350406
Short name T122
Test name
Test status
Simulation time 115656697 ps
CPU time 2.33 seconds
Started Apr 28 12:55:15 PM PDT 24
Finished Apr 28 12:55:18 PM PDT 24
Peak memory 221296 kb
Host smart-99a30c2b-8152-4749-b11b-78eae2344007
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109350406 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.109350406
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.995422001
Short name T285
Test name
Test status
Simulation time 133965757 ps
CPU time 2.15 seconds
Started Apr 28 12:55:14 PM PDT 24
Finished Apr 28 12:55:17 PM PDT 24
Peak memory 213040 kb
Host smart-db251f23-ea17-46d9-9f7c-d4a2c5a9ec2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995422001 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.995422001
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.1298540589
Short name T184
Test name
Test status
Simulation time 406744234 ps
CPU time 2.49 seconds
Started Apr 28 12:55:15 PM PDT 24
Finished Apr 28 12:55:18 PM PDT 24
Peak memory 204856 kb
Host smart-1cc38da9-c8c9-45cf-8705-046fb0ecd023
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298540589 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
1298540589
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.4078589809
Short name T277
Test name
Test status
Simulation time 58821910 ps
CPU time 0.71 seconds
Started Apr 28 12:55:17 PM PDT 24
Finished Apr 28 12:55:18 PM PDT 24
Peak memory 204536 kb
Host smart-bbc51056-44aa-41b5-8865-bd39f0243ffc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078589809 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
4078589809
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.436122732
Short name T118
Test name
Test status
Simulation time 1653078311 ps
CPU time 7.67 seconds
Started Apr 28 12:55:13 PM PDT 24
Finished Apr 28 12:55:22 PM PDT 24
Peak memory 204804 kb
Host smart-63fb57d3-a507-4f0e-98dc-87662dd9d5f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436122732 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same_
csr_outstanding.436122732
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.519258301
Short name T126
Test name
Test status
Simulation time 1104618353 ps
CPU time 16.33 seconds
Started Apr 28 12:55:13 PM PDT 24
Finished Apr 28 12:55:30 PM PDT 24
Peak memory 213092 kb
Host smart-bbac0934-77f4-4ff7-9cfc-14f41ef3a32c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519258301 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.519258301
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2507288475
Short name T188
Test name
Test status
Simulation time 2786534202 ps
CPU time 4.63 seconds
Started Apr 28 12:55:14 PM PDT 24
Finished Apr 28 12:55:19 PM PDT 24
Peak memory 218540 kb
Host smart-7da314db-6132-4780-b60f-b3a7a4c8a11f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507288475 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.2507288475
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.3208141766
Short name T109
Test name
Test status
Simulation time 243043417 ps
CPU time 1.41 seconds
Started Apr 28 12:55:13 PM PDT 24
Finished Apr 28 12:55:15 PM PDT 24
Peak memory 218080 kb
Host smart-40ac1d6b-bd34-4a8b-aaa9-b84df5e25fb4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208141766 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.3208141766
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1145718865
Short name T174
Test name
Test status
Simulation time 668361402 ps
CPU time 2.31 seconds
Started Apr 28 12:55:21 PM PDT 24
Finished Apr 28 12:55:23 PM PDT 24
Peak memory 204864 kb
Host smart-464d50cb-6b45-49ec-92e1-4e059973d71f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145718865 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
1145718865
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.3573268347
Short name T235
Test name
Test status
Simulation time 154555198 ps
CPU time 0.78 seconds
Started Apr 28 12:55:14 PM PDT 24
Finished Apr 28 12:55:16 PM PDT 24
Peak memory 204512 kb
Host smart-2dde2576-f86c-424d-a7fb-d9f337c6c114
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573268347 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
3573268347
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.584157342
Short name T83
Test name
Test status
Simulation time 1059417079 ps
CPU time 4.36 seconds
Started Apr 28 12:55:18 PM PDT 24
Finished Apr 28 12:55:23 PM PDT 24
Peak memory 204988 kb
Host smart-5130ecd0-9358-43b0-81ef-74d17cd6a557
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584157342 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same_
csr_outstanding.584157342
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tap_fsm_rand_reset.3805050507
Short name T66
Test name
Test status
Simulation time 9373237505 ps
CPU time 17.36 seconds
Started Apr 28 12:55:17 PM PDT 24
Finished Apr 28 12:55:35 PM PDT 24
Peak memory 214500 kb
Host smart-5a2c4459-3efd-4f51-840a-b34c7443bb0f
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805050507 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rv_dm_tap_fsm_rand_reset.3805050507
Directory /workspace/18.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.205050313
Short name T257
Test name
Test status
Simulation time 277275908 ps
CPU time 4.54 seconds
Started Apr 28 12:55:16 PM PDT 24
Finished Apr 28 12:55:21 PM PDT 24
Peak memory 213192 kb
Host smart-c31cd489-2f87-4e85-9f43-84b4cea7e7aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205050313 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.205050313
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.1568748211
Short name T280
Test name
Test status
Simulation time 1162407481 ps
CPU time 20.09 seconds
Started Apr 28 12:55:15 PM PDT 24
Finished Apr 28 12:55:36 PM PDT 24
Peak memory 221224 kb
Host smart-3abd01c4-f440-4bd9-a535-2b72a9f81944
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568748211 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.1
568748211
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1950033857
Short name T75
Test name
Test status
Simulation time 246829793 ps
CPU time 3.61 seconds
Started Apr 28 12:55:19 PM PDT 24
Finished Apr 28 12:55:23 PM PDT 24
Peak memory 218124 kb
Host smart-f4ffd2c6-e1d2-49b3-bd9f-75d46e9944c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950033857 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.1950033857
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.1195845647
Short name T254
Test name
Test status
Simulation time 117423729 ps
CPU time 2.34 seconds
Started Apr 28 12:55:13 PM PDT 24
Finished Apr 28 12:55:16 PM PDT 24
Peak memory 221184 kb
Host smart-7434e2bb-ddf8-457e-99f4-4449c3731254
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195845647 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.1195845647
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.978716427
Short name T212
Test name
Test status
Simulation time 190382582 ps
CPU time 0.95 seconds
Started Apr 28 12:55:13 PM PDT 24
Finished Apr 28 12:55:14 PM PDT 24
Peak memory 204744 kb
Host smart-785b0db2-2d2f-43c5-a5aa-7925113f67b7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978716427 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.978716427
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.478437679
Short name T225
Test name
Test status
Simulation time 28724612 ps
CPU time 0.73 seconds
Started Apr 28 12:55:16 PM PDT 24
Finished Apr 28 12:55:17 PM PDT 24
Peak memory 204600 kb
Host smart-22a0809b-38a5-43fe-8739-fb953b60a369
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478437679 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.478437679
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.4022964066
Short name T105
Test name
Test status
Simulation time 600307710 ps
CPU time 4.4 seconds
Started Apr 28 12:55:14 PM PDT 24
Finished Apr 28 12:55:20 PM PDT 24
Peak memory 204860 kb
Host smart-2aa09ec8-3a35-4e13-b4ad-5e628764e632
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022964066 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.4022964066
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.235537829
Short name T279
Test name
Test status
Simulation time 2360094411 ps
CPU time 5.93 seconds
Started Apr 28 12:55:17 PM PDT 24
Finished Apr 28 12:55:24 PM PDT 24
Peak memory 213248 kb
Host smart-96acaf51-7ea1-47ce-83f7-9a98988e3724
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235537829 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.235537829
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.1835749871
Short name T133
Test name
Test status
Simulation time 600830344 ps
CPU time 16.43 seconds
Started Apr 28 12:55:16 PM PDT 24
Finished Apr 28 12:55:33 PM PDT 24
Peak memory 213120 kb
Host smart-174030f6-ba8b-4b90-ba81-f5864b31fe28
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835749871 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.1
835749871
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.895107879
Short name T69
Test name
Test status
Simulation time 15013009259 ps
CPU time 66.65 seconds
Started Apr 28 12:54:42 PM PDT 24
Finished Apr 28 12:55:50 PM PDT 24
Peak memory 213300 kb
Host smart-7ae6d638-3a33-4cef-880f-668768dd512f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895107879 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.rv_dm_csr_aliasing.895107879
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2041252156
Short name T217
Test name
Test status
Simulation time 19593291732 ps
CPU time 65.1 seconds
Started Apr 28 12:54:49 PM PDT 24
Finished Apr 28 12:55:54 PM PDT 24
Peak memory 205060 kb
Host smart-d1faaeb7-4dc1-4728-92a6-9dfad94ff0af
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041252156 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.2041252156
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.4276335662
Short name T206
Test name
Test status
Simulation time 272358925 ps
CPU time 2.49 seconds
Started Apr 28 12:54:49 PM PDT 24
Finished Apr 28 12:54:53 PM PDT 24
Peak memory 213160 kb
Host smart-c200a0e7-bc5a-4d93-a650-1298476164a5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276335662 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.4276335662
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.1120628998
Short name T193
Test name
Test status
Simulation time 69150237 ps
CPU time 2.42 seconds
Started Apr 28 12:54:49 PM PDT 24
Finished Apr 28 12:54:52 PM PDT 24
Peak memory 218172 kb
Host smart-a7241b83-923c-4f89-a3f2-33f1039f3fd0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120628998 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.1120628998
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.2866431528
Short name T119
Test name
Test status
Simulation time 150558998 ps
CPU time 2.15 seconds
Started Apr 28 12:54:48 PM PDT 24
Finished Apr 28 12:54:51 PM PDT 24
Peak memory 221304 kb
Host smart-4398ffe5-db90-471b-bbe9-b459125a9011
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866431528 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.2866431528
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.1337898394
Short name T305
Test name
Test status
Simulation time 7798519125 ps
CPU time 16.46 seconds
Started Apr 28 12:54:50 PM PDT 24
Finished Apr 28 12:55:08 PM PDT 24
Peak memory 204872 kb
Host smart-5699ed66-5834-458a-af38-dc64461a8f57
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337898394 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.1337898394
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.784584509
Short name T179
Test name
Test status
Simulation time 27595458572 ps
CPU time 14.83 seconds
Started Apr 28 12:54:51 PM PDT 24
Finished Apr 28 12:55:07 PM PDT 24
Peak memory 204836 kb
Host smart-b26efc3f-75bc-45df-829f-7071b019d4fa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784584509 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr
_bit_bash.784584509
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2447778100
Short name T95
Test name
Test status
Simulation time 579185292 ps
CPU time 1.83 seconds
Started Apr 28 12:54:44 PM PDT 24
Finished Apr 28 12:54:47 PM PDT 24
Peak memory 204852 kb
Host smart-acce051d-2c4e-4d99-bc77-eb7e7c375382
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447778100 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.2447778100
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.3772952325
Short name T294
Test name
Test status
Simulation time 593763860 ps
CPU time 0.98 seconds
Started Apr 28 12:54:51 PM PDT 24
Finished Apr 28 12:54:53 PM PDT 24
Peak memory 204704 kb
Host smart-8d33a124-416c-4ae3-9d6f-aac3655fac22
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772952325 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.3
772952325
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3266213986
Short name T234
Test name
Test status
Simulation time 216124587 ps
CPU time 1.26 seconds
Started Apr 28 12:54:44 PM PDT 24
Finished Apr 28 12:54:46 PM PDT 24
Peak memory 204600 kb
Host smart-fd3d5d68-1471-46ba-ba08-7abf4b376982
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266213986 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_aliasing.3266213986
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1456506146
Short name T251
Test name
Test status
Simulation time 700524424 ps
CPU time 1.3 seconds
Started Apr 28 12:54:45 PM PDT 24
Finished Apr 28 12:54:47 PM PDT 24
Peak memory 204808 kb
Host smart-8c19d9ed-c2fb-4aa7-8f25-d40e66747200
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456506146 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.1456506146
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1497890078
Short name T284
Test name
Test status
Simulation time 209111830 ps
CPU time 0.88 seconds
Started Apr 28 12:54:41 PM PDT 24
Finished Apr 28 12:54:43 PM PDT 24
Peak memory 204632 kb
Host smart-543f66d2-d72e-4f16-8bcd-aa59c6bd9455
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497890078 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.1497890078
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2107822629
Short name T185
Test name
Test status
Simulation time 40822322 ps
CPU time 0.75 seconds
Started Apr 28 12:54:45 PM PDT 24
Finished Apr 28 12:54:46 PM PDT 24
Peak memory 204528 kb
Host smart-69658fe4-9224-4140-8b6b-98bb8ed880f2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107822629 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.2
107822629
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1653043473
Short name T302
Test name
Test status
Simulation time 38755805 ps
CPU time 0.71 seconds
Started Apr 28 12:54:47 PM PDT 24
Finished Apr 28 12:54:48 PM PDT 24
Peak memory 204512 kb
Host smart-8d83863d-2577-4c7e-b707-de6d0f4ca510
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653043473 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.1653043473
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.2189825935
Short name T288
Test name
Test status
Simulation time 32196866 ps
CPU time 0.77 seconds
Started Apr 28 12:54:43 PM PDT 24
Finished Apr 28 12:54:45 PM PDT 24
Peak memory 204512 kb
Host smart-a857123a-c038-4bbb-be83-bf134933080d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189825935 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.2189825935
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3517677172
Short name T116
Test name
Test status
Simulation time 461076432 ps
CPU time 6.54 seconds
Started Apr 28 12:54:51 PM PDT 24
Finished Apr 28 12:54:58 PM PDT 24
Peak memory 204840 kb
Host smart-c5edd746-b903-4c49-9397-854d2a6d1a7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517677172 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.3517677172
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.3297688023
Short name T187
Test name
Test status
Simulation time 53755854 ps
CPU time 3.3 seconds
Started Apr 28 12:54:44 PM PDT 24
Finished Apr 28 12:54:48 PM PDT 24
Peak memory 213216 kb
Host smart-5d0cfbdc-8237-4d05-87d3-d548d8057416
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297688023 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.3297688023
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.2247620643
Short name T47
Test name
Test status
Simulation time 859148969 ps
CPU time 16.43 seconds
Started Apr 28 12:54:45 PM PDT 24
Finished Apr 28 12:55:02 PM PDT 24
Peak memory 221140 kb
Host smart-b1f24963-3141-4c83-928a-c55a55c882e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247620643 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.2247620643
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_dm_tap_fsm_rand_reset.3606166104
Short name T124
Test name
Test status
Simulation time 12735440524 ps
CPU time 47.29 seconds
Started Apr 28 12:55:22 PM PDT 24
Finished Apr 28 12:56:10 PM PDT 24
Peak memory 221292 kb
Host smart-402134c0-1998-4442-ac92-a6057efec610
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606166104 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 20.rv_dm_tap_fsm_rand_reset.3606166104
Directory /workspace/20.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/27.rv_dm_tap_fsm_rand_reset.2400709776
Short name T209
Test name
Test status
Simulation time 13105683440 ps
CPU time 45.45 seconds
Started Apr 28 12:55:18 PM PDT 24
Finished Apr 28 12:56:04 PM PDT 24
Peak memory 216472 kb
Host smart-36ddf858-a0ba-478b-ac13-1ccfa0f725b9
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400709776 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 27.rv_dm_tap_fsm_rand_reset.2400709776
Directory /workspace/27.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/28.rv_dm_tap_fsm_rand_reset.2813921799
Short name T233
Test name
Test status
Simulation time 15403707959 ps
CPU time 48.13 seconds
Started Apr 28 12:55:18 PM PDT 24
Finished Apr 28 12:56:07 PM PDT 24
Peak memory 221392 kb
Host smart-2a154426-5bad-4e7b-a1e4-5870bf3d79e1
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813921799 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 28.rv_dm_tap_fsm_rand_reset.2813921799
Directory /workspace/28.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2012661632
Short name T106
Test name
Test status
Simulation time 6204146800 ps
CPU time 31.2 seconds
Started Apr 28 12:54:48 PM PDT 24
Finished Apr 28 12:55:20 PM PDT 24
Peak memory 205060 kb
Host smart-2b3710bd-d573-4968-bbe3-81546590f53b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012661632 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.2012661632
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.3811614084
Short name T259
Test name
Test status
Simulation time 2572585671 ps
CPU time 33.35 seconds
Started Apr 28 12:54:51 PM PDT 24
Finished Apr 28 12:55:25 PM PDT 24
Peak memory 204932 kb
Host smart-e7af5940-3eb9-406f-b24e-aa624663c685
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811614084 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.3811614084
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.533100537
Short name T197
Test name
Test status
Simulation time 56069713 ps
CPU time 1.66 seconds
Started Apr 28 12:54:49 PM PDT 24
Finished Apr 28 12:54:51 PM PDT 24
Peak memory 213060 kb
Host smart-4082abfc-5b78-4c05-92ed-db514dbf1f5c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533100537 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.533100537
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2121549022
Short name T301
Test name
Test status
Simulation time 177948829 ps
CPU time 2.39 seconds
Started Apr 28 12:54:50 PM PDT 24
Finished Apr 28 12:54:53 PM PDT 24
Peak memory 217932 kb
Host smart-5944de22-7727-4e95-b8a3-4735d51eb600
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121549022 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.2121549022
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1411642379
Short name T303
Test name
Test status
Simulation time 18974788386 ps
CPU time 17.29 seconds
Started Apr 28 12:54:47 PM PDT 24
Finished Apr 28 12:55:05 PM PDT 24
Peak memory 204744 kb
Host smart-6c1a22bb-2ffd-40e9-b70e-03d03f6d5b40
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411642379 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.1411642379
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1795199040
Short name T238
Test name
Test status
Simulation time 11596482708 ps
CPU time 26.09 seconds
Started Apr 28 12:54:49 PM PDT 24
Finished Apr 28 12:55:16 PM PDT 24
Peak memory 204960 kb
Host smart-7221112d-3c3b-4e27-8eb0-c19a872b502a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795199040 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_bit_bash.1795199040
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2753418893
Short name T210
Test name
Test status
Simulation time 1270618295 ps
CPU time 2.97 seconds
Started Apr 28 12:54:48 PM PDT 24
Finished Apr 28 12:54:52 PM PDT 24
Peak memory 204932 kb
Host smart-2e4ac222-9e61-424b-b50f-84a440bf317a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753418893 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.2753418893
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1718140996
Short name T292
Test name
Test status
Simulation time 669636036 ps
CPU time 2.17 seconds
Started Apr 28 12:54:50 PM PDT 24
Finished Apr 28 12:54:53 PM PDT 24
Peak memory 204800 kb
Host smart-83f746bd-3a70-43d1-8f81-ea146f69b154
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718140996 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.1
718140996
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.2588090528
Short name T218
Test name
Test status
Simulation time 122566136 ps
CPU time 0.71 seconds
Started Apr 28 12:54:50 PM PDT 24
Finished Apr 28 12:54:52 PM PDT 24
Peak memory 204508 kb
Host smart-8b4dae0b-be7b-4b61-a2bc-2c2c885c66eb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588090528 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.2588090528
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2035661382
Short name T265
Test name
Test status
Simulation time 2020446704 ps
CPU time 7.19 seconds
Started Apr 28 12:54:47 PM PDT 24
Finished Apr 28 12:54:55 PM PDT 24
Peak memory 204820 kb
Host smart-97ba4d37-d8fe-4262-b60c-f2f2d3d7ff26
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035661382 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.2035661382
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3394730526
Short name T195
Test name
Test status
Simulation time 62475992 ps
CPU time 0.76 seconds
Started Apr 28 12:54:49 PM PDT 24
Finished Apr 28 12:54:51 PM PDT 24
Peak memory 204684 kb
Host smart-bde07291-0007-45d3-b681-3da23c818083
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394730526 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.3394730526
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1500553331
Short name T261
Test name
Test status
Simulation time 40649802 ps
CPU time 0.75 seconds
Started Apr 28 12:54:47 PM PDT 24
Finished Apr 28 12:54:49 PM PDT 24
Peak memory 204592 kb
Host smart-828718ee-c165-4ccb-a250-b4711bfebb76
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500553331 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.1
500553331
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.1949186114
Short name T274
Test name
Test status
Simulation time 17945179 ps
CPU time 0.72 seconds
Started Apr 28 12:54:48 PM PDT 24
Finished Apr 28 12:54:49 PM PDT 24
Peak memory 204608 kb
Host smart-b562376f-ca11-4f85-9db7-853d8ae911d5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949186114 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.1949186114
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.2928310062
Short name T263
Test name
Test status
Simulation time 38989421 ps
CPU time 0.67 seconds
Started Apr 28 12:54:50 PM PDT 24
Finished Apr 28 12:54:51 PM PDT 24
Peak memory 204592 kb
Host smart-c2365c71-6b79-43ba-a08f-016496b7b621
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928310062 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.2928310062
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.22349414
Short name T104
Test name
Test status
Simulation time 185597180 ps
CPU time 3.42 seconds
Started Apr 28 12:54:48 PM PDT 24
Finished Apr 28 12:54:52 PM PDT 24
Peak memory 204964 kb
Host smart-e00abc4a-0406-4e36-80b5-14d0a4d9b92b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22349414 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_cs
r_outstanding.22349414
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2713966833
Short name T76
Test name
Test status
Simulation time 71619066 ps
CPU time 4.6 seconds
Started Apr 28 12:54:48 PM PDT 24
Finished Apr 28 12:54:53 PM PDT 24
Peak memory 213184 kb
Host smart-4603c855-83ea-4c76-9232-f440e9770932
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713966833 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.2713966833
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2186863109
Short name T135
Test name
Test status
Simulation time 704358273 ps
CPU time 16.11 seconds
Started Apr 28 12:54:47 PM PDT 24
Finished Apr 28 12:55:04 PM PDT 24
Peak memory 221260 kb
Host smart-ecd958e8-fbf0-4360-9fd3-e9e5853e8ea8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186863109 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.2186863109
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_dm_tap_fsm_rand_reset.736535958
Short name T137
Test name
Test status
Simulation time 6965924449 ps
CPU time 14.72 seconds
Started Apr 28 12:55:20 PM PDT 24
Finished Apr 28 12:55:35 PM PDT 24
Peak memory 218716 kb
Host smart-9cc660c7-c834-49e0-9650-b9fb6c93ad5f
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736535958 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 30.rv_dm_tap_fsm_rand_reset.736535958
Directory /workspace/30.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/33.rv_dm_tap_fsm_rand_reset.4121107794
Short name T298
Test name
Test status
Simulation time 9734241182 ps
CPU time 19.26 seconds
Started Apr 28 12:55:19 PM PDT 24
Finished Apr 28 12:55:39 PM PDT 24
Peak memory 214696 kb
Host smart-afe39140-b59d-46e7-a59f-93765a76493c
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121107794 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 33.rv_dm_tap_fsm_rand_reset.4121107794
Directory /workspace/33.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/37.rv_dm_tap_fsm_rand_reset.2965075203
Short name T220
Test name
Test status
Simulation time 15348312380 ps
CPU time 34.84 seconds
Started Apr 28 12:55:18 PM PDT 24
Finished Apr 28 12:55:53 PM PDT 24
Peak memory 221448 kb
Host smart-b0af8793-78c8-4d51-a6c7-e2a6c8e84d56
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965075203 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 37.rv_dm_tap_fsm_rand_reset.2965075203
Directory /workspace/37.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1043149664
Short name T53
Test name
Test status
Simulation time 6712284954 ps
CPU time 71.05 seconds
Started Apr 28 12:54:53 PM PDT 24
Finished Apr 28 12:56:06 PM PDT 24
Peak memory 205024 kb
Host smart-25a055c4-215c-449c-a54a-2324d4d74b49
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043149664 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.1043149664
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.1929489693
Short name T114
Test name
Test status
Simulation time 30786098752 ps
CPU time 37.02 seconds
Started Apr 28 12:54:53 PM PDT 24
Finished Apr 28 12:55:31 PM PDT 24
Peak memory 205108 kb
Host smart-b8297bc1-a412-4ee2-966c-abca242b36bd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929489693 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.1929489693
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.754464990
Short name T107
Test name
Test status
Simulation time 79062269 ps
CPU time 2.3 seconds
Started Apr 28 12:54:56 PM PDT 24
Finished Apr 28 12:54:59 PM PDT 24
Peak memory 213204 kb
Host smart-c558dc21-795f-4867-b4e5-4145fee645e3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754464990 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.754464990
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.877633635
Short name T304
Test name
Test status
Simulation time 2460819603 ps
CPU time 3.47 seconds
Started Apr 28 12:54:52 PM PDT 24
Finished Apr 28 12:54:56 PM PDT 24
Peak memory 221384 kb
Host smart-7ebaa1cc-be13-4d10-ab90-33d07b28a3e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877633635 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.877633635
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.3793282158
Short name T81
Test name
Test status
Simulation time 61078202 ps
CPU time 1.52 seconds
Started Apr 28 12:54:54 PM PDT 24
Finished Apr 28 12:54:57 PM PDT 24
Peak memory 212992 kb
Host smart-5d28ad83-6526-4f8d-9c84-c81228abe104
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793282158 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.3793282158
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2944810800
Short name T256
Test name
Test status
Simulation time 9581403423 ps
CPU time 34.07 seconds
Started Apr 28 12:54:55 PM PDT 24
Finished Apr 28 12:55:30 PM PDT 24
Peak memory 204932 kb
Host smart-89b256be-637d-496c-946d-c83e9d479dfd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944810800 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.2944810800
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3152529645
Short name T295
Test name
Test status
Simulation time 11604972613 ps
CPU time 40.24 seconds
Started Apr 28 12:54:55 PM PDT 24
Finished Apr 28 12:55:36 PM PDT 24
Peak memory 204900 kb
Host smart-d3ac2d25-e10d-4f45-b717-0438a84fafc5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152529645 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_bit_bash.3152529645
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.1137234565
Short name T96
Test name
Test status
Simulation time 411930860 ps
CPU time 1.12 seconds
Started Apr 28 12:54:53 PM PDT 24
Finished Apr 28 12:54:56 PM PDT 24
Peak memory 204860 kb
Host smart-1dd13e96-5921-42ea-b68f-6562f9b917a9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137234565 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.1137234565
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.1944114761
Short name T287
Test name
Test status
Simulation time 758934712 ps
CPU time 1.38 seconds
Started Apr 28 12:54:54 PM PDT 24
Finished Apr 28 12:54:56 PM PDT 24
Peak memory 204768 kb
Host smart-a1f50224-b6e0-4de2-b37e-fa3728c64f60
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944114761 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.1
944114761
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.96434009
Short name T237
Test name
Test status
Simulation time 167973722 ps
CPU time 1.1 seconds
Started Apr 28 12:54:54 PM PDT 24
Finished Apr 28 12:54:56 PM PDT 24
Peak memory 204596 kb
Host smart-d3c49c35-9047-4792-9bcd-083317e49885
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96434009 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_
aliasing.96434009
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.4213622554
Short name T189
Test name
Test status
Simulation time 975511358 ps
CPU time 4.72 seconds
Started Apr 28 12:54:55 PM PDT 24
Finished Apr 28 12:55:01 PM PDT 24
Peak memory 204680 kb
Host smart-01efffbc-b4a3-4c08-a02c-81de489599bb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213622554 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.4213622554
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.4084339491
Short name T186
Test name
Test status
Simulation time 120712556 ps
CPU time 0.91 seconds
Started Apr 28 12:54:53 PM PDT 24
Finished Apr 28 12:54:54 PM PDT 24
Peak memory 204680 kb
Host smart-2ae4d8f0-c2ff-40a9-bc8c-fc6122438c35
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084339491 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.4084339491
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.40318675
Short name T72
Test name
Test status
Simulation time 33483889 ps
CPU time 0.76 seconds
Started Apr 28 12:54:58 PM PDT 24
Finished Apr 28 12:54:59 PM PDT 24
Peak memory 204592 kb
Host smart-11032339-eff8-4992-9340-a51ada5e410f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40318675 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.40318675
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.3989791780
Short name T253
Test name
Test status
Simulation time 26845320 ps
CPU time 0.66 seconds
Started Apr 28 12:54:55 PM PDT 24
Finished Apr 28 12:54:57 PM PDT 24
Peak memory 204572 kb
Host smart-1e0cd10f-6484-46f7-a2da-3a3fff7a45f5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989791780 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.3989791780
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.1757187911
Short name T266
Test name
Test status
Simulation time 27776885 ps
CPU time 0.69 seconds
Started Apr 28 12:54:53 PM PDT 24
Finished Apr 28 12:54:54 PM PDT 24
Peak memory 204464 kb
Host smart-1cb28136-6582-4f92-9a06-a7fc580c6a52
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757187911 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.1757187911
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.836623817
Short name T293
Test name
Test status
Simulation time 1473860854 ps
CPU time 8.3 seconds
Started Apr 28 12:54:58 PM PDT 24
Finished Apr 28 12:55:07 PM PDT 24
Peak memory 204908 kb
Host smart-879eef2d-f5e9-4e01-b873-b1af43a2861e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836623817 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_c
sr_outstanding.836623817
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.1522994954
Short name T73
Test name
Test status
Simulation time 234835126 ps
CPU time 2.34 seconds
Started Apr 28 12:54:54 PM PDT 24
Finished Apr 28 12:54:57 PM PDT 24
Peak memory 213240 kb
Host smart-716253ec-36fd-480f-8cd3-0752cb0eb304
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522994954 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.1522994954
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.4229632201
Short name T120
Test name
Test status
Simulation time 282164060 ps
CPU time 2.3 seconds
Started Apr 28 12:54:54 PM PDT 24
Finished Apr 28 12:54:57 PM PDT 24
Peak memory 213220 kb
Host smart-417a282b-41ff-4f94-b777-3ab5f202836f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229632201 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.4229632201
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.499545549
Short name T278
Test name
Test status
Simulation time 53432879 ps
CPU time 1.41 seconds
Started Apr 28 12:55:09 PM PDT 24
Finished Apr 28 12:55:11 PM PDT 24
Peak memory 213076 kb
Host smart-d7287a5b-ad05-4123-b8f0-af280e07ac24
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499545549 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.499545549
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.1171856835
Short name T252
Test name
Test status
Simulation time 228460046 ps
CPU time 1.08 seconds
Started Apr 28 12:54:53 PM PDT 24
Finished Apr 28 12:54:55 PM PDT 24
Peak memory 204656 kb
Host smart-8b617547-3fc0-4805-af45-d4dcdd2b3424
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171856835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.1
171856835
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.941283776
Short name T196
Test name
Test status
Simulation time 109689887 ps
CPU time 0.98 seconds
Started Apr 28 12:54:55 PM PDT 24
Finished Apr 28 12:54:56 PM PDT 24
Peak memory 204608 kb
Host smart-ec01363d-23b4-4823-961e-edf805be8f9c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941283776 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.941283776
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1300341857
Short name T85
Test name
Test status
Simulation time 234387286 ps
CPU time 4.04 seconds
Started Apr 28 12:54:53 PM PDT 24
Finished Apr 28 12:54:58 PM PDT 24
Peak memory 204956 kb
Host smart-34c16679-fd4f-4a00-8f30-e7e741a14599
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300341857 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.1300341857
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.3926467293
Short name T48
Test name
Test status
Simulation time 74609570 ps
CPU time 2.04 seconds
Started Apr 28 12:54:58 PM PDT 24
Finished Apr 28 12:55:00 PM PDT 24
Peak memory 213172 kb
Host smart-56e79f5d-adce-444e-8630-ba6472a1d4dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926467293 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.3926467293
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.1266260319
Short name T132
Test name
Test status
Simulation time 276171015 ps
CPU time 7.91 seconds
Started Apr 28 12:54:54 PM PDT 24
Finished Apr 28 12:55:03 PM PDT 24
Peak memory 213000 kb
Host smart-9a803797-9ff2-47a8-88b8-b87df495946e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266260319 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.1266260319
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2505903864
Short name T247
Test name
Test status
Simulation time 315268119 ps
CPU time 2.18 seconds
Started Apr 28 12:54:57 PM PDT 24
Finished Apr 28 12:55:00 PM PDT 24
Peak memory 216892 kb
Host smart-11a7897b-1be1-4940-a72d-02ec02520b08
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505903864 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.2505903864
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.2190159508
Short name T244
Test name
Test status
Simulation time 131013966 ps
CPU time 1.62 seconds
Started Apr 28 12:54:59 PM PDT 24
Finished Apr 28 12:55:01 PM PDT 24
Peak memory 221296 kb
Host smart-ae4c5946-0ef1-4b68-ae3e-284d7d89c781
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190159508 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.2190159508
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.122913175
Short name T178
Test name
Test status
Simulation time 317648072 ps
CPU time 1.47 seconds
Started Apr 28 12:54:52 PM PDT 24
Finished Apr 28 12:54:54 PM PDT 24
Peak memory 204800 kb
Host smart-0da35bce-9118-4993-9ecb-0832946f434e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122913175 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.122913175
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.73612903
Short name T70
Test name
Test status
Simulation time 118686415 ps
CPU time 0.75 seconds
Started Apr 28 12:54:54 PM PDT 24
Finished Apr 28 12:54:56 PM PDT 24
Peak memory 204400 kb
Host smart-26a886be-290f-4d44-bb2c-023b39b08a5e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73612903 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.73612903
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.1283638240
Short name T290
Test name
Test status
Simulation time 405466521 ps
CPU time 4.24 seconds
Started Apr 28 12:54:58 PM PDT 24
Finished Apr 28 12:55:03 PM PDT 24
Peak memory 204920 kb
Host smart-efe20e8c-7b3b-471f-b148-c4650035283b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283638240 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.1283638240
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.3728944201
Short name T150
Test name
Test status
Simulation time 1475817201 ps
CPU time 6.95 seconds
Started Apr 28 12:54:59 PM PDT 24
Finished Apr 28 12:55:07 PM PDT 24
Peak memory 213156 kb
Host smart-560425b8-e236-4434-9e85-a559de6277d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728944201 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.3728944201
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.1586256928
Short name T299
Test name
Test status
Simulation time 130398593 ps
CPU time 3.8 seconds
Started Apr 28 12:54:58 PM PDT 24
Finished Apr 28 12:55:02 PM PDT 24
Peak memory 221288 kb
Host smart-9dff3cd4-0592-43a9-9253-85de707e1ffd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586256928 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.1586256928
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.1292806263
Short name T229
Test name
Test status
Simulation time 225615755 ps
CPU time 1.63 seconds
Started Apr 28 12:55:00 PM PDT 24
Finished Apr 28 12:55:03 PM PDT 24
Peak memory 213144 kb
Host smart-d921eb4f-1d00-44bc-a907-deccca456470
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292806263 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.1292806263
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2621670500
Short name T282
Test name
Test status
Simulation time 217129327 ps
CPU time 1.6 seconds
Started Apr 28 12:54:59 PM PDT 24
Finished Apr 28 12:55:02 PM PDT 24
Peak memory 204712 kb
Host smart-7dc18a66-ef86-4677-8aee-f449f45a6ae2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621670500 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.2
621670500
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.2331115800
Short name T175
Test name
Test status
Simulation time 137114676 ps
CPU time 0.71 seconds
Started Apr 28 12:54:57 PM PDT 24
Finished Apr 28 12:54:58 PM PDT 24
Peak memory 204496 kb
Host smart-24cfd744-38e3-4048-a8b6-fbb2f9a2977a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331115800 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.2
331115800
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.1440046642
Short name T49
Test name
Test status
Simulation time 397116023 ps
CPU time 3.87 seconds
Started Apr 28 12:54:58 PM PDT 24
Finished Apr 28 12:55:02 PM PDT 24
Peak memory 204804 kb
Host smart-5a2d9dfb-8d20-4f68-979d-949c4cc21e65
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440046642 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.1440046642
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.3729867588
Short name T67
Test name
Test status
Simulation time 24467963955 ps
CPU time 22.6 seconds
Started Apr 28 12:54:59 PM PDT 24
Finished Apr 28 12:55:22 PM PDT 24
Peak memory 229636 kb
Host smart-123bb475-dadb-4959-87d5-d9aa2dd70986
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729867588 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.3729867588
Directory /workspace/7.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.2008265045
Short name T239
Test name
Test status
Simulation time 321276518 ps
CPU time 2.62 seconds
Started Apr 28 12:54:58 PM PDT 24
Finished Apr 28 12:55:01 PM PDT 24
Peak memory 213224 kb
Host smart-3321923d-9514-45c2-a85c-7fc19d3db41c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008265045 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.2008265045
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1345416629
Short name T207
Test name
Test status
Simulation time 49701668 ps
CPU time 2.6 seconds
Started Apr 28 12:54:57 PM PDT 24
Finished Apr 28 12:55:00 PM PDT 24
Peak memory 216940 kb
Host smart-c6f6eda6-c1cb-40de-8330-a8bf8c0cf6b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345416629 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.1345416629
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1974625261
Short name T113
Test name
Test status
Simulation time 119100511 ps
CPU time 2.37 seconds
Started Apr 28 12:55:00 PM PDT 24
Finished Apr 28 12:55:03 PM PDT 24
Peak memory 213124 kb
Host smart-21f59c82-91f0-4798-ba06-c7cb808bdb27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974625261 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.1974625261
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.280691381
Short name T222
Test name
Test status
Simulation time 577247914 ps
CPU time 1.49 seconds
Started Apr 28 12:54:59 PM PDT 24
Finished Apr 28 12:55:01 PM PDT 24
Peak memory 204696 kb
Host smart-218fd13b-964b-4667-ae97-c95fd375b274
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280691381 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.280691381
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.4130061881
Short name T202
Test name
Test status
Simulation time 92669738 ps
CPU time 0.94 seconds
Started Apr 28 12:55:01 PM PDT 24
Finished Apr 28 12:55:02 PM PDT 24
Peak memory 204572 kb
Host smart-3659f9ea-9bcc-4951-8e25-a9a72a0ebc62
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130061881 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.4
130061881
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.3949487167
Short name T242
Test name
Test status
Simulation time 391560167 ps
CPU time 7.09 seconds
Started Apr 28 12:55:00 PM PDT 24
Finished Apr 28 12:55:07 PM PDT 24
Peak memory 204884 kb
Host smart-aba784c5-3647-45bd-92c9-5d17aef272aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949487167 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_
csr_outstanding.3949487167
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.4186977031
Short name T216
Test name
Test status
Simulation time 2764874550 ps
CPU time 5.8 seconds
Started Apr 28 12:55:00 PM PDT 24
Finished Apr 28 12:55:06 PM PDT 24
Peak memory 213184 kb
Host smart-d903c641-7ebe-4840-aa1c-197d7eab2e77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186977031 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.4186977031
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.1801113702
Short name T136
Test name
Test status
Simulation time 3424344297 ps
CPU time 19.13 seconds
Started Apr 28 12:54:58 PM PDT 24
Finished Apr 28 12:55:18 PM PDT 24
Peak memory 221252 kb
Host smart-b962fb33-c93b-41f9-81d4-dd7f00912f60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801113702 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.1801113702
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3486562961
Short name T230
Test name
Test status
Simulation time 4240444314 ps
CPU time 6 seconds
Started Apr 28 12:54:58 PM PDT 24
Finished Apr 28 12:55:05 PM PDT 24
Peak memory 219908 kb
Host smart-9fef678f-c300-478d-8a06-ccb6019fbe5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486562961 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.3486562961
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.756708751
Short name T289
Test name
Test status
Simulation time 90544540 ps
CPU time 1.64 seconds
Started Apr 28 12:55:00 PM PDT 24
Finished Apr 28 12:55:02 PM PDT 24
Peak memory 213068 kb
Host smart-09bc5070-0fb7-40ca-924d-8a686ab3a525
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756708751 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.756708751
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3359521853
Short name T198
Test name
Test status
Simulation time 313610772 ps
CPU time 1.29 seconds
Started Apr 28 12:55:00 PM PDT 24
Finished Apr 28 12:55:02 PM PDT 24
Peak memory 204808 kb
Host smart-ebc2229b-6673-4e64-b5c2-aa9d0db9062a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359521853 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.3
359521853
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.4057345696
Short name T215
Test name
Test status
Simulation time 38933595 ps
CPU time 0.77 seconds
Started Apr 28 12:54:58 PM PDT 24
Finished Apr 28 12:55:00 PM PDT 24
Peak memory 204444 kb
Host smart-75e11ed5-dc04-4065-98e5-50911cda0cca
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057345696 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.4
057345696
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.305888099
Short name T99
Test name
Test status
Simulation time 835140144 ps
CPU time 7.31 seconds
Started Apr 28 12:54:59 PM PDT 24
Finished Apr 28 12:55:07 PM PDT 24
Peak memory 204872 kb
Host smart-04e9e395-2a51-4355-92f1-7f596ce323d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305888099 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_c
sr_outstanding.305888099
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.393859635
Short name T269
Test name
Test status
Simulation time 161816880 ps
CPU time 5.19 seconds
Started Apr 28 12:55:04 PM PDT 24
Finished Apr 28 12:55:10 PM PDT 24
Peak memory 213208 kb
Host smart-65de00ab-1013-42a1-82c8-d17db540fb86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393859635 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.393859635
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.3043127652
Short name T128
Test name
Test status
Simulation time 3308314871 ps
CPU time 21.64 seconds
Started Apr 28 12:54:59 PM PDT 24
Finished Apr 28 12:55:22 PM PDT 24
Peak memory 213224 kb
Host smart-1ac6840d-2b06-4aae-be56-d74bae5cab7a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043127652 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.3043127652
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.3667757248
Short name T58
Test name
Test status
Simulation time 140179078 ps
CPU time 0.73 seconds
Started Apr 28 04:25:34 PM PDT 24
Finished Apr 28 04:25:35 PM PDT 24
Peak memory 205152 kb
Host smart-22c62daa-65fb-48d8-a55f-9bc084b0c869
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667757248 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.3667757248
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.457663233
Short name T6
Test name
Test status
Simulation time 3034821096 ps
CPU time 6.74 seconds
Started Apr 28 04:25:17 PM PDT 24
Finished Apr 28 04:25:24 PM PDT 24
Peak memory 205492 kb
Host smart-4c453b8d-2b45-448a-988b-c633e9590378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457663233 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.457663233
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.1450276986
Short name T13
Test name
Test status
Simulation time 303496160 ps
CPU time 1.26 seconds
Started Apr 28 04:25:19 PM PDT 24
Finished Apr 28 04:25:20 PM PDT 24
Peak memory 205200 kb
Host smart-fa6df85b-0f3c-48e0-83cc-98c0e9eba1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450276986 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.1450276986
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.1497388559
Short name T12
Test name
Test status
Simulation time 2053099795 ps
CPU time 4.47 seconds
Started Apr 28 04:25:16 PM PDT 24
Finished Apr 28 04:25:21 PM PDT 24
Peak memory 205392 kb
Host smart-3f2c6dfc-b2d5-4741-9ab4-a1c48b96db2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497388559 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.1497388559
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.1771865381
Short name T141
Test name
Test status
Simulation time 31271333 ps
CPU time 0.79 seconds
Started Apr 28 04:25:29 PM PDT 24
Finished Apr 28 04:25:30 PM PDT 24
Peak memory 205164 kb
Host smart-92efa015-e915-41b3-b68f-875c8cc4b101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771865381 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.1771865381
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.3700262584
Short name T169
Test name
Test status
Simulation time 49797870 ps
CPU time 0.81 seconds
Started Apr 28 04:25:19 PM PDT 24
Finished Apr 28 04:25:20 PM PDT 24
Peak memory 205076 kb
Host smart-39eedfe2-f78b-45dd-a0cb-b41e24fe16e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700262584 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.3700262584
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.2981919709
Short name T166
Test name
Test status
Simulation time 68571915 ps
CPU time 0.95 seconds
Started Apr 28 04:25:33 PM PDT 24
Finished Apr 28 04:25:34 PM PDT 24
Peak memory 205048 kb
Host smart-5bbb4ed2-0560-4365-aef8-02c25f122c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981919709 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.2981919709
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.2513630709
Short name T35
Test name
Test status
Simulation time 171703472 ps
CPU time 0.91 seconds
Started Apr 28 04:25:33 PM PDT 24
Finished Apr 28 04:25:35 PM PDT 24
Peak memory 204924 kb
Host smart-0f22084c-f60d-4fe1-8f1b-491d051fb290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513630709 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.2513630709
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.2728647455
Short name T139
Test name
Test status
Simulation time 78450598 ps
CPU time 0.82 seconds
Started Apr 28 04:25:19 PM PDT 24
Finished Apr 28 04:25:21 PM PDT 24
Peak memory 205168 kb
Host smart-43372f0e-92e2-4340-85fc-4a5eb1e8b837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728647455 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.2728647455
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.2605360917
Short name T14
Test name
Test status
Simulation time 531111889 ps
CPU time 1.76 seconds
Started Apr 28 04:25:19 PM PDT 24
Finished Apr 28 04:25:21 PM PDT 24
Peak memory 205372 kb
Host smart-1c3f2751-c188-41fe-86d0-0b59e6f32292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605360917 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.2605360917
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.3397378740
Short name T22
Test name
Test status
Simulation time 534459223 ps
CPU time 2.54 seconds
Started Apr 28 04:25:28 PM PDT 24
Finished Apr 28 04:25:31 PM PDT 24
Peak memory 205384 kb
Host smart-13428ae8-d819-44d9-aa2b-c7809ff8e46b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397378740 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.3397378740
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.801749342
Short name T24
Test name
Test status
Simulation time 103300384 ps
CPU time 0.99 seconds
Started Apr 28 04:25:33 PM PDT 24
Finished Apr 28 04:25:35 PM PDT 24
Peak memory 205000 kb
Host smart-cf04f189-d66e-4661-ac01-ccc294f724e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801749342 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.801749342
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.3763864386
Short name T172
Test name
Test status
Simulation time 297887822 ps
CPU time 1.31 seconds
Started Apr 28 04:25:07 PM PDT 24
Finished Apr 28 04:25:09 PM PDT 24
Peak memory 205236 kb
Host smart-3d95c0b4-fcd7-4d2e-af16-095da6698a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763864386 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.3763864386
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.3436824248
Short name T8
Test name
Test status
Simulation time 137697300 ps
CPU time 0.76 seconds
Started Apr 28 04:25:52 PM PDT 24
Finished Apr 28 04:25:53 PM PDT 24
Peak memory 205220 kb
Host smart-da8a7085-98b1-4c1b-9ad3-dfe13ba64865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436824248 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.3436824248
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.211902147
Short name T157
Test name
Test status
Simulation time 47046439 ps
CPU time 0.78 seconds
Started Apr 28 04:25:55 PM PDT 24
Finished Apr 28 04:25:56 PM PDT 24
Peak memory 205196 kb
Host smart-e1f655da-4aa7-41d1-9e6f-8816c081dca9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211902147 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.211902147
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.1177344192
Short name T31
Test name
Test status
Simulation time 2428490562 ps
CPU time 10.55 seconds
Started Apr 28 04:25:44 PM PDT 24
Finished Apr 28 04:25:55 PM PDT 24
Peak memory 205480 kb
Host smart-4d54768a-defc-4f0f-ba35-13c20b987500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177344192 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.1177344192
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.1962036937
Short name T10
Test name
Test status
Simulation time 449491101 ps
CPU time 2.05 seconds
Started Apr 28 04:25:54 PM PDT 24
Finished Apr 28 04:25:56 PM PDT 24
Peak memory 205016 kb
Host smart-b06819ab-21f2-4f24-bf19-8fb44796a76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962036937 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.1962036937
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.2536865650
Short name T20
Test name
Test status
Simulation time 116357998 ps
CPU time 0.81 seconds
Started Apr 28 04:25:51 PM PDT 24
Finished Apr 28 04:25:53 PM PDT 24
Peak memory 205088 kb
Host smart-8d39910a-8f0f-448f-9ddb-9fcc7a408c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536865650 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.2536865650
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.2126773047
Short name T3
Test name
Test status
Simulation time 46756075 ps
CPU time 0.85 seconds
Started Apr 28 04:25:47 PM PDT 24
Finished Apr 28 04:25:48 PM PDT 24
Peak memory 205044 kb
Host smart-634d083d-d130-4066-879c-121b7c8e19b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126773047 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.2126773047
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.3924748468
Short name T36
Test name
Test status
Simulation time 293798880 ps
CPU time 1.07 seconds
Started Apr 28 04:25:53 PM PDT 24
Finished Apr 28 04:25:55 PM PDT 24
Peak memory 205076 kb
Host smart-08e3ed42-0e88-40b6-a68e-c48a1aca9370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924748468 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.3924748468
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.2641430841
Short name T37
Test name
Test status
Simulation time 372921443 ps
CPU time 1.01 seconds
Started Apr 28 04:25:50 PM PDT 24
Finished Apr 28 04:25:52 PM PDT 24
Peak memory 205092 kb
Host smart-f607cf5e-1689-4003-8eeb-625b12a236d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641430841 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.2641430841
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.3431976561
Short name T140
Test name
Test status
Simulation time 69579578 ps
CPU time 0.8 seconds
Started Apr 28 04:25:42 PM PDT 24
Finished Apr 28 04:25:43 PM PDT 24
Peak memory 205196 kb
Host smart-820bb3b7-1b98-4794-bf44-40d6125735b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431976561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.3431976561
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.3960278165
Short name T16
Test name
Test status
Simulation time 203407972 ps
CPU time 1.04 seconds
Started Apr 28 04:25:49 PM PDT 24
Finished Apr 28 04:25:51 PM PDT 24
Peak memory 205164 kb
Host smart-4e6c2b1f-34f5-4c0c-bcdc-06155cfd9653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960278165 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.3960278165
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.1123304284
Short name T21
Test name
Test status
Simulation time 846086933 ps
CPU time 1.18 seconds
Started Apr 28 04:25:52 PM PDT 24
Finished Apr 28 04:25:53 PM PDT 24
Peak memory 205364 kb
Host smart-9558c231-2144-45d7-b01f-e3c90a89b624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123304284 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.1123304284
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.4081148940
Short name T28
Test name
Test status
Simulation time 87348472 ps
CPU time 0.82 seconds
Started Apr 28 04:25:56 PM PDT 24
Finished Apr 28 04:25:57 PM PDT 24
Peak memory 205196 kb
Host smart-f059516a-4c78-4b57-a459-4e5a17cfbffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081148940 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.4081148940
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.3894812428
Short name T18
Test name
Test status
Simulation time 25577370 ps
CPU time 0.8 seconds
Started Apr 28 04:25:51 PM PDT 24
Finished Apr 28 04:25:52 PM PDT 24
Peak memory 213412 kb
Host smart-72fbbc9c-90cf-4264-81bb-af38ebbed315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894812428 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.3894812428
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.3699368036
Short name T40
Test name
Test status
Simulation time 299812257 ps
CPU time 1.56 seconds
Started Apr 28 04:25:57 PM PDT 24
Finished Apr 28 04:25:59 PM PDT 24
Peak memory 229392 kb
Host smart-e844f2cf-d5ad-4223-abc2-dfe5151d2bcb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699368036 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.3699368036
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.1030336205
Short name T2
Test name
Test status
Simulation time 1222031996 ps
CPU time 1.64 seconds
Started Apr 28 04:25:34 PM PDT 24
Finished Apr 28 04:25:36 PM PDT 24
Peak memory 205232 kb
Host smart-564a8b23-d2b0-4cca-bd7c-26a9b08ca061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030336205 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.1030336205
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.1497085912
Short name T156
Test name
Test status
Simulation time 65973591 ps
CPU time 0.77 seconds
Started Apr 28 04:26:37 PM PDT 24
Finished Apr 28 04:26:38 PM PDT 24
Peak memory 205128 kb
Host smart-6c0689d4-ef71-4afa-9245-249684f81d40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497085912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.1497085912
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.1178621004
Short name T65
Test name
Test status
Simulation time 2849566727 ps
CPU time 4.96 seconds
Started Apr 28 04:26:32 PM PDT 24
Finished Apr 28 04:26:37 PM PDT 24
Peak memory 213856 kb
Host smart-721bd220-572a-44c5-94d0-4faf91eaa7d0
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1178621004 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.1178621004
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.1535915974
Short name T165
Test name
Test status
Simulation time 56886012 ps
CPU time 0.69 seconds
Started Apr 28 04:26:41 PM PDT 24
Finished Apr 28 04:26:43 PM PDT 24
Peak memory 205128 kb
Host smart-d2d7f055-31ce-4e9d-8b12-d86be0d7edc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535915974 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.1535915974
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.3917338627
Short name T54
Test name
Test status
Simulation time 41421219 ps
CPU time 0.75 seconds
Started Apr 28 04:26:44 PM PDT 24
Finished Apr 28 04:26:45 PM PDT 24
Peak memory 205196 kb
Host smart-5e55d30f-8701-4590-8846-4e1898f3b394
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917338627 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.3917338627
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.1596240170
Short name T1
Test name
Test status
Simulation time 20693411 ps
CPU time 0.72 seconds
Started Apr 28 04:26:45 PM PDT 24
Finished Apr 28 04:26:46 PM PDT 24
Peak memory 205172 kb
Host smart-bb4dd7ca-074f-45ab-9bf6-97c97a6bb204
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596240170 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.1596240170
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.2016743165
Short name T168
Test name
Test status
Simulation time 31226979 ps
CPU time 0.75 seconds
Started Apr 28 04:26:47 PM PDT 24
Finished Apr 28 04:26:48 PM PDT 24
Peak memory 205168 kb
Host smart-11ae53c4-4097-429a-ae41-178e78533a51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016743165 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.2016743165
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.3028594183
Short name T146
Test name
Test status
Simulation time 52964806 ps
CPU time 0.77 seconds
Started Apr 28 04:26:46 PM PDT 24
Finished Apr 28 04:26:47 PM PDT 24
Peak memory 205148 kb
Host smart-614a4e0a-6dc5-43db-ab06-78fbc068fc81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028594183 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.3028594183
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.332692560
Short name T32
Test name
Test status
Simulation time 596447105 ps
CPU time 1.63 seconds
Started Apr 28 04:26:45 PM PDT 24
Finished Apr 28 04:26:48 PM PDT 24
Peak memory 205468 kb
Host smart-cbb9ec40-7f99-4990-95e9-50cc9eae3937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332692560 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.332692560
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.1511872427
Short name T155
Test name
Test status
Simulation time 91185983 ps
CPU time 0.76 seconds
Started Apr 28 04:26:50 PM PDT 24
Finished Apr 28 04:26:51 PM PDT 24
Peak memory 205104 kb
Host smart-f0533c10-4389-4838-8b7a-9f5369bbfbe4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511872427 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.1511872427
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_stress_all.205203187
Short name T43
Test name
Test status
Simulation time 3536569817 ps
CPU time 12.35 seconds
Started Apr 28 04:26:51 PM PDT 24
Finished Apr 28 04:27:04 PM PDT 24
Peak memory 205560 kb
Host smart-d82fe000-c849-45bc-8a4a-7c82f16d2cf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205203187 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.205203187
Directory /workspace/16.rv_dm_stress_all/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.2749954968
Short name T44
Test name
Test status
Simulation time 45083422 ps
CPU time 0.74 seconds
Started Apr 28 04:26:51 PM PDT 24
Finished Apr 28 04:26:52 PM PDT 24
Peak memory 205144 kb
Host smart-58b7950b-b223-4aa7-a967-cdf735fa8a95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749954968 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.2749954968
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.1238598613
Short name T63
Test name
Test status
Simulation time 53036825 ps
CPU time 0.74 seconds
Started Apr 28 04:26:57 PM PDT 24
Finished Apr 28 04:26:58 PM PDT 24
Peak memory 205124 kb
Host smart-b9aa3af8-be56-40a9-9ae2-4bbc47eed1fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238598613 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.1238598613
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.3065093176
Short name T148
Test name
Test status
Simulation time 49585910 ps
CPU time 0.76 seconds
Started Apr 28 04:27:00 PM PDT 24
Finished Apr 28 04:27:02 PM PDT 24
Peak memory 205192 kb
Host smart-caa26a2b-355b-44f8-afa3-f3713193c084
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065093176 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.3065093176
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.199064306
Short name T55
Test name
Test status
Simulation time 32148743 ps
CPU time 0.73 seconds
Started Apr 28 04:26:02 PM PDT 24
Finished Apr 28 04:26:03 PM PDT 24
Peak memory 205212 kb
Host smart-a6eb3a84-b1d1-4971-a12a-1673da38347b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199064306 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.199064306
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.2191883752
Short name T92
Test name
Test status
Simulation time 41097486 ps
CPU time 0.84 seconds
Started Apr 28 04:25:59 PM PDT 24
Finished Apr 28 04:26:00 PM PDT 24
Peak memory 205012 kb
Host smart-6c21e928-bd60-48f2-b6c3-5cfc7a195a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191883752 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.2191883752
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.1904275599
Short name T60
Test name
Test status
Simulation time 347952843 ps
CPU time 2.05 seconds
Started Apr 28 04:26:02 PM PDT 24
Finished Apr 28 04:26:05 PM PDT 24
Peak memory 229392 kb
Host smart-5e5000f2-7b27-40dd-a4d7-1a41ec0d3860
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904275599 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.1904275599
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.2684716094
Short name T170
Test name
Test status
Simulation time 102789659 ps
CPU time 0.73 seconds
Started Apr 28 04:27:07 PM PDT 24
Finished Apr 28 04:27:08 PM PDT 24
Peak memory 205164 kb
Host smart-17564077-e3f1-4d7e-87b6-88c958b421b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684716094 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.2684716094
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.1353617376
Short name T161
Test name
Test status
Simulation time 53776560 ps
CPU time 0.74 seconds
Started Apr 28 04:27:06 PM PDT 24
Finished Apr 28 04:27:07 PM PDT 24
Peak memory 205164 kb
Host smart-0a1e05ba-0609-4a3d-a29a-36e6455320bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353617376 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.1353617376
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.675785358
Short name T4
Test name
Test status
Simulation time 51587485 ps
CPU time 0.73 seconds
Started Apr 28 04:27:06 PM PDT 24
Finished Apr 28 04:27:07 PM PDT 24
Peak memory 205172 kb
Host smart-0d8fd53e-d848-4da6-9e11-cf3d90dc80a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675785358 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.675785358
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.1160495983
Short name T151
Test name
Test status
Simulation time 29654425 ps
CPU time 0.77 seconds
Started Apr 28 04:27:06 PM PDT 24
Finished Apr 28 04:27:07 PM PDT 24
Peak memory 205176 kb
Host smart-4bb401da-110b-463f-b571-1b6fb9fbeea2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160495983 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.1160495983
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.1194006019
Short name T56
Test name
Test status
Simulation time 39278019 ps
CPU time 0.76 seconds
Started Apr 28 04:27:05 PM PDT 24
Finished Apr 28 04:27:06 PM PDT 24
Peak memory 205172 kb
Host smart-22c9e96e-57a1-4bbe-84ff-f139aa6eb855
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194006019 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.1194006019
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.2169768371
Short name T59
Test name
Test status
Simulation time 42425525 ps
CPU time 0.75 seconds
Started Apr 28 04:27:10 PM PDT 24
Finished Apr 28 04:27:11 PM PDT 24
Peak memory 205176 kb
Host smart-e90a14b3-b2bd-4b7e-b8d0-f779e293cc4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169768371 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.2169768371
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.2578995276
Short name T163
Test name
Test status
Simulation time 19098966 ps
CPU time 0.83 seconds
Started Apr 28 04:27:12 PM PDT 24
Finished Apr 28 04:27:14 PM PDT 24
Peak memory 205172 kb
Host smart-647ba5a4-6b0e-421e-8173-5ed446951cf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578995276 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.2578995276
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.1891316704
Short name T173
Test name
Test status
Simulation time 58497961 ps
CPU time 0.74 seconds
Started Apr 28 04:27:11 PM PDT 24
Finished Apr 28 04:27:12 PM PDT 24
Peak memory 205088 kb
Host smart-97a65277-1f47-4f36-aace-1bf1128a8acf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891316704 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.1891316704
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.2901338330
Short name T91
Test name
Test status
Simulation time 47425231 ps
CPU time 0.75 seconds
Started Apr 28 04:27:09 PM PDT 24
Finished Apr 28 04:27:10 PM PDT 24
Peak memory 205156 kb
Host smart-a07d525a-01b3-4090-8d46-a52e50895b59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901338330 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.2901338330
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.1163550745
Short name T51
Test name
Test status
Simulation time 85248020 ps
CPU time 0.7 seconds
Started Apr 28 04:26:07 PM PDT 24
Finished Apr 28 04:26:08 PM PDT 24
Peak memory 205172 kb
Host smart-4b88d1dc-2d5d-4e68-acc7-3eeb08ae4828
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163550745 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.1163550745
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.2165098098
Short name T171
Test name
Test status
Simulation time 175906301 ps
CPU time 1.3 seconds
Started Apr 28 04:26:04 PM PDT 24
Finished Apr 28 04:26:06 PM PDT 24
Peak memory 205048 kb
Host smart-ece14337-4aaa-4da4-a57e-4b778f466a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165098098 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.2165098098
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.3495081324
Short name T38
Test name
Test status
Simulation time 387517193 ps
CPU time 2.14 seconds
Started Apr 28 04:26:10 PM PDT 24
Finished Apr 28 04:26:12 PM PDT 24
Peak memory 229340 kb
Host smart-097acacc-0da9-4ee7-96ac-90b50fc44dbf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495081324 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.3495081324
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.3442997648
Short name T154
Test name
Test status
Simulation time 33250351 ps
CPU time 0.78 seconds
Started Apr 28 04:27:08 PM PDT 24
Finished Apr 28 04:27:09 PM PDT 24
Peak memory 205204 kb
Host smart-d5373c8b-e975-4603-a494-579fa0a1f180
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442997648 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.3442997648
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.1587997267
Short name T41
Test name
Test status
Simulation time 26648767 ps
CPU time 0.75 seconds
Started Apr 28 04:27:13 PM PDT 24
Finished Apr 28 04:27:14 PM PDT 24
Peak memory 205188 kb
Host smart-5401ed27-7f39-4d38-b2ea-c8eaeb4ff219
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587997267 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.1587997267
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.3923113155
Short name T152
Test name
Test status
Simulation time 27139160 ps
CPU time 0.81 seconds
Started Apr 28 04:27:14 PM PDT 24
Finished Apr 28 04:27:15 PM PDT 24
Peak memory 205184 kb
Host smart-b8e7ba18-297f-4981-ad85-5e6388f1eadd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923113155 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.3923113155
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.1968914328
Short name T88
Test name
Test status
Simulation time 33835161 ps
CPU time 0.79 seconds
Started Apr 28 04:27:14 PM PDT 24
Finished Apr 28 04:27:15 PM PDT 24
Peak memory 205180 kb
Host smart-30028e3a-719b-423b-b6b6-5883932d4074
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968914328 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.1968914328
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.4015444807
Short name T42
Test name
Test status
Simulation time 49833765 ps
CPU time 0.7 seconds
Started Apr 28 04:27:18 PM PDT 24
Finished Apr 28 04:27:20 PM PDT 24
Peak memory 205172 kb
Host smart-d0c69ef3-d806-4c8d-a051-6bb0f5732aa9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015444807 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.4015444807
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.2968247005
Short name T147
Test name
Test status
Simulation time 28892246 ps
CPU time 0.75 seconds
Started Apr 28 04:27:18 PM PDT 24
Finished Apr 28 04:27:20 PM PDT 24
Peak memory 205152 kb
Host smart-809dbc68-33d1-4583-922d-cfc5b8b594b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968247005 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.2968247005
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.878965199
Short name T121
Test name
Test status
Simulation time 20508036 ps
CPU time 0.76 seconds
Started Apr 28 04:27:22 PM PDT 24
Finished Apr 28 04:27:23 PM PDT 24
Peak memory 205176 kb
Host smart-ba95dfa4-a163-475a-96a8-2b1311a76193
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878965199 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.878965199
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.1367345500
Short name T164
Test name
Test status
Simulation time 114832355 ps
CPU time 0.79 seconds
Started Apr 28 04:27:23 PM PDT 24
Finished Apr 28 04:27:24 PM PDT 24
Peak memory 205164 kb
Host smart-acdf9a64-b2a0-4a57-8b73-cea983340198
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367345500 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.1367345500
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.862954727
Short name T145
Test name
Test status
Simulation time 56111450 ps
CPU time 0.82 seconds
Started Apr 28 04:27:31 PM PDT 24
Finished Apr 28 04:27:32 PM PDT 24
Peak memory 205128 kb
Host smart-4a2a7c48-2d2b-4c7e-b036-6db00a5bf8ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862954727 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.862954727
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.292305866
Short name T142
Test name
Test status
Simulation time 26065429 ps
CPU time 0.74 seconds
Started Apr 28 04:27:26 PM PDT 24
Finished Apr 28 04:27:27 PM PDT 24
Peak memory 205148 kb
Host smart-f27e2fa6-d1fb-45f6-892b-3c3724040841
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292305866 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.292305866
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.2466496642
Short name T149
Test name
Test status
Simulation time 20507553 ps
CPU time 0.76 seconds
Started Apr 28 04:26:08 PM PDT 24
Finished Apr 28 04:26:10 PM PDT 24
Peak memory 205164 kb
Host smart-bef75098-6019-42da-a2c7-c88ad9354af3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466496642 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.2466496642
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.221533064
Short name T167
Test name
Test status
Simulation time 65046535 ps
CPU time 0.94 seconds
Started Apr 28 04:26:07 PM PDT 24
Finished Apr 28 04:26:09 PM PDT 24
Peak memory 205036 kb
Host smart-efd55663-dcab-4f94-a95d-ec03bbfd7a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221533064 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.221533064
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.677420604
Short name T39
Test name
Test status
Simulation time 345173379 ps
CPU time 1.19 seconds
Started Apr 28 04:26:13 PM PDT 24
Finished Apr 28 04:26:14 PM PDT 24
Peak memory 229476 kb
Host smart-5c22b7a6-52ce-46a2-b9ed-8882838dd75f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677420604 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.677420604
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.1673932691
Short name T143
Test name
Test status
Simulation time 81208711 ps
CPU time 0.78 seconds
Started Apr 28 04:27:25 PM PDT 24
Finished Apr 28 04:27:26 PM PDT 24
Peak memory 205168 kb
Host smart-04b637c9-5691-4a01-977f-6d26ae215531
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673932691 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.1673932691
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.797517516
Short name T153
Test name
Test status
Simulation time 28036330 ps
CPU time 0.75 seconds
Started Apr 28 04:27:23 PM PDT 24
Finished Apr 28 04:27:24 PM PDT 24
Peak memory 205212 kb
Host smart-e997e5c2-3fc9-4997-85c5-f41731e2ede5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797517516 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.797517516
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.495810577
Short name T64
Test name
Test status
Simulation time 22307671 ps
CPU time 0.81 seconds
Started Apr 28 04:27:25 PM PDT 24
Finished Apr 28 04:27:27 PM PDT 24
Peak memory 205196 kb
Host smart-7f633014-382a-4576-b1bc-3bf64662ab89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495810577 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.495810577
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.3725553324
Short name T162
Test name
Test status
Simulation time 65953233 ps
CPU time 0.77 seconds
Started Apr 28 04:27:31 PM PDT 24
Finished Apr 28 04:27:32 PM PDT 24
Peak memory 205108 kb
Host smart-0e631af0-cbd2-428e-98e7-ff53be0317d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725553324 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.3725553324
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.1542224801
Short name T160
Test name
Test status
Simulation time 57356125 ps
CPU time 0.76 seconds
Started Apr 28 04:27:24 PM PDT 24
Finished Apr 28 04:27:25 PM PDT 24
Peak memory 205160 kb
Host smart-9e5dd249-f79d-46b8-b5ce-b1755fe68380
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542224801 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.1542224801
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.3363290565
Short name T57
Test name
Test status
Simulation time 27403127 ps
CPU time 0.72 seconds
Started Apr 28 04:27:29 PM PDT 24
Finished Apr 28 04:27:30 PM PDT 24
Peak memory 205172 kb
Host smart-37a2011a-a756-4a22-98ea-fdcc7add6ec1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363290565 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.3363290565
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.2665262798
Short name T90
Test name
Test status
Simulation time 18342528 ps
CPU time 0.74 seconds
Started Apr 28 04:27:29 PM PDT 24
Finished Apr 28 04:27:30 PM PDT 24
Peak memory 205144 kb
Host smart-1a9d75bf-4181-4846-8fc8-1f149658837b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665262798 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.2665262798
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.2343616900
Short name T159
Test name
Test status
Simulation time 49185439 ps
CPU time 0.74 seconds
Started Apr 28 04:27:27 PM PDT 24
Finished Apr 28 04:27:29 PM PDT 24
Peak memory 205184 kb
Host smart-52c8b490-10b3-48af-9046-755e45b56b70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343616900 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.2343616900
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.1929984287
Short name T62
Test name
Test status
Simulation time 27800345 ps
CPU time 0.76 seconds
Started Apr 28 04:27:28 PM PDT 24
Finished Apr 28 04:27:29 PM PDT 24
Peak memory 205164 kb
Host smart-8751f2e0-5db7-4b22-a041-67d1ec223221
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929984287 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.1929984287
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.4179287368
Short name T74
Test name
Test status
Simulation time 20219901 ps
CPU time 0.72 seconds
Started Apr 28 04:27:31 PM PDT 24
Finished Apr 28 04:27:32 PM PDT 24
Peak memory 205172 kb
Host smart-4862ab51-04d9-405a-8f54-a4f027943613
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179287368 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.4179287368
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.3725819512
Short name T144
Test name
Test status
Simulation time 37576478 ps
CPU time 0.76 seconds
Started Apr 28 04:26:17 PM PDT 24
Finished Apr 28 04:26:18 PM PDT 24
Peak memory 205164 kb
Host smart-496336ab-163e-4502-8252-f95d33237b90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725819512 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.3725819512
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.3149538612
Short name T158
Test name
Test status
Simulation time 167656262 ps
CPU time 0.77 seconds
Started Apr 28 04:26:20 PM PDT 24
Finished Apr 28 04:26:21 PM PDT 24
Peak memory 205148 kb
Host smart-2d9b09cb-f0dc-4b33-9bae-0c502e91570d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149538612 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.3149538612
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.1975740079
Short name T89
Test name
Test status
Simulation time 25714325 ps
CPU time 0.76 seconds
Started Apr 28 04:26:32 PM PDT 24
Finished Apr 28 04:26:33 PM PDT 24
Peak memory 205156 kb
Host smart-c00f1a48-a9a8-46e6-ba3f-9ef8119cbdb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975740079 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.1975740079
Directory /workspace/8.rv_dm_alert_test/latest
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