Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
79.17 93.86 81.18 87.61 73.08 82.33 98.52 37.60


Total tests in report: 305
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
51.90 51.90 81.92 81.92 46.29 46.29 32.10 32.10 50.00 50.00 60.67 60.67 91.76 91.76 0.54 0.54 /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.1051600093
58.30 6.40 84.69 2.77 54.40 8.10 57.96 25.86 50.00 0.00 65.50 4.83 92.93 1.16 2.63 2.09 /workspace/coverage/default/1.rv_dm_cmderr_not_supported.3789410558
63.25 4.94 86.91 2.22 61.81 7.42 77.88 19.91 50.00 0.00 68.00 2.50 94.40 1.48 3.72 1.09 /workspace/coverage/default/7.rv_dm_alert_test.1849434339
67.33 4.08 87.06 0.15 66.76 4.95 81.42 3.54 50.00 0.00 69.17 1.17 95.46 1.06 21.44 17.71 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1220357809
71.13 3.80 89.88 2.82 71.70 4.95 83.67 2.25 60.26 10.26 74.17 5.00 95.99 0.53 22.25 0.82 /workspace/coverage/default/26.rv_dm_stress_all.2777379177
72.81 1.68 90.13 0.25 72.12 0.41 83.67 0.00 67.95 7.69 74.83 0.67 95.99 0.00 24.98 2.72 /workspace/coverage/cover_reg_top/12.rv_dm_tap_fsm_rand_reset.1370525239
74.20 1.39 91.74 1.61 76.79 4.67 83.83 0.16 69.23 1.28 76.83 2.00 95.99 0.00 24.98 0.00 /workspace/coverage/default/21.rv_dm_stress_all.1454110384
75.49 1.30 91.74 0.00 76.79 0.00 83.91 0.08 69.23 0.00 76.83 0.00 96.62 0.63 33.33 8.36 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.1242335710
76.51 1.02 92.70 0.96 77.88 1.10 84.47 0.56 71.79 2.56 78.67 1.83 96.62 0.00 33.42 0.09 /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.132231166
77.27 0.76 92.90 0.20 79.40 1.51 85.04 0.56 71.79 0.00 79.33 0.67 96.83 0.21 35.60 2.18 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1627132869
77.51 0.24 92.90 0.00 79.81 0.41 85.84 0.80 71.79 0.00 79.33 0.00 96.83 0.00 36.06 0.45 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.3749557451
77.74 0.23 92.95 0.05 79.81 0.00 85.92 0.08 73.08 1.28 79.50 0.17 96.83 0.00 36.06 0.00 /workspace/coverage/default/0.rv_dm_tap_fsm.2957500470
77.87 0.13 92.95 0.00 80.22 0.41 86.16 0.24 73.08 0.00 79.50 0.00 96.94 0.11 36.24 0.18 /workspace/coverage/default/0.rv_dm_sec_cm.1203393672
77.99 0.12 93.15 0.20 80.22 0.00 86.16 0.00 73.08 0.00 80.17 0.67 96.94 0.00 36.24 0.00 /workspace/coverage/default/1.rv_dm_cmderr_exception.514965244
78.11 0.12 93.15 0.00 80.22 0.00 86.52 0.36 73.08 0.00 80.17 0.00 96.94 0.00 36.69 0.45 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.3421859849
78.22 0.11 93.45 0.30 80.22 0.00 86.52 0.00 73.08 0.00 80.67 0.50 96.94 0.00 36.69 0.00 /workspace/coverage/default/0.rv_dm_abstractcmd_status.4011937887
78.34 0.11 93.50 0.05 80.63 0.41 86.52 0.00 73.08 0.00 81.00 0.33 96.94 0.00 36.69 0.00 /workspace/coverage/default/1.rv_dm_progbuf_busy.755080345
78.44 0.11 93.61 0.10 80.77 0.14 86.52 0.00 73.08 0.00 81.50 0.50 96.94 0.00 36.69 0.00 /workspace/coverage/default/0.rv_dm_rom_read_access.1198734923
78.55 0.10 93.61 0.00 80.77 0.00 86.52 0.00 73.08 0.00 81.50 0.00 97.57 0.63 36.78 0.09 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1053143485
78.65 0.10 93.66 0.05 80.91 0.14 86.77 0.24 73.08 0.00 81.67 0.17 97.57 0.00 36.88 0.09 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3978255629
78.74 0.09 93.71 0.05 80.91 0.00 87.09 0.32 73.08 0.00 81.83 0.17 97.57 0.00 36.97 0.09 /workspace/coverage/default/9.rv_dm_alert_test.1968357885
78.81 0.08 93.71 0.00 80.91 0.00 87.09 0.00 73.08 0.00 81.83 0.00 98.10 0.53 36.97 0.00 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.935758542
78.87 0.06 93.81 0.10 80.91 0.00 87.09 0.00 73.08 0.00 82.17 0.33 98.10 0.00 36.97 0.00 /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.2595904710
78.93 0.06 93.81 0.00 80.91 0.00 87.25 0.16 73.08 0.00 82.17 0.00 98.10 0.00 37.24 0.27 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.3072701159
78.99 0.05 93.86 0.05 81.04 0.14 87.25 0.00 73.08 0.00 82.33 0.17 98.10 0.00 37.24 0.00 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.1349084261
79.02 0.03 93.86 0.00 81.04 0.00 87.29 0.04 73.08 0.00 82.33 0.00 98.10 0.00 37.42 0.18 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.511811443
79.05 0.03 93.86 0.00 81.04 0.00 87.29 0.00 73.08 0.00 82.33 0.00 98.31 0.21 37.42 0.00 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.1219580296
79.07 0.02 93.86 0.00 81.04 0.00 87.45 0.16 73.08 0.00 82.33 0.00 98.31 0.00 37.42 0.00 /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.3652021756
79.09 0.02 93.86 0.00 81.04 0.00 87.61 0.16 73.08 0.00 82.33 0.00 98.31 0.00 37.42 0.00 /workspace/coverage/default/24.rv_dm_alert_test.3935482305
79.11 0.02 93.86 0.00 81.18 0.14 87.61 0.00 73.08 0.00 82.33 0.00 98.31 0.00 37.42 0.00 /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.1062597171
79.13 0.02 93.86 0.00 81.18 0.00 87.61 0.00 73.08 0.00 82.33 0.00 98.42 0.11 37.42 0.00 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3522698025
79.14 0.02 93.86 0.00 81.18 0.00 87.61 0.00 73.08 0.00 82.33 0.00 98.52 0.11 37.42 0.00 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.682465789
79.16 0.01 93.86 0.00 81.18 0.00 87.61 0.00 73.08 0.00 82.33 0.00 98.52 0.00 37.51 0.09 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.2891863163
79.17 0.01 93.86 0.00 81.18 0.00 87.61 0.00 73.08 0.00 82.33 0.00 98.52 0.00 37.60 0.09 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1527368374

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.1197376007
/workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3170845905
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.2665171807
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.615021164
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.1718442073
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.1595860124
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.13514206
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3086312204
/workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.2897583454
/workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.1522507901
/workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.771129557
/workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.2010687708
/workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.1407332721
/workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2797163201
/workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2935645218
/workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2274346494
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.4285034205
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2051280903
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.86027723
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.2473604127
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3867927375
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.579623665
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.3468589607
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.2495264181
/workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2482191698
/workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.336197237
/workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2720646846
/workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.838911090
/workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.3918716754
/workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.982042359
/workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.2592007023
/workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.982514205
/workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1769758618
/workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.715648441
/workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.4136629744
/workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3447907823
/workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.680608269
/workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.343054846
/workspace/coverage/cover_reg_top/11.rv_dm_tap_fsm_rand_reset.2158588664
/workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.977219396
/workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.798085173
/workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.2099416401
/workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.3750192485
/workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.4202877314
/workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3457279153
/workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1546388060
/workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.2128305877
/workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2966972066
/workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.921175584
/workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.1430657957
/workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.4175416897
/workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3117915274
/workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.439168885
/workspace/coverage/cover_reg_top/13.rv_dm_tap_fsm_rand_reset.3375331168
/workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.3218315834
/workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3607286078
/workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.2590737548
/workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.572489849
/workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.578140595
/workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2115037741
/workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2692107834
/workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.2066631026
/workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.4105835715
/workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.1040866440
/workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.1670139079
/workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3847354815
/workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.624408081
/workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.1301215877
/workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2789666548
/workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2566264216
/workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.523852185
/workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.180361566
/workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3947799598
/workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.728431720
/workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3421147155
/workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.2445287400
/workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.109350406
/workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.995422001
/workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.1298540589
/workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.4078589809
/workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.436122732
/workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.519258301
/workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2507288475
/workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.3208141766
/workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1145718865
/workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.3573268347
/workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.584157342
/workspace/coverage/cover_reg_top/18.rv_dm_tap_fsm_rand_reset.3805050507
/workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.205050313
/workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.1568748211
/workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1950033857
/workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.1195845647
/workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.978716427
/workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.478437679
/workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.4022964066
/workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.235537829
/workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.1835749871
/workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.895107879
/workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2041252156
/workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.4276335662
/workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.1120628998
/workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.2866431528
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.1337898394
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.784584509
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2447778100
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.3772952325
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3266213986
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1456506146
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1497890078
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2107822629
/workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1653043473
/workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.2189825935
/workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3517677172
/workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.3297688023
/workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.2247620643
/workspace/coverage/cover_reg_top/20.rv_dm_tap_fsm_rand_reset.3606166104
/workspace/coverage/cover_reg_top/27.rv_dm_tap_fsm_rand_reset.2400709776
/workspace/coverage/cover_reg_top/28.rv_dm_tap_fsm_rand_reset.2813921799
/workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2012661632
/workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.3811614084
/workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.533100537
/workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2121549022
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1411642379
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1795199040
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2753418893
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1718140996
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.2588090528
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2035661382
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3394730526
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1500553331
/workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.1949186114
/workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.2928310062
/workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.22349414
/workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2713966833
/workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2186863109
/workspace/coverage/cover_reg_top/30.rv_dm_tap_fsm_rand_reset.736535958
/workspace/coverage/cover_reg_top/33.rv_dm_tap_fsm_rand_reset.4121107794
/workspace/coverage/cover_reg_top/37.rv_dm_tap_fsm_rand_reset.2965075203
/workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1043149664
/workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.1929489693
/workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.754464990
/workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.877633635
/workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.3793282158
/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2944810800
/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3152529645
/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.1137234565
/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.1944114761
/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.96434009
/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.4213622554
/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.4084339491
/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.40318675
/workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.3989791780
/workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.1757187911
/workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.836623817
/workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.1522994954
/workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.4229632201
/workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.499545549
/workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.1171856835
/workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.941283776
/workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1300341857
/workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.3926467293
/workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.1266260319
/workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2505903864
/workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.2190159508
/workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.122913175
/workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.73612903
/workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.1283638240
/workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.3728944201
/workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.1586256928
/workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.1292806263
/workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2621670500
/workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.2331115800
/workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.1440046642
/workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.3729867588
/workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.2008265045
/workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1345416629
/workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1974625261
/workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.280691381
/workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.4130061881
/workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.3949487167
/workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.4186977031
/workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.1801113702
/workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3486562961
/workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.756708751
/workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3359521853
/workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.4057345696
/workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.305888099
/workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.393859635
/workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.3043127652
/workspace/coverage/default/0.rv_dm_alert_test.3667757248
/workspace/coverage/default/0.rv_dm_cmderr_busy.457663233
/workspace/coverage/default/0.rv_dm_cmderr_exception.1450276986
/workspace/coverage/default/0.rv_dm_cmderr_not_supported.1497388559
/workspace/coverage/default/0.rv_dm_dataaddr_rw_access.1771865381
/workspace/coverage/default/0.rv_dm_hart_unavail.3700262584
/workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.2981919709
/workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.2513630709
/workspace/coverage/default/0.rv_dm_mem_tl_access_halted.2728647455
/workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.2605360917
/workspace/coverage/default/0.rv_dm_ndmreset_req.3397378740
/workspace/coverage/default/0.rv_dm_progbuf_busy.801749342
/workspace/coverage/default/0.rv_dm_smoke.3763864386
/workspace/coverage/default/1.rv_dm_abstractcmd_status.3436824248
/workspace/coverage/default/1.rv_dm_alert_test.211902147
/workspace/coverage/default/1.rv_dm_cmderr_busy.1177344192
/workspace/coverage/default/1.rv_dm_cmderr_halt_resume.1962036937
/workspace/coverage/default/1.rv_dm_dataaddr_rw_access.2536865650
/workspace/coverage/default/1.rv_dm_hart_unavail.2126773047
/workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.3924748468
/workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.2641430841
/workspace/coverage/default/1.rv_dm_mem_tl_access_halted.3431976561
/workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.3960278165
/workspace/coverage/default/1.rv_dm_ndmreset_req.1123304284
/workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.4081148940
/workspace/coverage/default/1.rv_dm_rom_read_access.3894812428
/workspace/coverage/default/1.rv_dm_sec_cm.3699368036
/workspace/coverage/default/1.rv_dm_smoke.1030336205
/workspace/coverage/default/10.rv_dm_alert_test.1497085912
/workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.1178621004
/workspace/coverage/default/11.rv_dm_alert_test.1535915974
/workspace/coverage/default/12.rv_dm_alert_test.3917338627
/workspace/coverage/default/13.rv_dm_alert_test.1596240170
/workspace/coverage/default/14.rv_dm_alert_test.2016743165
/workspace/coverage/default/15.rv_dm_alert_test.3028594183
/workspace/coverage/default/15.rv_dm_sba_tl_access.332692560
/workspace/coverage/default/16.rv_dm_alert_test.1511872427
/workspace/coverage/default/16.rv_dm_stress_all.205203187
/workspace/coverage/default/17.rv_dm_alert_test.2749954968
/workspace/coverage/default/18.rv_dm_alert_test.1238598613
/workspace/coverage/default/19.rv_dm_alert_test.3065093176
/workspace/coverage/default/2.rv_dm_alert_test.199064306
/workspace/coverage/default/2.rv_dm_hart_unavail.2191883752
/workspace/coverage/default/2.rv_dm_sec_cm.1904275599
/workspace/coverage/default/20.rv_dm_alert_test.2684716094
/workspace/coverage/default/21.rv_dm_alert_test.1353617376
/workspace/coverage/default/22.rv_dm_alert_test.675785358
/workspace/coverage/default/23.rv_dm_alert_test.1160495983
/workspace/coverage/default/25.rv_dm_alert_test.1194006019
/workspace/coverage/default/26.rv_dm_alert_test.2169768371
/workspace/coverage/default/27.rv_dm_alert_test.2578995276
/workspace/coverage/default/28.rv_dm_alert_test.1891316704
/workspace/coverage/default/29.rv_dm_alert_test.2901338330
/workspace/coverage/default/3.rv_dm_alert_test.1163550745
/workspace/coverage/default/3.rv_dm_hart_unavail.2165098098
/workspace/coverage/default/3.rv_dm_sec_cm.3495081324
/workspace/coverage/default/30.rv_dm_alert_test.3442997648
/workspace/coverage/default/31.rv_dm_alert_test.1587997267
/workspace/coverage/default/32.rv_dm_alert_test.3923113155
/workspace/coverage/default/33.rv_dm_alert_test.1968914328
/workspace/coverage/default/34.rv_dm_alert_test.4015444807
/workspace/coverage/default/35.rv_dm_alert_test.2968247005
/workspace/coverage/default/36.rv_dm_alert_test.878965199
/workspace/coverage/default/37.rv_dm_alert_test.1367345500
/workspace/coverage/default/38.rv_dm_alert_test.862954727
/workspace/coverage/default/39.rv_dm_alert_test.292305866
/workspace/coverage/default/4.rv_dm_alert_test.2466496642
/workspace/coverage/default/4.rv_dm_hart_unavail.221533064
/workspace/coverage/default/4.rv_dm_sec_cm.677420604
/workspace/coverage/default/40.rv_dm_alert_test.1673932691
/workspace/coverage/default/41.rv_dm_alert_test.797517516
/workspace/coverage/default/42.rv_dm_alert_test.495810577
/workspace/coverage/default/43.rv_dm_alert_test.3725553324
/workspace/coverage/default/44.rv_dm_alert_test.1542224801
/workspace/coverage/default/45.rv_dm_alert_test.3363290565
/workspace/coverage/default/46.rv_dm_alert_test.2665262798
/workspace/coverage/default/47.rv_dm_alert_test.2343616900
/workspace/coverage/default/48.rv_dm_alert_test.1929984287
/workspace/coverage/default/49.rv_dm_alert_test.4179287368
/workspace/coverage/default/5.rv_dm_alert_test.3725819512
/workspace/coverage/default/6.rv_dm_alert_test.3149538612
/workspace/coverage/default/8.rv_dm_alert_test.1975740079



Total test records in report: 305
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/13.rv_dm_alert_test.1596240170 Apr 28 04:26:45 PM PDT 24 Apr 28 04:26:46 PM PDT 24 20693411 ps
T2 /workspace/coverage/default/1.rv_dm_smoke.1030336205 Apr 28 04:25:34 PM PDT 24 Apr 28 04:25:36 PM PDT 24 1222031996 ps
T3 /workspace/coverage/default/1.rv_dm_hart_unavail.2126773047 Apr 28 04:25:47 PM PDT 24 Apr 28 04:25:48 PM PDT 24 46756075 ps
T41 /workspace/coverage/default/31.rv_dm_alert_test.1587997267 Apr 28 04:27:13 PM PDT 24 Apr 28 04:27:14 PM PDT 24 26648767 ps
T42 /workspace/coverage/default/34.rv_dm_alert_test.4015444807 Apr 28 04:27:18 PM PDT 24 Apr 28 04:27:20 PM PDT 24 49833765 ps
T4 /workspace/coverage/default/22.rv_dm_alert_test.675785358 Apr 28 04:27:06 PM PDT 24 Apr 28 04:27:07 PM PDT 24 51587485 ps
T5 /workspace/coverage/default/7.rv_dm_alert_test.1849434339 Apr 28 04:26:29 PM PDT 24 Apr 28 04:26:30 PM PDT 24 138654491 ps
T19 /workspace/coverage/default/9.rv_dm_alert_test.1968357885 Apr 28 04:26:32 PM PDT 24 Apr 28 04:26:34 PM PDT 24 33561074 ps
T44 /workspace/coverage/default/17.rv_dm_alert_test.2749954968 Apr 28 04:26:51 PM PDT 24 Apr 28 04:26:52 PM PDT 24 45083422 ps
T30 /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.1051600093 Apr 28 04:26:05 PM PDT 24 Apr 28 04:26:11 PM PDT 24 3484172513 ps
T6 /workspace/coverage/default/0.rv_dm_cmderr_busy.457663233 Apr 28 04:25:17 PM PDT 24 Apr 28 04:25:24 PM PDT 24 3034821096 ps
T74 /workspace/coverage/default/49.rv_dm_alert_test.4179287368 Apr 28 04:27:31 PM PDT 24 Apr 28 04:27:32 PM PDT 24 20219901 ps
T38 /workspace/coverage/default/3.rv_dm_sec_cm.3495081324 Apr 28 04:26:10 PM PDT 24 Apr 28 04:26:12 PM PDT 24 387517193 ps
T39 /workspace/coverage/default/4.rv_dm_sec_cm.677420604 Apr 28 04:26:13 PM PDT 24 Apr 28 04:26:14 PM PDT 24 345173379 ps
T62 /workspace/coverage/default/48.rv_dm_alert_test.1929984287 Apr 28 04:27:28 PM PDT 24 Apr 28 04:27:29 PM PDT 24 27800345 ps
T7 /workspace/coverage/default/1.rv_dm_cmderr_not_supported.3789410558 Apr 28 04:25:44 PM PDT 24 Apr 28 04:25:48 PM PDT 24 765623435 ps
T63 /workspace/coverage/default/18.rv_dm_alert_test.1238598613 Apr 28 04:26:57 PM PDT 24 Apr 28 04:26:58 PM PDT 24 53036825 ps
T64 /workspace/coverage/default/42.rv_dm_alert_test.495810577 Apr 28 04:27:25 PM PDT 24 Apr 28 04:27:27 PM PDT 24 22307671 ps
T54 /workspace/coverage/default/12.rv_dm_alert_test.3917338627 Apr 28 04:26:44 PM PDT 24 Apr 28 04:26:45 PM PDT 24 41421219 ps
T26 /workspace/coverage/default/0.rv_dm_tap_fsm.2957500470 Apr 28 04:25:12 PM PDT 24 Apr 28 04:25:16 PM PDT 24 3605151089 ps
T55 /workspace/coverage/default/2.rv_dm_alert_test.199064306 Apr 28 04:26:02 PM PDT 24 Apr 28 04:26:03 PM PDT 24 32148743 ps
T20 /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.2536865650 Apr 28 04:25:51 PM PDT 24 Apr 28 04:25:53 PM PDT 24 116357998 ps
T35 /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.2513630709 Apr 28 04:25:33 PM PDT 24 Apr 28 04:25:35 PM PDT 24 171703472 ps
T51 /workspace/coverage/default/3.rv_dm_alert_test.1163550745 Apr 28 04:26:07 PM PDT 24 Apr 28 04:26:08 PM PDT 24 85248020 ps
T8 /workspace/coverage/default/1.rv_dm_abstractcmd_status.3436824248 Apr 28 04:25:52 PM PDT 24 Apr 28 04:25:53 PM PDT 24 137697300 ps
T88 /workspace/coverage/default/33.rv_dm_alert_test.1968914328 Apr 28 04:27:14 PM PDT 24 Apr 28 04:27:15 PM PDT 24 33835161 ps
T89 /workspace/coverage/default/8.rv_dm_alert_test.1975740079 Apr 28 04:26:32 PM PDT 24 Apr 28 04:26:33 PM PDT 24 25714325 ps
T90 /workspace/coverage/default/46.rv_dm_alert_test.2665262798 Apr 28 04:27:29 PM PDT 24 Apr 28 04:27:30 PM PDT 24 18342528 ps
T52 /workspace/coverage/default/24.rv_dm_alert_test.3935482305 Apr 28 04:27:04 PM PDT 24 Apr 28 04:27:05 PM PDT 24 41816132 ps
T91 /workspace/coverage/default/29.rv_dm_alert_test.2901338330 Apr 28 04:27:09 PM PDT 24 Apr 28 04:27:10 PM PDT 24 47425231 ps
T92 /workspace/coverage/default/2.rv_dm_hart_unavail.2191883752 Apr 28 04:25:59 PM PDT 24 Apr 28 04:26:00 PM PDT 24 41097486 ps
T32 /workspace/coverage/default/15.rv_dm_sba_tl_access.332692560 Apr 28 04:26:45 PM PDT 24 Apr 28 04:26:48 PM PDT 24 596447105 ps
T56 /workspace/coverage/default/25.rv_dm_alert_test.1194006019 Apr 28 04:27:05 PM PDT 24 Apr 28 04:27:06 PM PDT 24 39278019 ps
T59 /workspace/coverage/default/26.rv_dm_alert_test.2169768371 Apr 28 04:27:10 PM PDT 24 Apr 28 04:27:11 PM PDT 24 42425525 ps
T17 /workspace/coverage/default/0.rv_dm_rom_read_access.1198734923 Apr 28 04:25:31 PM PDT 24 Apr 28 04:25:32 PM PDT 24 31941037 ps
T58 /workspace/coverage/default/0.rv_dm_alert_test.3667757248 Apr 28 04:25:34 PM PDT 24 Apr 28 04:25:35 PM PDT 24 140179078 ps
T33 /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.3652021756 Apr 28 04:25:56 PM PDT 24 Apr 28 04:26:02 PM PDT 24 6034848962 ps
T144 /workspace/coverage/default/5.rv_dm_alert_test.3725819512 Apr 28 04:26:17 PM PDT 24 Apr 28 04:26:18 PM PDT 24 37576478 ps
T27 /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.2595904710 Apr 28 04:25:34 PM PDT 24 Apr 28 04:25:35 PM PDT 24 226512398 ps
T142 /workspace/coverage/default/39.rv_dm_alert_test.292305866 Apr 28 04:27:26 PM PDT 24 Apr 28 04:27:27 PM PDT 24 26065429 ps
T9 /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.1062597171 Apr 28 04:25:24 PM PDT 24 Apr 28 04:25:26 PM PDT 24 214652741 ps
T158 /workspace/coverage/default/6.rv_dm_alert_test.3149538612 Apr 28 04:26:20 PM PDT 24 Apr 28 04:26:21 PM PDT 24 167656262 ps
T147 /workspace/coverage/default/35.rv_dm_alert_test.2968247005 Apr 28 04:27:18 PM PDT 24 Apr 28 04:27:20 PM PDT 24 28892246 ps
T57 /workspace/coverage/default/45.rv_dm_alert_test.3363290565 Apr 28 04:27:29 PM PDT 24 Apr 28 04:27:30 PM PDT 24 27403127 ps
T14 /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.2605360917 Apr 28 04:25:19 PM PDT 24 Apr 28 04:25:21 PM PDT 24 531111889 ps
T21 /workspace/coverage/default/1.rv_dm_ndmreset_req.1123304284 Apr 28 04:25:52 PM PDT 24 Apr 28 04:25:53 PM PDT 24 846086933 ps
T13 /workspace/coverage/default/0.rv_dm_cmderr_exception.1450276986 Apr 28 04:25:19 PM PDT 24 Apr 28 04:25:20 PM PDT 24 303496160 ps
T36 /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.3924748468 Apr 28 04:25:53 PM PDT 24 Apr 28 04:25:55 PM PDT 24 293798880 ps
T159 /workspace/coverage/default/47.rv_dm_alert_test.2343616900 Apr 28 04:27:27 PM PDT 24 Apr 28 04:27:29 PM PDT 24 49185439 ps
T25 /workspace/coverage/default/1.rv_dm_cmderr_exception.514965244 Apr 28 04:25:45 PM PDT 24 Apr 28 04:25:47 PM PDT 24 1313666486 ps
T22 /workspace/coverage/default/0.rv_dm_ndmreset_req.3397378740 Apr 28 04:25:28 PM PDT 24 Apr 28 04:25:31 PM PDT 24 534459223 ps
T160 /workspace/coverage/default/44.rv_dm_alert_test.1542224801 Apr 28 04:27:24 PM PDT 24 Apr 28 04:27:25 PM PDT 24 57356125 ps
T161 /workspace/coverage/default/21.rv_dm_alert_test.1353617376 Apr 28 04:27:06 PM PDT 24 Apr 28 04:27:07 PM PDT 24 53776560 ps
T149 /workspace/coverage/default/4.rv_dm_alert_test.2466496642 Apr 28 04:26:08 PM PDT 24 Apr 28 04:26:10 PM PDT 24 20507553 ps
T153 /workspace/coverage/default/41.rv_dm_alert_test.797517516 Apr 28 04:27:23 PM PDT 24 Apr 28 04:27:24 PM PDT 24 28036330 ps
T155 /workspace/coverage/default/16.rv_dm_alert_test.1511872427 Apr 28 04:26:50 PM PDT 24 Apr 28 04:26:51 PM PDT 24 91185983 ps
T37 /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.2641430841 Apr 28 04:25:50 PM PDT 24 Apr 28 04:25:52 PM PDT 24 372921443 ps
T154 /workspace/coverage/default/30.rv_dm_alert_test.3442997648 Apr 28 04:27:08 PM PDT 24 Apr 28 04:27:09 PM PDT 24 33250351 ps
T40 /workspace/coverage/default/1.rv_dm_sec_cm.3699368036 Apr 28 04:25:57 PM PDT 24 Apr 28 04:25:59 PM PDT 24 299812257 ps
T23 /workspace/coverage/default/1.rv_dm_progbuf_busy.755080345 Apr 28 04:25:51 PM PDT 24 Apr 28 04:25:53 PM PDT 24 230184247 ps
T162 /workspace/coverage/default/43.rv_dm_alert_test.3725553324 Apr 28 04:27:31 PM PDT 24 Apr 28 04:27:32 PM PDT 24 65953233 ps
T163 /workspace/coverage/default/27.rv_dm_alert_test.2578995276 Apr 28 04:27:12 PM PDT 24 Apr 28 04:27:14 PM PDT 24 19098966 ps
T28 /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.4081148940 Apr 28 04:25:56 PM PDT 24 Apr 28 04:25:57 PM PDT 24 87348472 ps
T18 /workspace/coverage/default/1.rv_dm_rom_read_access.3894812428 Apr 28 04:25:51 PM PDT 24 Apr 28 04:25:52 PM PDT 24 25577370 ps
T164 /workspace/coverage/default/37.rv_dm_alert_test.1367345500 Apr 28 04:27:23 PM PDT 24 Apr 28 04:27:24 PM PDT 24 114832355 ps
T165 /workspace/coverage/default/11.rv_dm_alert_test.1535915974 Apr 28 04:26:41 PM PDT 24 Apr 28 04:26:43 PM PDT 24 56886012 ps
T11 /workspace/coverage/default/26.rv_dm_stress_all.2777379177 Apr 28 04:27:07 PM PDT 24 Apr 28 04:27:18 PM PDT 24 7401895297 ps
T166 /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.2981919709 Apr 28 04:25:33 PM PDT 24 Apr 28 04:25:34 PM PDT 24 68571915 ps
T65 /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.1178621004 Apr 28 04:26:32 PM PDT 24 Apr 28 04:26:37 PM PDT 24 2849566727 ps
T60 /workspace/coverage/default/2.rv_dm_sec_cm.1904275599 Apr 28 04:26:02 PM PDT 24 Apr 28 04:26:05 PM PDT 24 347952843 ps
T167 /workspace/coverage/default/4.rv_dm_hart_unavail.221533064 Apr 28 04:26:07 PM PDT 24 Apr 28 04:26:09 PM PDT 24 65046535 ps
T146 /workspace/coverage/default/15.rv_dm_alert_test.3028594183 Apr 28 04:26:46 PM PDT 24 Apr 28 04:26:47 PM PDT 24 52964806 ps
T139 /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.2728647455 Apr 28 04:25:19 PM PDT 24 Apr 28 04:25:21 PM PDT 24 78450598 ps
T168 /workspace/coverage/default/14.rv_dm_alert_test.2016743165 Apr 28 04:26:47 PM PDT 24 Apr 28 04:26:48 PM PDT 24 31226979 ps
T141 /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.1771865381 Apr 28 04:25:29 PM PDT 24 Apr 28 04:25:30 PM PDT 24 31271333 ps
T10 /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.1962036937 Apr 28 04:25:54 PM PDT 24 Apr 28 04:25:56 PM PDT 24 449491101 ps
T151 /workspace/coverage/default/23.rv_dm_alert_test.1160495983 Apr 28 04:27:06 PM PDT 24 Apr 28 04:27:07 PM PDT 24 29654425 ps
T15 /workspace/coverage/default/21.rv_dm_stress_all.1454110384 Apr 28 04:27:04 PM PDT 24 Apr 28 04:27:10 PM PDT 24 4860773013 ps
T143 /workspace/coverage/default/40.rv_dm_alert_test.1673932691 Apr 28 04:27:25 PM PDT 24 Apr 28 04:27:26 PM PDT 24 81208711 ps
T12 /workspace/coverage/default/0.rv_dm_cmderr_not_supported.1497388559 Apr 28 04:25:16 PM PDT 24 Apr 28 04:25:21 PM PDT 24 2053099795 ps
T121 /workspace/coverage/default/36.rv_dm_alert_test.878965199 Apr 28 04:27:22 PM PDT 24 Apr 28 04:27:23 PM PDT 24 20508036 ps
T140 /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.3431976561 Apr 28 04:25:42 PM PDT 24 Apr 28 04:25:43 PM PDT 24 69579578 ps
T152 /workspace/coverage/default/32.rv_dm_alert_test.3923113155 Apr 28 04:27:14 PM PDT 24 Apr 28 04:27:15 PM PDT 24 27139160 ps
T156 /workspace/coverage/default/10.rv_dm_alert_test.1497085912 Apr 28 04:26:37 PM PDT 24 Apr 28 04:26:38 PM PDT 24 65973591 ps
T16 /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.3960278165 Apr 28 04:25:49 PM PDT 24 Apr 28 04:25:51 PM PDT 24 203407972 ps
T43 /workspace/coverage/default/16.rv_dm_stress_all.205203187 Apr 28 04:26:51 PM PDT 24 Apr 28 04:27:04 PM PDT 24 3536569817 ps
T29 /workspace/coverage/default/0.rv_dm_abstractcmd_status.4011937887 Apr 28 04:25:30 PM PDT 24 Apr 28 04:25:31 PM PDT 24 59021842 ps
T61 /workspace/coverage/default/0.rv_dm_sec_cm.1203393672 Apr 28 04:25:35 PM PDT 24 Apr 28 04:25:36 PM PDT 24 364280536 ps
T145 /workspace/coverage/default/38.rv_dm_alert_test.862954727 Apr 28 04:27:31 PM PDT 24 Apr 28 04:27:32 PM PDT 24 56111450 ps
T169 /workspace/coverage/default/0.rv_dm_hart_unavail.3700262584 Apr 28 04:25:19 PM PDT 24 Apr 28 04:25:20 PM PDT 24 49797870 ps
T170 /workspace/coverage/default/20.rv_dm_alert_test.2684716094 Apr 28 04:27:07 PM PDT 24 Apr 28 04:27:08 PM PDT 24 102789659 ps
T24 /workspace/coverage/default/0.rv_dm_progbuf_busy.801749342 Apr 28 04:25:33 PM PDT 24 Apr 28 04:25:35 PM PDT 24 103300384 ps
T34 /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.132231166 Apr 28 04:26:35 PM PDT 24 Apr 28 04:26:40 PM PDT 24 1336202882 ps
T157 /workspace/coverage/default/1.rv_dm_alert_test.211902147 Apr 28 04:25:55 PM PDT 24 Apr 28 04:25:56 PM PDT 24 47046439 ps
T31 /workspace/coverage/default/1.rv_dm_cmderr_busy.1177344192 Apr 28 04:25:44 PM PDT 24 Apr 28 04:25:55 PM PDT 24 2428490562 ps
T171 /workspace/coverage/default/3.rv_dm_hart_unavail.2165098098 Apr 28 04:26:04 PM PDT 24 Apr 28 04:26:06 PM PDT 24 175906301 ps
T172 /workspace/coverage/default/0.rv_dm_smoke.3763864386 Apr 28 04:25:07 PM PDT 24 Apr 28 04:25:09 PM PDT 24 297887822 ps
T173 /workspace/coverage/default/28.rv_dm_alert_test.1891316704 Apr 28 04:27:11 PM PDT 24 Apr 28 04:27:12 PM PDT 24 58497961 ps
T148 /workspace/coverage/default/19.rv_dm_alert_test.3065093176 Apr 28 04:27:00 PM PDT 24 Apr 28 04:27:02 PM PDT 24 49585910 ps
T70 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.73612903 Apr 28 12:54:54 PM PDT 24 Apr 28 12:54:56 PM PDT 24 118686415 ps
T71 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.680608269 Apr 28 12:55:05 PM PDT 24 Apr 28 12:55:06 PM PDT 24 64177350 ps
T49 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.1440046642 Apr 28 12:54:58 PM PDT 24 Apr 28 12:55:02 PM PDT 24 397116023 ps
T50 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.728431720 Apr 28 12:55:14 PM PDT 24 Apr 28 12:55:19 PM PDT 24 3386268052 ps
T53 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1043149664 Apr 28 12:54:53 PM PDT 24 Apr 28 12:56:06 PM PDT 24 6712284954 ps
T174 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1145718865 Apr 28 12:55:21 PM PDT 24 Apr 28 12:55:23 PM PDT 24 668361402 ps
T48 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.3926467293 Apr 28 12:54:58 PM PDT 24 Apr 28 12:55:00 PM PDT 24 74609570 ps
T72 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.40318675 Apr 28 12:54:58 PM PDT 24 Apr 28 12:54:59 PM PDT 24 33483889 ps
T175 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.2331115800 Apr 28 12:54:57 PM PDT 24 Apr 28 12:54:58 PM PDT 24 137114676 ps
T45 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1627132869 Apr 28 12:54:57 PM PDT 24 Apr 28 12:55:07 PM PDT 24 723685407 ps
T81 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.3793282158 Apr 28 12:54:54 PM PDT 24 Apr 28 12:54:57 PM PDT 24 61078202 ps
T176 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.579623665 Apr 28 12:54:42 PM PDT 24 Apr 28 12:54:47 PM PDT 24 853752236 ps
T177 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.336197237 Apr 28 12:54:45 PM PDT 24 Apr 28 12:54:47 PM PDT 24 18425451 ps
T178 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.122913175 Apr 28 12:54:52 PM PDT 24 Apr 28 12:54:54 PM PDT 24 317648072 ps
T46 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1220357809 Apr 28 12:54:49 PM PDT 24 Apr 28 12:54:54 PM PDT 24 1872011680 ps
T82 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.935758542 Apr 28 12:55:05 PM PDT 24 Apr 28 12:55:13 PM PDT 24 1890388309 ps
T83 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.584157342 Apr 28 12:55:18 PM PDT 24 Apr 28 12:55:23 PM PDT 24 1059417079 ps
T179 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.784584509 Apr 28 12:54:51 PM PDT 24 Apr 28 12:55:07 PM PDT 24 27595458572 ps
T180 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.1522507901 Apr 28 12:54:38 PM PDT 24 Apr 28 12:54:40 PM PDT 24 36421397 ps
T84 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.3918716754 Apr 28 12:55:06 PM PDT 24 Apr 28 12:55:08 PM PDT 24 57942350 ps
T181 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2482191698 Apr 28 12:54:41 PM PDT 24 Apr 28 12:54:43 PM PDT 24 37159232 ps
T85 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1300341857 Apr 28 12:54:53 PM PDT 24 Apr 28 12:54:58 PM PDT 24 234387286 ps
T47 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.2247620643 Apr 28 12:54:45 PM PDT 24 Apr 28 12:55:02 PM PDT 24 859148969 ps
T86 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.1197376007 Apr 28 12:54:37 PM PDT 24 Apr 28 12:54:39 PM PDT 24 201414327 ps
T182 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.180361566 Apr 28 12:55:15 PM PDT 24 Apr 28 12:55:18 PM PDT 24 1525447296 ps
T87 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2797163201 Apr 28 12:54:45 PM PDT 24 Apr 28 12:54:47 PM PDT 24 206856421 ps
T73 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.1522994954 Apr 28 12:54:54 PM PDT 24 Apr 28 12:54:57 PM PDT 24 234835126 ps
T75 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1950033857 Apr 28 12:55:19 PM PDT 24 Apr 28 12:55:23 PM PDT 24 246829793 ps
T98 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.1242335710 Apr 28 12:54:39 PM PDT 24 Apr 28 12:55:34 PM PDT 24 1465132992 ps
T115 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.343054846 Apr 28 12:55:04 PM PDT 24 Apr 28 12:55:09 PM PDT 24 804300129 ps
T93 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1769758618 Apr 28 12:55:05 PM PDT 24 Apr 28 12:55:15 PM PDT 24 528179727 ps
T66 /workspace/coverage/cover_reg_top/18.rv_dm_tap_fsm_rand_reset.3805050507 Apr 28 12:55:17 PM PDT 24 Apr 28 12:55:35 PM PDT 24 9373237505 ps
T76 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2713966833 Apr 28 12:54:48 PM PDT 24 Apr 28 12:54:53 PM PDT 24 71619066 ps
T183 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.2592007023 Apr 28 12:55:00 PM PDT 24 Apr 28 12:55:01 PM PDT 24 167486834 ps
T184 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.1298540589 Apr 28 12:55:15 PM PDT 24 Apr 28 12:55:18 PM PDT 24 406744234 ps
T77 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2935645218 Apr 28 12:54:43 PM PDT 24 Apr 28 12:54:53 PM PDT 24 4454423291 ps
T78 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.2066631026 Apr 28 12:55:07 PM PDT 24 Apr 28 12:55:11 PM PDT 24 124040865 ps
T185 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2107822629 Apr 28 12:54:45 PM PDT 24 Apr 28 12:54:46 PM PDT 24 40822322 ps
T79 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.3749557451 Apr 28 12:55:14 PM PDT 24 Apr 28 12:55:20 PM PDT 24 153869498 ps
T119 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.2866431528 Apr 28 12:54:48 PM PDT 24 Apr 28 12:54:51 PM PDT 24 150558998 ps
T107 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.754464990 Apr 28 12:54:56 PM PDT 24 Apr 28 12:54:59 PM PDT 24 79062269 ps
T80 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.2445287400 Apr 28 12:55:15 PM PDT 24 Apr 28 12:55:36 PM PDT 24 887603622 ps
T67 /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.3729867588 Apr 28 12:54:59 PM PDT 24 Apr 28 12:55:22 PM PDT 24 24467963955 ps
T108 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.682465789 Apr 28 12:54:39 PM PDT 24 Apr 28 12:54:43 PM PDT 24 596311077 ps
T186 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.4084339491 Apr 28 12:54:53 PM PDT 24 Apr 28 12:54:54 PM PDT 24 120712556 ps
T94 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.86027723 Apr 28 12:54:42 PM PDT 24 Apr 28 12:54:47 PM PDT 24 722513228 ps
T187 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.3297688023 Apr 28 12:54:44 PM PDT 24 Apr 28 12:54:48 PM PDT 24 53755854 ps
T188 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2507288475 Apr 28 12:55:14 PM PDT 24 Apr 28 12:55:19 PM PDT 24 2786534202 ps
T109 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.3208141766 Apr 28 12:55:13 PM PDT 24 Apr 28 12:55:15 PM PDT 24 243043417 ps
T189 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.4213622554 Apr 28 12:54:55 PM PDT 24 Apr 28 12:55:01 PM PDT 24 975511358 ps
T120 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.4229632201 Apr 28 12:54:54 PM PDT 24 Apr 28 12:54:57 PM PDT 24 282164060 ps
T122 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.109350406 Apr 28 12:55:15 PM PDT 24 Apr 28 12:55:18 PM PDT 24 115656697 ps
T95 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2447778100 Apr 28 12:54:44 PM PDT 24 Apr 28 12:54:47 PM PDT 24 579185292 ps
T150 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.3728944201 Apr 28 12:54:59 PM PDT 24 Apr 28 12:55:07 PM PDT 24 1475817201 ps
T125 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.3421859849 Apr 28 12:54:42 PM PDT 24 Apr 28 12:54:59 PM PDT 24 1116912809 ps
T128 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.3043127652 Apr 28 12:54:59 PM PDT 24 Apr 28 12:55:22 PM PDT 24 3308314871 ps
T137 /workspace/coverage/cover_reg_top/30.rv_dm_tap_fsm_rand_reset.736535958 Apr 28 12:55:20 PM PDT 24 Apr 28 12:55:35 PM PDT 24 6965924449 ps
T190 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.982042359 Apr 28 12:55:04 PM PDT 24 Apr 28 12:55:06 PM PDT 24 332724718 ps
T191 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.2010687708 Apr 28 12:54:37 PM PDT 24 Apr 28 12:54:42 PM PDT 24 159304563 ps
T116 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3517677172 Apr 28 12:54:51 PM PDT 24 Apr 28 12:54:58 PM PDT 24 461076432 ps
T192 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.1670139079 Apr 28 12:55:10 PM PDT 24 Apr 28 12:55:13 PM PDT 24 1083255041 ps
T193 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.1120628998 Apr 28 12:54:49 PM PDT 24 Apr 28 12:54:52 PM PDT 24 69150237 ps
T194 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.1349084261 Apr 28 12:54:46 PM PDT 24 Apr 28 12:54:48 PM PDT 24 105330003 ps
T195 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3394730526 Apr 28 12:54:49 PM PDT 24 Apr 28 12:54:51 PM PDT 24 62475992 ps
T117 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1546388060 Apr 28 12:55:02 PM PDT 24 Apr 28 12:55:07 PM PDT 24 222946771 ps
T118 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.436122732 Apr 28 12:55:13 PM PDT 24 Apr 28 12:55:22 PM PDT 24 1653078311 ps
T196 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.941283776 Apr 28 12:54:55 PM PDT 24 Apr 28 12:54:56 PM PDT 24 109689887 ps
T197 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.533100537 Apr 28 12:54:49 PM PDT 24 Apr 28 12:54:51 PM PDT 24 56069713 ps
T110 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.1040866440 Apr 28 12:55:13 PM PDT 24 Apr 28 12:55:16 PM PDT 24 220275949 ps
T198 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3359521853 Apr 28 12:55:00 PM PDT 24 Apr 28 12:55:02 PM PDT 24 313610772 ps
T111 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.572489849 Apr 28 12:55:09 PM PDT 24 Apr 28 12:55:12 PM PDT 24 108559700 ps
T99 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.305888099 Apr 28 12:54:59 PM PDT 24 Apr 28 12:55:07 PM PDT 24 835140144 ps
T199 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.977219396 Apr 28 12:55:05 PM PDT 24 Apr 28 12:55:08 PM PDT 24 307054307 ps
T200 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.2099416401 Apr 28 12:55:04 PM PDT 24 Apr 28 12:55:07 PM PDT 24 59970763 ps
T68 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3978255629 Apr 28 12:55:09 PM PDT 24 Apr 28 12:55:18 PM PDT 24 2252726720 ps
T201 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.4136629744 Apr 28 12:55:04 PM PDT 24 Apr 28 12:55:06 PM PDT 24 52479281 ps
T202 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.4130061881 Apr 28 12:55:01 PM PDT 24 Apr 28 12:55:02 PM PDT 24 92669738 ps
T203 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.4105835715 Apr 28 12:55:10 PM PDT 24 Apr 28 12:55:19 PM PDT 24 4309151929 ps
T204 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.523852185 Apr 28 12:55:14 PM PDT 24 Apr 28 12:55:17 PM PDT 24 86564663 ps
T138 /workspace/coverage/cover_reg_top/12.rv_dm_tap_fsm_rand_reset.1370525239 Apr 28 12:55:05 PM PDT 24 Apr 28 12:55:24 PM PDT 24 5014245435 ps
T123 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.982514205 Apr 28 12:55:03 PM PDT 24 Apr 28 12:55:09 PM PDT 24 209491130 ps
T205 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3170845905 Apr 28 12:54:38 PM PDT 24 Apr 28 12:54:41 PM PDT 24 73207493 ps
T96 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.1137234565 Apr 28 12:54:53 PM PDT 24 Apr 28 12:54:56 PM PDT 24 411930860 ps
T206 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.4276335662 Apr 28 12:54:49 PM PDT 24 Apr 28 12:54:53 PM PDT 24 272358925 ps
T100 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1053143485 Apr 28 12:54:50 PM PDT 24 Apr 28 12:55:22 PM PDT 24 11823079607 ps
T207 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1345416629 Apr 28 12:54:57 PM PDT 24 Apr 28 12:55:00 PM PDT 24 49701668 ps
T124 /workspace/coverage/cover_reg_top/20.rv_dm_tap_fsm_rand_reset.3606166104 Apr 28 12:55:22 PM PDT 24 Apr 28 12:56:10 PM PDT 24 12735440524 ps
T208 /workspace/coverage/cover_reg_top/11.rv_dm_tap_fsm_rand_reset.2158588664 Apr 28 12:55:04 PM PDT 24 Apr 28 12:55:36 PM PDT 24 19636140808 ps
T209 /workspace/coverage/cover_reg_top/27.rv_dm_tap_fsm_rand_reset.2400709776 Apr 28 12:55:18 PM PDT 24 Apr 28 12:56:04 PM PDT 24 13105683440 ps
T126 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.519258301 Apr 28 12:55:13 PM PDT 24 Apr 28 12:55:30 PM PDT 24 1104618353 ps
T210 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2753418893 Apr 28 12:54:48 PM PDT 24 Apr 28 12:54:52 PM PDT 24 1270618295 ps
T113 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1974625261 Apr 28 12:55:00 PM PDT 24 Apr 28 12:55:03 PM PDT 24 119100511 ps
T211 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.1301215877 Apr 28 12:55:07 PM PDT 24 Apr 28 12:55:12 PM PDT 24 67003341 ps
T131 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3607286078 Apr 28 12:55:12 PM PDT 24 Apr 28 12:55:29 PM PDT 24 788132195 ps
T212 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.978716427 Apr 28 12:55:13 PM PDT 24 Apr 28 12:55:14 PM PDT 24 190382582 ps
T213 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.1595860124 Apr 28 12:54:38 PM PDT 24 Apr 28 12:54:40 PM PDT 24 60523532 ps
T214 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1527368374 Apr 28 12:54:42 PM PDT 24 Apr 28 12:54:49 PM PDT 24 200961297 ps
T215 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.4057345696 Apr 28 12:54:58 PM PDT 24 Apr 28 12:55:00 PM PDT 24 38933595 ps
T216 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.4186977031 Apr 28 12:55:00 PM PDT 24 Apr 28 12:55:06 PM PDT 24 2764874550 ps
T101 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.771129557 Apr 28 12:54:39 PM PDT 24 Apr 28 12:54:47 PM PDT 24 884310580 ps
T217 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2041252156 Apr 28 12:54:49 PM PDT 24 Apr 28 12:55:54 PM PDT 24 19593291732 ps
T218 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.2588090528 Apr 28 12:54:50 PM PDT 24 Apr 28 12:54:52 PM PDT 24 122566136 ps
T219 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3447907823 Apr 28 12:55:04 PM PDT 24 Apr 28 12:55:07 PM PDT 24 1115302645 ps
T102 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.1430657957 Apr 28 12:55:07 PM PDT 24 Apr 28 12:55:10 PM PDT 24 224453009 ps
T220 /workspace/coverage/cover_reg_top/37.rv_dm_tap_fsm_rand_reset.2965075203 Apr 28 12:55:18 PM PDT 24 Apr 28 12:55:53 PM PDT 24 15348312380 ps
T221 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3947799598 Apr 28 12:55:14 PM PDT 24 Apr 28 12:55:15 PM PDT 24 59295264 ps
T222 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.280691381 Apr 28 12:54:59 PM PDT 24 Apr 28 12:55:01 PM PDT 24 577247914 ps
T223 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.2665171807 Apr 28 12:54:38 PM PDT 24 Apr 28 12:54:57 PM PDT 24 4389235507 ps
T224 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.578140595 Apr 28 12:55:08 PM PDT 24 Apr 28 12:55:12 PM PDT 24 538120969 ps
T225 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.478437679 Apr 28 12:55:16 PM PDT 24 Apr 28 12:55:17 PM PDT 24 28724612 ps
T226 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3847354815 Apr 28 12:55:09 PM PDT 24 Apr 28 12:55:11 PM PDT 24 59826572 ps
T227 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.4202877314 Apr 28 12:55:03 PM PDT 24 Apr 28 12:55:07 PM PDT 24 925866575 ps
T103 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2692107834 Apr 28 12:55:08 PM PDT 24 Apr 28 12:55:12 PM PDT 24 325179520 ps
T97 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.1219580296 Apr 28 12:54:39 PM PDT 24 Apr 28 12:54:43 PM PDT 24 1486386181 ps
T114 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.1929489693 Apr 28 12:54:53 PM PDT 24 Apr 28 12:55:31 PM PDT 24 30786098752 ps
T228 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.4175416897 Apr 28 12:55:10 PM PDT 24 Apr 28 12:55:12 PM PDT 24 540765160 ps
T229 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.1292806263 Apr 28 12:55:00 PM PDT 24 Apr 28 12:55:03 PM PDT 24 225615755 ps
T136 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.1801113702 Apr 28 12:54:58 PM PDT 24 Apr 28 12:55:18 PM PDT 24 3424344297 ps
T230 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3486562961 Apr 28 12:54:58 PM PDT 24 Apr 28 12:55:05 PM PDT 24 4240444314 ps
T231 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3086312204 Apr 28 12:54:40 PM PDT 24 Apr 28 12:54:42 PM PDT 24 101613803 ps
T232 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.2590737548 Apr 28 12:55:13 PM PDT 24 Apr 28 12:55:17 PM PDT 24 172764745 ps
T233 /workspace/coverage/cover_reg_top/28.rv_dm_tap_fsm_rand_reset.2813921799 Apr 28 12:55:18 PM PDT 24 Apr 28 12:56:07 PM PDT 24 15403707959 ps
T127 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.511811443 Apr 28 12:54:54 PM PDT 24 Apr 28 12:55:13 PM PDT 24 1822775401 ps
T234 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3266213986 Apr 28 12:54:44 PM PDT 24 Apr 28 12:54:46 PM PDT 24 216124587 ps
T132 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.1266260319 Apr 28 12:54:54 PM PDT 24 Apr 28 12:55:03 PM PDT 24 276171015 ps
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T238 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1795199040 Apr 28 12:54:49 PM PDT 24 Apr 28 12:55:16 PM PDT 24 11596482708 ps
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T245 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.1407332721 Apr 28 12:54:43 PM PDT 24 Apr 28 12:55:47 PM PDT 24 14829914678 ps
T246 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3867927375 Apr 28 12:54:51 PM PDT 24 Apr 28 12:54:52 PM PDT 24 35756249 ps
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T250 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.13514206 Apr 28 12:54:38 PM PDT 24 Apr 28 12:54:41 PM PDT 24 635626091 ps
T251 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1456506146 Apr 28 12:54:45 PM PDT 24 Apr 28 12:54:47 PM PDT 24 700524424 ps
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T252 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.1171856835 Apr 28 12:54:53 PM PDT 24 Apr 28 12:54:55 PM PDT 24 228460046 ps
T253 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.3989791780 Apr 28 12:54:55 PM PDT 24 Apr 28 12:54:57 PM PDT 24 26845320 ps
T254 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.1195845647 Apr 28 12:55:13 PM PDT 24 Apr 28 12:55:16 PM PDT 24 117423729 ps
T106 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2012661632 Apr 28 12:54:48 PM PDT 24 Apr 28 12:55:20 PM PDT 24 6204146800 ps
T255 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.838911090 Apr 28 12:55:03 PM PDT 24 Apr 28 12:55:09 PM PDT 24 3735609703 ps
T256 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2944810800 Apr 28 12:54:55 PM PDT 24 Apr 28 12:55:30 PM PDT 24 9581403423 ps
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