Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
79.45 93.96 82.01 87.61 73.08 82.50 98.42 38.60


Total test records in report: 310
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html
T129 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.1463867973 May 02 01:51:09 PM PDT 24 May 02 01:51:19 PM PDT 24 398474378 ps
T259 /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2447354023 May 02 01:50:59 PM PDT 24 May 02 01:51:15 PM PDT 24 26502375587 ps
T260 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3980798337 May 02 01:50:31 PM PDT 24 May 02 01:50:49 PM PDT 24 7306924448 ps
T261 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.2022303938 May 02 01:50:42 PM PDT 24 May 02 01:50:50 PM PDT 24 3887150589 ps
T70 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1848181432 May 02 01:50:32 PM PDT 24 May 02 01:50:45 PM PDT 24 7638815952 ps
T262 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.2404687313 May 02 01:50:47 PM PDT 24 May 02 01:51:10 PM PDT 24 12821478269 ps
T100 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.579808244 May 02 01:51:00 PM PDT 24 May 02 01:51:04 PM PDT 24 53860963 ps
T263 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1767472446 May 02 01:51:08 PM PDT 24 May 02 01:51:28 PM PDT 24 2553375439 ps
T264 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.4148232211 May 02 01:50:51 PM PDT 24 May 02 01:50:54 PM PDT 24 45328146 ps
T265 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2893546776 May 02 01:51:01 PM PDT 24 May 02 01:51:11 PM PDT 24 2195258408 ps
T266 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2583732083 May 02 01:50:30 PM PDT 24 May 02 01:50:32 PM PDT 24 164432923 ps
T267 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1491599402 May 02 01:50:30 PM PDT 24 May 02 01:50:35 PM PDT 24 2862444679 ps
T268 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3223521016 May 02 01:51:00 PM PDT 24 May 02 01:51:22 PM PDT 24 2035259285 ps
T269 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.2765797686 May 02 01:51:04 PM PDT 24 May 02 01:51:15 PM PDT 24 2272891252 ps
T270 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1550340814 May 02 01:50:54 PM PDT 24 May 02 01:50:59 PM PDT 24 260359648 ps
T271 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.3770100860 May 02 01:51:08 PM PDT 24 May 02 01:51:09 PM PDT 24 69707332 ps
T272 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.1714352757 May 02 01:51:02 PM PDT 24 May 02 01:51:08 PM PDT 24 291029689 ps
T273 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.4277747555 May 02 01:50:34 PM PDT 24 May 02 01:50:36 PM PDT 24 123586040 ps
T274 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.2120589692 May 02 01:50:43 PM PDT 24 May 02 01:50:46 PM PDT 24 518522592 ps
T127 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.119203814 May 02 01:50:49 PM PDT 24 May 02 01:50:59 PM PDT 24 261538499 ps
T275 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.1505016828 May 02 01:51:07 PM PDT 24 May 02 01:51:10 PM PDT 24 105215684 ps
T101 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.2415021949 May 02 01:50:45 PM PDT 24 May 02 01:50:48 PM PDT 24 46916355 ps
T276 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.1339640610 May 02 01:50:44 PM PDT 24 May 02 01:51:25 PM PDT 24 30770843447 ps
T94 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.1727639310 May 02 01:50:45 PM PDT 24 May 02 01:50:49 PM PDT 24 760350599 ps
T277 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3415222211 May 02 01:51:08 PM PDT 24 May 02 01:51:13 PM PDT 24 367940058 ps
T133 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.3425031499 May 02 01:50:29 PM PDT 24 May 02 01:50:46 PM PDT 24 1253092580 ps
T278 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.184897418 May 02 01:50:53 PM PDT 24 May 02 01:50:55 PM PDT 24 48402864 ps
T279 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1656846592 May 02 01:51:17 PM PDT 24 May 02 01:51:21 PM PDT 24 1826255458 ps
T280 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.4251818314 May 02 01:50:33 PM PDT 24 May 02 01:50:39 PM PDT 24 3248905007 ps
T281 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2738603291 May 02 01:51:20 PM PDT 24 May 02 01:51:23 PM PDT 24 210814592 ps
T282 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3915936675 May 02 01:50:59 PM PDT 24 May 02 01:51:02 PM PDT 24 59444608 ps
T283 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.2936206812 May 02 01:51:10 PM PDT 24 May 02 01:51:14 PM PDT 24 990500745 ps
T284 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.3078547057 May 02 01:51:18 PM PDT 24 May 02 01:51:30 PM PDT 24 1347368050 ps
T285 /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.3365128276 May 02 01:51:03 PM PDT 24 May 02 01:51:46 PM PDT 24 11051474138 ps
T286 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3916800068 May 02 01:50:24 PM PDT 24 May 02 01:50:26 PM PDT 24 116106393 ps
T287 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3896389118 May 02 01:50:43 PM PDT 24 May 02 01:50:45 PM PDT 24 74846872 ps
T288 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.1361355503 May 02 01:51:01 PM PDT 24 May 02 01:51:13 PM PDT 24 452590222 ps
T289 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.4143737293 May 02 01:50:29 PM PDT 24 May 02 01:50:33 PM PDT 24 252385153 ps
T290 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.1693809213 May 02 01:51:00 PM PDT 24 May 02 01:51:05 PM PDT 24 120567919 ps
T291 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1109732059 May 02 01:51:11 PM PDT 24 May 02 01:51:13 PM PDT 24 389776766 ps
T292 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.3665367166 May 02 01:51:21 PM PDT 24 May 02 01:51:25 PM PDT 24 24993849 ps
T293 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.570126286 May 02 01:51:20 PM PDT 24 May 02 01:51:26 PM PDT 24 4603915433 ps
T294 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.2054948639 May 02 01:50:32 PM PDT 24 May 02 01:51:27 PM PDT 24 1452740690 ps
T295 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.3902838469 May 02 01:51:09 PM PDT 24 May 02 01:51:12 PM PDT 24 176475138 ps
T102 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3290040107 May 02 01:50:51 PM PDT 24 May 02 01:51:00 PM PDT 24 534648062 ps
T296 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2000713359 May 02 01:50:52 PM PDT 24 May 02 01:50:55 PM PDT 24 759586847 ps
T297 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.820770539 May 02 01:50:32 PM PDT 24 May 02 01:50:36 PM PDT 24 497802315 ps
T298 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.559950690 May 02 01:50:41 PM PDT 24 May 02 01:51:47 PM PDT 24 20256343627 ps
T299 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.209332870 May 02 01:51:10 PM PDT 24 May 02 01:51:12 PM PDT 24 278921770 ps
T300 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2874551105 May 02 01:51:07 PM PDT 24 May 02 01:51:09 PM PDT 24 503557717 ps
T301 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2369887864 May 02 01:51:20 PM PDT 24 May 02 01:51:23 PM PDT 24 22201181 ps
T302 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.2081030912 May 02 01:50:44 PM PDT 24 May 02 01:50:53 PM PDT 24 418038726 ps
T303 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.561069534 May 02 01:50:50 PM PDT 24 May 02 01:50:51 PM PDT 24 86187340 ps
T304 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.651392646 May 02 01:51:12 PM PDT 24 May 02 01:51:14 PM PDT 24 109896863 ps
T305 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.3710136315 May 02 01:51:16 PM PDT 24 May 02 01:51:20 PM PDT 24 153410558 ps
T306 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2558867001 May 02 01:51:00 PM PDT 24 May 02 01:51:04 PM PDT 24 2406485772 ps
T307 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.3695346437 May 02 01:50:44 PM PDT 24 May 02 01:51:00 PM PDT 24 11209407721 ps
T308 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.857288800 May 02 01:50:51 PM PDT 24 May 02 01:51:24 PM PDT 24 8459569722 ps
T309 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.1369384517 May 02 01:50:42 PM PDT 24 May 02 01:50:53 PM PDT 24 1970111561 ps
T310 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.2224028679 May 02 01:50:49 PM PDT 24 May 02 01:51:55 PM PDT 24 5738267774 ps

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.2288791654
Short name T1
Test name
Test status
Simulation time 722439721 ps
CPU time 2.18 seconds
Started May 02 01:57:51 PM PDT 24
Finished May 02 01:57:54 PM PDT 24
Peak memory 205404 kb
Host smart-c2a230b4-2fc2-42a0-8d7e-9f09932bde11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288791654 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.2288791654
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/43.rv_dm_stress_all.1498141746
Short name T9
Test name
Test status
Simulation time 3436937963 ps
CPU time 6.27 seconds
Started May 02 01:59:17 PM PDT 24
Finished May 02 01:59:24 PM PDT 24
Peak memory 205476 kb
Host smart-2b9c0dd1-cfdd-4819-9442-63bdb729ab71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498141746 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.1498141746
Directory /workspace/43.rv_dm_stress_all/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.918733921
Short name T33
Test name
Test status
Simulation time 1897513977 ps
CPU time 4.43 seconds
Started May 02 01:58:10 PM PDT 24
Finished May 02 01:58:16 PM PDT 24
Peak memory 205432 kb
Host smart-7692a62e-a3f8-4903-b8f6-dc04ee4fb63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918733921 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.918733921
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/28.rv_dm_tap_fsm_rand_reset.1920573917
Short name T46
Test name
Test status
Simulation time 8612285645 ps
CPU time 29.41 seconds
Started May 02 01:51:19 PM PDT 24
Finished May 02 01:51:50 PM PDT 24
Peak memory 213320 kb
Host smart-aaf9d3d5-775f-4c27-9c51-f4aac48134a0
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920573917 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 28.rv_dm_tap_fsm_rand_reset.1920573917
Directory /workspace/28.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.1161296997
Short name T42
Test name
Test status
Simulation time 21048977 ps
CPU time 0.75 seconds
Started May 02 01:58:16 PM PDT 24
Finished May 02 01:58:18 PM PDT 24
Peak memory 205116 kb
Host smart-73bf7fdd-0918-4eb6-9cfb-717c7c46fcdd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161296997 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.1161296997
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.4032872783
Short name T48
Test name
Test status
Simulation time 676370648 ps
CPU time 15.72 seconds
Started May 02 01:50:51 PM PDT 24
Finished May 02 01:51:08 PM PDT 24
Peak memory 221232 kb
Host smart-9c0e326d-2509-4fa3-a02c-01290271f08a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032872783 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.4032872783
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/49.rv_dm_stress_all.560116627
Short name T24
Test name
Test status
Simulation time 27651982622 ps
CPU time 26.07 seconds
Started May 02 01:59:16 PM PDT 24
Finished May 02 01:59:44 PM PDT 24
Peak memory 205488 kb
Host smart-93ac41f9-a00e-451d-abdc-6d048c1ae09a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560116627 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.560116627
Directory /workspace/49.rv_dm_stress_all/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.2346980390
Short name T39
Test name
Test status
Simulation time 483932354 ps
CPU time 1.3 seconds
Started May 02 01:58:01 PM PDT 24
Finished May 02 01:58:04 PM PDT 24
Peak memory 229084 kb
Host smart-4b8a4fb6-3b5a-4628-81ed-a23a3c6795d9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346980390 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.2346980390
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.2442937581
Short name T50
Test name
Test status
Simulation time 1034313517 ps
CPU time 2.55 seconds
Started May 02 01:51:21 PM PDT 24
Finished May 02 01:51:25 PM PDT 24
Peak memory 213164 kb
Host smart-10ce62a8-e06b-4993-a0da-aaa91925cf64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442937581 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.2442937581
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1521589827
Short name T128
Test name
Test status
Simulation time 6508848248 ps
CPU time 20.02 seconds
Started May 02 01:50:59 PM PDT 24
Finished May 02 01:51:21 PM PDT 24
Peak memory 221408 kb
Host smart-3fafd4d7-8521-4007-b283-7a29cc29db11
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521589827 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.1521589827
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.2734762217
Short name T22
Test name
Test status
Simulation time 3695687489 ps
CPU time 1.54 seconds
Started May 02 01:57:45 PM PDT 24
Finished May 02 01:57:48 PM PDT 24
Peak memory 205508 kb
Host smart-e9ee45de-a915-4957-83d1-619fba18c106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734762217 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.2734762217
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tap_fsm_rand_reset.2384334106
Short name T67
Test name
Test status
Simulation time 13399822877 ps
CPU time 25.57 seconds
Started May 02 01:51:10 PM PDT 24
Finished May 02 01:51:37 PM PDT 24
Peak memory 221416 kb
Host smart-c960bef3-8321-4dfe-ac94-80a0897a538f
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384334106 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rv_dm_tap_fsm_rand_reset.2384334106
Directory /workspace/15.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.2002419170
Short name T29
Test name
Test status
Simulation time 166976536 ps
CPU time 0.71 seconds
Started May 02 01:57:31 PM PDT 24
Finished May 02 01:57:33 PM PDT 24
Peak memory 205140 kb
Host smart-e2f4c1a3-2c66-45a1-b102-0e37477acdea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002419170 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.2002419170
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.1044397679
Short name T18
Test name
Test status
Simulation time 32389715 ps
CPU time 0.79 seconds
Started May 02 01:57:31 PM PDT 24
Finished May 02 01:57:33 PM PDT 24
Peak memory 213344 kb
Host smart-e2cd7a3f-5b47-4a4d-bf61-7c47708df2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044397679 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.1044397679
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.252829364
Short name T81
Test name
Test status
Simulation time 726635597 ps
CPU time 16.45 seconds
Started May 02 01:51:23 PM PDT 24
Finished May 02 01:51:41 PM PDT 24
Peak memory 221204 kb
Host smart-407328ff-e845-4914-94e5-b25b33ee2116
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252829364 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.252829364
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.4122380800
Short name T98
Test name
Test status
Simulation time 28455411950 ps
CPU time 82.31 seconds
Started May 02 01:50:44 PM PDT 24
Finished May 02 01:52:08 PM PDT 24
Peak memory 213292 kb
Host smart-c58f0074-2731-402d-8c33-e6aad49a8c96
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122380800 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.4122380800
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.1072369727
Short name T14
Test name
Test status
Simulation time 579353395 ps
CPU time 2.48 seconds
Started May 02 01:57:53 PM PDT 24
Finished May 02 01:57:57 PM PDT 24
Peak memory 205300 kb
Host smart-3a2f101a-8ff7-4379-8900-5f8be2596218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072369727 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.1072369727
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.1748426827
Short name T43
Test name
Test status
Simulation time 33614290 ps
CPU time 0.71 seconds
Started May 02 01:58:46 PM PDT 24
Finished May 02 01:58:48 PM PDT 24
Peak memory 205136 kb
Host smart-a714d4f1-47c8-4f88-a142-9c96fffdb2c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748426827 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.1748426827
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.91373058
Short name T27
Test name
Test status
Simulation time 149992974 ps
CPU time 0.84 seconds
Started May 02 01:57:28 PM PDT 24
Finished May 02 01:57:30 PM PDT 24
Peak memory 205144 kb
Host smart-a453b5de-79b6-40d4-9e9e-dac74372c35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91373058 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.91373058
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2836053796
Short name T53
Test name
Test status
Simulation time 739076854 ps
CPU time 7.62 seconds
Started May 02 01:50:30 PM PDT 24
Finished May 02 01:50:38 PM PDT 24
Peak memory 204956 kb
Host smart-a872f663-1eec-4b2b-8e54-9279bfab3926
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836053796 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.2836053796
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3541335881
Short name T72
Test name
Test status
Simulation time 269232145 ps
CPU time 1.47 seconds
Started May 02 01:50:33 PM PDT 24
Finished May 02 01:50:35 PM PDT 24
Peak memory 204608 kb
Host smart-da3011f6-1fb8-4a43-82ab-5ada8847ce7c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541335881 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.3541335881
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2020249876
Short name T116
Test name
Test status
Simulation time 3105563582 ps
CPU time 19.06 seconds
Started May 02 01:51:01 PM PDT 24
Finished May 02 01:51:22 PM PDT 24
Peak memory 213184 kb
Host smart-62e6ab58-6f40-4331-813c-89b4c46f0fb7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020249876 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.2
020249876
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.3957065640
Short name T73
Test name
Test status
Simulation time 1677972841 ps
CPU time 3.79 seconds
Started May 02 01:58:16 PM PDT 24
Finished May 02 01:58:21 PM PDT 24
Peak memory 205532 kb
Host smart-e0ca3537-f4d9-4ca4-8c86-c4c981b0bf39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957065640 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.3957065640
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.3061481518
Short name T91
Test name
Test status
Simulation time 531649776 ps
CPU time 1.81 seconds
Started May 02 01:50:31 PM PDT 24
Finished May 02 01:50:33 PM PDT 24
Peak memory 204928 kb
Host smart-f463cb9d-23c6-4eea-ad81-1025d3c2b94e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061481518 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.3061481518
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.3116560067
Short name T126
Test name
Test status
Simulation time 1219200078 ps
CPU time 19 seconds
Started May 02 01:51:08 PM PDT 24
Finished May 02 01:51:28 PM PDT 24
Peak memory 220800 kb
Host smart-64324454-f912-4a38-89b1-5a5f95156d46
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116560067 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.3
116560067
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.3924111031
Short name T11
Test name
Test status
Simulation time 361425019 ps
CPU time 1.26 seconds
Started May 02 01:57:25 PM PDT 24
Finished May 02 01:57:27 PM PDT 24
Peak memory 205044 kb
Host smart-b218d9a9-ffe9-4eeb-b760-993aa4da308a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924111031 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.3924111031
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/45.rv_dm_stress_all.3556660428
Short name T16
Test name
Test status
Simulation time 3553576315 ps
CPU time 12.68 seconds
Started May 02 01:59:15 PM PDT 24
Finished May 02 01:59:29 PM PDT 24
Peak memory 205424 kb
Host smart-e680ffed-0d06-461a-98d6-10eeff89ecdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556660428 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.3556660428
Directory /workspace/45.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.4014156198
Short name T99
Test name
Test status
Simulation time 109961949 ps
CPU time 2.31 seconds
Started May 02 01:50:59 PM PDT 24
Finished May 02 01:51:03 PM PDT 24
Peak memory 212992 kb
Host smart-e3aad5c7-893b-47df-b286-c1c11fe6ccfc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014156198 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.4014156198
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.3961695140
Short name T103
Test name
Test status
Simulation time 2554891112 ps
CPU time 33.85 seconds
Started May 02 01:50:32 PM PDT 24
Finished May 02 01:51:06 PM PDT 24
Peak memory 205012 kb
Host smart-6ce9d1a2-b381-41b0-be7f-7cb38b4393a6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961695140 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.3961695140
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.2139846400
Short name T245
Test name
Test status
Simulation time 8572173370 ps
CPU time 80.7 seconds
Started May 02 01:50:24 PM PDT 24
Finished May 02 01:51:46 PM PDT 24
Peak memory 205044 kb
Host smart-504e8ddd-3d59-4d2f-ad13-13a9d51024c7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139846400 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.2139846400
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.4143737293
Short name T289
Test name
Test status
Simulation time 252385153 ps
CPU time 2.54 seconds
Started May 02 01:50:29 PM PDT 24
Finished May 02 01:50:33 PM PDT 24
Peak memory 213120 kb
Host smart-9bf3fd53-36e1-43f7-b79d-f76c6c7a8b6c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143737293 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.4143737293
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.4251818314
Short name T280
Test name
Test status
Simulation time 3248905007 ps
CPU time 4.67 seconds
Started May 02 01:50:33 PM PDT 24
Finished May 02 01:50:39 PM PDT 24
Peak memory 218484 kb
Host smart-f6fd90bb-2af9-4d40-ada3-886c601972e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251818314 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.4251818314
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.1605023483
Short name T106
Test name
Test status
Simulation time 189764241 ps
CPU time 1.47 seconds
Started May 02 01:50:29 PM PDT 24
Finished May 02 01:50:32 PM PDT 24
Peak memory 213164 kb
Host smart-bb602e61-bf69-4a07-b3ff-5d7e9e9874a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605023483 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.1605023483
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3980798337
Short name T260
Test name
Test status
Simulation time 7306924448 ps
CPU time 16.54 seconds
Started May 02 01:50:31 PM PDT 24
Finished May 02 01:50:49 PM PDT 24
Peak memory 204908 kb
Host smart-c93300fa-10d2-43f0-84bc-5ed6f5a861f9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980798337 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.3980798337
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.4185679439
Short name T224
Test name
Test status
Simulation time 261702957 ps
CPU time 1.8 seconds
Started May 02 01:50:30 PM PDT 24
Finished May 02 01:50:33 PM PDT 24
Peak memory 204880 kb
Host smart-6ec866b0-9824-4eb1-9787-6f5973232835
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185679439 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.4185679439
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.740971209
Short name T213
Test name
Test status
Simulation time 1016928023 ps
CPU time 3.61 seconds
Started May 02 01:50:31 PM PDT 24
Finished May 02 01:50:35 PM PDT 24
Peak memory 204780 kb
Host smart-412f4f70-2d1d-4bed-8609-d762ae39b5db
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740971209 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.740971209
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2583732083
Short name T266
Test name
Test status
Simulation time 164432923 ps
CPU time 0.82 seconds
Started May 02 01:50:30 PM PDT 24
Finished May 02 01:50:32 PM PDT 24
Peak memory 204576 kb
Host smart-6b04f934-190d-471d-b9ba-60c7169ca0ce
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583732083 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.2583732083
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1491599402
Short name T267
Test name
Test status
Simulation time 2862444679 ps
CPU time 3.81 seconds
Started May 02 01:50:30 PM PDT 24
Finished May 02 01:50:35 PM PDT 24
Peak memory 204848 kb
Host smart-17014939-c510-463f-881c-a8368a070d9c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491599402 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.1491599402
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3780135769
Short name T208
Test name
Test status
Simulation time 47298959 ps
CPU time 0.8 seconds
Started May 02 01:50:25 PM PDT 24
Finished May 02 01:50:27 PM PDT 24
Peak memory 204648 kb
Host smart-08b692b3-a99b-4ce7-8143-ad39829fe5a6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780135769 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.3780135769
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3916800068
Short name T286
Test name
Test status
Simulation time 116106393 ps
CPU time 0.68 seconds
Started May 02 01:50:24 PM PDT 24
Finished May 02 01:50:26 PM PDT 24
Peak memory 204624 kb
Host smart-3b7ad9b3-4678-455c-9421-3fee2efc1ea7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916800068 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.3
916800068
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.152225085
Short name T205
Test name
Test status
Simulation time 31307465 ps
CPU time 0.66 seconds
Started May 02 01:50:33 PM PDT 24
Finished May 02 01:50:35 PM PDT 24
Peak memory 204572 kb
Host smart-ddb64b77-d37d-4364-b980-6af538bc417b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152225085 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_part
ial_access.152225085
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.2678841268
Short name T186
Test name
Test status
Simulation time 85508304 ps
CPU time 0.71 seconds
Started May 02 01:50:36 PM PDT 24
Finished May 02 01:50:37 PM PDT 24
Peak memory 204584 kb
Host smart-f1a2a28c-c95a-4f11-8568-948534742d11
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678841268 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.2678841268
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.1532434174
Short name T117
Test name
Test status
Simulation time 977128657 ps
CPU time 3.94 seconds
Started May 02 01:50:30 PM PDT 24
Finished May 02 01:50:35 PM PDT 24
Peak memory 213216 kb
Host smart-532cde8b-d6ca-40b5-9733-9136256e6730
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532434174 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.1532434174
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.2237645079
Short name T130
Test name
Test status
Simulation time 7585574698 ps
CPU time 9.61 seconds
Started May 02 01:50:30 PM PDT 24
Finished May 02 01:50:41 PM PDT 24
Peak memory 213240 kb
Host smart-667ce3d5-2d85-4eed-8ab0-5c67e2e898d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237645079 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.2237645079
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.2732790277
Short name T109
Test name
Test status
Simulation time 11365134306 ps
CPU time 72.36 seconds
Started May 02 01:50:30 PM PDT 24
Finished May 02 01:51:44 PM PDT 24
Peak memory 213172 kb
Host smart-d96dadbd-01e6-4a66-b068-5a44fcdc6201
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732790277 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.2732790277
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.2054948639
Short name T294
Test name
Test status
Simulation time 1452740690 ps
CPU time 54.58 seconds
Started May 02 01:50:32 PM PDT 24
Finished May 02 01:51:27 PM PDT 24
Peak memory 204984 kb
Host smart-b022d1d9-74e2-4ca8-9ba3-340391c6a457
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054948639 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.2054948639
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.820770539
Short name T297
Test name
Test status
Simulation time 497802315 ps
CPU time 2.43 seconds
Started May 02 01:50:32 PM PDT 24
Finished May 02 01:50:36 PM PDT 24
Peak memory 213180 kb
Host smart-e0c9a1ad-2a1d-4c98-a23f-56e73bd33130
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820770539 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.820770539
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.1909051030
Short name T78
Test name
Test status
Simulation time 82027725 ps
CPU time 4.39 seconds
Started May 02 01:50:44 PM PDT 24
Finished May 02 01:50:50 PM PDT 24
Peak memory 219016 kb
Host smart-171c5e23-1ed3-4b3e-878d-7d67bd1fff4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909051030 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.1909051030
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.4277747555
Short name T273
Test name
Test status
Simulation time 123586040 ps
CPU time 1.6 seconds
Started May 02 01:50:34 PM PDT 24
Finished May 02 01:50:36 PM PDT 24
Peak memory 213164 kb
Host smart-f32e3f4d-2f9a-4319-8dfd-87c5011ee320
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277747555 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.4277747555
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1848181432
Short name T70
Test name
Test status
Simulation time 7638815952 ps
CPU time 11.39 seconds
Started May 02 01:50:32 PM PDT 24
Finished May 02 01:50:45 PM PDT 24
Peak memory 204876 kb
Host smart-2e703de3-bc3b-40c5-af6b-123c121bab68
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848181432 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.1848181432
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2771742035
Short name T177
Test name
Test status
Simulation time 11387455111 ps
CPU time 52.86 seconds
Started May 02 01:50:30 PM PDT 24
Finished May 02 01:51:23 PM PDT 24
Peak memory 204924 kb
Host smart-56b05ca9-da8a-4c46-b6bd-60992b2a01b6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771742035 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_bit_bash.2771742035
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.3629561635
Short name T175
Test name
Test status
Simulation time 1565909419 ps
CPU time 2 seconds
Started May 02 01:50:30 PM PDT 24
Finished May 02 01:50:33 PM PDT 24
Peak memory 204744 kb
Host smart-6d470750-689b-4abd-a694-a268c1be101c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629561635 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.3
629561635
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.4192961052
Short name T258
Test name
Test status
Simulation time 1260315439 ps
CPU time 1.73 seconds
Started May 02 01:50:30 PM PDT 24
Finished May 02 01:50:32 PM PDT 24
Peak memory 204816 kb
Host smart-c2769b66-9e01-4876-a7d5-ef8f37f31403
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192961052 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.4192961052
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.115287986
Short name T204
Test name
Test status
Simulation time 180757295 ps
CPU time 0.99 seconds
Started May 02 01:50:33 PM PDT 24
Finished May 02 01:50:35 PM PDT 24
Peak memory 204672 kb
Host smart-93cba682-0df2-4ab4-ac04-c5cbdcaefbdf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115287986 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_hw_reset.115287986
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3531694987
Short name T225
Test name
Test status
Simulation time 131328300 ps
CPU time 0.86 seconds
Started May 02 01:50:33 PM PDT 24
Finished May 02 01:50:35 PM PDT 24
Peak memory 204188 kb
Host smart-c84df644-f0ea-4c8f-9b9c-fd57b782a9d3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531694987 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.3
531694987
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3878833826
Short name T198
Test name
Test status
Simulation time 20006180 ps
CPU time 0.73 seconds
Started May 02 01:50:36 PM PDT 24
Finished May 02 01:50:37 PM PDT 24
Peak memory 204568 kb
Host smart-f4a34786-480c-4d8e-b4f7-6b158bc3730a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878833826 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.3878833826
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.3346803601
Short name T197
Test name
Test status
Simulation time 25832207 ps
CPU time 0.7 seconds
Started May 02 01:50:31 PM PDT 24
Finished May 02 01:50:32 PM PDT 24
Peak memory 204608 kb
Host smart-9a373d7f-eed5-4128-97ec-a83cc7d16dbc
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346803601 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.3346803601
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.923539725
Short name T96
Test name
Test status
Simulation time 157116226 ps
CPU time 6.46 seconds
Started May 02 01:50:36 PM PDT 24
Finished May 02 01:50:43 PM PDT 24
Peak memory 204884 kb
Host smart-20bfcef2-4b8a-49c9-aba1-c4bb544101ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923539725 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_c
sr_outstanding.923539725
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.2421632044
Short name T49
Test name
Test status
Simulation time 693738619 ps
CPU time 4.8 seconds
Started May 02 01:50:32 PM PDT 24
Finished May 02 01:50:38 PM PDT 24
Peak memory 213208 kb
Host smart-f7c289d6-a44d-4975-a470-8002fe813a84
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421632044 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.2421632044
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.3425031499
Short name T133
Test name
Test status
Simulation time 1253092580 ps
CPU time 16.26 seconds
Started May 02 01:50:29 PM PDT 24
Finished May 02 01:50:46 PM PDT 24
Peak memory 213056 kb
Host smart-a453f204-410c-4924-a2de-8e8122241611
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425031499 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.3425031499
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.37198232
Short name T184
Test name
Test status
Simulation time 2490927156 ps
CPU time 3.51 seconds
Started May 02 01:51:01 PM PDT 24
Finished May 02 01:51:07 PM PDT 24
Peak memory 216252 kb
Host smart-87a648d0-d2c1-4cb7-aef3-0e5bdf1f3762
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37198232 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.37198232
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2558867001
Short name T306
Test name
Test status
Simulation time 2406485772 ps
CPU time 1.82 seconds
Started May 02 01:51:00 PM PDT 24
Finished May 02 01:51:04 PM PDT 24
Peak memory 204836 kb
Host smart-9ecc44c3-2daa-4abe-80cb-5a8c3adda284
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558867001 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
2558867001
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.2492953161
Short name T201
Test name
Test status
Simulation time 89587996 ps
CPU time 0.77 seconds
Started May 02 01:51:01 PM PDT 24
Finished May 02 01:51:04 PM PDT 24
Peak memory 204624 kb
Host smart-14c1f21d-32c2-4def-b7a9-d09d930e1eb6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492953161 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
2492953161
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.4187603270
Short name T233
Test name
Test status
Simulation time 299865214 ps
CPU time 3.67 seconds
Started May 02 01:50:59 PM PDT 24
Finished May 02 01:51:04 PM PDT 24
Peak memory 204916 kb
Host smart-e92f1531-d0d3-4488-aa09-a5556b7097b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187603270 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same
_csr_outstanding.4187603270
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tap_fsm_rand_reset.1424453288
Short name T242
Test name
Test status
Simulation time 11421847719 ps
CPU time 11.26 seconds
Started May 02 01:50:59 PM PDT 24
Finished May 02 01:51:13 PM PDT 24
Peak memory 220336 kb
Host smart-717ce51f-b762-42b8-8acb-2d64dc81f5f6
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424453288 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rv_dm_tap_fsm_rand_reset.1424453288
Directory /workspace/10.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.861626045
Short name T235
Test name
Test status
Simulation time 225749824 ps
CPU time 5.21 seconds
Started May 02 01:51:00 PM PDT 24
Finished May 02 01:51:07 PM PDT 24
Peak memory 213180 kb
Host smart-a0ccf8ca-79ae-42c9-b891-34762ccb2aa0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861626045 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.861626045
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1521602669
Short name T79
Test name
Test status
Simulation time 4069885835 ps
CPU time 6.44 seconds
Started May 02 01:51:01 PM PDT 24
Finished May 02 01:51:10 PM PDT 24
Peak memory 218592 kb
Host smart-05cc8d1c-180d-40b6-b12e-97597a388bf7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521602669 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.1521602669
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.3991712970
Short name T85
Test name
Test status
Simulation time 79487356 ps
CPU time 1.39 seconds
Started May 02 01:50:58 PM PDT 24
Finished May 02 01:51:01 PM PDT 24
Peak memory 217652 kb
Host smart-a6eaa39c-628f-4c93-ab89-f388bcc3df0c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991712970 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.3991712970
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.479577139
Short name T180
Test name
Test status
Simulation time 376421976 ps
CPU time 1.97 seconds
Started May 02 01:50:58 PM PDT 24
Finished May 02 01:51:02 PM PDT 24
Peak memory 204864 kb
Host smart-8370da90-a1fb-47ae-9e48-8aa6aee47985
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479577139 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.479577139
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3915936675
Short name T282
Test name
Test status
Simulation time 59444608 ps
CPU time 0.81 seconds
Started May 02 01:50:59 PM PDT 24
Finished May 02 01:51:02 PM PDT 24
Peak memory 204620 kb
Host smart-2fe212c4-6ff5-485d-9151-bcfc0a322443
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915936675 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.
3915936675
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.3980894363
Short name T83
Test name
Test status
Simulation time 240664812 ps
CPU time 6.6 seconds
Started May 02 01:51:00 PM PDT 24
Finished May 02 01:51:09 PM PDT 24
Peak memory 204876 kb
Host smart-4a388f7f-a5a0-41d4-b462-c11b91558e02
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980894363 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same
_csr_outstanding.3980894363
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.671427772
Short name T82
Test name
Test status
Simulation time 139472612 ps
CPU time 3.14 seconds
Started May 02 01:50:58 PM PDT 24
Finished May 02 01:51:02 PM PDT 24
Peak memory 213100 kb
Host smart-6ca3cb26-8d99-42c1-86b8-64178e1c1ae0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671427772 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.671427772
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.2765797686
Short name T269
Test name
Test status
Simulation time 2272891252 ps
CPU time 9.85 seconds
Started May 02 01:51:04 PM PDT 24
Finished May 02 01:51:15 PM PDT 24
Peak memory 213168 kb
Host smart-b0d06e09-8411-4ecb-b456-37a25def4ea1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765797686 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.2
765797686
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.2637476330
Short name T80
Test name
Test status
Simulation time 4694314467 ps
CPU time 6.71 seconds
Started May 02 01:51:09 PM PDT 24
Finished May 02 01:51:17 PM PDT 24
Peak memory 220464 kb
Host smart-846232d0-8678-449f-a84e-54719a726979
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637476330 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.2637476330
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.3546939076
Short name T237
Test name
Test status
Simulation time 70824940 ps
CPU time 2.2 seconds
Started May 02 01:51:01 PM PDT 24
Finished May 02 01:51:06 PM PDT 24
Peak memory 213172 kb
Host smart-6efc6910-60f9-46b9-893c-39a91698a77e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546939076 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.3546939076
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1584001027
Short name T179
Test name
Test status
Simulation time 497398142 ps
CPU time 1.5 seconds
Started May 02 01:51:00 PM PDT 24
Finished May 02 01:51:03 PM PDT 24
Peak memory 204748 kb
Host smart-84434c20-291e-4872-b2f5-d3d1f5e52b76
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584001027 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
1584001027
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.392965945
Short name T228
Test name
Test status
Simulation time 61470062 ps
CPU time 0.82 seconds
Started May 02 01:51:01 PM PDT 24
Finished May 02 01:51:04 PM PDT 24
Peak memory 204544 kb
Host smart-102a57a1-4e49-4c20-8077-90396f2c63ce
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392965945 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.392965945
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1738795548
Short name T227
Test name
Test status
Simulation time 288718670 ps
CPU time 3.52 seconds
Started May 02 01:50:58 PM PDT 24
Finished May 02 01:51:03 PM PDT 24
Peak memory 204884 kb
Host smart-007f1c65-a54e-43c7-83d7-043b529693fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738795548 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.1738795548
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tap_fsm_rand_reset.549814064
Short name T148
Test name
Test status
Simulation time 17674503308 ps
CPU time 28.94 seconds
Started May 02 01:51:03 PM PDT 24
Finished May 02 01:51:33 PM PDT 24
Peak memory 229548 kb
Host smart-395e621d-e527-4dfd-8517-a8f3d92ffc42
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549814064 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.rv_dm_tap_fsm_rand_reset.549814064
Directory /workspace/12.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.1714352757
Short name T272
Test name
Test status
Simulation time 291029689 ps
CPU time 4.52 seconds
Started May 02 01:51:02 PM PDT 24
Finished May 02 01:51:08 PM PDT 24
Peak memory 213280 kb
Host smart-de559e41-d600-409b-85c0-e00f8b0ba879
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714352757 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.1714352757
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3223521016
Short name T268
Test name
Test status
Simulation time 2035259285 ps
CPU time 20.15 seconds
Started May 02 01:51:00 PM PDT 24
Finished May 02 01:51:22 PM PDT 24
Peak memory 221260 kb
Host smart-8c5b3e71-d297-4ef2-82e1-2db4f33a2254
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223521016 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.3
223521016
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.4233219104
Short name T212
Test name
Test status
Simulation time 2183617693 ps
CPU time 4.76 seconds
Started May 02 01:51:12 PM PDT 24
Finished May 02 01:51:18 PM PDT 24
Peak memory 218352 kb
Host smart-8c24ece7-6b4b-4afe-ad76-c38e64554544
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233219104 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.4233219104
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.3902838469
Short name T295
Test name
Test status
Simulation time 176475138 ps
CPU time 2.36 seconds
Started May 02 01:51:09 PM PDT 24
Finished May 02 01:51:12 PM PDT 24
Peak memory 213188 kb
Host smart-02ade41a-b8c4-431c-8cf6-407f7424e823
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902838469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.3902838469
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.3531522596
Short name T176
Test name
Test status
Simulation time 469278876 ps
CPU time 2.35 seconds
Started May 02 01:51:09 PM PDT 24
Finished May 02 01:51:12 PM PDT 24
Peak memory 204812 kb
Host smart-244f7813-f03b-4204-8545-bed550ff3c83
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531522596 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
3531522596
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2548523782
Short name T222
Test name
Test status
Simulation time 26641361 ps
CPU time 0.73 seconds
Started May 02 01:51:11 PM PDT 24
Finished May 02 01:51:13 PM PDT 24
Peak memory 204596 kb
Host smart-4ce89ee5-4692-4de9-a01b-e267628f8fe9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548523782 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
2548523782
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.890974405
Short name T51
Test name
Test status
Simulation time 311672282 ps
CPU time 4.19 seconds
Started May 02 01:51:10 PM PDT 24
Finished May 02 01:51:15 PM PDT 24
Peak memory 204884 kb
Host smart-999c1ae4-c67c-4a3d-8341-6f58d45833f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890974405 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same_
csr_outstanding.890974405
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.3898275422
Short name T75
Test name
Test status
Simulation time 3267086876 ps
CPU time 5.24 seconds
Started May 02 01:51:07 PM PDT 24
Finished May 02 01:51:13 PM PDT 24
Peak memory 213304 kb
Host smart-b4951d9c-8b07-47b3-8b19-c535fc1c1c03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898275422 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.3898275422
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1767472446
Short name T263
Test name
Test status
Simulation time 2553375439 ps
CPU time 19.69 seconds
Started May 02 01:51:08 PM PDT 24
Finished May 02 01:51:28 PM PDT 24
Peak memory 213148 kb
Host smart-b49ff5bf-94cf-485e-92af-3341ad08132d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767472446 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.1
767472446
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.1505016828
Short name T275
Test name
Test status
Simulation time 105215684 ps
CPU time 2.41 seconds
Started May 02 01:51:07 PM PDT 24
Finished May 02 01:51:10 PM PDT 24
Peak memory 213192 kb
Host smart-27676271-5318-475d-a665-e77c798723fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505016828 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.1505016828
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.949637766
Short name T218
Test name
Test status
Simulation time 90347249 ps
CPU time 1.64 seconds
Started May 02 01:51:10 PM PDT 24
Finished May 02 01:51:13 PM PDT 24
Peak memory 213100 kb
Host smart-2f4e19d7-dbc0-4a51-be47-f0f8f951f827
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949637766 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.949637766
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1109732059
Short name T291
Test name
Test status
Simulation time 389776766 ps
CPU time 1.71 seconds
Started May 02 01:51:11 PM PDT 24
Finished May 02 01:51:13 PM PDT 24
Peak memory 204784 kb
Host smart-31882727-5a28-4c63-8305-5fb532be4f2c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109732059 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
1109732059
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.3770100860
Short name T271
Test name
Test status
Simulation time 69707332 ps
CPU time 0.71 seconds
Started May 02 01:51:08 PM PDT 24
Finished May 02 01:51:09 PM PDT 24
Peak memory 204604 kb
Host smart-66a98f4e-3d8e-4bd7-af00-345812b92dd6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770100860 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
3770100860
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.338503489
Short name T112
Test name
Test status
Simulation time 521136244 ps
CPU time 7.65 seconds
Started May 02 01:51:09 PM PDT 24
Finished May 02 01:51:18 PM PDT 24
Peak memory 204888 kb
Host smart-df255c29-a96a-4623-8472-669a4bd1a099
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338503489 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same_
csr_outstanding.338503489
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.2223233907
Short name T187
Test name
Test status
Simulation time 276501541 ps
CPU time 6.29 seconds
Started May 02 01:51:11 PM PDT 24
Finished May 02 01:51:19 PM PDT 24
Peak memory 213252 kb
Host smart-e3096a4a-e5b7-4dec-99b3-896896ee7501
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223233907 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.2223233907
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3746330513
Short name T132
Test name
Test status
Simulation time 1319649749 ps
CPU time 10.1 seconds
Started May 02 01:51:08 PM PDT 24
Finished May 02 01:51:19 PM PDT 24
Peak memory 213032 kb
Host smart-ee079327-73f3-4308-9f95-7aa4ed24e9f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746330513 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.3
746330513
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.561572419
Short name T202
Test name
Test status
Simulation time 1071055134 ps
CPU time 3.31 seconds
Started May 02 01:51:07 PM PDT 24
Finished May 02 01:51:11 PM PDT 24
Peak memory 213220 kb
Host smart-4e5cb640-2e4f-4718-a58b-dc26866174bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561572419 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.561572419
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.197472126
Short name T104
Test name
Test status
Simulation time 28798644 ps
CPU time 1.45 seconds
Started May 02 01:51:10 PM PDT 24
Finished May 02 01:51:13 PM PDT 24
Peak memory 221236 kb
Host smart-f30294a5-28d2-4690-8b49-133d2895d817
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197472126 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.197472126
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.209332870
Short name T299
Test name
Test status
Simulation time 278921770 ps
CPU time 1.13 seconds
Started May 02 01:51:10 PM PDT 24
Finished May 02 01:51:12 PM PDT 24
Peak memory 204808 kb
Host smart-56c16252-de58-4478-abb2-56b11e8b4dc9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209332870 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.209332870
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.651392646
Short name T304
Test name
Test status
Simulation time 109896863 ps
CPU time 0.73 seconds
Started May 02 01:51:12 PM PDT 24
Finished May 02 01:51:14 PM PDT 24
Peak memory 204564 kb
Host smart-379f6978-a75e-42eb-bf31-94e189cc7121
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651392646 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.651392646
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.1938398288
Short name T214
Test name
Test status
Simulation time 217483079 ps
CPU time 4.21 seconds
Started May 02 01:51:10 PM PDT 24
Finished May 02 01:51:15 PM PDT 24
Peak memory 204920 kb
Host smart-9c9d2cf2-0529-4244-83a3-9ae4ea47ce78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938398288 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.1938398288
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.4124870354
Short name T125
Test name
Test status
Simulation time 476811569 ps
CPU time 6.45 seconds
Started May 02 01:51:11 PM PDT 24
Finished May 02 01:51:19 PM PDT 24
Peak memory 213180 kb
Host smart-de624b5c-4341-44d0-b6a0-db408c30bd35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124870354 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.4124870354
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.1463867973
Short name T129
Test name
Test status
Simulation time 398474378 ps
CPU time 8.95 seconds
Started May 02 01:51:09 PM PDT 24
Finished May 02 01:51:19 PM PDT 24
Peak memory 213144 kb
Host smart-2c1113c2-d6cc-453b-a4b7-e10f8f19117d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463867973 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.1
463867973
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.1945317759
Short name T215
Test name
Test status
Simulation time 1088313060 ps
CPU time 4.79 seconds
Started May 02 01:51:09 PM PDT 24
Finished May 02 01:51:15 PM PDT 24
Peak memory 217832 kb
Host smart-03f5bac8-7875-41c9-8336-4a8163535952
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945317759 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.1945317759
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.2936206812
Short name T283
Test name
Test status
Simulation time 990500745 ps
CPU time 2.48 seconds
Started May 02 01:51:10 PM PDT 24
Finished May 02 01:51:14 PM PDT 24
Peak memory 218524 kb
Host smart-85a41145-46db-41b5-9116-b143708882b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936206812 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.2936206812
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2874551105
Short name T300
Test name
Test status
Simulation time 503557717 ps
CPU time 1.03 seconds
Started May 02 01:51:07 PM PDT 24
Finished May 02 01:51:09 PM PDT 24
Peak memory 204704 kb
Host smart-747d3d24-e792-4503-8b0e-746312e3f4e9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874551105 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
2874551105
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.209911091
Short name T219
Test name
Test status
Simulation time 44548535 ps
CPU time 0.75 seconds
Started May 02 01:51:09 PM PDT 24
Finished May 02 01:51:11 PM PDT 24
Peak memory 204592 kb
Host smart-b7f18967-3f97-45ae-b567-30902ce18291
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209911091 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.209911091
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3415222211
Short name T277
Test name
Test status
Simulation time 367940058 ps
CPU time 3.46 seconds
Started May 02 01:51:08 PM PDT 24
Finished May 02 01:51:13 PM PDT 24
Peak memory 204312 kb
Host smart-b0d7c3ce-758b-4db7-af5d-5bde87fd5903
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415222211 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.3415222211
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.1421028395
Short name T203
Test name
Test status
Simulation time 147025227 ps
CPU time 2.59 seconds
Started May 02 01:51:10 PM PDT 24
Finished May 02 01:51:13 PM PDT 24
Peak memory 213216 kb
Host smart-566e1afa-62ea-4c45-9b56-2ac346282c10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421028395 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.1421028395
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.1557386095
Short name T234
Test name
Test status
Simulation time 271244234 ps
CPU time 2.24 seconds
Started May 02 01:51:18 PM PDT 24
Finished May 02 01:51:21 PM PDT 24
Peak memory 215484 kb
Host smart-ae898e97-5ca0-4cbb-a3b0-26577c2ccac5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557386095 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.1557386095
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.4271675756
Short name T252
Test name
Test status
Simulation time 2263494025 ps
CPU time 3.63 seconds
Started May 02 01:51:19 PM PDT 24
Finished May 02 01:51:25 PM PDT 24
Peak memory 204860 kb
Host smart-c6b14386-d82f-46f0-a594-73677b8d644a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271675756 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
4271675756
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.967768851
Short name T257
Test name
Test status
Simulation time 73734309 ps
CPU time 0.84 seconds
Started May 02 01:51:08 PM PDT 24
Finished May 02 01:51:09 PM PDT 24
Peak memory 204532 kb
Host smart-644dfb26-2e72-4e68-810c-56765558d259
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967768851 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.967768851
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3307214231
Short name T246
Test name
Test status
Simulation time 824325818 ps
CPU time 4.56 seconds
Started May 02 01:51:23 PM PDT 24
Finished May 02 01:51:29 PM PDT 24
Peak memory 204896 kb
Host smart-a3e01a97-c4eb-4732-a65b-d913859767df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307214231 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.3307214231
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.245420539
Short name T183
Test name
Test status
Simulation time 190760255 ps
CPU time 2.85 seconds
Started May 02 01:51:20 PM PDT 24
Finished May 02 01:51:25 PM PDT 24
Peak memory 213192 kb
Host smart-d7a583ee-fa3f-4881-8afb-d60e2ebf48e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245420539 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.245420539
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.3078547057
Short name T284
Test name
Test status
Simulation time 1347368050 ps
CPU time 10.37 seconds
Started May 02 01:51:18 PM PDT 24
Finished May 02 01:51:30 PM PDT 24
Peak memory 213096 kb
Host smart-5fdbb8a9-7020-4534-bb8a-a641d5929426
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078547057 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.3
078547057
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2924209187
Short name T206
Test name
Test status
Simulation time 56119083 ps
CPU time 2.4 seconds
Started May 02 01:51:19 PM PDT 24
Finished May 02 01:51:23 PM PDT 24
Peak memory 216748 kb
Host smart-cf8315f4-8690-4478-90a3-e47a30872c5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924209187 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.2924209187
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.3665367166
Short name T292
Test name
Test status
Simulation time 24993849 ps
CPU time 1.51 seconds
Started May 02 01:51:21 PM PDT 24
Finished May 02 01:51:25 PM PDT 24
Peak memory 213164 kb
Host smart-a971a77d-a476-4c58-952f-c10fa264403b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665367166 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.3665367166
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1656846592
Short name T279
Test name
Test status
Simulation time 1826255458 ps
CPU time 2.34 seconds
Started May 02 01:51:17 PM PDT 24
Finished May 02 01:51:21 PM PDT 24
Peak memory 204788 kb
Host smart-39b67cee-d7a7-4cb0-8646-fdc79c6a6ee5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656846592 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
1656846592
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.1750709232
Short name T232
Test name
Test status
Simulation time 54799178 ps
CPU time 0.7 seconds
Started May 02 01:51:18 PM PDT 24
Finished May 02 01:51:20 PM PDT 24
Peak memory 204536 kb
Host smart-f0d5a17c-a594-495d-af55-1fce8e0a2039
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750709232 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
1750709232
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.2791167916
Short name T97
Test name
Test status
Simulation time 422297287 ps
CPU time 7.17 seconds
Started May 02 01:51:19 PM PDT 24
Finished May 02 01:51:28 PM PDT 24
Peak memory 204912 kb
Host smart-01bbf651-4cd2-4934-8c82-43ef2cb8161c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791167916 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.2791167916
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tap_fsm_rand_reset.1063197909
Short name T216
Test name
Test status
Simulation time 13659013418 ps
CPU time 14.29 seconds
Started May 02 01:51:22 PM PDT 24
Finished May 02 01:51:38 PM PDT 24
Peak memory 214420 kb
Host smart-a5ac3688-2dee-402c-aa8b-b2dcbfaa78f1
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063197909 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rv_dm_tap_fsm_rand_reset.1063197909
Directory /workspace/18.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.3710136315
Short name T305
Test name
Test status
Simulation time 153410558 ps
CPU time 2.9 seconds
Started May 02 01:51:16 PM PDT 24
Finished May 02 01:51:20 PM PDT 24
Peak memory 213132 kb
Host smart-d64a2ea0-554e-45a4-a46c-937e6cb97771
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710136315 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.3710136315
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.2160208672
Short name T122
Test name
Test status
Simulation time 984762567 ps
CPU time 15.37 seconds
Started May 02 01:51:20 PM PDT 24
Finished May 02 01:51:37 PM PDT 24
Peak memory 213844 kb
Host smart-2c55e210-09d3-443e-b2e5-35163079478b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160208672 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.2
160208672
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.570126286
Short name T293
Test name
Test status
Simulation time 4603915433 ps
CPU time 3.16 seconds
Started May 02 01:51:20 PM PDT 24
Finished May 02 01:51:26 PM PDT 24
Peak memory 215980 kb
Host smart-b4af4c1f-e92a-4ba8-9197-cee22f6687bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570126286 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.570126286
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.2029123925
Short name T87
Test name
Test status
Simulation time 253250939 ps
CPU time 1.53 seconds
Started May 02 01:51:19 PM PDT 24
Finished May 02 01:51:22 PM PDT 24
Peak memory 213064 kb
Host smart-bb89156e-d0e5-48ab-b901-626eee2ae47c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029123925 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.2029123925
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2738603291
Short name T281
Test name
Test status
Simulation time 210814592 ps
CPU time 1.07 seconds
Started May 02 01:51:20 PM PDT 24
Finished May 02 01:51:23 PM PDT 24
Peak memory 204816 kb
Host smart-6bfe6a0c-558b-4578-b328-704c3a7374fb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738603291 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
2738603291
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2369887864
Short name T301
Test name
Test status
Simulation time 22201181 ps
CPU time 0.74 seconds
Started May 02 01:51:20 PM PDT 24
Finished May 02 01:51:23 PM PDT 24
Peak memory 204564 kb
Host smart-7c75dd6f-4943-4ff5-8216-589e44d5a0a1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369887864 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
2369887864
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.514539727
Short name T110
Test name
Test status
Simulation time 521698502 ps
CPU time 3.67 seconds
Started May 02 01:51:17 PM PDT 24
Finished May 02 01:51:21 PM PDT 24
Peak memory 204892 kb
Host smart-da3ca0ce-6ab5-4c59-abc9-d76d369d95d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514539727 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same_
csr_outstanding.514539727
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tap_fsm_rand_reset.787587515
Short name T135
Test name
Test status
Simulation time 6398266122 ps
CPU time 21.98 seconds
Started May 02 01:51:20 PM PDT 24
Finished May 02 01:51:44 PM PDT 24
Peak memory 214936 kb
Host smart-f3e0ab83-58d7-47f6-9e07-7c5b679e000c
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787587515 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.rv_dm_tap_fsm_rand_reset.787587515
Directory /workspace/19.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3619350498
Short name T229
Test name
Test status
Simulation time 56039068 ps
CPU time 3.01 seconds
Started May 02 01:51:18 PM PDT 24
Finished May 02 01:51:23 PM PDT 24
Peak memory 213144 kb
Host smart-e6a503f5-0b2f-4879-bff0-489d34d10fd9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619350498 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.3619350498
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.1642720340
Short name T238
Test name
Test status
Simulation time 1747679236 ps
CPU time 33.15 seconds
Started May 02 01:50:45 PM PDT 24
Finished May 02 01:51:19 PM PDT 24
Peak memory 204832 kb
Host smart-9eb30f30-58a9-42ce-bcc3-bf716ee023fa
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642720340 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.1642720340
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.1339640610
Short name T276
Test name
Test status
Simulation time 30770843447 ps
CPU time 39.04 seconds
Started May 02 01:50:44 PM PDT 24
Finished May 02 01:51:25 PM PDT 24
Peak memory 205028 kb
Host smart-2c2f8db8-a422-4ea2-a3bc-eaeda930f1bd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339640610 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.1339640610
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3692269237
Short name T86
Test name
Test status
Simulation time 444144958 ps
CPU time 2.47 seconds
Started May 02 01:50:46 PM PDT 24
Finished May 02 01:50:50 PM PDT 24
Peak memory 213100 kb
Host smart-db057e3e-b6e1-450e-9b60-2721ffbd83b4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692269237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.3692269237
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.62414307
Short name T194
Test name
Test status
Simulation time 58327161 ps
CPU time 3.68 seconds
Started May 02 01:50:43 PM PDT 24
Finished May 02 01:50:48 PM PDT 24
Peak memory 218980 kb
Host smart-ab74f2a5-d044-46a3-905a-a424634d981d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62414307 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.62414307
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.2415021949
Short name T101
Test name
Test status
Simulation time 46916355 ps
CPU time 2.29 seconds
Started May 02 01:50:45 PM PDT 24
Finished May 02 01:50:48 PM PDT 24
Peak memory 213076 kb
Host smart-db76a555-4d33-483b-adcc-682cee5a1bf3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415021949 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.2415021949
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.3563527354
Short name T248
Test name
Test status
Simulation time 12410466417 ps
CPU time 38.5 seconds
Started May 02 01:50:41 PM PDT 24
Finished May 02 01:51:21 PM PDT 24
Peak memory 205016 kb
Host smart-47f7cbab-83e4-4aa3-9137-4eaae62658c7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563527354 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.3563527354
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.534292530
Short name T210
Test name
Test status
Simulation time 15858700644 ps
CPU time 35.18 seconds
Started May 02 01:50:43 PM PDT 24
Finished May 02 01:51:19 PM PDT 24
Peak memory 204916 kb
Host smart-449a015b-101b-4d0b-855e-1532085d7def
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534292530 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr
_bit_bash.534292530
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.4034464534
Short name T93
Test name
Test status
Simulation time 1832719858 ps
CPU time 6.09 seconds
Started May 02 01:50:45 PM PDT 24
Finished May 02 01:50:52 PM PDT 24
Peak memory 204892 kb
Host smart-4456f14b-26a4-4069-b718-3b4aa7c60613
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034464534 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.4034464534
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1612527181
Short name T217
Test name
Test status
Simulation time 603306993 ps
CPU time 1.35 seconds
Started May 02 01:50:46 PM PDT 24
Finished May 02 01:50:48 PM PDT 24
Peak memory 204728 kb
Host smart-efba8515-5224-4952-b7ea-41058663a6e9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612527181 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.1
612527181
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3648875598
Short name T236
Test name
Test status
Simulation time 41935013 ps
CPU time 0.83 seconds
Started May 02 01:50:45 PM PDT 24
Finished May 02 01:50:47 PM PDT 24
Peak memory 204548 kb
Host smart-7aa3ae45-a048-483b-baa3-75da64d391a1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648875598 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_aliasing.3648875598
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.2022303938
Short name T261
Test name
Test status
Simulation time 3887150589 ps
CPU time 7.41 seconds
Started May 02 01:50:42 PM PDT 24
Finished May 02 01:50:50 PM PDT 24
Peak memory 204756 kb
Host smart-5e85d8f6-603c-46a6-8e46-0ed0b6526bde
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022303938 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.2022303938
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3896389118
Short name T287
Test name
Test status
Simulation time 74846872 ps
CPU time 0.69 seconds
Started May 02 01:50:43 PM PDT 24
Finished May 02 01:50:45 PM PDT 24
Peak memory 204664 kb
Host smart-2109c63d-472c-4c47-8d72-1204dbf51e11
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896389118 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.3896389118
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2833423250
Short name T220
Test name
Test status
Simulation time 72400420 ps
CPU time 0.75 seconds
Started May 02 01:50:43 PM PDT 24
Finished May 02 01:50:44 PM PDT 24
Peak memory 204600 kb
Host smart-4d7d7e26-99b0-4d62-b1cd-3ef5c9ae99b4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833423250 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.2
833423250
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2540604246
Short name T178
Test name
Test status
Simulation time 28366134 ps
CPU time 0.72 seconds
Started May 02 01:50:44 PM PDT 24
Finished May 02 01:50:46 PM PDT 24
Peak memory 204572 kb
Host smart-af63799b-fbcb-4cf3-8e83-0dfd0c91d170
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540604246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.2540604246
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.3673589759
Short name T191
Test name
Test status
Simulation time 137878030 ps
CPU time 0.71 seconds
Started May 02 01:50:45 PM PDT 24
Finished May 02 01:50:46 PM PDT 24
Peak memory 204564 kb
Host smart-29804e46-9aa9-4c5b-93ff-c50fb0897671
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673589759 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.3673589759
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.2081030912
Short name T302
Test name
Test status
Simulation time 418038726 ps
CPU time 7.55 seconds
Started May 02 01:50:44 PM PDT 24
Finished May 02 01:50:53 PM PDT 24
Peak memory 204856 kb
Host smart-9ad926fb-e774-42b8-ae90-811fa98c9e19
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081030912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.2081030912
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.2329675828
Short name T114
Test name
Test status
Simulation time 784228018 ps
CPU time 4.66 seconds
Started May 02 01:50:46 PM PDT 24
Finished May 02 01:50:52 PM PDT 24
Peak memory 213212 kb
Host smart-9f6e574d-aa0c-4e16-a467-2221972a8dc2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329675828 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.2329675828
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.1369384517
Short name T309
Test name
Test status
Simulation time 1970111561 ps
CPU time 9.73 seconds
Started May 02 01:50:42 PM PDT 24
Finished May 02 01:50:53 PM PDT 24
Peak memory 213160 kb
Host smart-f03faff4-60d7-47b9-b178-cd08419df842
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369384517 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.1369384517
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/23.rv_dm_tap_fsm_rand_reset.2840181840
Short name T121
Test name
Test status
Simulation time 16557259410 ps
CPU time 15.13 seconds
Started May 02 01:51:19 PM PDT 24
Finished May 02 01:51:36 PM PDT 24
Peak memory 221240 kb
Host smart-9c662aec-e5fb-45ab-8cfa-e48f5cbc5004
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840181840 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 23.rv_dm_tap_fsm_rand_reset.2840181840
Directory /workspace/23.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/24.rv_dm_tap_fsm_rand_reset.2909901033
Short name T209
Test name
Test status
Simulation time 14139623572 ps
CPU time 32.4 seconds
Started May 02 01:51:21 PM PDT 24
Finished May 02 01:51:56 PM PDT 24
Peak memory 221456 kb
Host smart-9347c951-9621-4dc4-9483-139ff5109d6a
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909901033 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 24.rv_dm_tap_fsm_rand_reset.2909901033
Directory /workspace/24.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/29.rv_dm_tap_fsm_rand_reset.2563260591
Short name T136
Test name
Test status
Simulation time 6799804554 ps
CPU time 14.51 seconds
Started May 02 01:51:21 PM PDT 24
Finished May 02 01:51:38 PM PDT 24
Peak memory 220408 kb
Host smart-01203a47-b631-4bc4-b671-6d6bcd88b1b3
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563260591 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 29.rv_dm_tap_fsm_rand_reset.2563260591
Directory /workspace/29.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.559950690
Short name T298
Test name
Test status
Simulation time 20256343627 ps
CPU time 64.9 seconds
Started May 02 01:50:41 PM PDT 24
Finished May 02 01:51:47 PM PDT 24
Peak memory 205116 kb
Host smart-5399239c-af1f-4ff1-8220-0a067dd0cdf2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559950690 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.559950690
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.2404337480
Short name T107
Test name
Test status
Simulation time 50801507 ps
CPU time 2.15 seconds
Started May 02 01:50:41 PM PDT 24
Finished May 02 01:50:44 PM PDT 24
Peak memory 213084 kb
Host smart-7945e2c3-644e-4842-b1c5-c8ae65890d11
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404337480 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.2404337480
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.2125961131
Short name T115
Test name
Test status
Simulation time 257469155 ps
CPU time 2.26 seconds
Started May 02 01:50:45 PM PDT 24
Finished May 02 01:50:49 PM PDT 24
Peak memory 217044 kb
Host smart-69d2bca9-0146-4f00-b434-e246e4e04d0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125961131 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.2125961131
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.4149884943
Short name T88
Test name
Test status
Simulation time 218843838 ps
CPU time 1.58 seconds
Started May 02 01:50:43 PM PDT 24
Finished May 02 01:50:46 PM PDT 24
Peak memory 213104 kb
Host smart-efb8da24-31de-4fca-9f63-aec54f738f82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149884943 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.4149884943
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.3695346437
Short name T307
Test name
Test status
Simulation time 11209407721 ps
CPU time 14.85 seconds
Started May 02 01:50:44 PM PDT 24
Finished May 02 01:51:00 PM PDT 24
Peak memory 204888 kb
Host smart-847f9199-e06d-4a0f-ba83-9bb07d5d2334
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695346437 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.3695346437
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.2404687313
Short name T262
Test name
Test status
Simulation time 12821478269 ps
CPU time 21.66 seconds
Started May 02 01:50:47 PM PDT 24
Finished May 02 01:51:10 PM PDT 24
Peak memory 204896 kb
Host smart-53f4c408-2c97-401c-ba08-c802736d5b6f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404687313 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_bit_bash.2404687313
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.1727639310
Short name T94
Test name
Test status
Simulation time 760350599 ps
CPU time 2.49 seconds
Started May 02 01:50:45 PM PDT 24
Finished May 02 01:50:49 PM PDT 24
Peak memory 204936 kb
Host smart-6b9ebf58-4e38-4325-99f7-ec862c035055
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727639310 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.1727639310
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.2120589692
Short name T274
Test name
Test status
Simulation time 518522592 ps
CPU time 1.87 seconds
Started May 02 01:50:43 PM PDT 24
Finished May 02 01:50:46 PM PDT 24
Peak memory 204856 kb
Host smart-fec209ac-545e-4960-a76e-36dd79277372
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120589692 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.2
120589692
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3826724706
Short name T240
Test name
Test status
Simulation time 132259560 ps
CPU time 0.8 seconds
Started May 02 01:50:42 PM PDT 24
Finished May 02 01:50:43 PM PDT 24
Peak memory 204596 kb
Host smart-a7b47374-e4ef-402e-a7de-f4c9e5771c1e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826724706 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.3826724706
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.3263372266
Short name T207
Test name
Test status
Simulation time 1113167458 ps
CPU time 3.99 seconds
Started May 02 01:50:42 PM PDT 24
Finished May 02 01:50:47 PM PDT 24
Peak memory 204808 kb
Host smart-d03d96f2-f13b-40d7-9a87-bc4a052bd996
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263372266 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.3263372266
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1041255582
Short name T199
Test name
Test status
Simulation time 226294257 ps
CPU time 0.83 seconds
Started May 02 01:50:43 PM PDT 24
Finished May 02 01:50:45 PM PDT 24
Peak memory 204628 kb
Host smart-9ca7a844-be6a-4c8d-a7fb-87447cc0b518
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041255582 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.1041255582
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.4004832733
Short name T74
Test name
Test status
Simulation time 135896900 ps
CPU time 0.71 seconds
Started May 02 01:50:43 PM PDT 24
Finished May 02 01:50:45 PM PDT 24
Peak memory 204572 kb
Host smart-5a63231d-e72e-4a19-9bd3-d2d9c2558375
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004832733 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.4
004832733
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.3920573482
Short name T196
Test name
Test status
Simulation time 16169197 ps
CPU time 0.68 seconds
Started May 02 01:50:45 PM PDT 24
Finished May 02 01:50:47 PM PDT 24
Peak memory 204596 kb
Host smart-2ca52ffe-c5cb-4ea0-8076-f2319b2ce773
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920573482 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.3920573482
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1405016057
Short name T173
Test name
Test status
Simulation time 39948507 ps
CPU time 0.67 seconds
Started May 02 01:50:41 PM PDT 24
Finished May 02 01:50:43 PM PDT 24
Peak memory 204536 kb
Host smart-0c9affec-09a2-4fc2-8040-fce9a532451a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405016057 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.1405016057
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.3152535440
Short name T52
Test name
Test status
Simulation time 298568490 ps
CPU time 3.57 seconds
Started May 02 01:50:44 PM PDT 24
Finished May 02 01:50:49 PM PDT 24
Peak memory 204940 kb
Host smart-2bc7291d-0fdb-436a-aa0f-c4c291fb7959
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152535440 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_
csr_outstanding.3152535440
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.1683327064
Short name T251
Test name
Test status
Simulation time 91346735 ps
CPU time 2.94 seconds
Started May 02 01:50:46 PM PDT 24
Finished May 02 01:50:50 PM PDT 24
Peak memory 213192 kb
Host smart-9ce47f00-4e5e-447a-9a7e-09f3a6e7ca78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683327064 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.1683327064
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.1281923564
Short name T256
Test name
Test status
Simulation time 1010586319 ps
CPU time 18.94 seconds
Started May 02 01:50:45 PM PDT 24
Finished May 02 01:51:05 PM PDT 24
Peak memory 213152 kb
Host smart-b1ccd66b-b4b7-4a44-b524-940235c41880
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281923564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.1281923564
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/31.rv_dm_tap_fsm_rand_reset.1355618654
Short name T253
Test name
Test status
Simulation time 24250904688 ps
CPU time 22.29 seconds
Started May 02 01:51:20 PM PDT 24
Finished May 02 01:51:45 PM PDT 24
Peak memory 221416 kb
Host smart-8969eb65-99b7-462b-87ea-982b6acf34ff
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355618654 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 31.rv_dm_tap_fsm_rand_reset.1355618654
Directory /workspace/31.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/37.rv_dm_tap_fsm_rand_reset.3718879679
Short name T89
Test name
Test status
Simulation time 11321618667 ps
CPU time 11.68 seconds
Started May 02 01:51:29 PM PDT 24
Finished May 02 01:51:42 PM PDT 24
Peak memory 219048 kb
Host smart-7314a942-d1d7-44cd-8df4-7df16a009329
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718879679 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 37.rv_dm_tap_fsm_rand_reset.3718879679
Directory /workspace/37.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1520096941
Short name T105
Test name
Test status
Simulation time 1154296147 ps
CPU time 68.22 seconds
Started May 02 01:50:47 PM PDT 24
Finished May 02 01:51:56 PM PDT 24
Peak memory 213176 kb
Host smart-489d78bc-1cfd-40c3-87d5-2899cddef5c1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520096941 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.1520096941
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.2224028679
Short name T310
Test name
Test status
Simulation time 5738267774 ps
CPU time 65.58 seconds
Started May 02 01:50:49 PM PDT 24
Finished May 02 01:51:55 PM PDT 24
Peak memory 205096 kb
Host smart-f164765a-38cb-466a-8a84-370a6cec5dcc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224028679 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.2224028679
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2000713359
Short name T296
Test name
Test status
Simulation time 759586847 ps
CPU time 1.64 seconds
Started May 02 01:50:52 PM PDT 24
Finished May 02 01:50:55 PM PDT 24
Peak memory 213092 kb
Host smart-34880a11-2e8c-418b-8fd5-4f2a7286da47
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000713359 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.2000713359
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.1479653121
Short name T239
Test name
Test status
Simulation time 3776841444 ps
CPU time 8.53 seconds
Started May 02 01:50:52 PM PDT 24
Finished May 02 01:51:02 PM PDT 24
Peak memory 218920 kb
Host smart-785a3f66-2fbc-4fc7-94ca-d2738c248fdb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479653121 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.1479653121
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.1425524795
Short name T108
Test name
Test status
Simulation time 39948705 ps
CPU time 2.19 seconds
Started May 02 01:50:54 PM PDT 24
Finished May 02 01:50:58 PM PDT 24
Peak memory 213128 kb
Host smart-7b2e3cbf-46d8-41a8-b749-5673b43b776a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425524795 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.1425524795
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.857288800
Short name T308
Test name
Test status
Simulation time 8459569722 ps
CPU time 31.45 seconds
Started May 02 01:50:51 PM PDT 24
Finished May 02 01:51:24 PM PDT 24
Peak memory 204904 kb
Host smart-389298d1-6e58-41f6-9580-ca9f1f04ec77
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857288800 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr
_aliasing.857288800
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3014161665
Short name T226
Test name
Test status
Simulation time 5405586188 ps
CPU time 24.17 seconds
Started May 02 01:50:50 PM PDT 24
Finished May 02 01:51:15 PM PDT 24
Peak memory 204896 kb
Host smart-f8565b69-d0c3-418b-bd7f-25131e6c4ce4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014161665 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_bit_bash.3014161665
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2300035433
Short name T92
Test name
Test status
Simulation time 523510539 ps
CPU time 2.5 seconds
Started May 02 01:50:50 PM PDT 24
Finished May 02 01:50:53 PM PDT 24
Peak memory 204848 kb
Host smart-24e7bc26-3f59-4ff0-8df8-cf24bf6294be
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300035433 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.2300035433
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.936579812
Short name T247
Test name
Test status
Simulation time 255092171 ps
CPU time 1.19 seconds
Started May 02 01:50:52 PM PDT 24
Finished May 02 01:50:54 PM PDT 24
Peak memory 204756 kb
Host smart-21aa1fc9-7649-4e71-b523-340715af4be2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936579812 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.936579812
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.184897418
Short name T278
Test name
Test status
Simulation time 48402864 ps
CPU time 0.87 seconds
Started May 02 01:50:53 PM PDT 24
Finished May 02 01:50:55 PM PDT 24
Peak memory 204592 kb
Host smart-6ad9e680-19b0-4821-a71e-ca85b8f34c90
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184897418 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr
_aliasing.184897418
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.1280223337
Short name T195
Test name
Test status
Simulation time 5116801269 ps
CPU time 3.03 seconds
Started May 02 01:50:50 PM PDT 24
Finished May 02 01:50:54 PM PDT 24
Peak memory 204924 kb
Host smart-5fa403b3-2534-485f-b9f6-0198245c3430
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280223337 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.1280223337
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2335903556
Short name T230
Test name
Test status
Simulation time 148525986 ps
CPU time 0.75 seconds
Started May 02 01:50:44 PM PDT 24
Finished May 02 01:50:46 PM PDT 24
Peak memory 204668 kb
Host smart-a28fb299-e0ce-41ca-a98f-61a4c22de09e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335903556 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.2335903556
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.964324075
Short name T69
Test name
Test status
Simulation time 162373059 ps
CPU time 0.7 seconds
Started May 02 01:50:44 PM PDT 24
Finished May 02 01:50:46 PM PDT 24
Peak memory 204616 kb
Host smart-af0ba462-5cf2-4fd2-89ce-80a233a6411c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964324075 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.964324075
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.3093876748
Short name T249
Test name
Test status
Simulation time 54136575 ps
CPU time 0.66 seconds
Started May 02 01:50:54 PM PDT 24
Finished May 02 01:50:56 PM PDT 24
Peak memory 204576 kb
Host smart-5699dce7-2123-4c0f-a3ef-b2980b68df39
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093876748 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.3093876748
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.3422216904
Short name T192
Test name
Test status
Simulation time 27806499 ps
CPU time 0.67 seconds
Started May 02 01:50:50 PM PDT 24
Finished May 02 01:50:52 PM PDT 24
Peak memory 204628 kb
Host smart-147abf33-f06f-4c0f-8f1b-41a7570b066f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422216904 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.3422216904
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3290040107
Short name T102
Test name
Test status
Simulation time 534648062 ps
CPU time 7.81 seconds
Started May 02 01:50:51 PM PDT 24
Finished May 02 01:51:00 PM PDT 24
Peak memory 204936 kb
Host smart-e58f9373-9d40-4e08-a908-9f2aac4ffa1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290040107 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.3290040107
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2447354023
Short name T259
Test name
Test status
Simulation time 26502375587 ps
CPU time 13.5 seconds
Started May 02 01:50:59 PM PDT 24
Finished May 02 01:51:15 PM PDT 24
Peak memory 215940 kb
Host smart-afd2d1aa-a3d9-4527-9f9d-a316d3a88157
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447354023 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.2447354023
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.1218708398
Short name T124
Test name
Test status
Simulation time 510328466 ps
CPU time 3.12 seconds
Started May 02 01:50:50 PM PDT 24
Finished May 02 01:50:54 PM PDT 24
Peak memory 213180 kb
Host smart-caf70b8d-a713-496f-a5e5-16d9528241f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218708398 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.1218708398
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.1041680035
Short name T255
Test name
Test status
Simulation time 300017716 ps
CPU time 2.25 seconds
Started May 02 01:50:48 PM PDT 24
Finished May 02 01:50:51 PM PDT 24
Peak memory 214676 kb
Host smart-4a435bb8-7c1f-4422-a283-711c3292a13e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041680035 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.1041680035
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.3712328340
Short name T250
Test name
Test status
Simulation time 144694218 ps
CPU time 2.23 seconds
Started May 02 01:50:50 PM PDT 24
Finished May 02 01:50:54 PM PDT 24
Peak memory 213112 kb
Host smart-87783b2d-fc90-4d84-841b-a38a0375dae2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712328340 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.3712328340
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3356409475
Short name T174
Test name
Test status
Simulation time 462317830 ps
CPU time 2.49 seconds
Started May 02 01:50:53 PM PDT 24
Finished May 02 01:50:57 PM PDT 24
Peak memory 204752 kb
Host smart-6bd17166-09fb-439a-8cef-cd58f740e3c9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356409475 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.3
356409475
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.561069534
Short name T303
Test name
Test status
Simulation time 86187340 ps
CPU time 0.9 seconds
Started May 02 01:50:50 PM PDT 24
Finished May 02 01:50:51 PM PDT 24
Peak memory 204600 kb
Host smart-52909d0c-dbe5-46c7-b99d-27223e2a3e94
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561069534 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.561069534
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1550340814
Short name T270
Test name
Test status
Simulation time 260359648 ps
CPU time 4.36 seconds
Started May 02 01:50:54 PM PDT 24
Finished May 02 01:50:59 PM PDT 24
Peak memory 204904 kb
Host smart-458d6430-0828-4fc4-9e6d-de350bf14e6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550340814 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.1550340814
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.4193957786
Short name T200
Test name
Test status
Simulation time 1296839346 ps
CPU time 6.36 seconds
Started May 02 01:50:51 PM PDT 24
Finished May 02 01:50:58 PM PDT 24
Peak memory 213136 kb
Host smart-193ec24e-f61b-4f0c-8903-aafcf0b008b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193957786 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.4193957786
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.119203814
Short name T127
Test name
Test status
Simulation time 261538499 ps
CPU time 8.88 seconds
Started May 02 01:50:49 PM PDT 24
Finished May 02 01:50:59 PM PDT 24
Peak memory 213372 kb
Host smart-a56871db-ea02-4715-8da7-e496a35053eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119203814 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.119203814
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.39432045
Short name T223
Test name
Test status
Simulation time 64297860 ps
CPU time 2.32 seconds
Started May 02 01:50:50 PM PDT 24
Finished May 02 01:50:53 PM PDT 24
Peak memory 213152 kb
Host smart-4fd1148e-bd9e-4f26-af66-4e0186cf38c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39432045 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.39432045
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.4148232211
Short name T264
Test name
Test status
Simulation time 45328146 ps
CPU time 2.09 seconds
Started May 02 01:50:51 PM PDT 24
Finished May 02 01:50:54 PM PDT 24
Peak memory 213164 kb
Host smart-0db8bb4b-32d0-4407-bf56-7059632cc929
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148232211 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.4148232211
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.3237575170
Short name T243
Test name
Test status
Simulation time 2065949637 ps
CPU time 1.67 seconds
Started May 02 01:50:51 PM PDT 24
Finished May 02 01:50:54 PM PDT 24
Peak memory 204796 kb
Host smart-2f5fd615-cb58-4a10-a342-eb1f6706d48e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237575170 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.3
237575170
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.4243801780
Short name T188
Test name
Test status
Simulation time 90706131 ps
CPU time 0.74 seconds
Started May 02 01:50:51 PM PDT 24
Finished May 02 01:50:53 PM PDT 24
Peak memory 204612 kb
Host smart-dd1324d0-e036-492b-8726-29daad27ce23
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243801780 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.4
243801780
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2360894740
Short name T84
Test name
Test status
Simulation time 3679973953 ps
CPU time 8.72 seconds
Started May 02 01:50:54 PM PDT 24
Finished May 02 01:51:04 PM PDT 24
Peak memory 204964 kb
Host smart-d391d292-c64b-4541-bcbe-7302b4207925
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360894740 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.2360894740
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.1457385002
Short name T231
Test name
Test status
Simulation time 403703128 ps
CPU time 5.62 seconds
Started May 02 01:50:52 PM PDT 24
Finished May 02 01:50:59 PM PDT 24
Peak memory 213216 kb
Host smart-59009dbe-273d-4a42-b212-d99325f71f16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457385002 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.1457385002
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.3507895493
Short name T131
Test name
Test status
Simulation time 2420701308 ps
CPU time 16.91 seconds
Started May 02 01:50:48 PM PDT 24
Finished May 02 01:51:06 PM PDT 24
Peak memory 213232 kb
Host smart-5b9e82b9-3833-4ed3-9f3f-e4c8806327c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507895493 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.3507895493
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2859181414
Short name T47
Test name
Test status
Simulation time 1653812180 ps
CPU time 4.05 seconds
Started May 02 01:50:53 PM PDT 24
Finished May 02 01:50:58 PM PDT 24
Peak memory 218048 kb
Host smart-ea34953f-55f6-46c6-be38-fb35141c53cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859181414 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.2859181414
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.605032694
Short name T241
Test name
Test status
Simulation time 29166428 ps
CPU time 1.53 seconds
Started May 02 01:50:52 PM PDT 24
Finished May 02 01:50:55 PM PDT 24
Peak memory 213104 kb
Host smart-dfce3baa-7a17-4405-84df-aded649323a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605032694 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.605032694
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2656960311
Short name T181
Test name
Test status
Simulation time 1206836406 ps
CPU time 2.75 seconds
Started May 02 01:50:49 PM PDT 24
Finished May 02 01:50:53 PM PDT 24
Peak memory 204720 kb
Host smart-1db40cfa-aee9-45c8-b6c4-715751133642
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656960311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.2
656960311
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.984210146
Short name T71
Test name
Test status
Simulation time 65180169 ps
CPU time 0.7 seconds
Started May 02 01:50:51 PM PDT 24
Finished May 02 01:50:53 PM PDT 24
Peak memory 204540 kb
Host smart-aa578b1f-6895-47d2-8c90-a251d31cbd29
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984210146 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.984210146
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.707760685
Short name T111
Test name
Test status
Simulation time 786037209 ps
CPU time 3.82 seconds
Started May 02 01:50:55 PM PDT 24
Finished May 02 01:51:00 PM PDT 24
Peak memory 204908 kb
Host smart-7f0253b3-41e9-4d41-96a1-f8c0be4870b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707760685 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_c
sr_outstanding.707760685
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.2789412913
Short name T189
Test name
Test status
Simulation time 104398940 ps
CPU time 2.4 seconds
Started May 02 01:50:48 PM PDT 24
Finished May 02 01:50:51 PM PDT 24
Peak memory 213248 kb
Host smart-6d12a6da-9e1c-4404-89b2-57d8b798b2e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789412913 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.2789412913
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.4053335433
Short name T244
Test name
Test status
Simulation time 3109358587 ps
CPU time 7.92 seconds
Started May 02 01:51:00 PM PDT 24
Finished May 02 01:51:10 PM PDT 24
Peak memory 217344 kb
Host smart-67356252-9e59-4bd1-b46c-26a931d2acc8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053335433 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.4053335433
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.2638189445
Short name T95
Test name
Test status
Simulation time 70239636 ps
CPU time 1.56 seconds
Started May 02 01:50:59 PM PDT 24
Finished May 02 01:51:03 PM PDT 24
Peak memory 213068 kb
Host smart-168e47a0-a5b8-4882-b6cb-2ca047af3609
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638189445 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.2638189445
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3567697516
Short name T193
Test name
Test status
Simulation time 678482654 ps
CPU time 1.29 seconds
Started May 02 01:50:53 PM PDT 24
Finished May 02 01:50:55 PM PDT 24
Peak memory 204756 kb
Host smart-1ba59bb4-e317-419e-9174-edf24aa3ca72
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567697516 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.3
567697516
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.3802616352
Short name T211
Test name
Test status
Simulation time 53650226 ps
CPU time 0.72 seconds
Started May 02 01:50:50 PM PDT 24
Finished May 02 01:50:52 PM PDT 24
Peak memory 204600 kb
Host smart-e8413996-9d35-481e-9bfc-ba119dd136a4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802616352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.3
802616352
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2893546776
Short name T265
Test name
Test status
Simulation time 2195258408 ps
CPU time 8.19 seconds
Started May 02 01:51:01 PM PDT 24
Finished May 02 01:51:11 PM PDT 24
Peak memory 205008 kb
Host smart-c9facb8f-2d14-4bef-b55a-5e0ecc6a4098
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893546776 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_
csr_outstanding.2893546776
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.1197878308
Short name T254
Test name
Test status
Simulation time 63628617 ps
CPU time 1.98 seconds
Started May 02 01:50:54 PM PDT 24
Finished May 02 01:50:58 PM PDT 24
Peak memory 213128 kb
Host smart-26f27a4c-8a2b-4206-a466-e5aeda8028a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197878308 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.1197878308
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.1836975308
Short name T134
Test name
Test status
Simulation time 1879434209 ps
CPU time 10.76 seconds
Started May 02 01:51:03 PM PDT 24
Finished May 02 01:51:15 PM PDT 24
Peak memory 213040 kb
Host smart-c0e8b6f9-739c-472d-96a6-1a5d93b4def1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836975308 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.1836975308
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.241056709
Short name T221
Test name
Test status
Simulation time 2946989194 ps
CPU time 6.27 seconds
Started May 02 01:50:57 PM PDT 24
Finished May 02 01:51:05 PM PDT 24
Peak memory 218112 kb
Host smart-bd71884b-acd0-48b8-a6ec-cf445c63f788
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241056709 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.241056709
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.579808244
Short name T100
Test name
Test status
Simulation time 53860963 ps
CPU time 1.39 seconds
Started May 02 01:51:00 PM PDT 24
Finished May 02 01:51:04 PM PDT 24
Peak memory 213092 kb
Host smart-2d42dc90-2645-40fe-a3f9-a4521c6df9d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579808244 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.579808244
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.2059933463
Short name T182
Test name
Test status
Simulation time 725075060 ps
CPU time 2.06 seconds
Started May 02 01:51:00 PM PDT 24
Finished May 02 01:51:04 PM PDT 24
Peak memory 204720 kb
Host smart-bd7adc51-dd32-4c73-b791-585fe8214767
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059933463 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.2
059933463
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.2873945301
Short name T185
Test name
Test status
Simulation time 134736954 ps
CPU time 0.69 seconds
Started May 02 01:51:01 PM PDT 24
Finished May 02 01:51:04 PM PDT 24
Peak memory 204592 kb
Host smart-a5f11513-f43a-4818-ae71-78ef981a2566
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873945301 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.2
873945301
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.762082472
Short name T190
Test name
Test status
Simulation time 2883885253 ps
CPU time 7.96 seconds
Started May 02 01:51:00 PM PDT 24
Finished May 02 01:51:10 PM PDT 24
Peak memory 205008 kb
Host smart-5570fef3-f905-47de-bdf4-c6828647e9d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762082472 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_c
sr_outstanding.762082472
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.3365128276
Short name T285
Test name
Test status
Simulation time 11051474138 ps
CPU time 41.34 seconds
Started May 02 01:51:03 PM PDT 24
Finished May 02 01:51:46 PM PDT 24
Peak memory 221448 kb
Host smart-f6da22c7-f226-4283-a8fe-4c86b68c0085
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365128276 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.3365128276
Directory /workspace/9.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.1693809213
Short name T290
Test name
Test status
Simulation time 120567919 ps
CPU time 2.59 seconds
Started May 02 01:51:00 PM PDT 24
Finished May 02 01:51:05 PM PDT 24
Peak memory 213172 kb
Host smart-ab839260-a221-4cb9-9173-296d348eaf33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693809213 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.1693809213
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.1361355503
Short name T288
Test name
Test status
Simulation time 452590222 ps
CPU time 9.78 seconds
Started May 02 01:51:01 PM PDT 24
Finished May 02 01:51:13 PM PDT 24
Peak memory 221228 kb
Host smart-de2b1430-c210-4b96-a1ef-552fcf4e1b0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361355503 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.1361355503
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.2625048572
Short name T142
Test name
Test status
Simulation time 54858052 ps
CPU time 0.73 seconds
Started May 02 01:57:39 PM PDT 24
Finished May 02 01:57:40 PM PDT 24
Peak memory 205136 kb
Host smart-c72747d0-ddb3-4fe5-8e53-c729d7b929b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625048572 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.2625048572
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.171385468
Short name T31
Test name
Test status
Simulation time 4880586829 ps
CPU time 7.81 seconds
Started May 02 01:57:22 PM PDT 24
Finished May 02 01:57:31 PM PDT 24
Peak memory 205468 kb
Host smart-4ba738aa-0e3f-4928-b82a-aead62762c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171385468 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.171385468
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.1401344120
Short name T23
Test name
Test status
Simulation time 95785670 ps
CPU time 0.9 seconds
Started May 02 01:57:24 PM PDT 24
Finished May 02 01:57:26 PM PDT 24
Peak memory 205184 kb
Host smart-34b58a53-c942-4a0e-8192-ecdc85ff406c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401344120 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.1401344120
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.3753883451
Short name T7
Test name
Test status
Simulation time 893920164 ps
CPU time 4.18 seconds
Started May 02 01:57:22 PM PDT 24
Finished May 02 01:57:27 PM PDT 24
Peak memory 205364 kb
Host smart-b4888d01-3cab-4637-8d15-38a9215aab45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753883451 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.3753883451
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.166414521
Short name T20
Test name
Test status
Simulation time 86800526 ps
CPU time 0.8 seconds
Started May 02 01:57:24 PM PDT 24
Finished May 02 01:57:26 PM PDT 24
Peak memory 205140 kb
Host smart-f91790a2-ae27-411c-862f-6c7e09df9654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166414521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.166414521
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.785401239
Short name T30
Test name
Test status
Simulation time 66523241 ps
CPU time 0.83 seconds
Started May 02 01:57:24 PM PDT 24
Finished May 02 01:57:26 PM PDT 24
Peak memory 205024 kb
Host smart-cd5a7716-f8f1-480e-a7dc-fa1d44688d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785401239 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.785401239
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.4006995256
Short name T37
Test name
Test status
Simulation time 226474616 ps
CPU time 1.28 seconds
Started May 02 01:57:32 PM PDT 24
Finished May 02 01:57:35 PM PDT 24
Peak memory 205004 kb
Host smart-492aed8a-e300-4266-8fb9-8707a27f7bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006995256 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.4006995256
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.911067897
Short name T169
Test name
Test status
Simulation time 104297263 ps
CPU time 0.84 seconds
Started May 02 01:57:29 PM PDT 24
Finished May 02 01:57:30 PM PDT 24
Peak memory 205060 kb
Host smart-a1221cb4-1139-4183-a9b9-38fa4bad01ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911067897 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.911067897
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.2997906532
Short name T36
Test name
Test status
Simulation time 274394181 ps
CPU time 1.67 seconds
Started May 02 01:57:30 PM PDT 24
Finished May 02 01:57:33 PM PDT 24
Peak memory 205204 kb
Host smart-e244ad91-a849-4fd8-830f-0ace8a19d9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997906532 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.2997906532
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.647455530
Short name T163
Test name
Test status
Simulation time 56649268 ps
CPU time 0.9 seconds
Started May 02 01:57:22 PM PDT 24
Finished May 02 01:57:25 PM PDT 24
Peak memory 205168 kb
Host smart-88ebb1bc-98fb-4753-b69e-01c31fae1b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647455530 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.647455530
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.1919128853
Short name T8
Test name
Test status
Simulation time 721225786 ps
CPU time 1.15 seconds
Started May 02 01:57:22 PM PDT 24
Finished May 02 01:57:24 PM PDT 24
Peak memory 205396 kb
Host smart-f26a117b-08b6-4fb4-8d69-998f199ccb33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919128853 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.1919128853
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.1383882182
Short name T19
Test name
Test status
Simulation time 1858028347 ps
CPU time 1.78 seconds
Started May 02 01:57:24 PM PDT 24
Finished May 02 01:57:27 PM PDT 24
Peak memory 205368 kb
Host smart-bb595caf-5aff-457f-948b-61c13495469a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383882182 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.1383882182
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.364852253
Short name T21
Test name
Test status
Simulation time 53014812 ps
CPU time 0.84 seconds
Started May 02 01:57:30 PM PDT 24
Finished May 02 01:57:32 PM PDT 24
Peak memory 205132 kb
Host smart-32593988-c4f9-4117-848d-44041ac2ceda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364852253 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.364852253
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.3716840188
Short name T60
Test name
Test status
Simulation time 96319848 ps
CPU time 1.03 seconds
Started May 02 01:57:37 PM PDT 24
Finished May 02 01:57:38 PM PDT 24
Peak memory 228464 kb
Host smart-97942522-0f98-4681-8b8a-c463c7167737
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716840188 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.3716840188
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.73973783
Short name T66
Test name
Test status
Simulation time 3039044618 ps
CPU time 2.95 seconds
Started May 02 01:57:13 PM PDT 24
Finished May 02 01:57:18 PM PDT 24
Peak memory 205424 kb
Host smart-09ec1189-c688-488e-bc5a-43cf0d0acc86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73973783 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.73973783
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.1301056228
Short name T13
Test name
Test status
Simulation time 62986687 ps
CPU time 0.86 seconds
Started May 02 01:57:54 PM PDT 24
Finished May 02 01:57:56 PM PDT 24
Peak memory 205156 kb
Host smart-9860f562-6d5a-4a68-957a-54815aa7fdc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301056228 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.1301056228
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.3270571370
Short name T153
Test name
Test status
Simulation time 59746613 ps
CPU time 0.67 seconds
Started May 02 01:57:51 PM PDT 24
Finished May 02 01:57:54 PM PDT 24
Peak memory 205172 kb
Host smart-9f0b62df-7a26-46b0-a814-861fba883fae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270571370 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.3270571370
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.1821556795
Short name T15
Test name
Test status
Simulation time 3357311303 ps
CPU time 12.3 seconds
Started May 02 01:57:36 PM PDT 24
Finished May 02 01:57:49 PM PDT 24
Peak memory 205452 kb
Host smart-d4dc764c-0e26-4b13-b944-9aa8aba3f5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821556795 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.1821556795
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.24370178
Short name T10
Test name
Test status
Simulation time 104929503 ps
CPU time 0.9 seconds
Started May 02 01:57:46 PM PDT 24
Finished May 02 01:57:48 PM PDT 24
Peak memory 205012 kb
Host smart-e9c45485-4001-45d6-a818-6aa785a1f992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24370178 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.24370178
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.60241505
Short name T12
Test name
Test status
Simulation time 928628679 ps
CPU time 3.8 seconds
Started May 02 01:57:37 PM PDT 24
Finished May 02 01:57:41 PM PDT 24
Peak memory 205336 kb
Host smart-b9caded9-5182-4319-9d6e-ecd3c855aa4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60241505 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.60241505
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.1508467128
Short name T170
Test name
Test status
Simulation time 62170073 ps
CPU time 0.84 seconds
Started May 02 01:57:45 PM PDT 24
Finished May 02 01:57:47 PM PDT 24
Peak memory 205164 kb
Host smart-145b6b59-1365-4aa4-8d65-5db88fd3b5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508467128 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.1508467128
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.2736709242
Short name T166
Test name
Test status
Simulation time 42974888 ps
CPU time 0.72 seconds
Started May 02 01:57:45 PM PDT 24
Finished May 02 01:57:46 PM PDT 24
Peak memory 205024 kb
Host smart-471de01a-e36c-4898-8169-a810d353fc88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736709242 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.2736709242
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.3352944420
Short name T160
Test name
Test status
Simulation time 239274221 ps
CPU time 0.87 seconds
Started May 02 01:57:51 PM PDT 24
Finished May 02 01:57:54 PM PDT 24
Peak memory 205012 kb
Host smart-c8e988b9-1d50-4225-9605-52dfb390ec3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352944420 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.3352944420
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.2268508273
Short name T165
Test name
Test status
Simulation time 544216701 ps
CPU time 1.99 seconds
Started May 02 01:57:51 PM PDT 24
Finished May 02 01:57:55 PM PDT 24
Peak memory 205216 kb
Host smart-953c2485-9418-43c5-9b4d-255efcf5596a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268508273 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.2268508273
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.497334639
Short name T138
Test name
Test status
Simulation time 49462079 ps
CPU time 0.82 seconds
Started May 02 01:57:44 PM PDT 24
Finished May 02 01:57:46 PM PDT 24
Peak memory 205200 kb
Host smart-60b32c22-101d-49a7-9085-4ba51283b341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497334639 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.497334639
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.3787965903
Short name T137
Test name
Test status
Simulation time 137073840 ps
CPU time 1.14 seconds
Started May 02 01:57:47 PM PDT 24
Finished May 02 01:57:49 PM PDT 24
Peak memory 205336 kb
Host smart-da4a5279-a7a8-424f-af7e-be2f1f3379ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787965903 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.3787965903
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.2536628068
Short name T28
Test name
Test status
Simulation time 175200191 ps
CPU time 0.94 seconds
Started May 02 01:57:52 PM PDT 24
Finished May 02 01:57:55 PM PDT 24
Peak memory 205160 kb
Host smart-229bb6e2-8c86-49ef-8011-9839191f2221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536628068 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.2536628068
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.75987203
Short name T17
Test name
Test status
Simulation time 34230202 ps
CPU time 0.84 seconds
Started May 02 01:57:51 PM PDT 24
Finished May 02 01:57:53 PM PDT 24
Peak memory 213288 kb
Host smart-0908e34d-58d3-4efa-9bbf-6434b5afa65e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75987203 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.75987203
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.3982714340
Short name T61
Test name
Test status
Simulation time 218231191 ps
CPU time 1.11 seconds
Started May 02 01:57:53 PM PDT 24
Finished May 02 01:57:56 PM PDT 24
Peak memory 228952 kb
Host smart-d9b3dc0d-84fb-43c5-a2ba-313db8535343
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982714340 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.3982714340
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.4269065037
Short name T26
Test name
Test status
Simulation time 268371310 ps
CPU time 1.48 seconds
Started May 02 01:57:37 PM PDT 24
Finished May 02 01:57:39 PM PDT 24
Peak memory 205028 kb
Host smart-efd28bea-b027-4bfa-9a14-19a98d1dfe4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269065037 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.4269065037
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.3886439010
Short name T76
Test name
Test status
Simulation time 47702275 ps
CPU time 0.71 seconds
Started May 02 01:58:26 PM PDT 24
Finished May 02 01:58:27 PM PDT 24
Peak memory 205156 kb
Host smart-9766780e-59c0-4ef9-8de8-8f3f3b48e71a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886439010 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.3886439010
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.2253174768
Short name T35
Test name
Test status
Simulation time 795910906 ps
CPU time 1.23 seconds
Started May 02 01:58:28 PM PDT 24
Finished May 02 01:58:30 PM PDT 24
Peak memory 205436 kb
Host smart-b5c2cb65-09d3-45f3-8414-c43944daf9a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253174768 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.2253174768
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.565063023
Short name T147
Test name
Test status
Simulation time 62227420 ps
CPU time 0.74 seconds
Started May 02 01:58:24 PM PDT 24
Finished May 02 01:58:26 PM PDT 24
Peak memory 205104 kb
Host smart-4211baa7-c61b-4558-bb95-4eebb9cec6fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565063023 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.565063023
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.887543295
Short name T143
Test name
Test status
Simulation time 18453701 ps
CPU time 0.74 seconds
Started May 02 01:58:30 PM PDT 24
Finished May 02 01:58:32 PM PDT 24
Peak memory 205184 kb
Host smart-eb595e25-0b79-4048-8e9d-5eb6e8279b3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887543295 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.887543295
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.3127086024
Short name T4
Test name
Test status
Simulation time 66174515 ps
CPU time 0.72 seconds
Started May 02 01:58:30 PM PDT 24
Finished May 02 01:58:32 PM PDT 24
Peak memory 205168 kb
Host smart-f01301f7-4fcf-4174-b0c9-6d5b3ea8cd5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127086024 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.3127086024
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.2712471459
Short name T56
Test name
Test status
Simulation time 27619054 ps
CPU time 0.73 seconds
Started May 02 01:58:41 PM PDT 24
Finished May 02 01:58:43 PM PDT 24
Peak memory 205156 kb
Host smart-bfca3dfd-6f70-4d72-870c-842923214a54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712471459 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.2712471459
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.3239882712
Short name T44
Test name
Test status
Simulation time 19281559 ps
CPU time 0.73 seconds
Started May 02 01:58:39 PM PDT 24
Finished May 02 01:58:41 PM PDT 24
Peak memory 205140 kb
Host smart-97cff704-85d9-48db-891c-e96095935631
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239882712 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.3239882712
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.3895586060
Short name T32
Test name
Test status
Simulation time 4984428492 ps
CPU time 6.9 seconds
Started May 02 01:58:42 PM PDT 24
Finished May 02 01:58:50 PM PDT 24
Peak memory 205564 kb
Host smart-a44cd7a8-ea0c-4892-a050-218df632b88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895586060 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.3895586060
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_stress_all.4010901155
Short name T68
Test name
Test status
Simulation time 4681646295 ps
CPU time 5.46 seconds
Started May 02 01:58:39 PM PDT 24
Finished May 02 01:58:46 PM PDT 24
Peak memory 213676 kb
Host smart-694e477b-ffec-42a4-8bfe-544f1407764b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010901155 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.4010901155
Directory /workspace/15.rv_dm_stress_all/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.2461579373
Short name T149
Test name
Test status
Simulation time 44593374 ps
CPU time 0.72 seconds
Started May 02 01:58:46 PM PDT 24
Finished May 02 01:58:48 PM PDT 24
Peak memory 205112 kb
Host smart-336a0e0e-d241-4103-9397-075199a23641
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461579373 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.2461579373
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.583180105
Short name T5
Test name
Test status
Simulation time 31223363 ps
CPU time 0.75 seconds
Started May 02 01:58:48 PM PDT 24
Finished May 02 01:58:50 PM PDT 24
Peak memory 205188 kb
Host smart-410031e6-3456-4af3-ae10-38c62882e666
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583180105 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.583180105
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.106005748
Short name T34
Test name
Test status
Simulation time 2876116000 ps
CPU time 4.13 seconds
Started May 02 01:58:39 PM PDT 24
Finished May 02 01:58:45 PM PDT 24
Peak memory 205596 kb
Host smart-48ddc453-567c-42bf-93fd-94ee3746e846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106005748 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.106005748
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.236401496
Short name T156
Test name
Test status
Simulation time 23052816 ps
CPU time 0.75 seconds
Started May 02 01:58:47 PM PDT 24
Finished May 02 01:58:50 PM PDT 24
Peak memory 205124 kb
Host smart-364be740-8ea6-4689-8a86-c9f513738599
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236401496 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.236401496
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.2970865626
Short name T154
Test name
Test status
Simulation time 17311739 ps
CPU time 0.71 seconds
Started May 02 01:58:00 PM PDT 24
Finished May 02 01:58:02 PM PDT 24
Peak memory 205140 kb
Host smart-b116412c-77d9-40dd-b746-740f20b1f6d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970865626 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.2970865626
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.3313821507
Short name T171
Test name
Test status
Simulation time 113438121 ps
CPU time 1.05 seconds
Started May 02 01:58:02 PM PDT 24
Finished May 02 01:58:04 PM PDT 24
Peak memory 204980 kb
Host smart-185dd6d9-c72c-45d7-9f3e-d9dc94aa2a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313821507 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.3313821507
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.3086273222
Short name T2
Test name
Test status
Simulation time 29978028 ps
CPU time 0.76 seconds
Started May 02 01:58:48 PM PDT 24
Finished May 02 01:58:50 PM PDT 24
Peak memory 205172 kb
Host smart-f6c35e34-0363-4e6e-a3d0-2b69315312ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086273222 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.3086273222
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.2228335682
Short name T3
Test name
Test status
Simulation time 24719444 ps
CPU time 0.71 seconds
Started May 02 01:58:55 PM PDT 24
Finished May 02 01:58:57 PM PDT 24
Peak memory 205112 kb
Host smart-296575c1-612c-42fb-b8c9-dd2d3bdfb866
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228335682 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.2228335682
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.728675512
Short name T159
Test name
Test status
Simulation time 31969719 ps
CPU time 0.71 seconds
Started May 02 01:58:46 PM PDT 24
Finished May 02 01:58:48 PM PDT 24
Peak memory 205136 kb
Host smart-a3e286a8-4566-4ba4-ac47-539f21af99e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728675512 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.728675512
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.2533426409
Short name T120
Test name
Test status
Simulation time 61583357 ps
CPU time 0.72 seconds
Started May 02 01:58:50 PM PDT 24
Finished May 02 01:58:52 PM PDT 24
Peak memory 205140 kb
Host smart-e896b06e-3c29-485e-a067-d0968d607f9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533426409 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.2533426409
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.2222954277
Short name T144
Test name
Test status
Simulation time 78745078 ps
CPU time 0.69 seconds
Started May 02 01:58:47 PM PDT 24
Finished May 02 01:58:50 PM PDT 24
Peak memory 205164 kb
Host smart-67c14161-04b7-46b5-9fcd-781cc414448b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222954277 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.2222954277
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.590071188
Short name T77
Test name
Test status
Simulation time 32963576 ps
CPU time 0.74 seconds
Started May 02 01:58:53 PM PDT 24
Finished May 02 01:58:55 PM PDT 24
Peak memory 205176 kb
Host smart-7c1792d6-b961-4d14-b7e9-b1ff74d13bab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590071188 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.590071188
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_stress_all.724297145
Short name T25
Test name
Test status
Simulation time 8371387526 ps
CPU time 12.49 seconds
Started May 02 01:58:53 PM PDT 24
Finished May 02 01:59:06 PM PDT 24
Peak memory 205488 kb
Host smart-b9c1ff8b-fb15-4b13-95b4-d7a3fb9718b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724297145 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.724297145
Directory /workspace/25.rv_dm_stress_all/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.1313958545
Short name T113
Test name
Test status
Simulation time 32146028 ps
CPU time 0.69 seconds
Started May 02 01:58:54 PM PDT 24
Finished May 02 01:58:56 PM PDT 24
Peak memory 205152 kb
Host smart-24e9b40a-d2b0-4a9e-9677-5478650caae0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313958545 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.1313958545
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.2385233791
Short name T161
Test name
Test status
Simulation time 54009070 ps
CPU time 0.71 seconds
Started May 02 01:58:53 PM PDT 24
Finished May 02 01:58:56 PM PDT 24
Peak memory 205132 kb
Host smart-ab836808-8ef8-4052-abe4-d8f85a65516f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385233791 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.2385233791
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.4289294505
Short name T58
Test name
Test status
Simulation time 31889004 ps
CPU time 0.73 seconds
Started May 02 01:58:54 PM PDT 24
Finished May 02 01:58:56 PM PDT 24
Peak memory 205128 kb
Host smart-7e016562-2450-40fb-87e1-a239982f3d68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289294505 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.4289294505
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.2467498614
Short name T158
Test name
Test status
Simulation time 44430440 ps
CPU time 0.69 seconds
Started May 02 01:58:53 PM PDT 24
Finished May 02 01:58:55 PM PDT 24
Peak memory 205148 kb
Host smart-107cd94c-6214-4171-8d00-51b3530d0f6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467498614 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.2467498614
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.2801362466
Short name T6
Test name
Test status
Simulation time 38051335 ps
CPU time 0.68 seconds
Started May 02 01:57:58 PM PDT 24
Finished May 02 01:58:00 PM PDT 24
Peak memory 205132 kb
Host smart-bc1049ae-a8b1-4f77-823c-bb16e2bab2ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801362466 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.2801362466
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.2811090207
Short name T118
Test name
Test status
Simulation time 70314507 ps
CPU time 0.77 seconds
Started May 02 01:57:58 PM PDT 24
Finished May 02 01:58:00 PM PDT 24
Peak memory 205008 kb
Host smart-14a003b6-a860-4f90-8c71-2ba6c8615c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811090207 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.2811090207
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.970352137
Short name T40
Test name
Test status
Simulation time 366304936 ps
CPU time 1.02 seconds
Started May 02 01:57:59 PM PDT 24
Finished May 02 01:58:01 PM PDT 24
Peak memory 229796 kb
Host smart-4c5482e5-f3c4-4be6-8e0f-ae6dfa756fd1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970352137 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.970352137
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.2051407002
Short name T55
Test name
Test status
Simulation time 41788456 ps
CPU time 0.73 seconds
Started May 02 01:58:52 PM PDT 24
Finished May 02 01:58:53 PM PDT 24
Peak memory 205172 kb
Host smart-d5f40572-c0ca-4693-b50d-aa482e42c707
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051407002 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.2051407002
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.4014710664
Short name T119
Test name
Test status
Simulation time 64229865 ps
CPU time 0.73 seconds
Started May 02 01:59:06 PM PDT 24
Finished May 02 01:59:09 PM PDT 24
Peak memory 204736 kb
Host smart-e1ad2550-1dfb-4cfc-a9cd-39160952c2ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014710664 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.4014710664
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.1175193294
Short name T54
Test name
Test status
Simulation time 154409915 ps
CPU time 0.71 seconds
Started May 02 01:59:05 PM PDT 24
Finished May 02 01:59:08 PM PDT 24
Peak memory 205132 kb
Host smart-28768c21-791a-4bed-827e-181fc9586c27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175193294 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.1175193294
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.2795509981
Short name T139
Test name
Test status
Simulation time 39405674 ps
CPU time 0.76 seconds
Started May 02 01:59:02 PM PDT 24
Finished May 02 01:59:04 PM PDT 24
Peak memory 205148 kb
Host smart-cb749d4b-9cec-4594-a9d2-d7424d036b9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795509981 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.2795509981
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.1202254337
Short name T57
Test name
Test status
Simulation time 26195058 ps
CPU time 0.73 seconds
Started May 02 01:59:04 PM PDT 24
Finished May 02 01:59:07 PM PDT 24
Peak memory 205172 kb
Host smart-556a3d08-212b-438a-b116-18f39b7fb856
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202254337 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.1202254337
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.1279697445
Short name T157
Test name
Test status
Simulation time 31406516 ps
CPU time 0.74 seconds
Started May 02 01:59:04 PM PDT 24
Finished May 02 01:59:06 PM PDT 24
Peak memory 205092 kb
Host smart-401e6ef5-f0eb-4bd9-9a8d-4b2489e4ac3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279697445 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.1279697445
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.3615134770
Short name T45
Test name
Test status
Simulation time 40456069 ps
CPU time 0.75 seconds
Started May 02 01:59:03 PM PDT 24
Finished May 02 01:59:06 PM PDT 24
Peak memory 205124 kb
Host smart-6e55ec8f-3354-4e69-9150-3700830e7789
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615134770 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.3615134770
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.2469551521
Short name T155
Test name
Test status
Simulation time 32655784 ps
CPU time 0.72 seconds
Started May 02 01:59:06 PM PDT 24
Finished May 02 01:59:09 PM PDT 24
Peak memory 205156 kb
Host smart-ff4a457c-1ee6-4639-84bf-2dea185659b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469551521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.2469551521
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.1626168892
Short name T140
Test name
Test status
Simulation time 26768728 ps
CPU time 0.76 seconds
Started May 02 01:59:04 PM PDT 24
Finished May 02 01:59:06 PM PDT 24
Peak memory 205188 kb
Host smart-210d4923-7d77-473e-872d-9b683b82ae31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626168892 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.1626168892
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.2188218285
Short name T146
Test name
Test status
Simulation time 24416895 ps
CPU time 0.72 seconds
Started May 02 01:59:05 PM PDT 24
Finished May 02 01:59:08 PM PDT 24
Peak memory 205144 kb
Host smart-079ab1dc-23ce-496e-ba61-40a0f6f680ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188218285 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.2188218285
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_stress_all.796547869
Short name T41
Test name
Test status
Simulation time 2842632426 ps
CPU time 5.65 seconds
Started May 02 01:59:06 PM PDT 24
Finished May 02 01:59:14 PM PDT 24
Peak memory 205480 kb
Host smart-e9d9b6ac-46dd-487e-960e-297452fde1ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796547869 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.796547869
Directory /workspace/39.rv_dm_stress_all/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.1430757133
Short name T167
Test name
Test status
Simulation time 17908643 ps
CPU time 0.72 seconds
Started May 02 01:58:08 PM PDT 24
Finished May 02 01:58:10 PM PDT 24
Peak memory 205144 kb
Host smart-293bf665-ee1b-4973-b863-0b094e7eeadb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430757133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.1430757133
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.2932339247
Short name T64
Test name
Test status
Simulation time 142142250 ps
CPU time 0.79 seconds
Started May 02 01:58:07 PM PDT 24
Finished May 02 01:58:10 PM PDT 24
Peak memory 205016 kb
Host smart-3490d84a-cf00-47c1-9d58-72f412b85e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932339247 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.2932339247
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.1258056617
Short name T38
Test name
Test status
Simulation time 1199692768 ps
CPU time 1.28 seconds
Started May 02 01:58:07 PM PDT 24
Finished May 02 01:58:10 PM PDT 24
Peak memory 229276 kb
Host smart-a428fb1e-b75f-4422-b635-dc77e2f2fc2e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258056617 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.1258056617
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.590953399
Short name T65
Test name
Test status
Simulation time 16481202 ps
CPU time 0.71 seconds
Started May 02 01:59:06 PM PDT 24
Finished May 02 01:59:09 PM PDT 24
Peak memory 204668 kb
Host smart-ff2ca14f-a58f-4019-bfa3-baec626848b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590953399 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.590953399
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.2482999757
Short name T62
Test name
Test status
Simulation time 53744056 ps
CPU time 0.72 seconds
Started May 02 01:59:03 PM PDT 24
Finished May 02 01:59:06 PM PDT 24
Peak memory 205144 kb
Host smart-954b8dbf-8951-428a-a9e1-282085385585
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482999757 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.2482999757
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.1232008137
Short name T59
Test name
Test status
Simulation time 20913447 ps
CPU time 0.74 seconds
Started May 02 01:59:14 PM PDT 24
Finished May 02 01:59:16 PM PDT 24
Peak memory 205132 kb
Host smart-0f8a8066-224c-46fb-8342-1b89090e4a2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232008137 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.1232008137
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.990836887
Short name T168
Test name
Test status
Simulation time 51132623 ps
CPU time 0.73 seconds
Started May 02 01:59:15 PM PDT 24
Finished May 02 01:59:17 PM PDT 24
Peak memory 205140 kb
Host smart-2340de47-529f-4d3f-8a27-15698e655437
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990836887 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.990836887
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.765148175
Short name T63
Test name
Test status
Simulation time 121837482 ps
CPU time 0.78 seconds
Started May 02 01:59:17 PM PDT 24
Finished May 02 01:59:19 PM PDT 24
Peak memory 205128 kb
Host smart-1e812e7e-9f91-4afe-af37-902bdae8045d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765148175 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.765148175
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.1274463272
Short name T141
Test name
Test status
Simulation time 23275672 ps
CPU time 0.73 seconds
Started May 02 01:59:16 PM PDT 24
Finished May 02 01:59:17 PM PDT 24
Peak memory 205136 kb
Host smart-77b6ec9d-abe6-4e8b-90ce-228cab62c477
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274463272 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.1274463272
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.2777480803
Short name T152
Test name
Test status
Simulation time 33098232 ps
CPU time 0.75 seconds
Started May 02 01:59:16 PM PDT 24
Finished May 02 01:59:18 PM PDT 24
Peak memory 205172 kb
Host smart-25761c6b-c715-4f01-bf2a-2e86d61a49de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777480803 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.2777480803
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.2421804311
Short name T123
Test name
Test status
Simulation time 26987008 ps
CPU time 0.76 seconds
Started May 02 01:59:16 PM PDT 24
Finished May 02 01:59:18 PM PDT 24
Peak memory 205104 kb
Host smart-613ac790-458e-4861-90d2-b72fcb384bd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421804311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.2421804311
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.3049580479
Short name T150
Test name
Test status
Simulation time 19246859 ps
CPU time 0.73 seconds
Started May 02 01:59:18 PM PDT 24
Finished May 02 01:59:20 PM PDT 24
Peak memory 205172 kb
Host smart-cafd6fe6-25f2-45e8-80af-fc94e81d6c44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049580479 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.3049580479
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.285886060
Short name T151
Test name
Test status
Simulation time 20087965 ps
CPU time 0.7 seconds
Started May 02 01:59:15 PM PDT 24
Finished May 02 01:59:16 PM PDT 24
Peak memory 205060 kb
Host smart-594f0fec-9ff2-4b02-8720-0d7bf446bd67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285886060 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.285886060
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.3746622073
Short name T164
Test name
Test status
Simulation time 33978721 ps
CPU time 0.75 seconds
Started May 02 01:58:07 PM PDT 24
Finished May 02 01:58:10 PM PDT 24
Peak memory 205152 kb
Host smart-8f2802e5-32eb-43f1-a15d-c56105b41d87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746622073 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.3746622073
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.1616004289
Short name T162
Test name
Test status
Simulation time 19898636 ps
CPU time 0.74 seconds
Started May 02 01:58:19 PM PDT 24
Finished May 02 01:58:20 PM PDT 24
Peak memory 205128 kb
Host smart-82fc6cae-5966-46cf-a2bf-9bf93bd545be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616004289 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.1616004289
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.1550423351
Short name T90
Test name
Test status
Simulation time 747177796 ps
CPU time 2.45 seconds
Started May 02 01:58:18 PM PDT 24
Finished May 02 01:58:21 PM PDT 24
Peak memory 205536 kb
Host smart-d5c04580-0f37-4e84-bb24-de0b1565ea36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550423351 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.1550423351
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.288604679
Short name T172
Test name
Test status
Simulation time 16620284 ps
CPU time 0.7 seconds
Started May 02 01:58:20 PM PDT 24
Finished May 02 01:58:23 PM PDT 24
Peak memory 205184 kb
Host smart-64330e8a-8e28-417a-859c-0a9b6b2ce805
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288604679 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.288604679
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.4170899174
Short name T145
Test name
Test status
Simulation time 86727377 ps
CPU time 0.72 seconds
Started May 02 01:58:22 PM PDT 24
Finished May 02 01:58:24 PM PDT 24
Peak memory 205112 kb
Host smart-8d4a5e60-a358-43c8-914b-4f57d3849005
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170899174 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.4170899174
Directory /workspace/9.rv_dm_alert_test/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%