SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
79.42 | 93.91 | 81.32 | 87.69 | 74.36 | 82.67 | 98.42 | 37.60 |
T258 | /workspace/coverage/cover_reg_top/10.rv_dm_tap_fsm_rand_reset.1004152678 | May 05 01:03:53 PM PDT 24 | May 05 01:04:22 PM PDT 24 | 31816554083 ps | ||
T259 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1010875925 | May 05 01:03:23 PM PDT 24 | May 05 01:03:24 PM PDT 24 | 185802899 ps | ||
T260 | /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.1174983527 | May 05 01:03:53 PM PDT 24 | May 05 01:03:56 PM PDT 24 | 118039533 ps | ||
T261 | /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2281091173 | May 05 01:03:36 PM PDT 24 | May 05 01:03:38 PM PDT 24 | 31890509 ps | ||
T262 | /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.776870294 | May 05 01:04:00 PM PDT 24 | May 05 01:04:03 PM PDT 24 | 44975850 ps | ||
T263 | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.22150968 | May 05 01:03:47 PM PDT 24 | May 05 01:03:50 PM PDT 24 | 1008066060 ps | ||
T264 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.4015978883 | May 05 01:03:36 PM PDT 24 | May 05 01:04:09 PM PDT 24 | 2550454848 ps | ||
T265 | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.3896757824 | May 05 01:03:42 PM PDT 24 | May 05 01:03:44 PM PDT 24 | 179647018 ps | ||
T266 | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.781614078 | May 05 01:04:05 PM PDT 24 | May 05 01:04:06 PM PDT 24 | 172264270 ps | ||
T267 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2685689754 | May 05 01:03:23 PM PDT 24 | May 05 01:03:25 PM PDT 24 | 51447778 ps | ||
T85 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.4038745646 | May 05 01:03:33 PM PDT 24 | May 05 01:03:36 PM PDT 24 | 775606083 ps | ||
T268 | /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.3420895619 | May 05 01:03:32 PM PDT 24 | May 05 01:03:33 PM PDT 24 | 17972865 ps | ||
T269 | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.3191584675 | May 05 01:03:55 PM PDT 24 | May 05 01:03:58 PM PDT 24 | 1312113869 ps | ||
T270 | /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3534207965 | May 05 01:04:04 PM PDT 24 | May 05 01:04:25 PM PDT 24 | 9325803612 ps | ||
T271 | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1121890418 | May 05 01:04:01 PM PDT 24 | May 05 01:04:03 PM PDT 24 | 953383900 ps | ||
T119 | /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.135910270 | May 05 01:03:21 PM PDT 24 | May 05 01:03:32 PM PDT 24 | 826414430 ps | ||
T120 | /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1156096931 | May 05 01:03:36 PM PDT 24 | May 05 01:03:51 PM PDT 24 | 1337661125 ps | ||
T272 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1391954688 | May 05 01:03:25 PM PDT 24 | May 05 01:03:31 PM PDT 24 | 2985631445 ps | ||
T273 | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.41552071 | May 05 01:03:59 PM PDT 24 | May 05 01:04:01 PM PDT 24 | 97175807 ps | ||
T274 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.824547827 | May 05 01:03:17 PM PDT 24 | May 05 01:03:20 PM PDT 24 | 1951279470 ps | ||
T275 | /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.324393740 | May 05 01:03:28 PM PDT 24 | May 05 01:03:31 PM PDT 24 | 342260163 ps | ||
T276 | /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1910158919 | May 05 01:04:04 PM PDT 24 | May 05 01:04:14 PM PDT 24 | 2130655150 ps | ||
T277 | /workspace/coverage/cover_reg_top/35.rv_dm_tap_fsm_rand_reset.3730626445 | May 05 01:04:12 PM PDT 24 | May 05 01:04:49 PM PDT 24 | 18032576689 ps | ||
T116 | /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.2595086613 | May 05 01:03:47 PM PDT 24 | May 05 01:04:21 PM PDT 24 | 17635631468 ps | ||
T278 | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2959132259 | May 05 01:04:06 PM PDT 24 | May 05 01:04:07 PM PDT 24 | 20511407 ps | ||
T279 | /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.3943448639 | May 05 01:03:28 PM PDT 24 | May 05 01:03:30 PM PDT 24 | 40120168 ps | ||
T280 | /workspace/coverage/cover_reg_top/21.rv_dm_tap_fsm_rand_reset.1514525806 | May 05 01:04:05 PM PDT 24 | May 05 01:04:35 PM PDT 24 | 26284420648 ps | ||
T281 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.3145139152 | May 05 01:03:34 PM PDT 24 | May 05 01:05:40 PM PDT 24 | 41897190843 ps | ||
T282 | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.3122984917 | May 05 01:04:06 PM PDT 24 | May 05 01:04:08 PM PDT 24 | 130192946 ps | ||
T283 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1005725327 | May 05 01:03:22 PM PDT 24 | May 05 01:03:23 PM PDT 24 | 74645496 ps | ||
T284 | /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.4259595016 | May 05 01:03:43 PM PDT 24 | May 05 01:03:48 PM PDT 24 | 170651105 ps | ||
T285 | /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2391237000 | May 05 01:03:21 PM PDT 24 | May 05 01:03:26 PM PDT 24 | 257330745 ps | ||
T107 | /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.4079166008 | May 05 01:04:05 PM PDT 24 | May 05 01:04:07 PM PDT 24 | 89296520 ps | ||
T98 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.804913428 | May 05 01:03:32 PM PDT 24 | May 05 01:04:03 PM PDT 24 | 3339703643 ps | ||
T286 | /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.3976849520 | May 05 01:04:02 PM PDT 24 | May 05 01:04:04 PM PDT 24 | 56704702 ps | ||
T287 | /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.2001534627 | May 05 01:03:49 PM PDT 24 | May 05 01:03:53 PM PDT 24 | 1704521959 ps | ||
T288 | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.4080062884 | May 05 01:03:54 PM PDT 24 | May 05 01:03:56 PM PDT 24 | 35970767 ps | ||
T289 | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1473526451 | May 05 01:03:50 PM PDT 24 | May 05 01:03:51 PM PDT 24 | 45714594 ps | ||
T290 | /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.917047296 | May 05 01:03:38 PM PDT 24 | May 05 01:03:42 PM PDT 24 | 757921905 ps | ||
T291 | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.2340355786 | May 05 01:03:39 PM PDT 24 | May 05 01:03:41 PM PDT 24 | 224193093 ps | ||
T292 | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.927294009 | May 05 01:04:00 PM PDT 24 | May 05 01:04:02 PM PDT 24 | 24135061 ps | ||
T293 | /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.993008334 | May 05 01:03:55 PM PDT 24 | May 05 01:03:59 PM PDT 24 | 366061068 ps | ||
T294 | /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.914670109 | May 05 01:04:07 PM PDT 24 | May 05 01:04:10 PM PDT 24 | 56146231 ps | ||
T295 | /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.2318044144 | May 05 01:04:01 PM PDT 24 | May 05 01:04:07 PM PDT 24 | 5692399740 ps | ||
T86 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.877801307 | May 05 01:03:36 PM PDT 24 | May 05 01:03:41 PM PDT 24 | 1974320144 ps | ||
T296 | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.3531782386 | May 05 01:03:39 PM PDT 24 | May 05 01:03:42 PM PDT 24 | 238704781 ps | ||
T297 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2984670898 | May 05 01:03:29 PM PDT 24 | May 05 01:04:00 PM PDT 24 | 1773937484 ps | ||
T298 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.185227202 | May 05 01:03:28 PM PDT 24 | May 05 01:03:55 PM PDT 24 | 1423405129 ps | ||
T299 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3585930718 | May 05 01:03:35 PM PDT 24 | May 05 01:03:38 PM PDT 24 | 1009570225 ps | ||
T300 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1791201510 | May 05 01:03:15 PM PDT 24 | May 05 01:05:14 PM PDT 24 | 34076663536 ps | ||
T301 | /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1650525006 | May 05 01:03:37 PM PDT 24 | May 05 01:03:38 PM PDT 24 | 63788606 ps | ||
T302 | /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2018468078 | May 05 01:03:48 PM PDT 24 | May 05 01:03:51 PM PDT 24 | 139635240 ps | ||
T303 | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2870123343 | May 05 01:04:06 PM PDT 24 | May 05 01:04:10 PM PDT 24 | 1033229283 ps | ||
T304 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1433036131 | May 05 01:03:17 PM PDT 24 | May 05 01:03:45 PM PDT 24 | 8344566368 ps | ||
T305 | /workspace/coverage/cover_reg_top/11.rv_dm_tap_fsm_rand_reset.1587224157 | May 05 01:03:53 PM PDT 24 | May 05 01:04:07 PM PDT 24 | 5785577684 ps | ||
T306 | /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.527770952 | May 05 01:04:09 PM PDT 24 | May 05 01:04:12 PM PDT 24 | 167655153 ps | ||
T307 | /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.709784058 | May 05 01:03:41 PM PDT 24 | May 05 01:03:48 PM PDT 24 | 4627338027 ps | ||
T308 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.2741350826 | May 05 01:03:28 PM PDT 24 | May 05 01:03:31 PM PDT 24 | 956733060 ps | ||
T309 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3127106298 | May 05 01:03:16 PM PDT 24 | May 05 01:03:18 PM PDT 24 | 94198672 ps | ||
T310 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.1322718893 | May 05 01:03:22 PM PDT 24 | May 05 01:04:10 PM PDT 24 | 18118835570 ps | ||
T311 | /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.3415582361 | May 05 01:04:07 PM PDT 24 | May 05 01:04:12 PM PDT 24 | 215113387 ps | ||
T312 | /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3603152354 | May 05 01:04:05 PM PDT 24 | May 05 01:04:08 PM PDT 24 | 69792542 ps | ||
T313 | /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.3369980073 | May 05 01:03:23 PM PDT 24 | May 05 01:03:39 PM PDT 24 | 730942180 ps | ||
T314 | /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.3766313634 | May 05 01:04:07 PM PDT 24 | May 05 01:04:09 PM PDT 24 | 74477484 ps | ||
T315 | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.1024169083 | May 05 01:03:56 PM PDT 24 | May 05 01:04:00 PM PDT 24 | 1722642884 ps |
Test location | /workspace/coverage/default/25.rv_dm_stress_all.1397792311 |
Short name | T7 |
Test name | |
Test status | |
Simulation time | 10428508253 ps |
CPU time | 8.3 seconds |
Started | May 05 01:05:03 PM PDT 24 |
Finished | May 05 01:05:12 PM PDT 24 |
Peak memory | 205412 kb |
Host | smart-1381900f-7eed-4b34-9799-d35ee8d2c660 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397792311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.1397792311 |
Directory | /workspace/25.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.3032248613 |
Short name | T25 |
Test name | |
Test status | |
Simulation time | 2519298897 ps |
CPU time | 5.04 seconds |
Started | May 05 01:04:56 PM PDT 24 |
Finished | May 05 01:05:02 PM PDT 24 |
Peak memory | 205564 kb |
Host | smart-1954825f-092f-49d8-9f32-036a8af9d71c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3032248613 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.3032248613 |
Directory | /workspace/19.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/cover_reg_top/36.rv_dm_tap_fsm_rand_reset.103516953 |
Short name | T39 |
Test name | |
Test status | |
Simulation time | 6496832568 ps |
CPU time | 22.3 seconds |
Started | May 05 01:04:11 PM PDT 24 |
Finished | May 05 01:04:34 PM PDT 24 |
Peak memory | 218804 kb |
Host | smart-7c6bd542-47d2-4f4f-a550-b09a0042799e |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103516953 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 36.rv_dm_tap_fsm_rand_reset.103516953 |
Directory | /workspace/36.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/default/7.rv_dm_stress_all.666469584 |
Short name | T34 |
Test name | |
Test status | |
Simulation time | 4356474355 ps |
CPU time | 13.92 seconds |
Started | May 05 01:04:39 PM PDT 24 |
Finished | May 05 01:04:54 PM PDT 24 |
Peak memory | 213620 kb |
Host | smart-1e64dd2a-7b7f-4622-bbdb-9dfa1678ea9f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666469584 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.666469584 |
Directory | /workspace/7.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/29.rv_dm_alert_test.72595471 |
Short name | T33 |
Test name | |
Test status | |
Simulation time | 32794963 ps |
CPU time | 0.73 seconds |
Started | May 05 01:05:10 PM PDT 24 |
Finished | May 05 01:05:11 PM PDT 24 |
Peak memory | 205104 kb |
Host | smart-42ea6818-81d6-49a0-a21a-64622e4c8b32 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72595471 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.72595471 |
Directory | /workspace/29.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/6.rv_dm_stress_all.3373471722 |
Short name | T10 |
Test name | |
Test status | |
Simulation time | 3116748930 ps |
CPU time | 6.92 seconds |
Started | May 05 01:04:39 PM PDT 24 |
Finished | May 05 01:04:47 PM PDT 24 |
Peak memory | 205436 kb |
Host | smart-70486d4c-f900-424d-bded-77fc2bf226cc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373471722 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.3373471722 |
Directory | /workspace/6.rv_dm_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.2081762813 |
Short name | T68 |
Test name | |
Test status | |
Simulation time | 481552987 ps |
CPU time | 15.63 seconds |
Started | May 05 01:03:23 PM PDT 24 |
Finished | May 05 01:03:39 PM PDT 24 |
Peak memory | 221288 kb |
Host | smart-0057d80e-56df-4808-8461-459e3f94b18f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081762813 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.2081762813 |
Directory | /workspace/0.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.rv_dm_tap_fsm.342596065 |
Short name | T58 |
Test name | |
Test status | |
Simulation time | 1902370103 ps |
CPU time | 7.23 seconds |
Started | May 05 01:04:10 PM PDT 24 |
Finished | May 05 01:04:18 PM PDT 24 |
Peak memory | 205276 kb |
Host | smart-0bfcaa1a-4621-4505-83b1-43002a5b27c0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=342596065 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.342596065 |
Directory | /workspace/0.rv_dm_tap_fsm/latest |
Test location | /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.840320542 |
Short name | T28 |
Test name | |
Test status | |
Simulation time | 28356436281 ps |
CPU time | 17.55 seconds |
Started | May 05 01:04:46 PM PDT 24 |
Finished | May 05 01:05:04 PM PDT 24 |
Peak memory | 213740 kb |
Host | smart-aa31ac2a-065d-424b-96f5-265201c64759 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=840320542 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.840320542 |
Directory | /workspace/11.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.3394972879 |
Short name | T43 |
Test name | |
Test status | |
Simulation time | 1153646390 ps |
CPU time | 17.78 seconds |
Started | May 05 01:03:55 PM PDT 24 |
Finished | May 05 01:04:14 PM PDT 24 |
Peak memory | 221292 kb |
Host | smart-828452a4-604e-4e5f-845d-a9463979033a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394972879 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.3 394972879 |
Directory | /workspace/10.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.2302751716 |
Short name | T97 |
Test name | |
Test status | |
Simulation time | 1702352015 ps |
CPU time | 27.14 seconds |
Started | May 05 01:03:28 PM PDT 24 |
Finished | May 05 01:03:56 PM PDT 24 |
Peak memory | 204868 kb |
Host | smart-25a90452-e7a7-47cd-ad34-e84528146fd2 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302751716 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 1.rv_dm_csr_aliasing.2302751716 |
Directory | /workspace/1.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/default/0.rv_dm_sec_cm.1037855085 |
Short name | T30 |
Test name | |
Test status | |
Simulation time | 308948019 ps |
CPU time | 1.17 seconds |
Started | May 05 01:04:22 PM PDT 24 |
Finished | May 05 01:04:24 PM PDT 24 |
Peak memory | 229704 kb |
Host | smart-41dae9e5-a352-427c-95a7-1471c1eeff79 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037855085 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.1037855085 |
Directory | /workspace/0.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.2370557237 |
Short name | T26 |
Test name | |
Test status | |
Simulation time | 3304354316 ps |
CPU time | 6 seconds |
Started | May 05 01:04:39 PM PDT 24 |
Finished | May 05 01:04:46 PM PDT 24 |
Peak memory | 205504 kb |
Host | smart-bc34766e-1252-4cc6-b91d-361934cb5511 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2370557237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t l_access.2370557237 |
Directory | /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3914059008 |
Short name | T77 |
Test name | |
Test status | |
Simulation time | 808565096 ps |
CPU time | 4.11 seconds |
Started | May 05 01:03:49 PM PDT 24 |
Finished | May 05 01:03:54 PM PDT 24 |
Peak memory | 204936 kb |
Host | smart-d1bc5e2f-7af1-455f-9864-d11a48ecd7ec |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914059008 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_ csr_outstanding.3914059008 |
Directory | /workspace/7.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/default/0.rv_dm_abstractcmd_status.2994956272 |
Short name | T11 |
Test name | |
Test status | |
Simulation time | 110137198 ps |
CPU time | 0.76 seconds |
Started | May 05 01:04:26 PM PDT 24 |
Finished | May 05 01:04:27 PM PDT 24 |
Peak memory | 205128 kb |
Host | smart-1afffd0d-051b-43b0-ba7d-023edfaf041b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2994956272 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.2994956272 |
Directory | /workspace/0.rv_dm_abstractcmd_status/latest |
Test location | /workspace/coverage/default/0.rv_dm_rom_read_access.3094980378 |
Short name | T15 |
Test name | |
Test status | |
Simulation time | 52310085 ps |
CPU time | 0.83 seconds |
Started | May 05 01:04:22 PM PDT 24 |
Finished | May 05 01:04:23 PM PDT 24 |
Peak memory | 213308 kb |
Host | smart-c804924b-154a-495d-b9f4-dbef3c45a697 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3094980378 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.3094980378 |
Directory | /workspace/0.rv_dm_rom_read_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_exception.3703314898 |
Short name | T20 |
Test name | |
Test status | |
Simulation time | 783554176 ps |
CPU time | 0.94 seconds |
Started | May 05 01:04:14 PM PDT 24 |
Finished | May 05 01:04:15 PM PDT 24 |
Peak memory | 205144 kb |
Host | smart-b0baf185-2742-4408-b9bf-7ad77ef60490 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3703314898 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.3703314898 |
Directory | /workspace/0.rv_dm_cmderr_exception/latest |
Test location | /workspace/coverage/default/0.rv_dm_progbuf_busy.1266389534 |
Short name | T12 |
Test name | |
Test status | |
Simulation time | 653853336 ps |
CPU time | 1.89 seconds |
Started | May 05 01:04:22 PM PDT 24 |
Finished | May 05 01:04:25 PM PDT 24 |
Peak memory | 205392 kb |
Host | smart-78fcf6db-8928-4357-ad2e-bab6906fda27 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1266389534 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.1266389534 |
Directory | /workspace/0.rv_dm_progbuf_busy/latest |
Test location | /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.1809413301 |
Short name | T22 |
Test name | |
Test status | |
Simulation time | 60434100 ps |
CPU time | 0.75 seconds |
Started | May 05 01:04:21 PM PDT 24 |
Finished | May 05 01:04:22 PM PDT 24 |
Peak memory | 205156 kb |
Host | smart-965db5ac-f345-440b-8299-4834fe2e9059 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1809413301 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.1809413301 |
Directory | /workspace/0.rv_dm_progbuf_read_write_execute/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3285557727 |
Short name | T121 |
Test name | |
Test status | |
Simulation time | 362874962 ps |
CPU time | 8.34 seconds |
Started | May 05 01:04:00 PM PDT 24 |
Finished | May 05 01:04:10 PM PDT 24 |
Peak memory | 221252 kb |
Host | smart-0e24b588-299c-4492-89de-daa6a6234f1c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285557727 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.3 285557727 |
Directory | /workspace/13.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2632861580 |
Short name | T182 |
Test name | |
Test status | |
Simulation time | 348244297 ps |
CPU time | 0.84 seconds |
Started | May 05 01:03:21 PM PDT 24 |
Finished | May 05 01:03:22 PM PDT 24 |
Peak memory | 204572 kb |
Host | smart-59d88ca3-6f3d-4475-9ae1-e88a7cb70eb8 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632861580 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_aliasing.2632861580 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3244555750 |
Short name | T60 |
Test name | |
Test status | |
Simulation time | 3422888749 ps |
CPU time | 4.52 seconds |
Started | May 05 01:03:54 PM PDT 24 |
Finished | May 05 01:03:59 PM PDT 24 |
Peak memory | 217912 kb |
Host | smart-1c511234-061c-4bf9-b2d9-db31cf8d357c |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244555750 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.3244555750 |
Directory | /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.3978002296 |
Short name | T103 |
Test name | |
Test status | |
Simulation time | 753755946 ps |
CPU time | 27.99 seconds |
Started | May 05 01:03:19 PM PDT 24 |
Finished | May 05 01:03:48 PM PDT 24 |
Peak memory | 204972 kb |
Host | smart-39a4a22a-6ab1-4208-a74d-28ca86c44971 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978002296 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.3978002296 |
Directory | /workspace/0.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.183610986 |
Short name | T123 |
Test name | |
Test status | |
Simulation time | 1183624792 ps |
CPU time | 9.73 seconds |
Started | May 05 01:03:40 PM PDT 24 |
Finished | May 05 01:03:51 PM PDT 24 |
Peak memory | 213008 kb |
Host | smart-693a7034-6f03-430c-8605-2aab37d6db2f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183610986 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.183610986 |
Directory | /workspace/5.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.1275463381 |
Short name | T83 |
Test name | |
Test status | |
Simulation time | 3022580528 ps |
CPU time | 4.25 seconds |
Started | May 05 01:03:17 PM PDT 24 |
Finished | May 05 01:03:22 PM PDT 24 |
Peak memory | 204916 kb |
Host | smart-1ffb1c4c-f506-4960-b8b3-beeec4626dce |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275463381 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs r_hw_reset.1275463381 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/default/12.rv_dm_alert_test.1824802265 |
Short name | T56 |
Test name | |
Test status | |
Simulation time | 49728673 ps |
CPU time | 0.74 seconds |
Started | May 05 01:04:48 PM PDT 24 |
Finished | May 05 01:04:50 PM PDT 24 |
Peak memory | 205124 kb |
Host | smart-e7dcf3f1-5508-4f8d-8711-9f40a06493d5 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824802265 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.1824802265 |
Directory | /workspace/12.rv_dm_alert_test/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.3176410029 |
Short name | T117 |
Test name | |
Test status | |
Simulation time | 3932670521 ps |
CPU time | 18.96 seconds |
Started | May 05 01:04:07 PM PDT 24 |
Finished | May 05 01:04:27 PM PDT 24 |
Peak memory | 221328 kb |
Host | smart-15825adf-beaa-4904-a5b5-c406b9edf85a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176410029 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.3 176410029 |
Directory | /workspace/17.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_busy.2221135832 |
Short name | T24 |
Test name | |
Test status | |
Simulation time | 6560011652 ps |
CPU time | 2.73 seconds |
Started | May 05 01:04:28 PM PDT 24 |
Finished | May 05 01:04:32 PM PDT 24 |
Peak memory | 205696 kb |
Host | smart-c7ae95d5-7eba-4e66-8fa3-d0ab2d5b0759 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2221135832 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.2221135832 |
Directory | /workspace/1.rv_dm_cmderr_busy/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.3782515712 |
Short name | T8 |
Test name | |
Test status | |
Simulation time | 377381759 ps |
CPU time | 1.73 seconds |
Started | May 05 01:04:28 PM PDT 24 |
Finished | May 05 01:04:30 PM PDT 24 |
Peak memory | 204988 kb |
Host | smart-727a3f96-c6aa-4bf1-8e00-0ba1457dc7fa |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3782515712 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.3782515712 |
Directory | /workspace/1.rv_dm_cmderr_halt_resume/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_tap_fsm_rand_reset.1587224157 |
Short name | T305 |
Test name | |
Test status | |
Simulation time | 5785577684 ps |
CPU time | 13.39 seconds |
Started | May 05 01:03:53 PM PDT 24 |
Finished | May 05 01:04:07 PM PDT 24 |
Peak memory | 221300 kb |
Host | smart-22728487-a741-4296-b45a-657304733a00 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587224157 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 11.rv_dm_tap_fsm_rand_reset.1587224157 |
Directory | /workspace/11.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1205945370 |
Short name | T92 |
Test name | |
Test status | |
Simulation time | 1881357296 ps |
CPU time | 30.55 seconds |
Started | May 05 01:03:19 PM PDT 24 |
Finished | May 05 01:03:50 PM PDT 24 |
Peak memory | 214164 kb |
Host | smart-de371e6b-f422-4407-8424-83b437f0d382 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205945370 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 0.rv_dm_csr_aliasing.1205945370 |
Directory | /workspace/0.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.4098397075 |
Short name | T105 |
Test name | |
Test status | |
Simulation time | 189336854 ps |
CPU time | 2.42 seconds |
Started | May 05 01:03:21 PM PDT 24 |
Finished | May 05 01:03:24 PM PDT 24 |
Peak memory | 213152 kb |
Host | smart-cee6c6d7-02a1-4db4-be53-8c0db21555a9 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098397075 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.4098397075 |
Directory | /workspace/0.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1320269015 |
Short name | T193 |
Test name | |
Test status | |
Simulation time | 488019911 ps |
CPU time | 3.6 seconds |
Started | May 05 01:03:16 PM PDT 24 |
Finished | May 05 01:03:20 PM PDT 24 |
Peak memory | 217256 kb |
Host | smart-c10ce75d-9dd1-48b3-a9ac-a16f31019712 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320269015 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.1320269015 |
Directory | /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2685689754 |
Short name | T267 |
Test name | |
Test status | |
Simulation time | 51447778 ps |
CPU time | 1.55 seconds |
Started | May 05 01:03:23 PM PDT 24 |
Finished | May 05 01:03:25 PM PDT 24 |
Peak memory | 220452 kb |
Host | smart-2bae19a9-d11f-4316-8be1-78d96aa8470f |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685689754 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.2685689754 |
Directory | /workspace/0.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.4260640925 |
Short name | T196 |
Test name | |
Test status | |
Simulation time | 12696704845 ps |
CPU time | 15.61 seconds |
Started | May 05 01:03:16 PM PDT 24 |
Finished | May 05 01:03:32 PM PDT 24 |
Peak memory | 204880 kb |
Host | smart-19038277-63b2-4bcd-a88b-c7d3553e1d45 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260640925 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs r_aliasing.4260640925 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1791201510 |
Short name | T300 |
Test name | |
Test status | |
Simulation time | 34076663536 ps |
CPU time | 118.04 seconds |
Started | May 05 01:03:15 PM PDT 24 |
Finished | May 05 01:05:14 PM PDT 24 |
Peak memory | 204832 kb |
Host | smart-ee814e29-57a4-41ad-83cb-976f4ca62e13 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791201510 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs r_bit_bash.1791201510 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3991564278 |
Short name | T194 |
Test name | |
Test status | |
Simulation time | 324581016 ps |
CPU time | 1.54 seconds |
Started | May 05 01:03:18 PM PDT 24 |
Finished | May 05 01:03:20 PM PDT 24 |
Peak memory | 204808 kb |
Host | smart-e001ae5f-b8ef-4895-9b9b-81595e9765ea |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991564278 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.3 991564278 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.824547827 |
Short name | T274 |
Test name | |
Test status | |
Simulation time | 1951279470 ps |
CPU time | 3.08 seconds |
Started | May 05 01:03:17 PM PDT 24 |
Finished | May 05 01:03:20 PM PDT 24 |
Peak memory | 204832 kb |
Host | smart-f0106eb3-63d3-43a5-8c6c-0d727f54329b |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824547827 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr _bit_bash.824547827 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.1517101028 |
Short name | T216 |
Test name | |
Test status | |
Simulation time | 72600380 ps |
CPU time | 0.67 seconds |
Started | May 05 01:03:17 PM PDT 24 |
Finished | May 05 01:03:19 PM PDT 24 |
Peak memory | 204664 kb |
Host | smart-887f2710-a9de-45f9-b104-168ee93e7595 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517101028 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_hw_reset.1517101028 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3339528447 |
Short name | T248 |
Test name | |
Test status | |
Simulation time | 145398782 ps |
CPU time | 0.66 seconds |
Started | May 05 01:03:19 PM PDT 24 |
Finished | May 05 01:03:21 PM PDT 24 |
Peak memory | 204584 kb |
Host | smart-be90b780-190c-4785-96c3-9bb4d025ac24 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339528447 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.3 339528447 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.2478539481 |
Short name | T214 |
Test name | |
Test status | |
Simulation time | 218995621 ps |
CPU time | 0.74 seconds |
Started | May 05 01:03:28 PM PDT 24 |
Finished | May 05 01:03:30 PM PDT 24 |
Peak memory | 204508 kb |
Host | smart-09ee1fc2-f7c5-467c-8326-9bccd79b6eec |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478539481 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par tial_access.2478539481 |
Directory | /workspace/0.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.820463018 |
Short name | T178 |
Test name | |
Test status | |
Simulation time | 22396263 ps |
CPU time | 0.66 seconds |
Started | May 05 01:03:27 PM PDT 24 |
Finished | May 05 01:03:29 PM PDT 24 |
Peak memory | 204548 kb |
Host | smart-d7131634-436d-46e3-98f4-a44b64cbd8e2 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820463018 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.820463018 |
Directory | /workspace/0.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.498921502 |
Short name | T91 |
Test name | |
Test status | |
Simulation time | 2030530978 ps |
CPU time | 4.28 seconds |
Started | May 05 01:03:18 PM PDT 24 |
Finished | May 05 01:03:23 PM PDT 24 |
Peak memory | 204896 kb |
Host | smart-c2050847-1eab-416a-825c-dbf32cc30519 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498921502 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_c sr_outstanding.498921502 |
Directory | /workspace/0.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.100588898 |
Short name | T40 |
Test name | |
Test status | |
Simulation time | 14783636041 ps |
CPU time | 46.48 seconds |
Started | May 05 01:03:17 PM PDT 24 |
Finished | May 05 01:04:04 PM PDT 24 |
Peak memory | 220784 kb |
Host | smart-aa488c13-3b4b-4446-b67e-67752840c053 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100588898 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.100588898 |
Directory | /workspace/0.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.3622538679 |
Short name | T203 |
Test name | |
Test status | |
Simulation time | 309612500 ps |
CPU time | 4.56 seconds |
Started | May 05 01:03:19 PM PDT 24 |
Finished | May 05 01:03:25 PM PDT 24 |
Peak memory | 213184 kb |
Host | smart-6fe961e0-5c18-48de-8b66-9884a079712a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622538679 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.3622538679 |
Directory | /workspace/0.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.3046090877 |
Short name | T81 |
Test name | |
Test status | |
Simulation time | 7367086905 ps |
CPU time | 69.31 seconds |
Started | May 05 01:03:21 PM PDT 24 |
Finished | May 05 01:04:31 PM PDT 24 |
Peak memory | 205072 kb |
Host | smart-4ecbed17-ca8f-4512-8339-b62be17968fc |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046090877 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.3046090877 |
Directory | /workspace/1.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.3909480856 |
Short name | T79 |
Test name | |
Test status | |
Simulation time | 143870357 ps |
CPU time | 2.5 seconds |
Started | May 05 01:03:16 PM PDT 24 |
Finished | May 05 01:03:19 PM PDT 24 |
Peak memory | 213092 kb |
Host | smart-0892255f-d999-451d-8aff-cdd294f32905 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909480856 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.3909480856 |
Directory | /workspace/1.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.702291975 |
Short name | T206 |
Test name | |
Test status | |
Simulation time | 1580595950 ps |
CPU time | 2.85 seconds |
Started | May 05 01:03:21 PM PDT 24 |
Finished | May 05 01:03:25 PM PDT 24 |
Peak memory | 217320 kb |
Host | smart-2623d9e1-25ef-4683-9bb7-4f6c4093948a |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702291975 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.702291975 |
Directory | /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2599170403 |
Short name | T99 |
Test name | |
Test status | |
Simulation time | 50916659 ps |
CPU time | 1.5 seconds |
Started | May 05 01:03:19 PM PDT 24 |
Finished | May 05 01:03:22 PM PDT 24 |
Peak memory | 213060 kb |
Host | smart-ec24c296-e0ff-4be2-b8fc-e119b2426882 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599170403 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.2599170403 |
Directory | /workspace/1.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1433036131 |
Short name | T304 |
Test name | |
Test status | |
Simulation time | 8344566368 ps |
CPU time | 27.86 seconds |
Started | May 05 01:03:17 PM PDT 24 |
Finished | May 05 01:03:45 PM PDT 24 |
Peak memory | 204916 kb |
Host | smart-9b4e5b1a-fc53-43c6-bca9-e0d3b8477939 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433036131 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs r_aliasing.1433036131 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.367303101 |
Short name | T185 |
Test name | |
Test status | |
Simulation time | 14487769274 ps |
CPU time | 16.56 seconds |
Started | May 05 01:03:17 PM PDT 24 |
Finished | May 05 01:03:34 PM PDT 24 |
Peak memory | 204848 kb |
Host | smart-6c2d5102-738d-475c-a390-07f22f6e9bf6 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367303101 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr _bit_bash.367303101 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.4291185722 |
Short name | T84 |
Test name | |
Test status | |
Simulation time | 329656393 ps |
CPU time | 2.01 seconds |
Started | May 05 01:03:20 PM PDT 24 |
Finished | May 05 01:03:23 PM PDT 24 |
Peak memory | 204820 kb |
Host | smart-15d0d57d-271d-4bab-9007-180514b0ec7c |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291185722 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs r_hw_reset.4291185722 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.983088906 |
Short name | T217 |
Test name | |
Test status | |
Simulation time | 832368533 ps |
CPU time | 1.7 seconds |
Started | May 05 01:03:20 PM PDT 24 |
Finished | May 05 01:03:22 PM PDT 24 |
Peak memory | 204724 kb |
Host | smart-dc7f417b-e41e-4810-9dc7-4666076192b5 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983088906 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.983088906 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3718871200 |
Short name | T189 |
Test name | |
Test status | |
Simulation time | 73065450 ps |
CPU time | 0.92 seconds |
Started | May 05 01:03:18 PM PDT 24 |
Finished | May 05 01:03:20 PM PDT 24 |
Peak memory | 204536 kb |
Host | smart-89b0b397-34b9-4b66-80d2-1a53a6749a53 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718871200 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_aliasing.3718871200 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.1808112464 |
Short name | T202 |
Test name | |
Test status | |
Simulation time | 1515341470 ps |
CPU time | 3.59 seconds |
Started | May 05 01:03:19 PM PDT 24 |
Finished | May 05 01:03:24 PM PDT 24 |
Peak memory | 204804 kb |
Host | smart-5e0204b7-6dc0-4e57-81d1-827451a9aadf |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808112464 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_bit_bash.1808112464 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1010875925 |
Short name | T259 |
Test name | |
Test status | |
Simulation time | 185802899 ps |
CPU time | 1.07 seconds |
Started | May 05 01:03:23 PM PDT 24 |
Finished | May 05 01:03:24 PM PDT 24 |
Peak memory | 204312 kb |
Host | smart-29603942-6968-4358-82cb-d6da9aeac34a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010875925 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_hw_reset.1010875925 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3127106298 |
Short name | T309 |
Test name | |
Test status | |
Simulation time | 94198672 ps |
CPU time | 0.79 seconds |
Started | May 05 01:03:16 PM PDT 24 |
Finished | May 05 01:03:18 PM PDT 24 |
Peak memory | 204552 kb |
Host | smart-2cb27a8b-07c1-455a-a61c-e76139e71147 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127106298 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.3 127106298 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3316483249 |
Short name | T192 |
Test name | |
Test status | |
Simulation time | 21112766 ps |
CPU time | 0.73 seconds |
Started | May 05 01:03:28 PM PDT 24 |
Finished | May 05 01:03:30 PM PDT 24 |
Peak memory | 204548 kb |
Host | smart-b0560160-7dbc-4e29-b349-2636644af114 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316483249 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par tial_access.3316483249 |
Directory | /workspace/1.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.3943448639 |
Short name | T279 |
Test name | |
Test status | |
Simulation time | 40120168 ps |
CPU time | 0.73 seconds |
Started | May 05 01:03:28 PM PDT 24 |
Finished | May 05 01:03:30 PM PDT 24 |
Peak memory | 204548 kb |
Host | smart-053939d8-2edf-4051-bfef-d7dd948f58b7 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943448639 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.3943448639 |
Directory | /workspace/1.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2391237000 |
Short name | T285 |
Test name | |
Test status | |
Simulation time | 257330745 ps |
CPU time | 4.2 seconds |
Started | May 05 01:03:21 PM PDT 24 |
Finished | May 05 01:03:26 PM PDT 24 |
Peak memory | 204888 kb |
Host | smart-a8388d3a-bf1f-4400-ba52-1440312b5612 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391237000 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_ csr_outstanding.2391237000 |
Directory | /workspace/1.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1304061388 |
Short name | T67 |
Test name | |
Test status | |
Simulation time | 60762555 ps |
CPU time | 3.41 seconds |
Started | May 05 01:03:28 PM PDT 24 |
Finished | May 05 01:03:32 PM PDT 24 |
Peak memory | 213156 kb |
Host | smart-abc49640-1fbb-4c2e-8cec-db29f8971e66 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304061388 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.1304061388 |
Directory | /workspace/1.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.3369980073 |
Short name | T313 |
Test name | |
Test status | |
Simulation time | 730942180 ps |
CPU time | 15.72 seconds |
Started | May 05 01:03:23 PM PDT 24 |
Finished | May 05 01:03:39 PM PDT 24 |
Peak memory | 212324 kb |
Host | smart-5f15d4eb-d0d6-46c9-b49b-5ea997c3ce60 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369980073 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.3369980073 |
Directory | /workspace/1.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.1174983527 |
Short name | T260 |
Test name | |
Test status | |
Simulation time | 118039533 ps |
CPU time | 2.42 seconds |
Started | May 05 01:03:53 PM PDT 24 |
Finished | May 05 01:03:56 PM PDT 24 |
Peak memory | 218388 kb |
Host | smart-7d33612d-93e8-491f-967e-dd4fbcb3f760 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174983527 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.1174983527 |
Directory | /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.2697853065 |
Short name | T218 |
Test name | |
Test status | |
Simulation time | 89878892 ps |
CPU time | 1.51 seconds |
Started | May 05 01:03:53 PM PDT 24 |
Finished | May 05 01:03:55 PM PDT 24 |
Peak memory | 221300 kb |
Host | smart-1ac0f274-8a7f-46ca-9504-4c2f353ec520 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697853065 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.2697853065 |
Directory | /workspace/10.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2393110340 |
Short name | T256 |
Test name | |
Test status | |
Simulation time | 213273759 ps |
CPU time | 1.17 seconds |
Started | May 05 01:03:55 PM PDT 24 |
Finished | May 05 01:03:57 PM PDT 24 |
Peak memory | 204972 kb |
Host | smart-bd1ed6e7-1cdb-4ee3-917a-0862b2a8cde6 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393110340 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw. 2393110340 |
Directory | /workspace/10.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.847858666 |
Short name | T61 |
Test name | |
Test status | |
Simulation time | 80289948 ps |
CPU time | 0.88 seconds |
Started | May 05 01:03:53 PM PDT 24 |
Finished | May 05 01:03:55 PM PDT 24 |
Peak memory | 204556 kb |
Host | smart-de6accaf-07f8-4d47-842c-7fd72c560527 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847858666 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.847858666 |
Directory | /workspace/10.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.2397782145 |
Short name | T247 |
Test name | |
Test status | |
Simulation time | 536646798 ps |
CPU time | 7.89 seconds |
Started | May 05 01:03:55 PM PDT 24 |
Finished | May 05 01:04:04 PM PDT 24 |
Peak memory | 204900 kb |
Host | smart-f9b97b0c-bc6a-40e7-a76c-f48165bdd6c5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397782145 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same _csr_outstanding.2397782145 |
Directory | /workspace/10.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_tap_fsm_rand_reset.1004152678 |
Short name | T258 |
Test name | |
Test status | |
Simulation time | 31816554083 ps |
CPU time | 28.35 seconds |
Started | May 05 01:03:53 PM PDT 24 |
Finished | May 05 01:04:22 PM PDT 24 |
Peak memory | 229616 kb |
Host | smart-89a89259-dcb9-432b-ad38-023eb753ff5e |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004152678 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 10.rv_dm_tap_fsm_rand_reset.1004152678 |
Directory | /workspace/10.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.2053341897 |
Short name | T72 |
Test name | |
Test status | |
Simulation time | 1048822640 ps |
CPU time | 3.55 seconds |
Started | May 05 01:03:54 PM PDT 24 |
Finished | May 05 01:03:59 PM PDT 24 |
Peak memory | 213192 kb |
Host | smart-5ff032b3-d0ff-4737-981e-2093f47f9252 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053341897 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.2053341897 |
Directory | /workspace/10.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.3734223936 |
Short name | T75 |
Test name | |
Test status | |
Simulation time | 94699520 ps |
CPU time | 1.56 seconds |
Started | May 05 01:03:56 PM PDT 24 |
Finished | May 05 01:03:59 PM PDT 24 |
Peak memory | 218432 kb |
Host | smart-d5c593f6-eaab-4ae1-846e-38da35f4be71 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734223936 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.3734223936 |
Directory | /workspace/11.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.1024169083 |
Short name | T315 |
Test name | |
Test status | |
Simulation time | 1722642884 ps |
CPU time | 2.8 seconds |
Started | May 05 01:03:56 PM PDT 24 |
Finished | May 05 01:04:00 PM PDT 24 |
Peak memory | 204808 kb |
Host | smart-09ad9ac4-ac4a-461d-aed6-6c21f5d74d34 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024169083 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw. 1024169083 |
Directory | /workspace/11.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.4080062884 |
Short name | T288 |
Test name | |
Test status | |
Simulation time | 35970767 ps |
CPU time | 0.71 seconds |
Started | May 05 01:03:54 PM PDT 24 |
Finished | May 05 01:03:56 PM PDT 24 |
Peak memory | 204568 kb |
Host | smart-9c15d3fe-26c2-4d6c-901b-1ae9c6abd1ea |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080062884 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw. 4080062884 |
Directory | /workspace/11.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.993008334 |
Short name | T293 |
Test name | |
Test status | |
Simulation time | 366061068 ps |
CPU time | 3.68 seconds |
Started | May 05 01:03:55 PM PDT 24 |
Finished | May 05 01:03:59 PM PDT 24 |
Peak memory | 204924 kb |
Host | smart-46a3d4cd-809d-44ba-9169-75a173e21dd0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993008334 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same_ csr_outstanding.993008334 |
Directory | /workspace/11.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.1833888078 |
Short name | T231 |
Test name | |
Test status | |
Simulation time | 98931664 ps |
CPU time | 2.83 seconds |
Started | May 05 01:03:56 PM PDT 24 |
Finished | May 05 01:03:59 PM PDT 24 |
Peak memory | 213100 kb |
Host | smart-485916ae-d22f-4322-936e-d4287ab76195 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833888078 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.1833888078 |
Directory | /workspace/11.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.266502346 |
Short name | T124 |
Test name | |
Test status | |
Simulation time | 683883760 ps |
CPU time | 10.35 seconds |
Started | May 05 01:03:55 PM PDT 24 |
Finished | May 05 01:04:06 PM PDT 24 |
Peak memory | 213160 kb |
Host | smart-7fec64c5-04aa-4a7c-b5a8-0d7e52586702 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266502346 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.266502346 |
Directory | /workspace/11.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.2080281124 |
Short name | T234 |
Test name | |
Test status | |
Simulation time | 1840722546 ps |
CPU time | 5.06 seconds |
Started | May 05 01:04:01 PM PDT 24 |
Finished | May 05 01:04:07 PM PDT 24 |
Peak memory | 213136 kb |
Host | smart-4541037a-74d2-49d9-823e-75d00853d971 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080281124 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.2080281124 |
Directory | /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.1328326410 |
Short name | T76 |
Test name | |
Test status | |
Simulation time | 161538273 ps |
CPU time | 2.25 seconds |
Started | May 05 01:03:53 PM PDT 24 |
Finished | May 05 01:03:55 PM PDT 24 |
Peak memory | 213184 kb |
Host | smart-67df332b-ca59-4804-868d-35266cafd10e |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328326410 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.1328326410 |
Directory | /workspace/12.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.3191584675 |
Short name | T269 |
Test name | |
Test status | |
Simulation time | 1312113869 ps |
CPU time | 2.09 seconds |
Started | May 05 01:03:55 PM PDT 24 |
Finished | May 05 01:03:58 PM PDT 24 |
Peak memory | 204736 kb |
Host | smart-b3a7d7b2-1646-47ff-8b3c-6a69b699bc44 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191584675 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw. 3191584675 |
Directory | /workspace/12.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.478359322 |
Short name | T212 |
Test name | |
Test status | |
Simulation time | 99604298 ps |
CPU time | 0.68 seconds |
Started | May 05 01:03:56 PM PDT 24 |
Finished | May 05 01:03:58 PM PDT 24 |
Peak memory | 204580 kb |
Host | smart-8719a722-a10d-4e4e-82f0-00f2d458ed4a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478359322 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.478359322 |
Directory | /workspace/12.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.88364662 |
Short name | T80 |
Test name | |
Test status | |
Simulation time | 207810420 ps |
CPU time | 4.02 seconds |
Started | May 05 01:03:54 PM PDT 24 |
Finished | May 05 01:03:59 PM PDT 24 |
Peak memory | 204952 kb |
Host | smart-7ec00402-0cca-45fa-9271-1b1e9dbeee4e |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88364662 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same_c sr_outstanding.88364662 |
Directory | /workspace/12.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.1969775483 |
Short name | T251 |
Test name | |
Test status | |
Simulation time | 405660867 ps |
CPU time | 5.28 seconds |
Started | May 05 01:03:54 PM PDT 24 |
Finished | May 05 01:04:00 PM PDT 24 |
Peak memory | 213148 kb |
Host | smart-e0eb808d-9843-497e-83e0-d4fae78ee981 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969775483 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.1969775483 |
Directory | /workspace/12.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2471491035 |
Short name | T122 |
Test name | |
Test status | |
Simulation time | 2233633303 ps |
CPU time | 16.31 seconds |
Started | May 05 01:03:54 PM PDT 24 |
Finished | May 05 01:04:11 PM PDT 24 |
Peak memory | 213184 kb |
Host | smart-0d2299aa-6f87-4925-97a1-08207066e869 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471491035 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.2 471491035 |
Directory | /workspace/12.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.2498665017 |
Short name | T190 |
Test name | |
Test status | |
Simulation time | 2334970026 ps |
CPU time | 5.04 seconds |
Started | May 05 01:04:04 PM PDT 24 |
Finished | May 05 01:04:10 PM PDT 24 |
Peak memory | 221444 kb |
Host | smart-a5305045-a900-4723-8485-d3b2e94d7653 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498665017 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.2498665017 |
Directory | /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.3453989600 |
Short name | T227 |
Test name | |
Test status | |
Simulation time | 133996046 ps |
CPU time | 1.53 seconds |
Started | May 05 01:04:00 PM PDT 24 |
Finished | May 05 01:04:03 PM PDT 24 |
Peak memory | 213116 kb |
Host | smart-0eb67e6d-7c80-4349-ade7-bfa52423d366 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453989600 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.3453989600 |
Directory | /workspace/13.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.3682252908 |
Short name | T222 |
Test name | |
Test status | |
Simulation time | 259467224 ps |
CPU time | 1.17 seconds |
Started | May 05 01:03:59 PM PDT 24 |
Finished | May 05 01:04:01 PM PDT 24 |
Peak memory | 204764 kb |
Host | smart-53b2a4d7-bed5-4549-ad15-6fe0307149f1 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682252908 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw. 3682252908 |
Directory | /workspace/13.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1949688822 |
Short name | T179 |
Test name | |
Test status | |
Simulation time | 70398830 ps |
CPU time | 0.86 seconds |
Started | May 05 01:03:59 PM PDT 24 |
Finished | May 05 01:04:01 PM PDT 24 |
Peak memory | 204552 kb |
Host | smart-0dbc2db6-d16e-4750-9069-2cfda069952a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949688822 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw. 1949688822 |
Directory | /workspace/13.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2694660581 |
Short name | T78 |
Test name | |
Test status | |
Simulation time | 157176471 ps |
CPU time | 6.8 seconds |
Started | May 05 01:04:01 PM PDT 24 |
Finished | May 05 01:04:08 PM PDT 24 |
Peak memory | 205104 kb |
Host | smart-fb311e9e-4e6b-4845-a8f7-a10dbd5ad993 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694660581 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same _csr_outstanding.2694660581 |
Directory | /workspace/13.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.1081064497 |
Short name | T70 |
Test name | |
Test status | |
Simulation time | 622462834 ps |
CPU time | 5.1 seconds |
Started | May 05 01:04:01 PM PDT 24 |
Finished | May 05 01:04:07 PM PDT 24 |
Peak memory | 213140 kb |
Host | smart-bf0abd69-158a-41d8-9e3f-a4e6d0f4a884 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081064497 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.1081064497 |
Directory | /workspace/13.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.2318044144 |
Short name | T295 |
Test name | |
Test status | |
Simulation time | 5692399740 ps |
CPU time | 5.39 seconds |
Started | May 05 01:04:01 PM PDT 24 |
Finished | May 05 01:04:07 PM PDT 24 |
Peak memory | 218600 kb |
Host | smart-f7a7b9ac-3775-4ca9-86c5-6d98eecd2778 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318044144 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.2318044144 |
Directory | /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.2178667501 |
Short name | T255 |
Test name | |
Test status | |
Simulation time | 247531605 ps |
CPU time | 2.46 seconds |
Started | May 05 01:03:59 PM PDT 24 |
Finished | May 05 01:04:03 PM PDT 24 |
Peak memory | 213096 kb |
Host | smart-4b194e7f-1f94-4302-ae76-e39b9591ee53 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178667501 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.2178667501 |
Directory | /workspace/14.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1121890418 |
Short name | T271 |
Test name | |
Test status | |
Simulation time | 953383900 ps |
CPU time | 1.54 seconds |
Started | May 05 01:04:01 PM PDT 24 |
Finished | May 05 01:04:03 PM PDT 24 |
Peak memory | 204816 kb |
Host | smart-5737d8cf-807e-4f22-ac50-6029ed314a99 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121890418 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw. 1121890418 |
Directory | /workspace/14.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.927294009 |
Short name | T292 |
Test name | |
Test status | |
Simulation time | 24135061 ps |
CPU time | 0.7 seconds |
Started | May 05 01:04:00 PM PDT 24 |
Finished | May 05 01:04:02 PM PDT 24 |
Peak memory | 204596 kb |
Host | smart-9ce33ca9-fdc5-42d8-9461-5a238fdfeddf |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927294009 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.927294009 |
Directory | /workspace/14.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3521142825 |
Short name | T232 |
Test name | |
Test status | |
Simulation time | 292917112 ps |
CPU time | 6.37 seconds |
Started | May 05 01:04:01 PM PDT 24 |
Finished | May 05 01:04:09 PM PDT 24 |
Peak memory | 204940 kb |
Host | smart-226da626-1de7-4271-9afc-2552abb128d9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521142825 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same _csr_outstanding.3521142825 |
Directory | /workspace/14.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_tap_fsm_rand_reset.970125152 |
Short name | T215 |
Test name | |
Test status | |
Simulation time | 8439619157 ps |
CPU time | 16.49 seconds |
Started | May 05 01:03:59 PM PDT 24 |
Finished | May 05 01:04:17 PM PDT 24 |
Peak memory | 218976 kb |
Host | smart-707c8276-3785-480b-b69a-c497ed4df33c |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970125152 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 14.rv_dm_tap_fsm_rand_reset.970125152 |
Directory | /workspace/14.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.1396975360 |
Short name | T136 |
Test name | |
Test status | |
Simulation time | 187619426 ps |
CPU time | 4 seconds |
Started | May 05 01:03:59 PM PDT 24 |
Finished | May 05 01:04:04 PM PDT 24 |
Peak memory | 213200 kb |
Host | smart-d400f586-dffd-4e51-b572-7175f778b213 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396975360 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.1396975360 |
Directory | /workspace/14.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1910158919 |
Short name | T276 |
Test name | |
Test status | |
Simulation time | 2130655150 ps |
CPU time | 10.01 seconds |
Started | May 05 01:04:04 PM PDT 24 |
Finished | May 05 01:04:14 PM PDT 24 |
Peak memory | 221256 kb |
Host | smart-b5aefa2d-31dc-481f-abe3-7fc38c501e2c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910158919 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.1 910158919 |
Directory | /workspace/14.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.424185683 |
Short name | T240 |
Test name | |
Test status | |
Simulation time | 552847622 ps |
CPU time | 3.52 seconds |
Started | May 05 01:04:03 PM PDT 24 |
Finished | May 05 01:04:07 PM PDT 24 |
Peak memory | 217408 kb |
Host | smart-cb0907e3-e313-4dfc-8f1d-01819ea7968c |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424185683 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.424185683 |
Directory | /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.3976849520 |
Short name | T286 |
Test name | |
Test status | |
Simulation time | 56704702 ps |
CPU time | 1.58 seconds |
Started | May 05 01:04:02 PM PDT 24 |
Finished | May 05 01:04:04 PM PDT 24 |
Peak memory | 213052 kb |
Host | smart-bd8de312-bddf-4eb7-a74c-f40ddb61ee63 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976849520 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.3976849520 |
Directory | /workspace/15.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3869013413 |
Short name | T199 |
Test name | |
Test status | |
Simulation time | 518650115 ps |
CPU time | 2.43 seconds |
Started | May 05 01:03:58 PM PDT 24 |
Finished | May 05 01:04:02 PM PDT 24 |
Peak memory | 204804 kb |
Host | smart-d7ea292c-b5cf-4f4e-8ded-16b55de44bd1 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869013413 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw. 3869013413 |
Directory | /workspace/15.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.875102771 |
Short name | T211 |
Test name | |
Test status | |
Simulation time | 61140664 ps |
CPU time | 0.7 seconds |
Started | May 05 01:04:00 PM PDT 24 |
Finished | May 05 01:04:02 PM PDT 24 |
Peak memory | 204576 kb |
Host | smart-eac2fafe-a198-46b9-b2b5-69300f13983f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875102771 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.875102771 |
Directory | /workspace/15.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.1345921859 |
Short name | T108 |
Test name | |
Test status | |
Simulation time | 442149919 ps |
CPU time | 7.97 seconds |
Started | May 05 01:03:59 PM PDT 24 |
Finished | May 05 01:04:08 PM PDT 24 |
Peak memory | 204992 kb |
Host | smart-005c8a6a-cf7e-4f5e-9009-e9f4413227e3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345921859 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same _csr_outstanding.1345921859 |
Directory | /workspace/15.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.776870294 |
Short name | T262 |
Test name | |
Test status | |
Simulation time | 44975850 ps |
CPU time | 1.99 seconds |
Started | May 05 01:04:00 PM PDT 24 |
Finished | May 05 01:04:03 PM PDT 24 |
Peak memory | 213368 kb |
Host | smart-beb22a9e-c10a-4925-a441-3a511ce3f45e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776870294 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.776870294 |
Directory | /workspace/15.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2108128330 |
Short name | T118 |
Test name | |
Test status | |
Simulation time | 1363596667 ps |
CPU time | 18.41 seconds |
Started | May 05 01:03:59 PM PDT 24 |
Finished | May 05 01:04:19 PM PDT 24 |
Peak memory | 213076 kb |
Host | smart-e4daecf8-1d2b-4a95-ae0a-1400a6a917a0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108128330 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.2 108128330 |
Directory | /workspace/15.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.527770952 |
Short name | T306 |
Test name | |
Test status | |
Simulation time | 167655153 ps |
CPU time | 2.23 seconds |
Started | May 05 01:04:09 PM PDT 24 |
Finished | May 05 01:04:12 PM PDT 24 |
Peak memory | 216528 kb |
Host | smart-93cfddc0-0aaf-4a33-8f5f-72bb9ea69e8c |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527770952 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.527770952 |
Directory | /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.914670109 |
Short name | T294 |
Test name | |
Test status | |
Simulation time | 56146231 ps |
CPU time | 1.54 seconds |
Started | May 05 01:04:07 PM PDT 24 |
Finished | May 05 01:04:10 PM PDT 24 |
Peak memory | 213356 kb |
Host | smart-9279eaca-b89b-4aea-a8bd-a4c522a296be |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914670109 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.914670109 |
Directory | /workspace/16.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2150654404 |
Short name | T184 |
Test name | |
Test status | |
Simulation time | 918404035 ps |
CPU time | 1.22 seconds |
Started | May 05 01:04:02 PM PDT 24 |
Finished | May 05 01:04:04 PM PDT 24 |
Peak memory | 204780 kb |
Host | smart-d5d12007-d0b9-4fc0-b9b8-ae78eed9fa2d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150654404 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw. 2150654404 |
Directory | /workspace/16.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.41552071 |
Short name | T273 |
Test name | |
Test status | |
Simulation time | 97175807 ps |
CPU time | 0.89 seconds |
Started | May 05 01:03:59 PM PDT 24 |
Finished | May 05 01:04:01 PM PDT 24 |
Peak memory | 204540 kb |
Host | smart-e0c1343d-036a-43a6-80ea-ea7864005f8d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41552071 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.41552071 |
Directory | /workspace/16.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.2715243275 |
Short name | T250 |
Test name | |
Test status | |
Simulation time | 140172050 ps |
CPU time | 3.26 seconds |
Started | May 05 01:04:09 PM PDT 24 |
Finished | May 05 01:04:12 PM PDT 24 |
Peak memory | 204872 kb |
Host | smart-091fffb5-a689-444d-a401-4681a76d7a1d |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715243275 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same _csr_outstanding.2715243275 |
Directory | /workspace/16.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_tap_fsm_rand_reset.2011273084 |
Short name | T220 |
Test name | |
Test status | |
Simulation time | 13585696465 ps |
CPU time | 17.5 seconds |
Started | May 05 01:03:59 PM PDT 24 |
Finished | May 05 01:04:18 PM PDT 24 |
Peak memory | 213508 kb |
Host | smart-3d7ca258-2d60-4b5a-9224-cd2d9754a887 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011273084 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 16.rv_dm_tap_fsm_rand_reset.2011273084 |
Directory | /workspace/16.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.1890923226 |
Short name | T114 |
Test name | |
Test status | |
Simulation time | 482653553 ps |
CPU time | 3.85 seconds |
Started | May 05 01:04:03 PM PDT 24 |
Finished | May 05 01:04:07 PM PDT 24 |
Peak memory | 213180 kb |
Host | smart-ef72a1ee-5baf-429d-a6d1-b3837cc80397 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890923226 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.1890923226 |
Directory | /workspace/16.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.3503335852 |
Short name | T126 |
Test name | |
Test status | |
Simulation time | 3987394082 ps |
CPU time | 20.24 seconds |
Started | May 05 01:04:01 PM PDT 24 |
Finished | May 05 01:04:22 PM PDT 24 |
Peak memory | 221316 kb |
Host | smart-5f3c3d36-17c1-44b3-97e8-6f6a53d94f6f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503335852 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.3 503335852 |
Directory | /workspace/16.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2956194021 |
Short name | T109 |
Test name | |
Test status | |
Simulation time | 2614759268 ps |
CPU time | 4.54 seconds |
Started | May 05 01:04:04 PM PDT 24 |
Finished | May 05 01:04:09 PM PDT 24 |
Peak memory | 214728 kb |
Host | smart-a70c68bd-0075-4fee-905b-94ec6fb6f18d |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956194021 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.2956194021 |
Directory | /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.887932807 |
Short name | T104 |
Test name | |
Test status | |
Simulation time | 53557987 ps |
CPU time | 2.07 seconds |
Started | May 05 01:04:08 PM PDT 24 |
Finished | May 05 01:04:11 PM PDT 24 |
Peak memory | 213012 kb |
Host | smart-ddaf7fc3-75c8-4e05-9999-e2514b57b86c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887932807 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.887932807 |
Directory | /workspace/17.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.3138391257 |
Short name | T174 |
Test name | |
Test status | |
Simulation time | 437644508 ps |
CPU time | 1.83 seconds |
Started | May 05 01:04:06 PM PDT 24 |
Finished | May 05 01:04:08 PM PDT 24 |
Peak memory | 204720 kb |
Host | smart-56a6e615-b8d7-4817-9be0-a683c868e17a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138391257 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw. 3138391257 |
Directory | /workspace/17.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.781614078 |
Short name | T266 |
Test name | |
Test status | |
Simulation time | 172264270 ps |
CPU time | 0.9 seconds |
Started | May 05 01:04:05 PM PDT 24 |
Finished | May 05 01:04:06 PM PDT 24 |
Peak memory | 204604 kb |
Host | smart-6255e56a-f02d-41be-bda2-d2e897e11200 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781614078 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.781614078 |
Directory | /workspace/17.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2743558115 |
Short name | T228 |
Test name | |
Test status | |
Simulation time | 497518957 ps |
CPU time | 4.25 seconds |
Started | May 05 01:04:05 PM PDT 24 |
Finished | May 05 01:04:10 PM PDT 24 |
Peak memory | 204936 kb |
Host | smart-d7e972e0-de98-4aa8-ab0c-45cd089ee410 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743558115 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same _csr_outstanding.2743558115 |
Directory | /workspace/17.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_tap_fsm_rand_reset.2899139569 |
Short name | T244 |
Test name | |
Test status | |
Simulation time | 5994542456 ps |
CPU time | 21.91 seconds |
Started | May 05 01:04:09 PM PDT 24 |
Finished | May 05 01:04:32 PM PDT 24 |
Peak memory | 220356 kb |
Host | smart-9fc607a8-fbbe-489d-8db8-6a845ebc2a9c |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899139569 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 17.rv_dm_tap_fsm_rand_reset.2899139569 |
Directory | /workspace/17.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.361471540 |
Short name | T226 |
Test name | |
Test status | |
Simulation time | 146570570 ps |
CPU time | 5.19 seconds |
Started | May 05 01:04:05 PM PDT 24 |
Finished | May 05 01:04:11 PM PDT 24 |
Peak memory | 213076 kb |
Host | smart-f68d4fed-3545-4c83-8fbf-2d0f0f1b8527 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361471540 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.361471540 |
Directory | /workspace/17.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.3415582361 |
Short name | T311 |
Test name | |
Test status | |
Simulation time | 215113387 ps |
CPU time | 3.82 seconds |
Started | May 05 01:04:07 PM PDT 24 |
Finished | May 05 01:04:12 PM PDT 24 |
Peak memory | 219504 kb |
Host | smart-c2b6a096-428a-44f0-a170-962a0f0fdf70 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415582361 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.3415582361 |
Directory | /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.3766313634 |
Short name | T314 |
Test name | |
Test status | |
Simulation time | 74477484 ps |
CPU time | 1.59 seconds |
Started | May 05 01:04:07 PM PDT 24 |
Finished | May 05 01:04:09 PM PDT 24 |
Peak memory | 221332 kb |
Host | smart-13c0a2ba-0e26-409b-b2ba-84bd6243ed25 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766313634 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.3766313634 |
Directory | /workspace/18.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.3244723185 |
Short name | T176 |
Test name | |
Test status | |
Simulation time | 1163858079 ps |
CPU time | 1.52 seconds |
Started | May 05 01:04:10 PM PDT 24 |
Finished | May 05 01:04:12 PM PDT 24 |
Peak memory | 204760 kb |
Host | smart-7bc2e9b6-c7ab-49dd-9cd4-5b6f281626df |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244723185 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw. 3244723185 |
Directory | /workspace/18.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.3122984917 |
Short name | T282 |
Test name | |
Test status | |
Simulation time | 130192946 ps |
CPU time | 0.8 seconds |
Started | May 05 01:04:06 PM PDT 24 |
Finished | May 05 01:04:08 PM PDT 24 |
Peak memory | 204508 kb |
Host | smart-158c6fff-f569-45dc-b4db-9108da0f6fd1 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122984917 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw. 3122984917 |
Directory | /workspace/18.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3190188257 |
Short name | T93 |
Test name | |
Test status | |
Simulation time | 272378741 ps |
CPU time | 6.35 seconds |
Started | May 05 01:04:06 PM PDT 24 |
Finished | May 05 01:04:13 PM PDT 24 |
Peak memory | 204880 kb |
Host | smart-5529ea6b-faec-4455-891c-1ff1238e7687 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190188257 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same _csr_outstanding.3190188257 |
Directory | /workspace/18.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.4126587012 |
Short name | T197 |
Test name | |
Test status | |
Simulation time | 580210615 ps |
CPU time | 2.15 seconds |
Started | May 05 01:04:08 PM PDT 24 |
Finished | May 05 01:04:11 PM PDT 24 |
Peak memory | 213144 kb |
Host | smart-8df21251-3337-4923-92a9-151ff645edb3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126587012 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.4126587012 |
Directory | /workspace/18.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3534207965 |
Short name | T270 |
Test name | |
Test status | |
Simulation time | 9325803612 ps |
CPU time | 20.11 seconds |
Started | May 05 01:04:04 PM PDT 24 |
Finished | May 05 01:04:25 PM PDT 24 |
Peak memory | 213164 kb |
Host | smart-a3ac78c4-af48-4c14-93e6-5c97b382cb9c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534207965 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.3 534207965 |
Directory | /workspace/18.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3603152354 |
Short name | T312 |
Test name | |
Test status | |
Simulation time | 69792542 ps |
CPU time | 2.27 seconds |
Started | May 05 01:04:05 PM PDT 24 |
Finished | May 05 01:04:08 PM PDT 24 |
Peak memory | 221356 kb |
Host | smart-601a7fb4-f97b-4963-8227-ec9b70cb2705 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603152354 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.3603152354 |
Directory | /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.4079166008 |
Short name | T107 |
Test name | |
Test status | |
Simulation time | 89296520 ps |
CPU time | 2.07 seconds |
Started | May 05 01:04:05 PM PDT 24 |
Finished | May 05 01:04:07 PM PDT 24 |
Peak memory | 213104 kb |
Host | smart-48693a38-264e-40a8-8437-965d6f117c7e |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079166008 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.4079166008 |
Directory | /workspace/19.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2870123343 |
Short name | T303 |
Test name | |
Test status | |
Simulation time | 1033229283 ps |
CPU time | 3.74 seconds |
Started | May 05 01:04:06 PM PDT 24 |
Finished | May 05 01:04:10 PM PDT 24 |
Peak memory | 204776 kb |
Host | smart-8589becc-6ea0-4809-99da-ff231b91e5f6 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870123343 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw. 2870123343 |
Directory | /workspace/19.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2959132259 |
Short name | T278 |
Test name | |
Test status | |
Simulation time | 20511407 ps |
CPU time | 0.71 seconds |
Started | May 05 01:04:06 PM PDT 24 |
Finished | May 05 01:04:07 PM PDT 24 |
Peak memory | 204580 kb |
Host | smart-785b72a1-cd09-4ee1-a6e4-769ff965f2db |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959132259 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw. 2959132259 |
Directory | /workspace/19.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.2681157934 |
Short name | T82 |
Test name | |
Test status | |
Simulation time | 1026036417 ps |
CPU time | 8.09 seconds |
Started | May 05 01:04:09 PM PDT 24 |
Finished | May 05 01:04:17 PM PDT 24 |
Peak memory | 204872 kb |
Host | smart-31f5ac23-5f04-4ae0-97cf-713669034c9c |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681157934 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same _csr_outstanding.2681157934 |
Directory | /workspace/19.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.3221740849 |
Short name | T112 |
Test name | |
Test status | |
Simulation time | 558322126 ps |
CPU time | 10.4 seconds |
Started | May 05 01:04:06 PM PDT 24 |
Finished | May 05 01:04:18 PM PDT 24 |
Peak memory | 213072 kb |
Host | smart-58e73e3a-556a-4cdf-b0aa-0a3d30796368 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221740849 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.3 221740849 |
Directory | /workspace/19.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.4254447169 |
Short name | T233 |
Test name | |
Test status | |
Simulation time | 4401135785 ps |
CPU time | 66.08 seconds |
Started | May 05 01:03:21 PM PDT 24 |
Finished | May 05 01:04:27 PM PDT 24 |
Peak memory | 213176 kb |
Host | smart-c3066e03-77ee-49db-83a9-004844dfe8b1 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254447169 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 2.rv_dm_csr_aliasing.4254447169 |
Directory | /workspace/2.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.185227202 |
Short name | T298 |
Test name | |
Test status | |
Simulation time | 1423405129 ps |
CPU time | 26.64 seconds |
Started | May 05 01:03:28 PM PDT 24 |
Finished | May 05 01:03:55 PM PDT 24 |
Peak memory | 204960 kb |
Host | smart-01818842-dd9b-4de8-a9ce-ce524154f508 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185227202 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.185227202 |
Directory | /workspace/2.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.2741350826 |
Short name | T308 |
Test name | |
Test status | |
Simulation time | 956733060 ps |
CPU time | 2.38 seconds |
Started | May 05 01:03:28 PM PDT 24 |
Finished | May 05 01:03:31 PM PDT 24 |
Peak memory | 213044 kb |
Host | smart-b9d739cb-b317-4c5a-a8f8-17bb24cfd0a0 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741350826 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.2741350826 |
Directory | /workspace/2.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.1244185359 |
Short name | T210 |
Test name | |
Test status | |
Simulation time | 46067367 ps |
CPU time | 2.61 seconds |
Started | May 05 01:03:29 PM PDT 24 |
Finished | May 05 01:03:32 PM PDT 24 |
Peak memory | 213116 kb |
Host | smart-cf71fe3b-a044-4009-9186-ed0a1540cea7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244185359 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.1244185359 |
Directory | /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.2818199431 |
Short name | T254 |
Test name | |
Test status | |
Simulation time | 500522731 ps |
CPU time | 2.3 seconds |
Started | May 05 01:03:28 PM PDT 24 |
Finished | May 05 01:03:31 PM PDT 24 |
Peak memory | 213156 kb |
Host | smart-28449ab2-9b54-4dff-b6a4-d3026c9ac8d8 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818199431 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.2818199431 |
Directory | /workspace/2.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.1322718893 |
Short name | T310 |
Test name | |
Test status | |
Simulation time | 18118835570 ps |
CPU time | 47.93 seconds |
Started | May 05 01:03:22 PM PDT 24 |
Finished | May 05 01:04:10 PM PDT 24 |
Peak memory | 204912 kb |
Host | smart-3d1f0de8-da9e-4f1c-a0a5-4310830b6d57 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322718893 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs r_aliasing.1322718893 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.470953167 |
Short name | T181 |
Test name | |
Test status | |
Simulation time | 8849734257 ps |
CPU time | 16.11 seconds |
Started | May 05 01:03:22 PM PDT 24 |
Finished | May 05 01:03:39 PM PDT 24 |
Peak memory | 205092 kb |
Host | smart-a075faad-2f00-40d0-b7bf-928c5cfb4889 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470953167 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr _bit_bash.470953167 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.1842111647 |
Short name | T183 |
Test name | |
Test status | |
Simulation time | 281914266 ps |
CPU time | 1.66 seconds |
Started | May 05 01:03:21 PM PDT 24 |
Finished | May 05 01:03:23 PM PDT 24 |
Peak memory | 204872 kb |
Host | smart-1f792d35-8ccc-4d8c-9b41-724d6b75e792 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842111647 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs r_hw_reset.1842111647 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.348556283 |
Short name | T246 |
Test name | |
Test status | |
Simulation time | 824596457 ps |
CPU time | 1.8 seconds |
Started | May 05 01:03:25 PM PDT 24 |
Finished | May 05 01:03:28 PM PDT 24 |
Peak memory | 204796 kb |
Host | smart-8dc2e871-8ae3-4ed6-8144-2cfee23e39ee |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348556283 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.348556283 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.2141549463 |
Short name | T237 |
Test name | |
Test status | |
Simulation time | 368756367 ps |
CPU time | 0.91 seconds |
Started | May 05 01:03:21 PM PDT 24 |
Finished | May 05 01:03:22 PM PDT 24 |
Peak memory | 204596 kb |
Host | smart-e49cc800-2008-4a38-a264-959ae1082aec |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141549463 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_aliasing.2141549463 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1391954688 |
Short name | T272 |
Test name | |
Test status | |
Simulation time | 2985631445 ps |
CPU time | 5.55 seconds |
Started | May 05 01:03:25 PM PDT 24 |
Finished | May 05 01:03:31 PM PDT 24 |
Peak memory | 204820 kb |
Host | smart-ff3ee96a-e99c-4063-893c-2b447ca99c3b |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391954688 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_bit_bash.1391954688 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1005725327 |
Short name | T283 |
Test name | |
Test status | |
Simulation time | 74645496 ps |
CPU time | 0.71 seconds |
Started | May 05 01:03:22 PM PDT 24 |
Finished | May 05 01:03:23 PM PDT 24 |
Peak memory | 204576 kb |
Host | smart-0815f41d-6ba0-4763-a3a2-ebade3798eca |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005725327 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_hw_reset.1005725327 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.1488691998 |
Short name | T236 |
Test name | |
Test status | |
Simulation time | 193158389 ps |
CPU time | 0.73 seconds |
Started | May 05 01:03:23 PM PDT 24 |
Finished | May 05 01:03:25 PM PDT 24 |
Peak memory | 204584 kb |
Host | smart-47a4bdbc-b4e3-46c4-a75a-2ce053cec0d0 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488691998 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.1 488691998 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2281091173 |
Short name | T261 |
Test name | |
Test status | |
Simulation time | 31890509 ps |
CPU time | 0.67 seconds |
Started | May 05 01:03:36 PM PDT 24 |
Finished | May 05 01:03:38 PM PDT 24 |
Peak memory | 204484 kb |
Host | smart-2d07cbdd-c743-4b84-8212-224f7acff484 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281091173 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par tial_access.2281091173 |
Directory | /workspace/2.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.2403320836 |
Short name | T200 |
Test name | |
Test status | |
Simulation time | 23366438 ps |
CPU time | 0.68 seconds |
Started | May 05 01:03:29 PM PDT 24 |
Finished | May 05 01:03:31 PM PDT 24 |
Peak memory | 204596 kb |
Host | smart-3a9d9775-563b-4257-8593-d3cb7de0bde4 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403320836 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.2403320836 |
Directory | /workspace/2.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.1137012275 |
Short name | T95 |
Test name | |
Test status | |
Simulation time | 286080226 ps |
CPU time | 6.47 seconds |
Started | May 05 01:03:27 PM PDT 24 |
Finished | May 05 01:03:35 PM PDT 24 |
Peak memory | 204820 kb |
Host | smart-3705a656-8593-413b-a2e9-01c54e6bba08 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137012275 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_ csr_outstanding.1137012275 |
Directory | /workspace/2.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.459175411 |
Short name | T238 |
Test name | |
Test status | |
Simulation time | 429037675 ps |
CPU time | 4.84 seconds |
Started | May 05 01:03:21 PM PDT 24 |
Finished | May 05 01:03:27 PM PDT 24 |
Peak memory | 213192 kb |
Host | smart-5771f00a-e73e-4e72-af34-50f4378262ad |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459175411 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.459175411 |
Directory | /workspace/2.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.135910270 |
Short name | T119 |
Test name | |
Test status | |
Simulation time | 826414430 ps |
CPU time | 10.46 seconds |
Started | May 05 01:03:21 PM PDT 24 |
Finished | May 05 01:03:32 PM PDT 24 |
Peak memory | 221328 kb |
Host | smart-e124d5b8-3dc6-4e5b-bde2-948ac269f3f3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135910270 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.135910270 |
Directory | /workspace/2.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/20.rv_dm_tap_fsm_rand_reset.2130848605 |
Short name | T257 |
Test name | |
Test status | |
Simulation time | 16229900148 ps |
CPU time | 56.43 seconds |
Started | May 05 01:04:06 PM PDT 24 |
Finished | May 05 01:05:03 PM PDT 24 |
Peak memory | 221456 kb |
Host | smart-97b33732-798e-485d-9965-09437a26f9c7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130848605 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 20.rv_dm_tap_fsm_rand_reset.2130848605 |
Directory | /workspace/20.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/21.rv_dm_tap_fsm_rand_reset.1514525806 |
Short name | T280 |
Test name | |
Test status | |
Simulation time | 26284420648 ps |
CPU time | 30.22 seconds |
Started | May 05 01:04:05 PM PDT 24 |
Finished | May 05 01:04:35 PM PDT 24 |
Peak memory | 229552 kb |
Host | smart-eef8da66-8306-46c1-91a5-8b5da2acc6ed |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514525806 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 21.rv_dm_tap_fsm_rand_reset.1514525806 |
Directory | /workspace/21.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/25.rv_dm_tap_fsm_rand_reset.2613296911 |
Short name | T191 |
Test name | |
Test status | |
Simulation time | 13509907529 ps |
CPU time | 15.9 seconds |
Started | May 05 01:04:10 PM PDT 24 |
Finished | May 05 01:04:27 PM PDT 24 |
Peak memory | 213596 kb |
Host | smart-8eb75dcc-bbde-4b13-9cc9-45ec7aef1718 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613296911 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 25.rv_dm_tap_fsm_rand_reset.2613296911 |
Directory | /workspace/25.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/26.rv_dm_tap_fsm_rand_reset.3558655038 |
Short name | T69 |
Test name | |
Test status | |
Simulation time | 7621972063 ps |
CPU time | 9.55 seconds |
Started | May 05 01:04:10 PM PDT 24 |
Finished | May 05 01:04:20 PM PDT 24 |
Peak memory | 221084 kb |
Host | smart-97af0dbb-30f0-4ee9-a072-f341138ad35a |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558655038 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 26.rv_dm_tap_fsm_rand_reset.3558655038 |
Directory | /workspace/26.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2984670898 |
Short name | T297 |
Test name | |
Test status | |
Simulation time | 1773937484 ps |
CPU time | 30.94 seconds |
Started | May 05 01:03:29 PM PDT 24 |
Finished | May 05 01:04:00 PM PDT 24 |
Peak memory | 204860 kb |
Host | smart-67b9f9d3-efd2-42a3-af32-dafb8bc20481 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984670898 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 3.rv_dm_csr_aliasing.2984670898 |
Directory | /workspace/3.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.2121989533 |
Short name | T239 |
Test name | |
Test status | |
Simulation time | 10002774700 ps |
CPU time | 69.07 seconds |
Started | May 05 01:03:34 PM PDT 24 |
Finished | May 05 01:04:43 PM PDT 24 |
Peak memory | 213276 kb |
Host | smart-561cbf9c-5dfe-412e-bae7-3fbd7481f0be |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121989533 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.2121989533 |
Directory | /workspace/3.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1405768686 |
Short name | T242 |
Test name | |
Test status | |
Simulation time | 56679524 ps |
CPU time | 1.52 seconds |
Started | May 05 01:03:34 PM PDT 24 |
Finished | May 05 01:03:36 PM PDT 24 |
Peak memory | 213028 kb |
Host | smart-446fb4ff-72f1-4178-b278-8141470fa300 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405768686 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.1405768686 |
Directory | /workspace/3.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.2543341225 |
Short name | T71 |
Test name | |
Test status | |
Simulation time | 1570615111 ps |
CPU time | 3.81 seconds |
Started | May 05 01:03:32 PM PDT 24 |
Finished | May 05 01:03:36 PM PDT 24 |
Peak memory | 218776 kb |
Host | smart-6504fb6a-1533-45e4-8a15-a53bcec4ce48 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543341225 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.2543341225 |
Directory | /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2606469176 |
Short name | T89 |
Test name | |
Test status | |
Simulation time | 76319276 ps |
CPU time | 2.1 seconds |
Started | May 05 01:03:33 PM PDT 24 |
Finished | May 05 01:03:36 PM PDT 24 |
Peak memory | 213040 kb |
Host | smart-3df0405d-2334-4a55-93d0-f1bbd91bbeb4 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606469176 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.2606469176 |
Directory | /workspace/3.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.454821631 |
Short name | T209 |
Test name | |
Test status | |
Simulation time | 20493054792 ps |
CPU time | 32.51 seconds |
Started | May 05 01:03:28 PM PDT 24 |
Finished | May 05 01:04:01 PM PDT 24 |
Peak memory | 204872 kb |
Host | smart-51091969-1e15-486a-9564-7dfd923c27f8 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454821631 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr _aliasing.454821631 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.3145139152 |
Short name | T281 |
Test name | |
Test status | |
Simulation time | 41897190843 ps |
CPU time | 124.92 seconds |
Started | May 05 01:03:34 PM PDT 24 |
Finished | May 05 01:05:40 PM PDT 24 |
Peak memory | 204792 kb |
Host | smart-cb930120-629b-4a16-995c-ef6686736eba |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145139152 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs r_bit_bash.3145139152 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.877801307 |
Short name | T86 |
Test name | |
Test status | |
Simulation time | 1974320144 ps |
CPU time | 4 seconds |
Started | May 05 01:03:36 PM PDT 24 |
Finished | May 05 01:03:41 PM PDT 24 |
Peak memory | 204732 kb |
Host | smart-9c7f8693-2c33-4108-8e03-50c474a96dab |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877801307 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr _hw_reset.877801307 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.2890982014 |
Short name | T252 |
Test name | |
Test status | |
Simulation time | 2367020587 ps |
CPU time | 4.52 seconds |
Started | May 05 01:03:30 PM PDT 24 |
Finished | May 05 01:03:35 PM PDT 24 |
Peak memory | 204940 kb |
Host | smart-33ccbd20-893b-468e-8bc9-04c4f260836b |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890982014 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.2 890982014 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.1551359438 |
Short name | T63 |
Test name | |
Test status | |
Simulation time | 107317393 ps |
CPU time | 0.73 seconds |
Started | May 05 01:03:28 PM PDT 24 |
Finished | May 05 01:03:30 PM PDT 24 |
Peak memory | 204596 kb |
Host | smart-aa1be001-6abd-4952-8c7a-ef06705b3ea8 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551359438 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_aliasing.1551359438 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.1653170431 |
Short name | T186 |
Test name | |
Test status | |
Simulation time | 913890109 ps |
CPU time | 2.31 seconds |
Started | May 05 01:03:27 PM PDT 24 |
Finished | May 05 01:03:30 PM PDT 24 |
Peak memory | 204764 kb |
Host | smart-71ae14a3-c752-4712-b790-725f36efdee2 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653170431 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_bit_bash.1653170431 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1388086130 |
Short name | T241 |
Test name | |
Test status | |
Simulation time | 71624435 ps |
CPU time | 0.77 seconds |
Started | May 05 01:03:26 PM PDT 24 |
Finished | May 05 01:03:27 PM PDT 24 |
Peak memory | 204620 kb |
Host | smart-4cb33e29-8f7f-4d30-8376-038d2b1f88b4 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388086130 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_hw_reset.1388086130 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.11323408 |
Short name | T187 |
Test name | |
Test status | |
Simulation time | 26678766 ps |
CPU time | 0.72 seconds |
Started | May 05 01:03:26 PM PDT 24 |
Finished | May 05 01:03:27 PM PDT 24 |
Peak memory | 204604 kb |
Host | smart-73145305-3245-493d-a2bd-76e2c450b366 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11323408 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.11323408 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.3420895619 |
Short name | T268 |
Test name | |
Test status | |
Simulation time | 17972865 ps |
CPU time | 0.66 seconds |
Started | May 05 01:03:32 PM PDT 24 |
Finished | May 05 01:03:33 PM PDT 24 |
Peak memory | 204592 kb |
Host | smart-137c4529-15c0-4ebb-baa8-4df0a5dc997a |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420895619 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par tial_access.3420895619 |
Directory | /workspace/3.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1970428643 |
Short name | T208 |
Test name | |
Test status | |
Simulation time | 39776085 ps |
CPU time | 0.66 seconds |
Started | May 05 01:03:34 PM PDT 24 |
Finished | May 05 01:03:36 PM PDT 24 |
Peak memory | 204572 kb |
Host | smart-cece4969-214b-45dc-874a-8e7e440bafad |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970428643 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.1970428643 |
Directory | /workspace/3.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.1456019675 |
Short name | T96 |
Test name | |
Test status | |
Simulation time | 144916840 ps |
CPU time | 6.2 seconds |
Started | May 05 01:03:32 PM PDT 24 |
Finished | May 05 01:03:38 PM PDT 24 |
Peak memory | 204872 kb |
Host | smart-1ae16c59-3188-47c4-8c49-6fc0bb90e61e |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456019675 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_ csr_outstanding.1456019675 |
Directory | /workspace/3.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.324393740 |
Short name | T275 |
Test name | |
Test status | |
Simulation time | 342260163 ps |
CPU time | 2.64 seconds |
Started | May 05 01:03:28 PM PDT 24 |
Finished | May 05 01:03:31 PM PDT 24 |
Peak memory | 213240 kb |
Host | smart-917df9a1-3ce1-44ff-8899-1e7e1368427b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324393740 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.324393740 |
Directory | /workspace/3.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.441140190 |
Short name | T224 |
Test name | |
Test status | |
Simulation time | 1669366167 ps |
CPU time | 10.11 seconds |
Started | May 05 01:03:36 PM PDT 24 |
Finished | May 05 01:03:46 PM PDT 24 |
Peak memory | 213140 kb |
Host | smart-fd64b4e1-aa55-4eb0-9b92-e4558c46a0ed |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441140190 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.441140190 |
Directory | /workspace/3.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/32.rv_dm_tap_fsm_rand_reset.3316006703 |
Short name | T249 |
Test name | |
Test status | |
Simulation time | 25219195588 ps |
CPU time | 10.06 seconds |
Started | May 05 01:04:22 PM PDT 24 |
Finished | May 05 01:04:33 PM PDT 24 |
Peak memory | 221272 kb |
Host | smart-be150476-7533-4dea-9dd5-7acfd61f2afe |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316006703 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 32.rv_dm_tap_fsm_rand_reset.3316006703 |
Directory | /workspace/32.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/33.rv_dm_tap_fsm_rand_reset.1796937085 |
Short name | T38 |
Test name | |
Test status | |
Simulation time | 7478622992 ps |
CPU time | 24.94 seconds |
Started | May 05 01:04:10 PM PDT 24 |
Finished | May 05 01:04:36 PM PDT 24 |
Peak memory | 213232 kb |
Host | smart-73c11b7a-bd33-45dd-96e6-429794381522 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796937085 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 33.rv_dm_tap_fsm_rand_reset.1796937085 |
Directory | /workspace/33.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/34.rv_dm_tap_fsm_rand_reset.342752406 |
Short name | T235 |
Test name | |
Test status | |
Simulation time | 9166449211 ps |
CPU time | 16.53 seconds |
Started | May 05 01:04:12 PM PDT 24 |
Finished | May 05 01:04:29 PM PDT 24 |
Peak memory | 219684 kb |
Host | smart-b6aa4d8a-80a6-48a0-9937-fbdf3b56c02e |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342752406 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 34.rv_dm_tap_fsm_rand_reset.342752406 |
Directory | /workspace/34.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/35.rv_dm_tap_fsm_rand_reset.3730626445 |
Short name | T277 |
Test name | |
Test status | |
Simulation time | 18032576689 ps |
CPU time | 36.76 seconds |
Started | May 05 01:04:12 PM PDT 24 |
Finished | May 05 01:04:49 PM PDT 24 |
Peak memory | 220804 kb |
Host | smart-a832dcfd-8808-47da-b07e-b744ece221c9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730626445 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 35.rv_dm_tap_fsm_rand_reset.3730626445 |
Directory | /workspace/35.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.804913428 |
Short name | T98 |
Test name | |
Test status | |
Simulation time | 3339703643 ps |
CPU time | 30.41 seconds |
Started | May 05 01:03:32 PM PDT 24 |
Finished | May 05 01:04:03 PM PDT 24 |
Peak memory | 205020 kb |
Host | smart-d00122bb-35f4-4a0f-abfd-9b107be3564d |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804913428 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 4.rv_dm_csr_aliasing.804913428 |
Directory | /workspace/4.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.4015978883 |
Short name | T264 |
Test name | |
Test status | |
Simulation time | 2550454848 ps |
CPU time | 31.83 seconds |
Started | May 05 01:03:36 PM PDT 24 |
Finished | May 05 01:04:09 PM PDT 24 |
Peak memory | 205008 kb |
Host | smart-da45aea6-b6f4-465a-ac5c-8e0ee71846f6 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015978883 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.4015978883 |
Directory | /workspace/4.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2243760972 |
Short name | T101 |
Test name | |
Test status | |
Simulation time | 60691668 ps |
CPU time | 1.52 seconds |
Started | May 05 01:03:38 PM PDT 24 |
Finished | May 05 01:03:40 PM PDT 24 |
Peak memory | 213012 kb |
Host | smart-6c39847e-8b6c-4855-8923-c7d997dab841 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243760972 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.2243760972 |
Directory | /workspace/4.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.4003260585 |
Short name | T73 |
Test name | |
Test status | |
Simulation time | 404609983 ps |
CPU time | 3.81 seconds |
Started | May 05 01:03:40 PM PDT 24 |
Finished | May 05 01:03:45 PM PDT 24 |
Peak memory | 217632 kb |
Host | smart-701008a0-e3bb-4b34-ad32-ce3a9fc9ca12 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003260585 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.4003260585 |
Directory | /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.1915015065 |
Short name | T74 |
Test name | |
Test status | |
Simulation time | 98546676 ps |
CPU time | 1.45 seconds |
Started | May 05 01:03:38 PM PDT 24 |
Finished | May 05 01:03:40 PM PDT 24 |
Peak memory | 218264 kb |
Host | smart-5e07b89c-f026-49f9-9d21-f483543607b8 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915015065 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.1915015065 |
Directory | /workspace/4.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.3640471224 |
Short name | T188 |
Test name | |
Test status | |
Simulation time | 9280459227 ps |
CPU time | 23.1 seconds |
Started | May 05 01:03:33 PM PDT 24 |
Finished | May 05 01:03:57 PM PDT 24 |
Peak memory | 204952 kb |
Host | smart-bf5c7191-c2fa-4aa7-9f1b-8c1d71116f03 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640471224 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs r_aliasing.3640471224 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.1673134327 |
Short name | T175 |
Test name | |
Test status | |
Simulation time | 34427990452 ps |
CPU time | 28.69 seconds |
Started | May 05 01:03:33 PM PDT 24 |
Finished | May 05 01:04:02 PM PDT 24 |
Peak memory | 204968 kb |
Host | smart-43bd5f27-97fe-4e98-a62e-425e20b69c36 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673134327 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs r_bit_bash.1673134327 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.4038745646 |
Short name | T85 |
Test name | |
Test status | |
Simulation time | 775606083 ps |
CPU time | 2.16 seconds |
Started | May 05 01:03:33 PM PDT 24 |
Finished | May 05 01:03:36 PM PDT 24 |
Peak memory | 204840 kb |
Host | smart-c3037668-dbb6-40ff-90b3-89c04d5ab85d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038745646 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs r_hw_reset.4038745646 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3585930718 |
Short name | T299 |
Test name | |
Test status | |
Simulation time | 1009570225 ps |
CPU time | 2.41 seconds |
Started | May 05 01:03:35 PM PDT 24 |
Finished | May 05 01:03:38 PM PDT 24 |
Peak memory | 204788 kb |
Host | smart-c42d1ed1-dcd4-4a76-80b5-cb248c775d87 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585930718 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.3 585930718 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.1054824484 |
Short name | T253 |
Test name | |
Test status | |
Simulation time | 165816737 ps |
CPU time | 0.88 seconds |
Started | May 05 01:03:32 PM PDT 24 |
Finished | May 05 01:03:33 PM PDT 24 |
Peak memory | 204600 kb |
Host | smart-02be323d-52c5-42cb-bca5-ac3b5c946e8a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054824484 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs r_aliasing.1054824484 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.1565665450 |
Short name | T223 |
Test name | |
Test status | |
Simulation time | 577120756 ps |
CPU time | 2 seconds |
Started | May 05 01:03:32 PM PDT 24 |
Finished | May 05 01:03:35 PM PDT 24 |
Peak memory | 204828 kb |
Host | smart-4401a45e-333f-4c3d-b266-8a702a354c45 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565665450 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs r_bit_bash.1565665450 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.1490257832 |
Short name | T245 |
Test name | |
Test status | |
Simulation time | 48055402 ps |
CPU time | 0.67 seconds |
Started | May 05 01:03:32 PM PDT 24 |
Finished | May 05 01:03:34 PM PDT 24 |
Peak memory | 204664 kb |
Host | smart-f4dd7094-2de5-4ae1-b9a1-4eb4de972003 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490257832 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs r_hw_reset.1490257832 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.1937357399 |
Short name | T207 |
Test name | |
Test status | |
Simulation time | 69507558 ps |
CPU time | 0.73 seconds |
Started | May 05 01:03:35 PM PDT 24 |
Finished | May 05 01:03:37 PM PDT 24 |
Peak memory | 204600 kb |
Host | smart-dc9bfffb-46fc-411d-9f6e-3f6b82aac991 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937357399 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.1 937357399 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1650525006 |
Short name | T301 |
Test name | |
Test status | |
Simulation time | 63788606 ps |
CPU time | 0.63 seconds |
Started | May 05 01:03:37 PM PDT 24 |
Finished | May 05 01:03:38 PM PDT 24 |
Peak memory | 204576 kb |
Host | smart-81496c74-5705-4d11-9541-2ca24cb92d68 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650525006 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par tial_access.1650525006 |
Directory | /workspace/4.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.2694724669 |
Short name | T177 |
Test name | |
Test status | |
Simulation time | 37020913 ps |
CPU time | 0.68 seconds |
Started | May 05 01:03:41 PM PDT 24 |
Finished | May 05 01:03:43 PM PDT 24 |
Peak memory | 204484 kb |
Host | smart-bf91afb8-3607-4dd8-82fc-cca06c97210a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694724669 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.2694724669 |
Directory | /workspace/4.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.61986959 |
Short name | T88 |
Test name | |
Test status | |
Simulation time | 536839130 ps |
CPU time | 7.68 seconds |
Started | May 05 01:03:38 PM PDT 24 |
Finished | May 05 01:03:47 PM PDT 24 |
Peak memory | 204864 kb |
Host | smart-21b35408-bbb7-4f05-9bfb-d0ad1b49d21b |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61986959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_cs r_outstanding.61986959 |
Directory | /workspace/4.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.917047296 |
Short name | T290 |
Test name | |
Test status | |
Simulation time | 757921905 ps |
CPU time | 4.22 seconds |
Started | May 05 01:03:38 PM PDT 24 |
Finished | May 05 01:03:42 PM PDT 24 |
Peak memory | 213188 kb |
Host | smart-6827f5be-974e-493a-b737-cf4f445c5b93 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917047296 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.917047296 |
Directory | /workspace/4.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1156096931 |
Short name | T120 |
Test name | |
Test status | |
Simulation time | 1337661125 ps |
CPU time | 14.69 seconds |
Started | May 05 01:03:36 PM PDT 24 |
Finished | May 05 01:03:51 PM PDT 24 |
Peak memory | 221284 kb |
Host | smart-2d4d5478-4a6f-4a46-983d-db4158db601a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156096931 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.1156096931 |
Directory | /workspace/4.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.709784058 |
Short name | T307 |
Test name | |
Test status | |
Simulation time | 4627338027 ps |
CPU time | 7.28 seconds |
Started | May 05 01:03:41 PM PDT 24 |
Finished | May 05 01:03:48 PM PDT 24 |
Peak memory | 218600 kb |
Host | smart-54bc3ba7-8dc3-4728-86e0-cde1bc497c20 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709784058 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.709784058 |
Directory | /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.604351888 |
Short name | T100 |
Test name | |
Test status | |
Simulation time | 318316394 ps |
CPU time | 2.29 seconds |
Started | May 05 01:03:40 PM PDT 24 |
Finished | May 05 01:03:43 PM PDT 24 |
Peak memory | 213028 kb |
Host | smart-9288e0e6-cd9e-4bfa-b554-3f0fdd2b8b4d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604351888 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.604351888 |
Directory | /workspace/5.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.2340355786 |
Short name | T291 |
Test name | |
Test status | |
Simulation time | 224193093 ps |
CPU time | 1.27 seconds |
Started | May 05 01:03:39 PM PDT 24 |
Finished | May 05 01:03:41 PM PDT 24 |
Peak memory | 204752 kb |
Host | smart-3eec665a-fe24-45f6-ab4a-47d7de7dcf5a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340355786 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.2 340355786 |
Directory | /workspace/5.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.1218052341 |
Short name | T62 |
Test name | |
Test status | |
Simulation time | 42492685 ps |
CPU time | 0.76 seconds |
Started | May 05 01:03:37 PM PDT 24 |
Finished | May 05 01:03:38 PM PDT 24 |
Peak memory | 204568 kb |
Host | smart-f18574b3-cf0d-4404-9f99-552d6ddd87d5 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218052341 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.1 218052341 |
Directory | /workspace/5.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.3484207120 |
Short name | T87 |
Test name | |
Test status | |
Simulation time | 1111740601 ps |
CPU time | 7.39 seconds |
Started | May 05 01:03:37 PM PDT 24 |
Finished | May 05 01:03:45 PM PDT 24 |
Peak memory | 204896 kb |
Host | smart-754e64eb-e9af-4415-b33d-7c00a38db0b2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484207120 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_ csr_outstanding.3484207120 |
Directory | /workspace/5.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.3027824957 |
Short name | T115 |
Test name | |
Test status | |
Simulation time | 109943190 ps |
CPU time | 3.44 seconds |
Started | May 05 01:03:38 PM PDT 24 |
Finished | May 05 01:03:41 PM PDT 24 |
Peak memory | 213248 kb |
Host | smart-d49c1e90-a78c-4d51-8eea-05c6721bf6c4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027824957 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.3027824957 |
Directory | /workspace/5.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2047896989 |
Short name | T229 |
Test name | |
Test status | |
Simulation time | 1064752893 ps |
CPU time | 3.34 seconds |
Started | May 05 01:03:42 PM PDT 24 |
Finished | May 05 01:03:46 PM PDT 24 |
Peak memory | 216960 kb |
Host | smart-39d31b40-7550-45d1-a559-f7b2b166bfda |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047896989 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.2047896989 |
Directory | /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.2568652726 |
Short name | T219 |
Test name | |
Test status | |
Simulation time | 184022873 ps |
CPU time | 2.12 seconds |
Started | May 05 01:03:43 PM PDT 24 |
Finished | May 05 01:03:46 PM PDT 24 |
Peak memory | 218668 kb |
Host | smart-07b06ef2-16cf-491d-aa74-0b3d3709c8e7 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568652726 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.2568652726 |
Directory | /workspace/6.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.3531782386 |
Short name | T296 |
Test name | |
Test status | |
Simulation time | 238704781 ps |
CPU time | 1.53 seconds |
Started | May 05 01:03:39 PM PDT 24 |
Finished | May 05 01:03:42 PM PDT 24 |
Peak memory | 204684 kb |
Host | smart-2d3ac39d-6bc0-4bb9-9953-1c5868f0d884 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531782386 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.3 531782386 |
Directory | /workspace/6.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.4137235759 |
Short name | T213 |
Test name | |
Test status | |
Simulation time | 48704458 ps |
CPU time | 0.74 seconds |
Started | May 05 01:03:39 PM PDT 24 |
Finished | May 05 01:03:40 PM PDT 24 |
Peak memory | 204548 kb |
Host | smart-00151594-c7de-4c08-a7f9-ef4eb425bbe8 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137235759 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.4 137235759 |
Directory | /workspace/6.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.641086281 |
Short name | T90 |
Test name | |
Test status | |
Simulation time | 426791437 ps |
CPU time | 3.55 seconds |
Started | May 05 01:03:42 PM PDT 24 |
Finished | May 05 01:03:46 PM PDT 24 |
Peak memory | 204900 kb |
Host | smart-9dad7a59-d650-4791-97c7-0a5ea0d51dc9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641086281 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_c sr_outstanding.641086281 |
Directory | /workspace/6.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.4259595016 |
Short name | T284 |
Test name | |
Test status | |
Simulation time | 170651105 ps |
CPU time | 4.28 seconds |
Started | May 05 01:03:43 PM PDT 24 |
Finished | May 05 01:03:48 PM PDT 24 |
Peak memory | 213092 kb |
Host | smart-dc2ff01e-3549-4bc3-88cf-ee4a845dbc29 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259595016 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.4259595016 |
Directory | /workspace/6.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1427372294 |
Short name | T221 |
Test name | |
Test status | |
Simulation time | 608443304 ps |
CPU time | 16.05 seconds |
Started | May 05 01:03:43 PM PDT 24 |
Finished | May 05 01:04:00 PM PDT 24 |
Peak memory | 213024 kb |
Host | smart-a5daebe2-fae9-4f4b-8029-9aba9a6c929f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427372294 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.1427372294 |
Directory | /workspace/6.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2018468078 |
Short name | T302 |
Test name | |
Test status | |
Simulation time | 139635240 ps |
CPU time | 2.67 seconds |
Started | May 05 01:03:48 PM PDT 24 |
Finished | May 05 01:03:51 PM PDT 24 |
Peak memory | 221352 kb |
Host | smart-f32b80c7-c4c4-432d-a2c6-ab70771d435a |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018468078 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.2018468078 |
Directory | /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.2799144496 |
Short name | T195 |
Test name | |
Test status | |
Simulation time | 67081382 ps |
CPU time | 1.61 seconds |
Started | May 05 01:03:43 PM PDT 24 |
Finished | May 05 01:03:46 PM PDT 24 |
Peak memory | 213016 kb |
Host | smart-9268773b-024a-43a7-a3a3-cc49ac536d56 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799144496 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.2799144496 |
Directory | /workspace/7.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3343046445 |
Short name | T180 |
Test name | |
Test status | |
Simulation time | 150350331 ps |
CPU time | 1.3 seconds |
Started | May 05 01:03:43 PM PDT 24 |
Finished | May 05 01:03:44 PM PDT 24 |
Peak memory | 204848 kb |
Host | smart-5779f491-4a55-427f-bea3-723e47ac789e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343046445 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.3 343046445 |
Directory | /workspace/7.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.3896757824 |
Short name | T265 |
Test name | |
Test status | |
Simulation time | 179647018 ps |
CPU time | 0.73 seconds |
Started | May 05 01:03:42 PM PDT 24 |
Finished | May 05 01:03:44 PM PDT 24 |
Peak memory | 204600 kb |
Host | smart-0e9de512-aa5e-4f0e-a36a-561e1605a256 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896757824 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.3 896757824 |
Directory | /workspace/7.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.4124291670 |
Short name | T204 |
Test name | |
Test status | |
Simulation time | 7817244624 ps |
CPU time | 15.65 seconds |
Started | May 05 01:03:45 PM PDT 24 |
Finished | May 05 01:04:01 PM PDT 24 |
Peak memory | 218832 kb |
Host | smart-5081fdd8-ca4d-488a-998b-a4dd61078be5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124291670 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.4124291670 |
Directory | /workspace/7.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.2772529689 |
Short name | T41 |
Test name | |
Test status | |
Simulation time | 338586659 ps |
CPU time | 2.51 seconds |
Started | May 05 01:03:42 PM PDT 24 |
Finished | May 05 01:03:45 PM PDT 24 |
Peak memory | 213160 kb |
Host | smart-59059548-b4f0-4906-a157-162cdeb70e0b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772529689 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.2772529689 |
Directory | /workspace/7.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.572060708 |
Short name | T125 |
Test name | |
Test status | |
Simulation time | 472637824 ps |
CPU time | 9.92 seconds |
Started | May 05 01:03:41 PM PDT 24 |
Finished | May 05 01:03:52 PM PDT 24 |
Peak memory | 221292 kb |
Host | smart-3b8b85b6-da8d-4ee1-bb75-65df749df4c4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572060708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.572060708 |
Directory | /workspace/7.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.3808461729 |
Short name | T243 |
Test name | |
Test status | |
Simulation time | 170051008 ps |
CPU time | 2.42 seconds |
Started | May 05 01:03:49 PM PDT 24 |
Finished | May 05 01:03:51 PM PDT 24 |
Peak memory | 221120 kb |
Host | smart-cd227760-6976-4e3e-b994-50376d01b0d1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808461729 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.3808461729 |
Directory | /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.354825111 |
Short name | T106 |
Test name | |
Test status | |
Simulation time | 224516323 ps |
CPU time | 2.53 seconds |
Started | May 05 01:03:49 PM PDT 24 |
Finished | May 05 01:03:52 PM PDT 24 |
Peak memory | 213096 kb |
Host | smart-b71f0dab-a4f7-4883-9193-addf8af1eea3 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354825111 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.354825111 |
Directory | /workspace/8.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.22150968 |
Short name | T263 |
Test name | |
Test status | |
Simulation time | 1008066060 ps |
CPU time | 3.29 seconds |
Started | May 05 01:03:47 PM PDT 24 |
Finished | May 05 01:03:50 PM PDT 24 |
Peak memory | 204852 kb |
Host | smart-7740a447-69db-42a3-82e2-8bd05fee828d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22150968 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.22150968 |
Directory | /workspace/8.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2023297791 |
Short name | T198 |
Test name | |
Test status | |
Simulation time | 54908169 ps |
CPU time | 0.73 seconds |
Started | May 05 01:03:50 PM PDT 24 |
Finished | May 05 01:03:51 PM PDT 24 |
Peak memory | 204592 kb |
Host | smart-da7f8c58-13f5-46e2-bd3b-ce65226753ec |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023297791 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.2 023297791 |
Directory | /workspace/8.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.4131946155 |
Short name | T94 |
Test name | |
Test status | |
Simulation time | 1102126691 ps |
CPU time | 4.18 seconds |
Started | May 05 01:03:52 PM PDT 24 |
Finished | May 05 01:03:57 PM PDT 24 |
Peak memory | 204876 kb |
Host | smart-c7093b58-97a3-4a5b-9b46-9e8fb5eac445 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131946155 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_ csr_outstanding.4131946155 |
Directory | /workspace/8.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.1949306961 |
Short name | T225 |
Test name | |
Test status | |
Simulation time | 489231251 ps |
CPU time | 3.83 seconds |
Started | May 05 01:03:48 PM PDT 24 |
Finished | May 05 01:03:52 PM PDT 24 |
Peak memory | 213240 kb |
Host | smart-dd73f6d4-587a-44f2-8962-74e5b511b33f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949306961 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.1949306961 |
Directory | /workspace/8.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3596337264 |
Short name | T127 |
Test name | |
Test status | |
Simulation time | 853262690 ps |
CPU time | 8.05 seconds |
Started | May 05 01:03:48 PM PDT 24 |
Finished | May 05 01:03:57 PM PDT 24 |
Peak memory | 213088 kb |
Host | smart-21bfdc42-4146-4faf-900f-42cc17b54a35 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596337264 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.3596337264 |
Directory | /workspace/8.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.2041227754 |
Short name | T230 |
Test name | |
Test status | |
Simulation time | 8660918449 ps |
CPU time | 8.33 seconds |
Started | May 05 01:03:55 PM PDT 24 |
Finished | May 05 01:04:04 PM PDT 24 |
Peak memory | 219152 kb |
Host | smart-c47168e2-e3b3-4a84-8880-3e52aeaf123b |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041227754 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.2041227754 |
Directory | /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.2194720903 |
Short name | T102 |
Test name | |
Test status | |
Simulation time | 866704625 ps |
CPU time | 2.3 seconds |
Started | May 05 01:03:48 PM PDT 24 |
Finished | May 05 01:03:51 PM PDT 24 |
Peak memory | 217972 kb |
Host | smart-b96294a5-327c-45b2-962e-3eee31a971b3 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194720903 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.2194720903 |
Directory | /workspace/9.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3473680280 |
Short name | T201 |
Test name | |
Test status | |
Simulation time | 388955865 ps |
CPU time | 1.91 seconds |
Started | May 05 01:03:52 PM PDT 24 |
Finished | May 05 01:03:54 PM PDT 24 |
Peak memory | 204768 kb |
Host | smart-2338d5b0-9347-494d-b562-fa80dc8cec77 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473680280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.3 473680280 |
Directory | /workspace/9.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1473526451 |
Short name | T289 |
Test name | |
Test status | |
Simulation time | 45714594 ps |
CPU time | 0.69 seconds |
Started | May 05 01:03:50 PM PDT 24 |
Finished | May 05 01:03:51 PM PDT 24 |
Peak memory | 204560 kb |
Host | smart-64a3f808-b785-4df1-8fdd-e82f24ff9f31 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473526451 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.1 473526451 |
Directory | /workspace/9.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.3221494966 |
Short name | T42 |
Test name | |
Test status | |
Simulation time | 287554748 ps |
CPU time | 4.07 seconds |
Started | May 05 01:03:47 PM PDT 24 |
Finished | May 05 01:03:52 PM PDT 24 |
Peak memory | 204908 kb |
Host | smart-a35ac407-1ae9-4f31-9469-c572d4546ab4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221494966 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_ csr_outstanding.3221494966 |
Directory | /workspace/9.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.2595086613 |
Short name | T116 |
Test name | |
Test status | |
Simulation time | 17635631468 ps |
CPU time | 32.86 seconds |
Started | May 05 01:03:47 PM PDT 24 |
Finished | May 05 01:04:21 PM PDT 24 |
Peak memory | 221332 kb |
Host | smart-700f1b44-0ce4-4129-997a-f423e7166c73 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595086613 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.2595086613 |
Directory | /workspace/9.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.2001534627 |
Short name | T287 |
Test name | |
Test status | |
Simulation time | 1704521959 ps |
CPU time | 3.99 seconds |
Started | May 05 01:03:49 PM PDT 24 |
Finished | May 05 01:03:53 PM PDT 24 |
Peak memory | 213212 kb |
Host | smart-63055d2b-6f54-4945-ac66-b27f05a92dec |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001534627 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.2001534627 |
Directory | /workspace/9.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.27889640 |
Short name | T205 |
Test name | |
Test status | |
Simulation time | 2188517506 ps |
CPU time | 9.76 seconds |
Started | May 05 01:03:50 PM PDT 24 |
Finished | May 05 01:04:00 PM PDT 24 |
Peak memory | 213168 kb |
Host | smart-dae4d462-cdf0-4031-8bd6-f42f2c102848 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27889640 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.27889640 |
Directory | /workspace/9.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.rv_dm_alert_test.3231433566 |
Short name | T48 |
Test name | |
Test status | |
Simulation time | 36566574 ps |
CPU time | 0.72 seconds |
Started | May 05 01:04:22 PM PDT 24 |
Finished | May 05 01:04:24 PM PDT 24 |
Peak memory | 205052 kb |
Host | smart-a337f104-18c5-4e91-b9d3-f5b77d9046d7 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231433566 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.3231433566 |
Directory | /workspace/0.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_busy.1189582150 |
Short name | T128 |
Test name | |
Test status | |
Simulation time | 3962579209 ps |
CPU time | 13.8 seconds |
Started | May 05 01:04:18 PM PDT 24 |
Finished | May 05 01:04:32 PM PDT 24 |
Peak memory | 205416 kb |
Host | smart-cd8fbe6c-9d15-4cf4-9d1a-e9399b5041e2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1189582150 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.1189582150 |
Directory | /workspace/0.rv_dm_cmderr_busy/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_not_supported.570318284 |
Short name | T45 |
Test name | |
Test status | |
Simulation time | 3779086034 ps |
CPU time | 4.03 seconds |
Started | May 05 01:04:23 PM PDT 24 |
Finished | May 05 01:04:27 PM PDT 24 |
Peak memory | 205420 kb |
Host | smart-9727f19f-589b-465a-88f7-049cfd14d179 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=570318284 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.570318284 |
Directory | /workspace/0.rv_dm_cmderr_not_supported/latest |
Test location | /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.810800649 |
Short name | T173 |
Test name | |
Test status | |
Simulation time | 130315193 ps |
CPU time | 0.76 seconds |
Started | May 05 01:04:16 PM PDT 24 |
Finished | May 05 01:04:17 PM PDT 24 |
Peak memory | 205124 kb |
Host | smart-d13eb343-b1ad-4230-b5b9-a9434aa6a88a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=810800649 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.810800649 |
Directory | /workspace/0.rv_dm_dataaddr_rw_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_hart_unavail.1835642458 |
Short name | T160 |
Test name | |
Test status | |
Simulation time | 74239216 ps |
CPU time | 0.75 seconds |
Started | May 05 01:04:15 PM PDT 24 |
Finished | May 05 01:04:17 PM PDT 24 |
Peak memory | 205028 kb |
Host | smart-e9b17254-c7ff-421f-a49e-1bdfb55faf94 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1835642458 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.1835642458 |
Directory | /workspace/0.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.2044578458 |
Short name | T35 |
Test name | |
Test status | |
Simulation time | 442694043 ps |
CPU time | 1 seconds |
Started | May 05 01:04:14 PM PDT 24 |
Finished | May 05 01:04:16 PM PDT 24 |
Peak memory | 204988 kb |
Host | smart-74cd156d-5383-4383-bccc-c6e6e9380a6b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2044578458 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.2044578458 |
Directory | /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.1337312437 |
Short name | T66 |
Test name | |
Test status | |
Simulation time | 156695610 ps |
CPU time | 0.89 seconds |
Started | May 05 01:04:18 PM PDT 24 |
Finished | May 05 01:04:19 PM PDT 24 |
Peak memory | 204964 kb |
Host | smart-c5d26cf0-f63d-48f8-9ce7-9f06beb98a51 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1337312437 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.1337312437 |
Directory | /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.2587925125 |
Short name | T161 |
Test name | |
Test status | |
Simulation time | 160996093 ps |
CPU time | 0.81 seconds |
Started | May 05 01:04:21 PM PDT 24 |
Finished | May 05 01:04:23 PM PDT 24 |
Peak memory | 204964 kb |
Host | smart-cadf05e1-d563-4c05-9de5-2550296f1060 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2587925125 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.2587925125 |
Directory | /workspace/0.rv_dm_jtag_dtm_hard_reset/latest |
Test location | /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.3915284059 |
Short name | T5 |
Test name | |
Test status | |
Simulation time | 85841273 ps |
CPU time | 0.95 seconds |
Started | May 05 01:04:15 PM PDT 24 |
Finished | May 05 01:04:17 PM PDT 24 |
Peak memory | 205128 kb |
Host | smart-57f076be-9dba-4649-b3c0-e3bb5a06c102 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3915284059 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.3915284059 |
Directory | /workspace/0.rv_dm_mem_tl_access_halted/latest |
Test location | /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.1035972821 |
Short name | T172 |
Test name | |
Test status | |
Simulation time | 166090318 ps |
CPU time | 1.29 seconds |
Started | May 05 01:04:15 PM PDT 24 |
Finished | May 05 01:04:16 PM PDT 24 |
Peak memory | 205316 kb |
Host | smart-e1af8816-6889-414a-ac3b-bec472d81539 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1035972821 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.1035972821 |
Directory | /workspace/0.rv_dm_mem_tl_access_resuming/latest |
Test location | /workspace/coverage/default/0.rv_dm_ndmreset_req.2537344822 |
Short name | T130 |
Test name | |
Test status | |
Simulation time | 1088752560 ps |
CPU time | 1.78 seconds |
Started | May 05 01:04:22 PM PDT 24 |
Finished | May 05 01:04:25 PM PDT 24 |
Peak memory | 205284 kb |
Host | smart-94ec0864-6583-4b86-aa17-cf236e662da6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2537344822 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.2537344822 |
Directory | /workspace/0.rv_dm_ndmreset_req/latest |
Test location | /workspace/coverage/default/0.rv_dm_smoke.2429785391 |
Short name | T168 |
Test name | |
Test status | |
Simulation time | 330467858 ps |
CPU time | 1.91 seconds |
Started | May 05 01:04:22 PM PDT 24 |
Finished | May 05 01:04:25 PM PDT 24 |
Peak memory | 205056 kb |
Host | smart-446fcbf2-9b3b-4338-ab83-eed26e072f4a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2429785391 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.2429785391 |
Directory | /workspace/0.rv_dm_smoke/latest |
Test location | /workspace/coverage/default/0.rv_dm_stress_all.1556068918 |
Short name | T14 |
Test name | |
Test status | |
Simulation time | 3254075234 ps |
CPU time | 12.21 seconds |
Started | May 05 01:04:21 PM PDT 24 |
Finished | May 05 01:04:34 PM PDT 24 |
Peak memory | 205464 kb |
Host | smart-9552683c-8245-42d0-bc79-7a5ab4305f7e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556068918 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.1556068918 |
Directory | /workspace/0.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/1.rv_dm_abstractcmd_status.2585858216 |
Short name | T23 |
Test name | |
Test status | |
Simulation time | 89566322 ps |
CPU time | 0.72 seconds |
Started | May 05 01:04:31 PM PDT 24 |
Finished | May 05 01:04:33 PM PDT 24 |
Peak memory | 205128 kb |
Host | smart-83068dbc-ec3a-4c26-b487-ac1cc53fd3ff |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2585858216 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.2585858216 |
Directory | /workspace/1.rv_dm_abstractcmd_status/latest |
Test location | /workspace/coverage/default/1.rv_dm_alert_test.3424396961 |
Short name | T148 |
Test name | |
Test status | |
Simulation time | 43758801 ps |
CPU time | 0.72 seconds |
Started | May 05 01:04:34 PM PDT 24 |
Finished | May 05 01:04:36 PM PDT 24 |
Peak memory | 205100 kb |
Host | smart-8bb2be95-19aa-4280-990a-ae1e2bb2c722 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424396961 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.3424396961 |
Directory | /workspace/1.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_exception.2132632547 |
Short name | T18 |
Test name | |
Test status | |
Simulation time | 473916895 ps |
CPU time | 1.45 seconds |
Started | May 05 01:04:26 PM PDT 24 |
Finished | May 05 01:04:28 PM PDT 24 |
Peak memory | 205332 kb |
Host | smart-21b21516-a2b4-45a6-a53c-6617cdad7ec8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2132632547 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.2132632547 |
Directory | /workspace/1.rv_dm_cmderr_exception/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_not_supported.3521540860 |
Short name | T129 |
Test name | |
Test status | |
Simulation time | 2175292175 ps |
CPU time | 2.6 seconds |
Started | May 05 01:04:26 PM PDT 24 |
Finished | May 05 01:04:30 PM PDT 24 |
Peak memory | 205460 kb |
Host | smart-79c83e6e-ce56-40d2-a8a0-7e7236b9308d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3521540860 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.3521540860 |
Directory | /workspace/1.rv_dm_cmderr_not_supported/latest |
Test location | /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.3920055314 |
Short name | T1 |
Test name | |
Test status | |
Simulation time | 233244612 ps |
CPU time | 0.74 seconds |
Started | May 05 01:04:34 PM PDT 24 |
Finished | May 05 01:04:36 PM PDT 24 |
Peak memory | 205096 kb |
Host | smart-af0d8a48-a16d-430e-80fc-23153ec1fbca |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3920055314 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.3920055314 |
Directory | /workspace/1.rv_dm_dataaddr_rw_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_hart_unavail.4008021268 |
Short name | T156 |
Test name | |
Test status | |
Simulation time | 81211345 ps |
CPU time | 0.74 seconds |
Started | May 05 01:04:26 PM PDT 24 |
Finished | May 05 01:04:28 PM PDT 24 |
Peak memory | 205004 kb |
Host | smart-899009da-e147-4a83-be2b-300e267eaf09 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4008021268 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.4008021268 |
Directory | /workspace/1.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.3507263714 |
Short name | T57 |
Test name | |
Test status | |
Simulation time | 126183225 ps |
CPU time | 1.02 seconds |
Started | May 05 01:04:34 PM PDT 24 |
Finished | May 05 01:04:36 PM PDT 24 |
Peak memory | 204952 kb |
Host | smart-d970642e-fb76-4a54-891c-4f48f384610b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3507263714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.3507263714 |
Directory | /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.4060898075 |
Short name | T59 |
Test name | |
Test status | |
Simulation time | 385312025 ps |
CPU time | 1.13 seconds |
Started | May 05 01:04:27 PM PDT 24 |
Finished | May 05 01:04:29 PM PDT 24 |
Peak memory | 205192 kb |
Host | smart-f447976e-da78-47ae-a80e-fb2f3a28c433 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4060898075 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.4060898075 |
Directory | /workspace/1.rv_dm_jtag_dtm_hard_reset/latest |
Test location | /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.1199978346 |
Short name | T165 |
Test name | |
Test status | |
Simulation time | 70006345 ps |
CPU time | 0.82 seconds |
Started | May 05 01:04:25 PM PDT 24 |
Finished | May 05 01:04:26 PM PDT 24 |
Peak memory | 205148 kb |
Host | smart-0203664f-8b91-4d2c-91dd-672cd2d63898 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1199978346 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.1199978346 |
Directory | /workspace/1.rv_dm_mem_tl_access_halted/latest |
Test location | /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.3703112959 |
Short name | T13 |
Test name | |
Test status | |
Simulation time | 455067211 ps |
CPU time | 1.53 seconds |
Started | May 05 01:04:27 PM PDT 24 |
Finished | May 05 01:04:29 PM PDT 24 |
Peak memory | 205332 kb |
Host | smart-373f4cb9-aa0e-457f-9239-4df82bd702b0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3703112959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.3703112959 |
Directory | /workspace/1.rv_dm_mem_tl_access_resuming/latest |
Test location | /workspace/coverage/default/1.rv_dm_ndmreset_req.3946717194 |
Short name | T3 |
Test name | |
Test status | |
Simulation time | 66785475 ps |
CPU time | 0.87 seconds |
Started | May 05 01:04:25 PM PDT 24 |
Finished | May 05 01:04:26 PM PDT 24 |
Peak memory | 205140 kb |
Host | smart-ceaea6e2-d488-452a-b213-efbae3d222b4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3946717194 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.3946717194 |
Directory | /workspace/1.rv_dm_ndmreset_req/latest |
Test location | /workspace/coverage/default/1.rv_dm_progbuf_busy.138285920 |
Short name | T17 |
Test name | |
Test status | |
Simulation time | 102193583 ps |
CPU time | 0.87 seconds |
Started | May 05 01:04:29 PM PDT 24 |
Finished | May 05 01:04:31 PM PDT 24 |
Peak memory | 205128 kb |
Host | smart-c6426aa7-6720-452f-9373-64c1a64d0a45 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=138285920 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.138285920 |
Directory | /workspace/1.rv_dm_progbuf_busy/latest |
Test location | /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.3903239653 |
Short name | T21 |
Test name | |
Test status | |
Simulation time | 76361495 ps |
CPU time | 0.91 seconds |
Started | May 05 01:04:29 PM PDT 24 |
Finished | May 05 01:04:31 PM PDT 24 |
Peak memory | 205108 kb |
Host | smart-c6f916ed-86e6-4d51-bae9-faf217420cd5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3903239653 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.3903239653 |
Directory | /workspace/1.rv_dm_progbuf_read_write_execute/latest |
Test location | /workspace/coverage/default/1.rv_dm_rom_read_access.988190723 |
Short name | T16 |
Test name | |
Test status | |
Simulation time | 119138415 ps |
CPU time | 0.78 seconds |
Started | May 05 01:04:34 PM PDT 24 |
Finished | May 05 01:04:36 PM PDT 24 |
Peak memory | 213292 kb |
Host | smart-71e43378-7b78-471f-b25a-372c743d5fe5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=988190723 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.988190723 |
Directory | /workspace/1.rv_dm_rom_read_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_sec_cm.1881082748 |
Short name | T53 |
Test name | |
Test status | |
Simulation time | 432077534 ps |
CPU time | 1.34 seconds |
Started | May 05 01:04:28 PM PDT 24 |
Finished | May 05 01:04:30 PM PDT 24 |
Peak memory | 229232 kb |
Host | smart-00cb9a48-e646-47e4-866f-683fa59b5436 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881082748 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.1881082748 |
Directory | /workspace/1.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/1.rv_dm_smoke.2151431083 |
Short name | T157 |
Test name | |
Test status | |
Simulation time | 443727232 ps |
CPU time | 1.52 seconds |
Started | May 05 01:04:20 PM PDT 24 |
Finished | May 05 01:04:22 PM PDT 24 |
Peak memory | 205248 kb |
Host | smart-60c7d8c3-325c-4479-85a2-e28d63064290 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2151431083 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.2151431083 |
Directory | /workspace/1.rv_dm_smoke/latest |
Test location | /workspace/coverage/default/10.rv_dm_alert_test.794154422 |
Short name | T143 |
Test name | |
Test status | |
Simulation time | 25812174 ps |
CPU time | 0.71 seconds |
Started | May 05 01:04:46 PM PDT 24 |
Finished | May 05 01:04:47 PM PDT 24 |
Peak memory | 205128 kb |
Host | smart-19879e29-61ab-4ae7-aa37-2396b0c64134 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794154422 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.794154422 |
Directory | /workspace/10.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/11.rv_dm_alert_test.217196312 |
Short name | T141 |
Test name | |
Test status | |
Simulation time | 45832716 ps |
CPU time | 0.73 seconds |
Started | May 05 01:04:53 PM PDT 24 |
Finished | May 05 01:04:55 PM PDT 24 |
Peak memory | 205000 kb |
Host | smart-478aaebc-777b-439e-8b98-59b0d171198c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217196312 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.217196312 |
Directory | /workspace/11.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/13.rv_dm_alert_test.2834124190 |
Short name | T2 |
Test name | |
Test status | |
Simulation time | 32594789 ps |
CPU time | 0.69 seconds |
Started | May 05 01:04:47 PM PDT 24 |
Finished | May 05 01:04:48 PM PDT 24 |
Peak memory | 205124 kb |
Host | smart-5aa4faa9-f357-4b81-848c-f55baee64846 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834124190 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.2834124190 |
Directory | /workspace/13.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.1229481491 |
Short name | T27 |
Test name | |
Test status | |
Simulation time | 2412883731 ps |
CPU time | 4.75 seconds |
Started | May 05 01:04:46 PM PDT 24 |
Finished | May 05 01:04:52 PM PDT 24 |
Peak memory | 205536 kb |
Host | smart-f638cb3d-f6d5-4cd3-b0d8-3196fa34982e |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1229481491 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_ tl_access.1229481491 |
Directory | /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/14.rv_dm_alert_test.2879626248 |
Short name | T142 |
Test name | |
Test status | |
Simulation time | 59474825 ps |
CPU time | 0.71 seconds |
Started | May 05 01:04:51 PM PDT 24 |
Finished | May 05 01:04:52 PM PDT 24 |
Peak memory | 205116 kb |
Host | smart-efca2a2c-fd4b-4483-a494-e31279699271 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879626248 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.2879626248 |
Directory | /workspace/14.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/14.rv_dm_stress_all.2229339844 |
Short name | T19 |
Test name | |
Test status | |
Simulation time | 4749014826 ps |
CPU time | 14.58 seconds |
Started | May 05 01:04:53 PM PDT 24 |
Finished | May 05 01:05:08 PM PDT 24 |
Peak memory | 205444 kb |
Host | smart-02282530-0f78-4f0c-b35d-72d73be7957a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229339844 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.2229339844 |
Directory | /workspace/14.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/15.rv_dm_alert_test.2944885985 |
Short name | T50 |
Test name | |
Test status | |
Simulation time | 25847848 ps |
CPU time | 0.73 seconds |
Started | May 05 01:04:49 PM PDT 24 |
Finished | May 05 01:04:51 PM PDT 24 |
Peak memory | 205152 kb |
Host | smart-0a93c897-f7db-40a5-89ca-9caa2bad18fa |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944885985 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.2944885985 |
Directory | /workspace/15.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/16.rv_dm_alert_test.3445668487 |
Short name | T140 |
Test name | |
Test status | |
Simulation time | 34368957 ps |
CPU time | 0.67 seconds |
Started | May 05 01:04:48 PM PDT 24 |
Finished | May 05 01:04:49 PM PDT 24 |
Peak memory | 205128 kb |
Host | smart-00c75981-3354-4519-9720-c31c30038521 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445668487 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.3445668487 |
Directory | /workspace/16.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/17.rv_dm_alert_test.3241431245 |
Short name | T164 |
Test name | |
Test status | |
Simulation time | 61321842 ps |
CPU time | 0.7 seconds |
Started | May 05 01:04:54 PM PDT 24 |
Finished | May 05 01:04:55 PM PDT 24 |
Peak memory | 205200 kb |
Host | smart-b5533c6d-318b-4e4b-876c-3b8a84e7fabf |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241431245 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.3241431245 |
Directory | /workspace/17.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/18.rv_dm_alert_test.3876451557 |
Short name | T169 |
Test name | |
Test status | |
Simulation time | 34119418 ps |
CPU time | 0.76 seconds |
Started | May 05 01:04:55 PM PDT 24 |
Finished | May 05 01:04:57 PM PDT 24 |
Peak memory | 205136 kb |
Host | smart-39d77f3a-27a0-4ade-b338-e5d98b669ee8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876451557 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.3876451557 |
Directory | /workspace/18.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/19.rv_dm_alert_test.1175909801 |
Short name | T44 |
Test name | |
Test status | |
Simulation time | 149539402 ps |
CPU time | 0.7 seconds |
Started | May 05 01:04:58 PM PDT 24 |
Finished | May 05 01:05:00 PM PDT 24 |
Peak memory | 205092 kb |
Host | smart-9bae76c8-6e98-4083-9601-3a165e108b80 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175909801 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.1175909801 |
Directory | /workspace/19.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/2.rv_dm_alert_test.3996727408 |
Short name | T131 |
Test name | |
Test status | |
Simulation time | 74542039 ps |
CPU time | 0.77 seconds |
Started | May 05 01:04:34 PM PDT 24 |
Finished | May 05 01:04:35 PM PDT 24 |
Peak memory | 205124 kb |
Host | smart-28b48012-b156-4279-aa1a-5e4cd7b9a502 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996727408 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.3996727408 |
Directory | /workspace/2.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/2.rv_dm_hart_unavail.948432315 |
Short name | T158 |
Test name | |
Test status | |
Simulation time | 262314371 ps |
CPU time | 0.9 seconds |
Started | May 05 01:04:31 PM PDT 24 |
Finished | May 05 01:04:33 PM PDT 24 |
Peak memory | 204984 kb |
Host | smart-a89c2de6-5406-4bd6-8b25-9b3ec42573cc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=948432315 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.948432315 |
Directory | /workspace/2.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/2.rv_dm_sec_cm.629558898 |
Short name | T29 |
Test name | |
Test status | |
Simulation time | 511572899 ps |
CPU time | 1.33 seconds |
Started | May 05 01:04:32 PM PDT 24 |
Finished | May 05 01:04:34 PM PDT 24 |
Peak memory | 237072 kb |
Host | smart-33f4ec95-fa8b-43a2-8347-c060e80459f4 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629558898 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.629558898 |
Directory | /workspace/2.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/20.rv_dm_alert_test.1356518302 |
Short name | T111 |
Test name | |
Test status | |
Simulation time | 57542929 ps |
CPU time | 0.75 seconds |
Started | May 05 01:05:03 PM PDT 24 |
Finished | May 05 01:05:04 PM PDT 24 |
Peak memory | 205108 kb |
Host | smart-63f96116-5b45-4147-8bf5-fb3d519ba6a8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356518302 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.1356518302 |
Directory | /workspace/20.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/21.rv_dm_alert_test.977784615 |
Short name | T47 |
Test name | |
Test status | |
Simulation time | 58381484 ps |
CPU time | 0.72 seconds |
Started | May 05 01:05:00 PM PDT 24 |
Finished | May 05 01:05:02 PM PDT 24 |
Peak memory | 205052 kb |
Host | smart-ebc78780-e0f0-49d0-a17b-a30b09bc5b85 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977784615 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.977784615 |
Directory | /workspace/21.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/22.rv_dm_alert_test.2878984457 |
Short name | T144 |
Test name | |
Test status | |
Simulation time | 35157452 ps |
CPU time | 0.77 seconds |
Started | May 05 01:05:01 PM PDT 24 |
Finished | May 05 01:05:02 PM PDT 24 |
Peak memory | 205128 kb |
Host | smart-158cd029-7d56-498c-b618-bc002fd77db2 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878984457 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.2878984457 |
Directory | /workspace/22.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/23.rv_dm_alert_test.2308407349 |
Short name | T149 |
Test name | |
Test status | |
Simulation time | 25682824 ps |
CPU time | 0.77 seconds |
Started | May 05 01:05:01 PM PDT 24 |
Finished | May 05 01:05:03 PM PDT 24 |
Peak memory | 205136 kb |
Host | smart-38f66f11-240d-46cc-b2bd-537149195bf3 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308407349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.2308407349 |
Directory | /workspace/23.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/24.rv_dm_alert_test.1808689438 |
Short name | T55 |
Test name | |
Test status | |
Simulation time | 58864136 ps |
CPU time | 0.69 seconds |
Started | May 05 01:05:00 PM PDT 24 |
Finished | May 05 01:05:01 PM PDT 24 |
Peak memory | 205068 kb |
Host | smart-b9882ef8-6eaa-4407-b2e3-ca8925f2c692 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808689438 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.1808689438 |
Directory | /workspace/24.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/25.rv_dm_alert_test.2485064724 |
Short name | T171 |
Test name | |
Test status | |
Simulation time | 29032818 ps |
CPU time | 0.66 seconds |
Started | May 05 01:05:02 PM PDT 24 |
Finished | May 05 01:05:04 PM PDT 24 |
Peak memory | 205124 kb |
Host | smart-ddc04700-35dd-4bf7-8774-6eb5fc792276 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485064724 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.2485064724 |
Directory | /workspace/25.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/26.rv_dm_alert_test.2500521540 |
Short name | T138 |
Test name | |
Test status | |
Simulation time | 20083813 ps |
CPU time | 0.72 seconds |
Started | May 05 01:05:04 PM PDT 24 |
Finished | May 05 01:05:05 PM PDT 24 |
Peak memory | 205080 kb |
Host | smart-eb2a0802-198a-413c-b0bb-35810d246c7f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500521540 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.2500521540 |
Directory | /workspace/26.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/27.rv_dm_alert_test.420205768 |
Short name | T154 |
Test name | |
Test status | |
Simulation time | 21363958 ps |
CPU time | 0.72 seconds |
Started | May 05 01:05:00 PM PDT 24 |
Finished | May 05 01:05:02 PM PDT 24 |
Peak memory | 205144 kb |
Host | smart-95619c64-6afa-4296-9d10-ca35fa1ec564 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420205768 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.420205768 |
Directory | /workspace/27.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/28.rv_dm_alert_test.2766986004 |
Short name | T170 |
Test name | |
Test status | |
Simulation time | 19728869 ps |
CPU time | 0.77 seconds |
Started | May 05 01:05:02 PM PDT 24 |
Finished | May 05 01:05:03 PM PDT 24 |
Peak memory | 205052 kb |
Host | smart-cb769e0f-9aef-4ce1-99ad-64587c46031d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766986004 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.2766986004 |
Directory | /workspace/28.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/3.rv_dm_alert_test.2380906324 |
Short name | T132 |
Test name | |
Test status | |
Simulation time | 72304521 ps |
CPU time | 0.73 seconds |
Started | May 05 01:04:34 PM PDT 24 |
Finished | May 05 01:04:35 PM PDT 24 |
Peak memory | 205128 kb |
Host | smart-5d4da9bb-9293-462b-8f1b-2f8819f3298c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380906324 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.2380906324 |
Directory | /workspace/3.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/3.rv_dm_hart_unavail.4000392487 |
Short name | T166 |
Test name | |
Test status | |
Simulation time | 67333246 ps |
CPU time | 0.72 seconds |
Started | May 05 01:04:35 PM PDT 24 |
Finished | May 05 01:04:37 PM PDT 24 |
Peak memory | 205184 kb |
Host | smart-485e26a8-892e-4010-b883-80bdade23b05 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4000392487 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.4000392487 |
Directory | /workspace/3.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/3.rv_dm_sec_cm.2139040963 |
Short name | T31 |
Test name | |
Test status | |
Simulation time | 389632189 ps |
CPU time | 1.2 seconds |
Started | May 05 01:04:35 PM PDT 24 |
Finished | May 05 01:04:37 PM PDT 24 |
Peak memory | 229464 kb |
Host | smart-24820f49-746f-4444-b63e-ffb50f296ea8 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139040963 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.2139040963 |
Directory | /workspace/3.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/30.rv_dm_alert_test.242142004 |
Short name | T4 |
Test name | |
Test status | |
Simulation time | 76037440 ps |
CPU time | 0.71 seconds |
Started | May 05 01:05:12 PM PDT 24 |
Finished | May 05 01:05:13 PM PDT 24 |
Peak memory | 205132 kb |
Host | smart-51e857c6-8fc9-4be9-85d1-aa5914a7af00 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242142004 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.242142004 |
Directory | /workspace/30.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/31.rv_dm_alert_test.2760856962 |
Short name | T36 |
Test name | |
Test status | |
Simulation time | 39330897 ps |
CPU time | 0.68 seconds |
Started | May 05 01:05:09 PM PDT 24 |
Finished | May 05 01:05:11 PM PDT 24 |
Peak memory | 205108 kb |
Host | smart-d99717f1-0b10-400d-abf1-ab94640c1f6c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760856962 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.2760856962 |
Directory | /workspace/31.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/31.rv_dm_stress_all.1021312172 |
Short name | T110 |
Test name | |
Test status | |
Simulation time | 1286992332 ps |
CPU time | 4.78 seconds |
Started | May 05 01:05:08 PM PDT 24 |
Finished | May 05 01:05:13 PM PDT 24 |
Peak memory | 205312 kb |
Host | smart-edcdb4aa-4ef1-430d-a964-0ba00d96507b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021312172 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.1021312172 |
Directory | /workspace/31.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/32.rv_dm_alert_test.842166700 |
Short name | T153 |
Test name | |
Test status | |
Simulation time | 25745481 ps |
CPU time | 0.69 seconds |
Started | May 05 01:05:08 PM PDT 24 |
Finished | May 05 01:05:09 PM PDT 24 |
Peak memory | 205132 kb |
Host | smart-5f3ec7b2-ae79-454d-a19d-b3e79b07c355 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842166700 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.842166700 |
Directory | /workspace/32.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/33.rv_dm_alert_test.1845154592 |
Short name | T163 |
Test name | |
Test status | |
Simulation time | 35035664 ps |
CPU time | 0.73 seconds |
Started | May 05 01:05:09 PM PDT 24 |
Finished | May 05 01:05:11 PM PDT 24 |
Peak memory | 205132 kb |
Host | smart-a3a9766e-1e07-4d21-babe-226b9d1b7f52 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845154592 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.1845154592 |
Directory | /workspace/33.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/34.rv_dm_alert_test.1370622033 |
Short name | T49 |
Test name | |
Test status | |
Simulation time | 24619593 ps |
CPU time | 0.71 seconds |
Started | May 05 01:05:07 PM PDT 24 |
Finished | May 05 01:05:08 PM PDT 24 |
Peak memory | 205116 kb |
Host | smart-e2a7f2d6-c8d4-4dd3-89b8-a9b11afe19df |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370622033 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.1370622033 |
Directory | /workspace/34.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/35.rv_dm_alert_test.2370467143 |
Short name | T145 |
Test name | |
Test status | |
Simulation time | 18007931 ps |
CPU time | 0.85 seconds |
Started | May 05 01:05:05 PM PDT 24 |
Finished | May 05 01:05:07 PM PDT 24 |
Peak memory | 205316 kb |
Host | smart-22b1d308-57a0-449c-8b98-8bd838bfd30e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370467143 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.2370467143 |
Directory | /workspace/35.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/36.rv_dm_alert_test.1252123742 |
Short name | T162 |
Test name | |
Test status | |
Simulation time | 50459064 ps |
CPU time | 0.7 seconds |
Started | May 05 01:05:07 PM PDT 24 |
Finished | May 05 01:05:08 PM PDT 24 |
Peak memory | 205048 kb |
Host | smart-e8e67f9c-6e0a-44dc-b64b-24a460ec6e10 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252123742 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.1252123742 |
Directory | /workspace/36.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/37.rv_dm_alert_test.3496446910 |
Short name | T151 |
Test name | |
Test status | |
Simulation time | 24993063 ps |
CPU time | 0.72 seconds |
Started | May 05 01:05:17 PM PDT 24 |
Finished | May 05 01:05:19 PM PDT 24 |
Peak memory | 205044 kb |
Host | smart-2e93d41f-298f-4343-b73a-db18b1832a96 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496446910 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.3496446910 |
Directory | /workspace/37.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/38.rv_dm_alert_test.419413685 |
Short name | T159 |
Test name | |
Test status | |
Simulation time | 21639572 ps |
CPU time | 0.72 seconds |
Started | May 05 01:05:17 PM PDT 24 |
Finished | May 05 01:05:18 PM PDT 24 |
Peak memory | 205132 kb |
Host | smart-7e727c38-8963-4ced-9fc8-f04b2a40ab0e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419413685 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.419413685 |
Directory | /workspace/38.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/39.rv_dm_alert_test.2912755097 |
Short name | T150 |
Test name | |
Test status | |
Simulation time | 22985400 ps |
CPU time | 0.75 seconds |
Started | May 05 01:05:18 PM PDT 24 |
Finished | May 05 01:05:19 PM PDT 24 |
Peak memory | 205116 kb |
Host | smart-70044780-c9a1-4ff8-9431-06a00bc8f897 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912755097 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.2912755097 |
Directory | /workspace/39.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/4.rv_dm_alert_test.751152730 |
Short name | T46 |
Test name | |
Test status | |
Simulation time | 20700779 ps |
CPU time | 0.73 seconds |
Started | May 05 01:04:41 PM PDT 24 |
Finished | May 05 01:04:43 PM PDT 24 |
Peak memory | 205128 kb |
Host | smart-89645a84-5890-4325-9166-c92fc9807e6d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751152730 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.751152730 |
Directory | /workspace/4.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/4.rv_dm_hart_unavail.826847177 |
Short name | T167 |
Test name | |
Test status | |
Simulation time | 51882138 ps |
CPU time | 0.73 seconds |
Started | May 05 01:04:32 PM PDT 24 |
Finished | May 05 01:04:33 PM PDT 24 |
Peak memory | 205016 kb |
Host | smart-b51a4f0a-853a-457e-89a2-61ab7bbe10db |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=826847177 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.826847177 |
Directory | /workspace/4.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/4.rv_dm_sec_cm.2077586085 |
Short name | T54 |
Test name | |
Test status | |
Simulation time | 286362697 ps |
CPU time | 1.4 seconds |
Started | May 05 01:04:40 PM PDT 24 |
Finished | May 05 01:04:42 PM PDT 24 |
Peak memory | 229304 kb |
Host | smart-edff84b6-b72c-4843-9171-592ab5be1aba |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077586085 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.2077586085 |
Directory | /workspace/4.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/40.rv_dm_alert_test.3815308924 |
Short name | T139 |
Test name | |
Test status | |
Simulation time | 30593463 ps |
CPU time | 0.72 seconds |
Started | May 05 01:05:11 PM PDT 24 |
Finished | May 05 01:05:12 PM PDT 24 |
Peak memory | 205140 kb |
Host | smart-c0abc0aa-d709-4bee-98af-4fb35ced15d2 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815308924 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.3815308924 |
Directory | /workspace/40.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/41.rv_dm_alert_test.4183537634 |
Short name | T152 |
Test name | |
Test status | |
Simulation time | 44712501 ps |
CPU time | 0.75 seconds |
Started | May 05 01:05:18 PM PDT 24 |
Finished | May 05 01:05:19 PM PDT 24 |
Peak memory | 205044 kb |
Host | smart-1f5098d9-afe0-4ebb-9a28-d1031aaf3d82 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183537634 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.4183537634 |
Directory | /workspace/41.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/42.rv_dm_alert_test.2269791178 |
Short name | T65 |
Test name | |
Test status | |
Simulation time | 17664162 ps |
CPU time | 0.73 seconds |
Started | May 05 01:05:14 PM PDT 24 |
Finished | May 05 01:05:15 PM PDT 24 |
Peak memory | 205124 kb |
Host | smart-5cf8fc94-e86f-49dc-bf71-c7cbf5c11d7b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269791178 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.2269791178 |
Directory | /workspace/42.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/43.rv_dm_alert_test.3987028218 |
Short name | T113 |
Test name | |
Test status | |
Simulation time | 48558974 ps |
CPU time | 0.69 seconds |
Started | May 05 01:05:21 PM PDT 24 |
Finished | May 05 01:05:22 PM PDT 24 |
Peak memory | 205048 kb |
Host | smart-6a2d0f6c-47ac-4705-8a64-8575303916a4 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987028218 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.3987028218 |
Directory | /workspace/43.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/44.rv_dm_alert_test.2935382615 |
Short name | T135 |
Test name | |
Test status | |
Simulation time | 42814037 ps |
CPU time | 0.74 seconds |
Started | May 05 01:05:15 PM PDT 24 |
Finished | May 05 01:05:17 PM PDT 24 |
Peak memory | 205128 kb |
Host | smart-62b6bd21-294a-416e-ab0d-d9a7a75e52b8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935382615 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.2935382615 |
Directory | /workspace/44.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/45.rv_dm_alert_test.2756906615 |
Short name | T52 |
Test name | |
Test status | |
Simulation time | 204940110 ps |
CPU time | 0.7 seconds |
Started | May 05 01:05:13 PM PDT 24 |
Finished | May 05 01:05:14 PM PDT 24 |
Peak memory | 205124 kb |
Host | smart-6d7ad0d3-5eb8-4ee6-819b-bcf278ebb398 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756906615 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.2756906615 |
Directory | /workspace/45.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/46.rv_dm_alert_test.2526808165 |
Short name | T146 |
Test name | |
Test status | |
Simulation time | 21416021 ps |
CPU time | 0.79 seconds |
Started | May 05 01:05:15 PM PDT 24 |
Finished | May 05 01:05:17 PM PDT 24 |
Peak memory | 205316 kb |
Host | smart-c3154225-f9ec-49b5-9aa1-0921178614b4 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526808165 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.2526808165 |
Directory | /workspace/46.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/46.rv_dm_stress_all.3488525214 |
Short name | T9 |
Test name | |
Test status | |
Simulation time | 3677524733 ps |
CPU time | 7.09 seconds |
Started | May 05 01:05:12 PM PDT 24 |
Finished | May 05 01:05:20 PM PDT 24 |
Peak memory | 205464 kb |
Host | smart-dd89ac8d-657d-46a8-86e6-0fc5a0261e64 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488525214 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.3488525214 |
Directory | /workspace/46.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/47.rv_dm_alert_test.3460991139 |
Short name | T147 |
Test name | |
Test status | |
Simulation time | 29948003 ps |
CPU time | 0.71 seconds |
Started | May 05 01:05:17 PM PDT 24 |
Finished | May 05 01:05:19 PM PDT 24 |
Peak memory | 205148 kb |
Host | smart-ea7749f4-286d-4178-830a-9b99a31df95f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460991139 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.3460991139 |
Directory | /workspace/47.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/48.rv_dm_alert_test.4165772557 |
Short name | T133 |
Test name | |
Test status | |
Simulation time | 39261540 ps |
CPU time | 0.68 seconds |
Started | May 05 01:05:18 PM PDT 24 |
Finished | May 05 01:05:20 PM PDT 24 |
Peak memory | 205152 kb |
Host | smart-0234994a-c9c8-4feb-9cb6-aa6755236a60 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165772557 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.4165772557 |
Directory | /workspace/48.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/49.rv_dm_alert_test.2318425522 |
Short name | T37 |
Test name | |
Test status | |
Simulation time | 34250964 ps |
CPU time | 0.77 seconds |
Started | May 05 01:05:20 PM PDT 24 |
Finished | May 05 01:05:22 PM PDT 24 |
Peak memory | 205052 kb |
Host | smart-8280a1ed-3fbd-49de-8f8a-fca8ce24ad3b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318425522 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.2318425522 |
Directory | /workspace/49.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/5.rv_dm_alert_test.4180955231 |
Short name | T137 |
Test name | |
Test status | |
Simulation time | 17737158 ps |
CPU time | 0.72 seconds |
Started | May 05 01:04:41 PM PDT 24 |
Finished | May 05 01:04:42 PM PDT 24 |
Peak memory | 205308 kb |
Host | smart-76e399ca-dd94-44c3-bb1d-1e30ae6760e3 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180955231 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.4180955231 |
Directory | /workspace/5.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/5.rv_dm_stress_all.1314408784 |
Short name | T6 |
Test name | |
Test status | |
Simulation time | 4117236020 ps |
CPU time | 12.63 seconds |
Started | May 05 01:04:39 PM PDT 24 |
Finished | May 05 01:04:52 PM PDT 24 |
Peak memory | 205484 kb |
Host | smart-426d510f-7314-4011-884a-c6fc60242704 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314408784 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.1314408784 |
Directory | /workspace/5.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/6.rv_dm_alert_test.4159294591 |
Short name | T134 |
Test name | |
Test status | |
Simulation time | 34877656 ps |
CPU time | 0.74 seconds |
Started | May 05 01:04:39 PM PDT 24 |
Finished | May 05 01:04:40 PM PDT 24 |
Peak memory | 205124 kb |
Host | smart-94304972-5aca-41ef-bc6d-72799509c767 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159294591 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.4159294591 |
Directory | /workspace/6.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/7.rv_dm_alert_test.17482378 |
Short name | T51 |
Test name | |
Test status | |
Simulation time | 28992990 ps |
CPU time | 0.7 seconds |
Started | May 05 01:04:39 PM PDT 24 |
Finished | May 05 01:04:40 PM PDT 24 |
Peak memory | 205140 kb |
Host | smart-817a153d-017d-4a2c-ac76-06e41ff5e833 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17482378 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.17482378 |
Directory | /workspace/7.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/8.rv_dm_alert_test.1755985907 |
Short name | T155 |
Test name | |
Test status | |
Simulation time | 14839329 ps |
CPU time | 0.69 seconds |
Started | May 05 01:04:46 PM PDT 24 |
Finished | May 05 01:04:47 PM PDT 24 |
Peak memory | 205132 kb |
Host | smart-adc5f2fa-8f82-43ab-8a32-e04da6c39db9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755985907 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.1755985907 |
Directory | /workspace/8.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/9.rv_dm_alert_test.2296389948 |
Short name | T32 |
Test name | |
Test status | |
Simulation time | 43031210 ps |
CPU time | 0.74 seconds |
Started | May 05 01:04:44 PM PDT 24 |
Finished | May 05 01:04:46 PM PDT 24 |
Peak memory | 205136 kb |
Host | smart-9629a489-dd6c-4a69-9e1d-d70516b98add |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296389948 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.2296389948 |
Directory | /workspace/9.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/9.rv_dm_sba_tl_access.2615079580 |
Short name | T64 |
Test name | |
Test status | |
Simulation time | 3250135963 ps |
CPU time | 8.97 seconds |
Started | May 05 01:04:44 PM PDT 24 |
Finished | May 05 01:04:53 PM PDT 24 |
Peak memory | 205556 kb |
Host | smart-b2dbe4e0-f896-4cc4-a881-01d865a3bb1b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2615079580 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.2615079580 |
Directory | /workspace/9.rv_dm_sba_tl_access/latest |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |