Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
79.06 93.76 79.12 87.53 74.36 82.50 98.52 37.64


Total test records in report: 303
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html
T259 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.4169953309 May 07 03:10:12 PM PDT 24 May 07 03:10:16 PM PDT 24 114552876 ps
T260 /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.785393976 May 07 03:10:12 PM PDT 24 May 07 03:10:27 PM PDT 24 26141861320 ps
T261 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.1075238576 May 07 03:10:16 PM PDT 24 May 07 03:10:20 PM PDT 24 26587027 ps
T262 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3956508806 May 07 03:10:20 PM PDT 24 May 07 03:10:25 PM PDT 24 269971274 ps
T128 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2761822762 May 07 03:10:25 PM PDT 24 May 07 03:10:42 PM PDT 24 441692263 ps
T263 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3669995081 May 07 03:10:26 PM PDT 24 May 07 03:10:38 PM PDT 24 668950044 ps
T264 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.2292081352 May 07 03:10:12 PM PDT 24 May 07 03:10:16 PM PDT 24 48598429 ps
T265 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.3835153235 May 07 03:10:18 PM PDT 24 May 07 03:10:41 PM PDT 24 7267825309 ps
T266 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.3837912282 May 07 03:10:12 PM PDT 24 May 07 03:10:16 PM PDT 24 364027493 ps
T267 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.4034332010 May 07 03:10:20 PM PDT 24 May 07 03:10:23 PM PDT 24 163184724 ps
T268 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1050635527 May 07 03:10:18 PM PDT 24 May 07 03:10:22 PM PDT 24 49964303 ps
T269 /workspace/coverage/cover_reg_top/10.rv_dm_tap_fsm_rand_reset.2937666331 May 07 03:10:25 PM PDT 24 May 07 03:10:40 PM PDT 24 11089021881 ps
T132 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3612533289 May 07 03:10:41 PM PDT 24 May 07 03:11:03 PM PDT 24 4188039486 ps
T270 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2789780718 May 07 03:10:10 PM PDT 24 May 07 03:10:12 PM PDT 24 141573773 ps
T271 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.636948471 May 07 03:10:18 PM PDT 24 May 07 03:10:24 PM PDT 24 1181297251 ps
T272 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.2064841435 May 07 03:10:20 PM PDT 24 May 07 03:11:30 PM PDT 24 18817653624 ps
T273 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.3063813994 May 07 03:10:15 PM PDT 24 May 07 03:11:12 PM PDT 24 1450792889 ps
T274 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.273547353 May 07 03:10:19 PM PDT 24 May 07 03:10:47 PM PDT 24 3831726917 ps
T134 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3559622608 May 07 03:10:17 PM PDT 24 May 07 03:10:29 PM PDT 24 458159912 ps
T275 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.3131526090 May 07 03:10:22 PM PDT 24 May 07 03:10:26 PM PDT 24 50400936 ps
T276 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.1357678226 May 07 03:10:38 PM PDT 24 May 07 03:10:42 PM PDT 24 86773173 ps
T129 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.3293755935 May 07 03:10:26 PM PDT 24 May 07 03:10:44 PM PDT 24 3581506899 ps
T277 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.3293767418 May 07 03:10:20 PM PDT 24 May 07 03:10:24 PM PDT 24 41785183 ps
T278 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.898827983 May 07 03:10:26 PM PDT 24 May 07 03:10:28 PM PDT 24 30098523 ps
T279 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.1377940395 May 07 03:10:35 PM PDT 24 May 07 03:10:41 PM PDT 24 2112638744 ps
T280 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1377333167 May 07 03:10:11 PM PDT 24 May 07 03:10:21 PM PDT 24 3028087660 ps
T281 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.950591516 May 07 03:10:15 PM PDT 24 May 07 03:10:46 PM PDT 24 2342526055 ps
T282 /workspace/coverage/cover_reg_top/22.rv_dm_tap_fsm_rand_reset.1514107081 May 07 03:10:44 PM PDT 24 May 07 03:11:31 PM PDT 24 13933229294 ps
T283 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3417658877 May 07 03:10:37 PM PDT 24 May 07 03:10:46 PM PDT 24 2934402060 ps
T100 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.1679578138 May 07 03:10:33 PM PDT 24 May 07 03:10:37 PM PDT 24 77399850 ps
T284 /workspace/coverage/cover_reg_top/23.rv_dm_tap_fsm_rand_reset.2532880767 May 07 03:10:47 PM PDT 24 May 07 03:11:08 PM PDT 24 5287101559 ps
T285 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.3343812936 May 07 03:10:26 PM PDT 24 May 07 03:10:30 PM PDT 24 100025093 ps
T286 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.918774033 May 07 03:10:14 PM PDT 24 May 07 03:10:19 PM PDT 24 129537924 ps
T287 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.4181765797 May 07 03:10:15 PM PDT 24 May 07 03:10:21 PM PDT 24 629532801 ps
T288 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3996173480 May 07 03:10:46 PM PDT 24 May 07 03:10:50 PM PDT 24 403093446 ps
T289 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.2936853385 May 07 03:10:37 PM PDT 24 May 07 03:10:39 PM PDT 24 240612388 ps
T290 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2339531074 May 07 03:10:37 PM PDT 24 May 07 03:10:41 PM PDT 24 309091120 ps
T291 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.201076011 May 07 03:10:20 PM PDT 24 May 07 03:10:27 PM PDT 24 152206211 ps
T292 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.4228597434 May 07 03:10:20 PM PDT 24 May 07 03:10:24 PM PDT 24 85023601 ps
T293 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.882520535 May 07 03:10:15 PM PDT 24 May 07 03:10:36 PM PDT 24 15899043179 ps
T294 /workspace/coverage/cover_reg_top/32.rv_dm_tap_fsm_rand_reset.474724958 May 07 03:10:44 PM PDT 24 May 07 03:11:01 PM PDT 24 8729648144 ps
T295 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.4099408664 May 07 03:10:31 PM PDT 24 May 07 03:10:33 PM PDT 24 256583337 ps
T89 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.3900854469 May 07 03:10:21 PM PDT 24 May 07 03:10:25 PM PDT 24 676424257 ps
T296 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1071373486 May 07 03:10:30 PM PDT 24 May 07 03:10:36 PM PDT 24 582294733 ps
T297 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.702373294 May 07 03:10:18 PM PDT 24 May 07 03:10:22 PM PDT 24 61141404 ps
T298 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.661624593 May 07 03:10:15 PM PDT 24 May 07 03:10:20 PM PDT 24 382780226 ps
T299 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3605045784 May 07 03:10:12 PM PDT 24 May 07 03:10:46 PM PDT 24 3844419783 ps
T300 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2065263177 May 07 03:10:20 PM PDT 24 May 07 03:10:31 PM PDT 24 1051518218 ps
T301 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.2034709728 May 07 03:10:39 PM PDT 24 May 07 03:10:43 PM PDT 24 129075343 ps
T302 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.779726982 May 07 03:10:31 PM PDT 24 May 07 03:10:51 PM PDT 24 910975471 ps
T101 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.4082717611 May 07 03:10:25 PM PDT 24 May 07 03:10:34 PM PDT 24 590423477 ps
T303 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.4012923942 May 07 03:10:13 PM PDT 24 May 07 03:10:17 PM PDT 24 40286865 ps
T121 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.1749353957 May 07 03:10:20 PM PDT 24 May 07 03:10:27 PM PDT 24 144160540 ps

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.2014672375
Short name T3
Test name
Test status
Simulation time 3157875577 ps
CPU time 3.63 seconds
Started May 07 03:22:07 PM PDT 24
Finished May 07 03:22:13 PM PDT 24
Peak memory 205448 kb
Host smart-3a3fee9e-0d8b-44e6-87b2-faea05915672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014672375 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.2014672375
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.1015109043
Short name T2
Test name
Test status
Simulation time 133137653 ps
CPU time 0.73 seconds
Started May 07 03:22:27 PM PDT 24
Finished May 07 03:22:28 PM PDT 24
Peak memory 205212 kb
Host smart-ee699b64-a8d5-4d72-867c-f3195c0d0f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015109043 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.1015109043
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.3184393572
Short name T30
Test name
Test status
Simulation time 18437801637 ps
CPU time 34.24 seconds
Started May 07 03:22:42 PM PDT 24
Finished May 07 03:23:19 PM PDT 24
Peak memory 213860 kb
Host smart-24a30efd-27f3-44d0-af0d-3182a7d91137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184393572 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.3184393572
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2311895941
Short name T72
Test name
Test status
Simulation time 1382451567 ps
CPU time 4.23 seconds
Started May 07 03:10:30 PM PDT 24
Finished May 07 03:10:36 PM PDT 24
Peak memory 217924 kb
Host smart-bb64545c-36a2-4923-8a65-2f33d0be9a37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311895941 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.2311895941
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.448984311
Short name T36
Test name
Test status
Simulation time 20585945 ps
CPU time 0.77 seconds
Started May 07 03:22:47 PM PDT 24
Finished May 07 03:22:50 PM PDT 24
Peak memory 205148 kb
Host smart-76be5c4c-eb2b-48ae-95ab-72567be67e62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448984311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.448984311
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_stress_all.1667341702
Short name T13
Test name
Test status
Simulation time 8714383153 ps
CPU time 7.53 seconds
Started May 07 03:22:54 PM PDT 24
Finished May 07 03:23:04 PM PDT 24
Peak memory 205508 kb
Host smart-f2754826-a9a3-4961-a358-f2c41902004e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667341702 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.1667341702
Directory /workspace/44.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/20.rv_dm_tap_fsm_rand_reset.3325242940
Short name T86
Test name
Test status
Simulation time 10237608605 ps
CPU time 19.63 seconds
Started May 07 03:10:44 PM PDT 24
Finished May 07 03:11:05 PM PDT 24
Peak memory 221232 kb
Host smart-98b59975-b595-4aea-98e5-c9d1455fb10e
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325242940 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 20.rv_dm_tap_fsm_rand_reset.3325242940
Directory /workspace/20.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.410256546
Short name T33
Test name
Test status
Simulation time 170882955 ps
CPU time 1.2 seconds
Started May 07 03:22:15 PM PDT 24
Finished May 07 03:22:18 PM PDT 24
Peak memory 205044 kb
Host smart-a0faedf1-ab91-4587-a88e-50dccb40a648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410256546 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.410256546
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2818316899
Short name T46
Test name
Test status
Simulation time 456768470 ps
CPU time 8.16 seconds
Started May 07 03:10:37 PM PDT 24
Finished May 07 03:10:46 PM PDT 24
Peak memory 221260 kb
Host smart-83a26389-81f0-45a1-80eb-c08383e480cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818316899 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.2
818316899
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.3158549141
Short name T34
Test name
Test status
Simulation time 255704591 ps
CPU time 1.25 seconds
Started May 07 03:22:40 PM PDT 24
Finished May 07 03:22:43 PM PDT 24
Peak memory 229360 kb
Host smart-60059c30-62e8-401f-8120-045f33c10480
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158549141 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.3158549141
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.2679988221
Short name T17
Test name
Test status
Simulation time 458165473 ps
CPU time 1.14 seconds
Started May 07 03:22:10 PM PDT 24
Finished May 07 03:22:13 PM PDT 24
Peak memory 205288 kb
Host smart-23ed66a2-87fb-4fff-bdb6-3891a1747e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679988221 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.2679988221
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.226603805
Short name T8
Test name
Test status
Simulation time 2187135115 ps
CPU time 4.29 seconds
Started May 07 03:22:08 PM PDT 24
Finished May 07 03:22:15 PM PDT 24
Peak memory 205540 kb
Host smart-fa1170d6-4875-4f7a-a1d3-009001c38e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226603805 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.226603805
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.3460845509
Short name T76
Test name
Test status
Simulation time 334040836 ps
CPU time 2.24 seconds
Started May 07 03:10:11 PM PDT 24
Finished May 07 03:10:15 PM PDT 24
Peak memory 213216 kb
Host smart-2921279f-d510-4f93-a271-8f09ac00a4e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460845509 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.3460845509
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.3906646707
Short name T4
Test name
Test status
Simulation time 173605844 ps
CPU time 0.82 seconds
Started May 07 03:22:14 PM PDT 24
Finished May 07 03:22:16 PM PDT 24
Peak memory 205204 kb
Host smart-49307df4-a3b5-4466-85d6-6ece39da79e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906646707 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.3906646707
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.1710743811
Short name T14
Test name
Test status
Simulation time 57519926 ps
CPU time 0.84 seconds
Started May 07 03:22:38 PM PDT 24
Finished May 07 03:22:40 PM PDT 24
Peak memory 213424 kb
Host smart-4eee3503-b110-435c-aee0-a51cab6731a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710743811 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.1710743811
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.3184794740
Short name T95
Test name
Test status
Simulation time 61830152 ps
CPU time 2.3 seconds
Started May 07 03:10:20 PM PDT 24
Finished May 07 03:10:25 PM PDT 24
Peak memory 213148 kb
Host smart-f27fce5c-6f99-4e53-9090-89bec5706cea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184794740 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.3184794740
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tap_fsm_rand_reset.768692678
Short name T60
Test name
Test status
Simulation time 30079349549 ps
CPU time 29.31 seconds
Started May 07 03:10:37 PM PDT 24
Finished May 07 03:11:08 PM PDT 24
Peak memory 221448 kb
Host smart-4a7f6376-b908-4d8f-9253-79f668c8ceb3
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768692678 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.rv_dm_tap_fsm_rand_reset.768692678
Directory /workspace/13.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.2637511297
Short name T22
Test name
Test status
Simulation time 112956382 ps
CPU time 0.76 seconds
Started May 07 03:22:16 PM PDT 24
Finished May 07 03:22:18 PM PDT 24
Peak memory 205100 kb
Host smart-124d2e9a-13f6-45e8-8513-20aaa3188ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637511297 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.2637511297
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.717356578
Short name T58
Test name
Test status
Simulation time 310842778 ps
CPU time 0.78 seconds
Started May 07 03:10:14 PM PDT 24
Finished May 07 03:10:19 PM PDT 24
Peak memory 204508 kb
Host smart-77ce67df-1782-4e27-aae6-7cb02ad4b288
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717356578 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr
_hw_reset.717356578
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3802342898
Short name T124
Test name
Test status
Simulation time 784417362 ps
CPU time 10.93 seconds
Started May 07 03:10:14 PM PDT 24
Finished May 07 03:10:28 PM PDT 24
Peak memory 213168 kb
Host smart-d0c8fcea-54e2-45f2-8921-ee054708d526
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802342898 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.3802342898
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.3368106287
Short name T20
Test name
Test status
Simulation time 161112756 ps
CPU time 0.98 seconds
Started May 07 03:22:15 PM PDT 24
Finished May 07 03:22:18 PM PDT 24
Peak memory 205164 kb
Host smart-bfa67831-20ef-4dc6-88e3-a33c70216f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368106287 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.3368106287
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.2525184696
Short name T84
Test name
Test status
Simulation time 271272128 ps
CPU time 6.04 seconds
Started May 07 03:10:28 PM PDT 24
Finished May 07 03:10:36 PM PDT 24
Peak memory 204932 kb
Host smart-3e0e5b5f-dc60-4322-b772-981c80cf5306
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525184696 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same
_csr_outstanding.2525184696
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.1096918533
Short name T127
Test name
Test status
Simulation time 695932965 ps
CPU time 16.52 seconds
Started May 07 03:10:23 PM PDT 24
Finished May 07 03:10:41 PM PDT 24
Peak memory 213120 kb
Host smart-62f80f59-0549-402c-9289-aa32554f9975
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096918533 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.1096918533
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.3435957734
Short name T51
Test name
Test status
Simulation time 69226611 ps
CPU time 0.7 seconds
Started May 07 03:22:42 PM PDT 24
Finished May 07 03:22:44 PM PDT 24
Peak memory 205164 kb
Host smart-a90971f1-9645-4a4a-92bb-fbf210ae9afa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435957734 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.3435957734
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.376694952
Short name T88
Test name
Test status
Simulation time 1527728517 ps
CPU time 5.61 seconds
Started May 07 03:10:15 PM PDT 24
Finished May 07 03:10:24 PM PDT 24
Peak memory 204916 kb
Host smart-cd47f2ac-5ce8-42ab-bde9-95beae850285
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376694952 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr
_hw_reset.376694952
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.3729018898
Short name T123
Test name
Test status
Simulation time 2180111091 ps
CPU time 8.89 seconds
Started May 07 03:10:13 PM PDT 24
Finished May 07 03:10:25 PM PDT 24
Peak memory 221404 kb
Host smart-81827c34-babd-45bc-be0e-b5d82f204953
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729018898 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.3729018898
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.1473553021
Short name T6
Test name
Test status
Simulation time 532894764 ps
CPU time 1.35 seconds
Started May 07 03:22:11 PM PDT 24
Finished May 07 03:22:14 PM PDT 24
Peak memory 205048 kb
Host smart-4cad0503-3c59-4980-91b5-4bc04b818c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473553021 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.1473553021
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.1598921533
Short name T130
Test name
Test status
Simulation time 509990121 ps
CPU time 15.8 seconds
Started May 07 03:10:13 PM PDT 24
Finished May 07 03:10:32 PM PDT 24
Peak memory 221316 kb
Host smart-cd01530f-7c73-4e2c-8239-bc2de59df925
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598921533 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.1598921533
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.2715608892
Short name T120
Test name
Test status
Simulation time 1060077414 ps
CPU time 4.49 seconds
Started May 07 03:10:30 PM PDT 24
Finished May 07 03:10:36 PM PDT 24
Peak memory 213240 kb
Host smart-fc0159c0-0a7b-4c54-85d4-0b7572e673e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715608892 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.2715608892
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.559499656
Short name T23
Test name
Test status
Simulation time 135802291 ps
CPU time 1.11 seconds
Started May 07 03:22:09 PM PDT 24
Finished May 07 03:22:12 PM PDT 24
Peak memory 205168 kb
Host smart-e3bea259-1517-420a-8175-96b74cf19b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559499656 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.559499656
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.136917684
Short name T103
Test name
Test status
Simulation time 2291929011 ps
CPU time 31.61 seconds
Started May 07 03:10:12 PM PDT 24
Finished May 07 03:10:47 PM PDT 24
Peak memory 205008 kb
Host smart-2ab35d01-633e-4638-b982-31aa6f9c618a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136917684 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.rv_dm_csr_aliasing.136917684
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.3063813994
Short name T273
Test name
Test status
Simulation time 1450792889 ps
CPU time 52.71 seconds
Started May 07 03:10:15 PM PDT 24
Finished May 07 03:11:12 PM PDT 24
Peak memory 204832 kb
Host smart-260682c6-89d4-4c7d-a0dc-d215766b1685
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063813994 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.3063813994
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3909888899
Short name T225
Test name
Test status
Simulation time 210343068 ps
CPU time 1.66 seconds
Started May 07 03:10:12 PM PDT 24
Finished May 07 03:10:16 PM PDT 24
Peak memory 213156 kb
Host smart-0ce11157-3d9e-41fa-bce6-439efe482026
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909888899 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.3909888899
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1377333167
Short name T280
Test name
Test status
Simulation time 3028087660 ps
CPU time 8.9 seconds
Started May 07 03:10:11 PM PDT 24
Finished May 07 03:10:21 PM PDT 24
Peak memory 219252 kb
Host smart-fa700590-a73c-464f-8d60-da2561813269
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377333167 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.1377333167
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.2210185338
Short name T216
Test name
Test status
Simulation time 10145173738 ps
CPU time 16.17 seconds
Started May 07 03:10:16 PM PDT 24
Finished May 07 03:10:35 PM PDT 24
Peak memory 204896 kb
Host smart-d546772b-7b8d-4943-9e04-5e651930d58f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210185338 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.2210185338
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1726150125
Short name T221
Test name
Test status
Simulation time 20080504518 ps
CPU time 37.22 seconds
Started May 07 03:10:12 PM PDT 24
Finished May 07 03:10:51 PM PDT 24
Peak memory 204892 kb
Host smart-18ae90e5-abd3-417e-8a3f-646a5738493c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726150125 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_bit_bash.1726150125
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.3837912282
Short name T266
Test name
Test status
Simulation time 364027493 ps
CPU time 1.83 seconds
Started May 07 03:10:12 PM PDT 24
Finished May 07 03:10:16 PM PDT 24
Peak memory 204884 kb
Host smart-561a5b8e-c2f4-4330-bca8-1d491ef9b2cf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837912282 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.3837912282
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.1033989766
Short name T185
Test name
Test status
Simulation time 417961672 ps
CPU time 1.39 seconds
Started May 07 03:10:13 PM PDT 24
Finished May 07 03:10:17 PM PDT 24
Peak memory 204840 kb
Host smart-f7488f26-b2f8-4adb-86ec-e87aad7a9181
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033989766 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.1
033989766
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3591087707
Short name T214
Test name
Test status
Simulation time 101003710 ps
CPU time 0.78 seconds
Started May 07 03:10:12 PM PDT 24
Finished May 07 03:10:15 PM PDT 24
Peak memory 204640 kb
Host smart-d5af6516-b994-4d13-9aad-ec719464a03b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591087707 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.3591087707
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.2380370706
Short name T187
Test name
Test status
Simulation time 2082377707 ps
CPU time 7.91 seconds
Started May 07 03:10:11 PM PDT 24
Finished May 07 03:10:21 PM PDT 24
Peak memory 204808 kb
Host smart-3b07ddff-67a2-4ebe-9b46-4264c719bab4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380370706 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.2380370706
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.918774033
Short name T286
Test name
Test status
Simulation time 129537924 ps
CPU time 0.71 seconds
Started May 07 03:10:14 PM PDT 24
Finished May 07 03:10:19 PM PDT 24
Peak memory 204576 kb
Host smart-5920c849-8c19-464b-90b3-c5a465c11323
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918774033 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.918774033
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.4012923942
Short name T303
Test name
Test status
Simulation time 40286865 ps
CPU time 0.68 seconds
Started May 07 03:10:13 PM PDT 24
Finished May 07 03:10:17 PM PDT 24
Peak memory 204632 kb
Host smart-15f1c8cf-f312-4089-a753-4bfd3a1854a9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012923942 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.4012923942
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.3762445557
Short name T179
Test name
Test status
Simulation time 31212784 ps
CPU time 0.7 seconds
Started May 07 03:10:14 PM PDT 24
Finished May 07 03:10:19 PM PDT 24
Peak memory 204464 kb
Host smart-aabb3aca-bbaa-46f1-9c12-3d561b69c320
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762445557 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.3762445557
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.3197239134
Short name T81
Test name
Test status
Simulation time 471170621 ps
CPU time 6.87 seconds
Started May 07 03:10:16 PM PDT 24
Finished May 07 03:10:27 PM PDT 24
Peak memory 205016 kb
Host smart-77dc4e3c-6a56-4833-8ac0-d6c4b5dfe519
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197239134 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.3197239134
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.785393976
Short name T260
Test name
Test status
Simulation time 26141861320 ps
CPU time 12.3 seconds
Started May 07 03:10:12 PM PDT 24
Finished May 07 03:10:27 PM PDT 24
Peak memory 214724 kb
Host smart-68b51714-552a-4475-9897-6561bcf89471
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785393976 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.785393976
Directory /workspace/0.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.2094742913
Short name T64
Test name
Test status
Simulation time 143391363 ps
CPU time 3.29 seconds
Started May 07 03:10:12 PM PDT 24
Finished May 07 03:10:18 PM PDT 24
Peak memory 213224 kb
Host smart-b4593614-c809-465a-805b-38c556da6e81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094742913 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.2094742913
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3605045784
Short name T299
Test name
Test status
Simulation time 3844419783 ps
CPU time 31.77 seconds
Started May 07 03:10:12 PM PDT 24
Finished May 07 03:10:46 PM PDT 24
Peak memory 214332 kb
Host smart-292b2264-7c77-4727-920e-c79dd6406226
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605045784 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.3605045784
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.4143815536
Short name T104
Test name
Test status
Simulation time 739132532 ps
CPU time 27.42 seconds
Started May 07 03:10:17 PM PDT 24
Finished May 07 03:10:48 PM PDT 24
Peak memory 204836 kb
Host smart-da20894a-a050-44fe-b13f-d0698e688ebe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143815536 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.4143815536
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.3546474708
Short name T250
Test name
Test status
Simulation time 1753011465 ps
CPU time 2.68 seconds
Started May 07 03:10:13 PM PDT 24
Finished May 07 03:10:19 PM PDT 24
Peak memory 213220 kb
Host smart-d88f77e4-50ca-44fa-9cd2-872421d58f97
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546474708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.3546474708
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3989404996
Short name T212
Test name
Test status
Simulation time 1489927812 ps
CPU time 5.01 seconds
Started May 07 03:10:15 PM PDT 24
Finished May 07 03:10:24 PM PDT 24
Peak memory 213128 kb
Host smart-0a7252dd-5b6f-4f93-80fd-9756dfb0c8e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989404996 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.3989404996
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2127526591
Short name T242
Test name
Test status
Simulation time 98664992 ps
CPU time 1.5 seconds
Started May 07 03:10:13 PM PDT 24
Finished May 07 03:10:19 PM PDT 24
Peak memory 218264 kb
Host smart-acbf496c-1a91-433f-9a94-46262f5f8900
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127526591 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.2127526591
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2133735100
Short name T194
Test name
Test status
Simulation time 5950074884 ps
CPU time 22.14 seconds
Started May 07 03:10:11 PM PDT 24
Finished May 07 03:10:36 PM PDT 24
Peak memory 204944 kb
Host smart-953d6018-ebb5-426b-b4af-dc5babb96c4a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133735100 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.2133735100
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.4276921542
Short name T232
Test name
Test status
Simulation time 9824117658 ps
CPU time 39.61 seconds
Started May 07 03:10:17 PM PDT 24
Finished May 07 03:11:00 PM PDT 24
Peak memory 204772 kb
Host smart-ec58e065-e85e-47f1-b108-74e652118710
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276921542 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_bit_bash.4276921542
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.2051498964
Short name T206
Test name
Test status
Simulation time 627131529 ps
CPU time 1 seconds
Started May 07 03:10:16 PM PDT 24
Finished May 07 03:10:20 PM PDT 24
Peak memory 204796 kb
Host smart-3997cd67-8476-4d9a-9277-688f2172b1bc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051498964 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.2
051498964
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.1653184214
Short name T62
Test name
Test status
Simulation time 47584232 ps
CPU time 0.8 seconds
Started May 07 03:10:14 PM PDT 24
Finished May 07 03:10:18 PM PDT 24
Peak memory 204592 kb
Host smart-a2d0871a-cd31-4c91-818a-d30caa8511ad
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653184214 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.1653184214
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.1796713053
Short name T198
Test name
Test status
Simulation time 1653065338 ps
CPU time 6.99 seconds
Started May 07 03:10:11 PM PDT 24
Finished May 07 03:10:20 PM PDT 24
Peak memory 204796 kb
Host smart-d62bdf2f-c7eb-4f19-a565-4ef18dec4411
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796713053 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.1796713053
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2789780718
Short name T270
Test name
Test status
Simulation time 141573773 ps
CPU time 0.7 seconds
Started May 07 03:10:10 PM PDT 24
Finished May 07 03:10:12 PM PDT 24
Peak memory 204640 kb
Host smart-3de0af75-69d9-4dd8-91aa-ccb52c72784d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789780718 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.2789780718
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.2709517360
Short name T234
Test name
Test status
Simulation time 168120597 ps
CPU time 0.76 seconds
Started May 07 03:10:15 PM PDT 24
Finished May 07 03:10:20 PM PDT 24
Peak memory 204488 kb
Host smart-6e0dd7df-ffc6-4159-aa6d-e4433d9cea24
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709517360 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.2
709517360
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2080025673
Short name T191
Test name
Test status
Simulation time 32177371 ps
CPU time 0.7 seconds
Started May 07 03:10:13 PM PDT 24
Finished May 07 03:10:18 PM PDT 24
Peak memory 204628 kb
Host smart-f5aec07c-a61b-41f5-9e16-1d9d87f4ea06
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080025673 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.2080025673
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.723939935
Short name T213
Test name
Test status
Simulation time 32481794 ps
CPU time 0.65 seconds
Started May 07 03:10:11 PM PDT 24
Finished May 07 03:10:14 PM PDT 24
Peak memory 204676 kb
Host smart-2a849f6b-9158-4547-a604-785a3c6df066
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723939935 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.723939935
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.170553115
Short name T96
Test name
Test status
Simulation time 582060875 ps
CPU time 7.64 seconds
Started May 07 03:10:16 PM PDT 24
Finished May 07 03:10:27 PM PDT 24
Peak memory 204880 kb
Host smart-b4bea16e-e4b8-407d-948b-11ae9c544868
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170553115 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_c
sr_outstanding.170553115
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.697654987
Short name T238
Test name
Test status
Simulation time 349868837 ps
CPU time 4.84 seconds
Started May 07 03:10:14 PM PDT 24
Finished May 07 03:10:23 PM PDT 24
Peak memory 213248 kb
Host smart-638d5bbe-2dc1-4151-a898-e4c45006f2c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697654987 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.697654987
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.397912545
Short name T223
Test name
Test status
Simulation time 2484444573 ps
CPU time 3.7 seconds
Started May 07 03:10:27 PM PDT 24
Finished May 07 03:10:33 PM PDT 24
Peak memory 215444 kb
Host smart-6e0af8f9-dd30-4289-b08b-ce247f73720b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397912545 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.397912545
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.4007360405
Short name T91
Test name
Test status
Simulation time 34535765 ps
CPU time 1.44 seconds
Started May 07 03:10:25 PM PDT 24
Finished May 07 03:10:27 PM PDT 24
Peak memory 213048 kb
Host smart-8040e7a1-f868-49ba-9e34-af75f14e27f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007360405 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.4007360405
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.518197198
Short name T256
Test name
Test status
Simulation time 538539620 ps
CPU time 1.47 seconds
Started May 07 03:10:23 PM PDT 24
Finished May 07 03:10:26 PM PDT 24
Peak memory 204828 kb
Host smart-606ede22-287a-4099-bb6e-16e51aef10e1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518197198 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.518197198
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.3466321237
Short name T181
Test name
Test status
Simulation time 71794695 ps
CPU time 0.73 seconds
Started May 07 03:10:23 PM PDT 24
Finished May 07 03:10:26 PM PDT 24
Peak memory 204648 kb
Host smart-23a4fdd5-9382-44ba-b485-b2aca6c69746
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466321237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
3466321237
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tap_fsm_rand_reset.2937666331
Short name T269
Test name
Test status
Simulation time 11089021881 ps
CPU time 13.51 seconds
Started May 07 03:10:25 PM PDT 24
Finished May 07 03:10:40 PM PDT 24
Peak memory 217944 kb
Host smart-9831da24-405a-4c05-ab19-571bb8a74490
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937666331 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rv_dm_tap_fsm_rand_reset.2937666331
Directory /workspace/10.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.1443358759
Short name T230
Test name
Test status
Simulation time 334575310 ps
CPU time 3.42 seconds
Started May 07 03:10:25 PM PDT 24
Finished May 07 03:10:30 PM PDT 24
Peak memory 213276 kb
Host smart-9f5a38db-b32c-4bc5-818d-640defb40a45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443358759 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.1443358759
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.4224449494
Short name T85
Test name
Test status
Simulation time 241508714 ps
CPU time 8.24 seconds
Started May 07 03:10:30 PM PDT 24
Finished May 07 03:10:40 PM PDT 24
Peak memory 213140 kb
Host smart-4a79aa80-7f0c-448d-b19c-b2aa5fd8d47b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224449494 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.4
224449494
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.2533359174
Short name T247
Test name
Test status
Simulation time 2648456677 ps
CPU time 2.71 seconds
Started May 07 03:10:32 PM PDT 24
Finished May 07 03:10:36 PM PDT 24
Peak memory 216788 kb
Host smart-6d03af5e-cdf1-4001-bb10-a1f99174ef73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533359174 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.2533359174
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.784578998
Short name T105
Test name
Test status
Simulation time 642346147 ps
CPU time 2.49 seconds
Started May 07 03:10:25 PM PDT 24
Finished May 07 03:10:30 PM PDT 24
Peak memory 213120 kb
Host smart-7262483f-72b6-4d2b-b8b5-53cf0b5fa685
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784578998 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.784578998
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.1418686570
Short name T178
Test name
Test status
Simulation time 515383722 ps
CPU time 2.32 seconds
Started May 07 03:10:26 PM PDT 24
Finished May 07 03:10:30 PM PDT 24
Peak memory 204828 kb
Host smart-15cecd63-62b8-4fc0-a054-07c215f98bf2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418686570 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
1418686570
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.1682115364
Short name T231
Test name
Test status
Simulation time 78173774 ps
CPU time 0.71 seconds
Started May 07 03:10:24 PM PDT 24
Finished May 07 03:10:27 PM PDT 24
Peak memory 204620 kb
Host smart-a7ee1c96-41e2-4568-a72b-3ac398b7b8d1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682115364 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.
1682115364
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.4082717611
Short name T101
Test name
Test status
Simulation time 590423477 ps
CPU time 6.78 seconds
Started May 07 03:10:25 PM PDT 24
Finished May 07 03:10:34 PM PDT 24
Peak memory 205000 kb
Host smart-7c3e0911-23b5-4ae9-ad07-d183ab23a28a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082717611 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same
_csr_outstanding.4082717611
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.367816101
Short name T210
Test name
Test status
Simulation time 87931547 ps
CPU time 5.05 seconds
Started May 07 03:10:25 PM PDT 24
Finished May 07 03:10:32 PM PDT 24
Peak memory 212800 kb
Host smart-ad7a94b1-8015-4928-916c-7231ae51e6f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367816101 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.367816101
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3669995081
Short name T263
Test name
Test status
Simulation time 668950044 ps
CPU time 10.31 seconds
Started May 07 03:10:26 PM PDT 24
Finished May 07 03:10:38 PM PDT 24
Peak memory 213212 kb
Host smart-cd909163-7238-4e82-9f73-c9dcf4f2ba64
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669995081 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.3
669995081
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.3270988182
Short name T240
Test name
Test status
Simulation time 1461808336 ps
CPU time 4.91 seconds
Started May 07 03:10:37 PM PDT 24
Finished May 07 03:10:43 PM PDT 24
Peak memory 221420 kb
Host smart-bb2f34a6-aa52-4601-902c-a08698ee23d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270988182 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.3270988182
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.2626412013
Short name T246
Test name
Test status
Simulation time 239013815 ps
CPU time 2.13 seconds
Started May 07 03:10:30 PM PDT 24
Finished May 07 03:10:34 PM PDT 24
Peak memory 213180 kb
Host smart-e56d8e36-b407-45fa-9d17-5d6289a5559f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626412013 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.2626412013
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.4099408664
Short name T295
Test name
Test status
Simulation time 256583337 ps
CPU time 1 seconds
Started May 07 03:10:31 PM PDT 24
Finished May 07 03:10:33 PM PDT 24
Peak memory 204876 kb
Host smart-f40bf3c0-46d7-48f5-b8d6-83e6c9dbb531
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099408664 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
4099408664
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1688709213
Short name T197
Test name
Test status
Simulation time 44515690 ps
CPU time 0.78 seconds
Started May 07 03:10:32 PM PDT 24
Finished May 07 03:10:34 PM PDT 24
Peak memory 204636 kb
Host smart-baa45a11-89cc-4aef-9442-363b0ebdc4da
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688709213 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
1688709213
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1071373486
Short name T296
Test name
Test status
Simulation time 582294733 ps
CPU time 4.34 seconds
Started May 07 03:10:30 PM PDT 24
Finished May 07 03:10:36 PM PDT 24
Peak memory 205020 kb
Host smart-f93288ce-3f02-43a5-853e-97cd810022d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071373486 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.1071373486
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tap_fsm_rand_reset.1860586892
Short name T59
Test name
Test status
Simulation time 8477277361 ps
CPU time 17.74 seconds
Started May 07 03:10:31 PM PDT 24
Finished May 07 03:10:50 PM PDT 24
Peak memory 213600 kb
Host smart-9c73bc8b-9096-4c47-94f1-194180564f3b
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860586892 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rv_dm_tap_fsm_rand_reset.1860586892
Directory /workspace/12.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.1649251622
Short name T239
Test name
Test status
Simulation time 197483976 ps
CPU time 2.25 seconds
Started May 07 03:10:30 PM PDT 24
Finished May 07 03:10:34 PM PDT 24
Peak memory 213216 kb
Host smart-f7722997-9d01-4632-a716-a7f83a707dd7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649251622 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.1649251622
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.565802534
Short name T73
Test name
Test status
Simulation time 2008181859 ps
CPU time 9.69 seconds
Started May 07 03:10:39 PM PDT 24
Finished May 07 03:10:50 PM PDT 24
Peak memory 213188 kb
Host smart-9784f544-aa01-4711-82f0-0e48b7d23bdc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565802534 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.565802534
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.2034709728
Short name T301
Test name
Test status
Simulation time 129075343 ps
CPU time 2.45 seconds
Started May 07 03:10:39 PM PDT 24
Finished May 07 03:10:43 PM PDT 24
Peak memory 213208 kb
Host smart-647df721-97f0-42bd-bbba-b2ad8b98d881
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034709728 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.2034709728
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.2936853385
Short name T289
Test name
Test status
Simulation time 240612388 ps
CPU time 1.56 seconds
Started May 07 03:10:37 PM PDT 24
Finished May 07 03:10:39 PM PDT 24
Peak memory 218360 kb
Host smart-9008cc79-e4c4-4980-825f-bc62c1ea2729
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936853385 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.2936853385
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.3484787540
Short name T201
Test name
Test status
Simulation time 459839346 ps
CPU time 1.45 seconds
Started May 07 03:10:35 PM PDT 24
Finished May 07 03:10:37 PM PDT 24
Peak memory 204808 kb
Host smart-5f015a1b-e4d7-421b-be76-941c452024e3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484787540 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
3484787540
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3198015073
Short name T236
Test name
Test status
Simulation time 110795953 ps
CPU time 0.71 seconds
Started May 07 03:10:39 PM PDT 24
Finished May 07 03:10:42 PM PDT 24
Peak memory 204652 kb
Host smart-a09d50ef-bdcf-4d94-941f-a999fd88e42e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198015073 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
3198015073
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.765742086
Short name T94
Test name
Test status
Simulation time 414642347 ps
CPU time 7.29 seconds
Started May 07 03:10:31 PM PDT 24
Finished May 07 03:10:40 PM PDT 24
Peak memory 204956 kb
Host smart-33cbac76-6e18-4e74-9792-f70bb1c4f548
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765742086 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same_
csr_outstanding.765742086
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.3932430545
Short name T224
Test name
Test status
Simulation time 565628190 ps
CPU time 3.34 seconds
Started May 07 03:10:31 PM PDT 24
Finished May 07 03:10:36 PM PDT 24
Peak memory 213212 kb
Host smart-18dc95d3-f300-4cd2-adb2-0a32cba40c81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932430545 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.3932430545
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.779726982
Short name T302
Test name
Test status
Simulation time 910975471 ps
CPU time 18.8 seconds
Started May 07 03:10:31 PM PDT 24
Finished May 07 03:10:51 PM PDT 24
Peak memory 213176 kb
Host smart-9b755b4b-3c75-4e33-bf52-625b922dafbb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779726982 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.779726982
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3417658877
Short name T283
Test name
Test status
Simulation time 2934402060 ps
CPU time 7.7 seconds
Started May 07 03:10:37 PM PDT 24
Finished May 07 03:10:46 PM PDT 24
Peak memory 219040 kb
Host smart-ef4b5183-98e1-4ab8-823b-60f15d6e6b9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417658877 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.3417658877
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.2058633004
Short name T102
Test name
Test status
Simulation time 72236737 ps
CPU time 2.07 seconds
Started May 07 03:10:31 PM PDT 24
Finished May 07 03:10:35 PM PDT 24
Peak memory 218364 kb
Host smart-63669141-c840-47e6-b705-76421d8fd01a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058633004 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.2058633004
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2644424745
Short name T182
Test name
Test status
Simulation time 1211842424 ps
CPU time 3.28 seconds
Started May 07 03:10:30 PM PDT 24
Finished May 07 03:10:36 PM PDT 24
Peak memory 204876 kb
Host smart-ee9fde82-3726-4e09-aacf-59687c56c3d6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644424745 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
2644424745
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.4140875826
Short name T235
Test name
Test status
Simulation time 147542392 ps
CPU time 0.98 seconds
Started May 07 03:10:33 PM PDT 24
Finished May 07 03:10:35 PM PDT 24
Peak memory 204660 kb
Host smart-e70841a0-ad87-47c9-b7a0-81b903875450
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140875826 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
4140875826
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3085420159
Short name T110
Test name
Test status
Simulation time 467443251 ps
CPU time 7.3 seconds
Started May 07 03:10:30 PM PDT 24
Finished May 07 03:10:39 PM PDT 24
Peak memory 205004 kb
Host smart-0c991319-fe4e-45b4-a50a-8c8bb556b22f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085420159 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.3085420159
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3706049650
Short name T122
Test name
Test status
Simulation time 850194765 ps
CPU time 9.72 seconds
Started May 07 03:10:31 PM PDT 24
Finished May 07 03:10:43 PM PDT 24
Peak memory 215596 kb
Host smart-7af14e51-2ee5-4f88-8f6f-e17288401379
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706049650 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.3
706049650
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.2240928213
Short name T220
Test name
Test status
Simulation time 2340704566 ps
CPU time 4.96 seconds
Started May 07 03:10:32 PM PDT 24
Finished May 07 03:10:38 PM PDT 24
Peak memory 218728 kb
Host smart-a76abed3-10df-4a69-b723-50aaf689bab5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240928213 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.2240928213
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.1357678226
Short name T276
Test name
Test status
Simulation time 86773173 ps
CPU time 2.25 seconds
Started May 07 03:10:38 PM PDT 24
Finished May 07 03:10:42 PM PDT 24
Peak memory 213196 kb
Host smart-01264896-6302-43c7-a01e-59463fc15230
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357678226 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.1357678226
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3842690046
Short name T196
Test name
Test status
Simulation time 470247041 ps
CPU time 0.95 seconds
Started May 07 03:10:31 PM PDT 24
Finished May 07 03:10:34 PM PDT 24
Peak memory 204780 kb
Host smart-2a5e3b39-4cd2-448d-8c51-bab32a6a6936
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842690046 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
3842690046
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.2350208751
Short name T61
Test name
Test status
Simulation time 75343417 ps
CPU time 0.79 seconds
Started May 07 03:10:33 PM PDT 24
Finished May 07 03:10:35 PM PDT 24
Peak memory 204620 kb
Host smart-32e163eb-b886-4e26-b8cf-8aeea7cbb2f8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350208751 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
2350208751
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.1679578138
Short name T100
Test name
Test status
Simulation time 77399850 ps
CPU time 3.38 seconds
Started May 07 03:10:33 PM PDT 24
Finished May 07 03:10:37 PM PDT 24
Peak memory 205032 kb
Host smart-d8aab3cb-961d-48f1-b308-5ba62c863d56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679578138 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.1679578138
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.2074769824
Short name T195
Test name
Test status
Simulation time 658936443 ps
CPU time 3.05 seconds
Started May 07 03:10:39 PM PDT 24
Finished May 07 03:10:43 PM PDT 24
Peak memory 213208 kb
Host smart-bb887573-4c05-4748-a13b-6c9e7f598586
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074769824 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.2074769824
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2236006338
Short name T144
Test name
Test status
Simulation time 180963589 ps
CPU time 4 seconds
Started May 07 03:10:41 PM PDT 24
Finished May 07 03:10:46 PM PDT 24
Peak memory 218616 kb
Host smart-0c30cf64-f2fd-419b-963e-087c81a52db9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236006338 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.2236006338
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.826597984
Short name T79
Test name
Test status
Simulation time 241098140 ps
CPU time 1.59 seconds
Started May 07 03:10:40 PM PDT 24
Finished May 07 03:10:43 PM PDT 24
Peak memory 221260 kb
Host smart-c25fc15e-4b17-4864-b7e0-674468c68698
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826597984 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.826597984
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.1822930777
Short name T199
Test name
Test status
Simulation time 680554155 ps
CPU time 1.79 seconds
Started May 07 03:10:31 PM PDT 24
Finished May 07 03:10:34 PM PDT 24
Peak memory 204796 kb
Host smart-ada320de-5bbd-4890-8f4e-26e76a332d63
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822930777 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
1822930777
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.1213199609
Short name T193
Test name
Test status
Simulation time 39996592 ps
CPU time 0.71 seconds
Started May 07 03:10:29 PM PDT 24
Finished May 07 03:10:32 PM PDT 24
Peak memory 204648 kb
Host smart-fe4e9b63-0374-4b52-994a-69534f482c92
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213199609 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
1213199609
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1146839543
Short name T80
Test name
Test status
Simulation time 308970467 ps
CPU time 3.36 seconds
Started May 07 03:10:37 PM PDT 24
Finished May 07 03:10:42 PM PDT 24
Peak memory 204932 kb
Host smart-c43fc701-4970-4f4a-9b76-e72d776e1bf3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146839543 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.1146839543
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3396302229
Short name T255
Test name
Test status
Simulation time 64849283 ps
CPU time 3.77 seconds
Started May 07 03:10:34 PM PDT 24
Finished May 07 03:10:39 PM PDT 24
Peak memory 213252 kb
Host smart-a04230b1-913a-45dd-b819-dba6c783f493
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396302229 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.3396302229
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.1269468554
Short name T125
Test name
Test status
Simulation time 546304977 ps
CPU time 16.4 seconds
Started May 07 03:10:43 PM PDT 24
Finished May 07 03:11:01 PM PDT 24
Peak memory 221180 kb
Host smart-00e9a95d-75d0-495c-b979-e2e2f5bc3e19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269468554 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.1
269468554
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2583955617
Short name T114
Test name
Test status
Simulation time 1980129881 ps
CPU time 4.09 seconds
Started May 07 03:10:41 PM PDT 24
Finished May 07 03:10:46 PM PDT 24
Peak memory 217192 kb
Host smart-0bad6537-8463-43f3-ae88-a1f9855d92d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583955617 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.2583955617
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.2649273121
Short name T222
Test name
Test status
Simulation time 141029339 ps
CPU time 2.08 seconds
Started May 07 03:10:36 PM PDT 24
Finished May 07 03:10:39 PM PDT 24
Peak memory 221220 kb
Host smart-a5fc8207-9983-4b46-ba1f-9ca7bcf8931a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649273121 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.2649273121
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.3185956093
Short name T205
Test name
Test status
Simulation time 388267451 ps
CPU time 1.61 seconds
Started May 07 03:10:37 PM PDT 24
Finished May 07 03:10:40 PM PDT 24
Peak memory 204828 kb
Host smart-517dfb5d-1e0d-4b8b-a39e-2289b810675b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185956093 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
3185956093
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.789029060
Short name T186
Test name
Test status
Simulation time 76850602 ps
CPU time 0.69 seconds
Started May 07 03:10:40 PM PDT 24
Finished May 07 03:10:42 PM PDT 24
Peak memory 204636 kb
Host smart-16e1d4ed-f682-4425-a5d4-75027c11c245
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789029060 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.789029060
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.1737512013
Short name T92
Test name
Test status
Simulation time 281486485 ps
CPU time 6.16 seconds
Started May 07 03:10:39 PM PDT 24
Finished May 07 03:10:47 PM PDT 24
Peak memory 204904 kb
Host smart-c38fb564-02d0-40ed-bf91-aead92ccb84c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737512013 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.1737512013
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.3308567109
Short name T147
Test name
Test status
Simulation time 1014541885 ps
CPU time 4.29 seconds
Started May 07 03:10:40 PM PDT 24
Finished May 07 03:10:45 PM PDT 24
Peak memory 213188 kb
Host smart-f6f0032b-1cdf-4220-b46e-67d1065efeb8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308567109 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.3308567109
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.3914856551
Short name T45
Test name
Test status
Simulation time 988662291 ps
CPU time 8.07 seconds
Started May 07 03:10:36 PM PDT 24
Finished May 07 03:10:45 PM PDT 24
Peak memory 221328 kb
Host smart-e6658930-d691-482f-9425-21fc6c123d43
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914856551 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.3
914856551
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.1377940395
Short name T279
Test name
Test status
Simulation time 2112638744 ps
CPU time 5.17 seconds
Started May 07 03:10:35 PM PDT 24
Finished May 07 03:10:41 PM PDT 24
Peak memory 218472 kb
Host smart-46a3517c-f46a-42c1-9b51-4789197cbbbf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377940395 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.1377940395
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.4257485730
Short name T48
Test name
Test status
Simulation time 1544805110 ps
CPU time 2.42 seconds
Started May 07 03:10:44 PM PDT 24
Finished May 07 03:10:48 PM PDT 24
Peak memory 213128 kb
Host smart-1a74ccb3-cb9d-42a1-8955-b7c86c76fab7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257485730 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.4257485730
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2339531074
Short name T290
Test name
Test status
Simulation time 309091120 ps
CPU time 2.05 seconds
Started May 07 03:10:37 PM PDT 24
Finished May 07 03:10:41 PM PDT 24
Peak memory 204812 kb
Host smart-7a998cbf-5299-4897-8d4b-a7d21d95f87c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339531074 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
2339531074
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.3595665125
Short name T176
Test name
Test status
Simulation time 86804755 ps
CPU time 0.74 seconds
Started May 07 03:10:39 PM PDT 24
Finished May 07 03:10:41 PM PDT 24
Peak memory 204652 kb
Host smart-11828ec9-3b6e-4a17-bf30-61a0b048378f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595665125 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
3595665125
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.4211942025
Short name T98
Test name
Test status
Simulation time 784519919 ps
CPU time 7.14 seconds
Started May 07 03:10:38 PM PDT 24
Finished May 07 03:10:47 PM PDT 24
Peak memory 204948 kb
Host smart-0fed3224-3e48-4eb2-99aa-c2c270bbccc3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211942025 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.4211942025
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2421929187
Short name T117
Test name
Test status
Simulation time 167329195 ps
CPU time 4.23 seconds
Started May 07 03:10:35 PM PDT 24
Finished May 07 03:10:41 PM PDT 24
Peak memory 213216 kb
Host smart-8b79089c-34cd-4d9f-bd68-39f700e68980
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421929187 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.2421929187
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3612533289
Short name T132
Test name
Test status
Simulation time 4188039486 ps
CPU time 20.43 seconds
Started May 07 03:10:41 PM PDT 24
Finished May 07 03:11:03 PM PDT 24
Peak memory 220424 kb
Host smart-cd7ed8af-6755-402e-8e67-49610dfc8111
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612533289 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.3
612533289
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2726586565
Short name T75
Test name
Test status
Simulation time 631013098 ps
CPU time 2.98 seconds
Started May 07 03:10:45 PM PDT 24
Finished May 07 03:10:49 PM PDT 24
Peak memory 214516 kb
Host smart-e0e25db1-b9b3-4c11-8250-d4da1035b793
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726586565 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.2726586565
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3996173480
Short name T288
Test name
Test status
Simulation time 403093446 ps
CPU time 2.48 seconds
Started May 07 03:10:46 PM PDT 24
Finished May 07 03:10:50 PM PDT 24
Peak memory 212912 kb
Host smart-761057b6-e1c6-4a8e-b012-773bba443143
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996173480 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.3996173480
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.492005895
Short name T189
Test name
Test status
Simulation time 784771477 ps
CPU time 1.49 seconds
Started May 07 03:10:35 PM PDT 24
Finished May 07 03:10:38 PM PDT 24
Peak memory 204864 kb
Host smart-6af7de8b-15b1-4a20-b2ea-9d858affdfdd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492005895 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.492005895
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.1734944955
Short name T244
Test name
Test status
Simulation time 59462764 ps
CPU time 0.69 seconds
Started May 07 03:10:37 PM PDT 24
Finished May 07 03:10:39 PM PDT 24
Peak memory 204568 kb
Host smart-670689ea-18ba-445e-b176-a80698c051cf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734944955 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
1734944955
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.2192425353
Short name T90
Test name
Test status
Simulation time 2351944561 ps
CPU time 3.92 seconds
Started May 07 03:10:43 PM PDT 24
Finished May 07 03:10:48 PM PDT 24
Peak memory 204992 kb
Host smart-da3b4ebb-03d1-4c68-84cf-50bf059d45b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192425353 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.2192425353
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3847239970
Short name T245
Test name
Test status
Simulation time 1389571848 ps
CPU time 3.28 seconds
Started May 07 03:10:45 PM PDT 24
Finished May 07 03:10:49 PM PDT 24
Peak memory 213256 kb
Host smart-6824412c-51a1-415e-bebd-175952dd7bd4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847239970 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.3847239970
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.985230159
Short name T131
Test name
Test status
Simulation time 1532020553 ps
CPU time 15.48 seconds
Started May 07 03:10:46 PM PDT 24
Finished May 07 03:11:03 PM PDT 24
Peak memory 221344 kb
Host smart-e39611ca-5df6-4133-859e-c23947390e36
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985230159 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.985230159
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.558777381
Short name T111
Test name
Test status
Simulation time 27098201726 ps
CPU time 76.72 seconds
Started May 07 03:10:16 PM PDT 24
Finished May 07 03:11:36 PM PDT 24
Peak memory 213212 kb
Host smart-17b7b436-7b14-4e31-b32b-2dde2e127734
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558777381 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.rv_dm_csr_aliasing.558777381
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.4169953309
Short name T259
Test name
Test status
Simulation time 114552876 ps
CPU time 1.5 seconds
Started May 07 03:10:12 PM PDT 24
Finished May 07 03:10:16 PM PDT 24
Peak memory 212984 kb
Host smart-52feafd5-47a6-4347-8c12-995257454bea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169953309 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.4169953309
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.4148086515
Short name T243
Test name
Test status
Simulation time 155765149 ps
CPU time 2.18 seconds
Started May 07 03:10:16 PM PDT 24
Finished May 07 03:10:22 PM PDT 24
Peak memory 216960 kb
Host smart-813165bf-6cff-409e-ae5c-8ab5bb99485c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148086515 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.4148086515
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1186944681
Short name T251
Test name
Test status
Simulation time 187373499 ps
CPU time 2.36 seconds
Started May 07 03:10:15 PM PDT 24
Finished May 07 03:10:21 PM PDT 24
Peak memory 218708 kb
Host smart-50d57bf3-db81-4b42-8968-97dc3ae2ecd1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186944681 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.1186944681
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.882520535
Short name T293
Test name
Test status
Simulation time 15899043179 ps
CPU time 17.44 seconds
Started May 07 03:10:15 PM PDT 24
Finished May 07 03:10:36 PM PDT 24
Peak memory 204936 kb
Host smart-ae393eff-0710-4900-982b-c06fb9242eb8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882520535 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr
_aliasing.882520535
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.2509087187
Short name T200
Test name
Test status
Simulation time 42365889332 ps
CPU time 38.71 seconds
Started May 07 03:10:15 PM PDT 24
Finished May 07 03:10:58 PM PDT 24
Peak memory 204944 kb
Host smart-1c3f4576-fc31-404e-9a2a-bd981b38d0cf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509087187 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_bit_bash.2509087187
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.3888528983
Short name T254
Test name
Test status
Simulation time 761914535 ps
CPU time 2.49 seconds
Started May 07 03:10:16 PM PDT 24
Finished May 07 03:10:22 PM PDT 24
Peak memory 204880 kb
Host smart-b3fc487f-1c80-4224-8e0b-cc83bef3d3ec
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888528983 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.3888528983
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.661624593
Short name T298
Test name
Test status
Simulation time 382780226 ps
CPU time 1.92 seconds
Started May 07 03:10:15 PM PDT 24
Finished May 07 03:10:20 PM PDT 24
Peak memory 204804 kb
Host smart-b185264d-cb18-4151-a7a5-070edfa30840
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661624593 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.661624593
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.2109192477
Short name T209
Test name
Test status
Simulation time 140795805 ps
CPU time 0.88 seconds
Started May 07 03:10:15 PM PDT 24
Finished May 07 03:10:20 PM PDT 24
Peak memory 204576 kb
Host smart-323bd229-8339-4322-a7cb-2f3f0cf9d0a9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109192477 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_aliasing.2109192477
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.4181765797
Short name T287
Test name
Test status
Simulation time 629532801 ps
CPU time 2.11 seconds
Started May 07 03:10:15 PM PDT 24
Finished May 07 03:10:21 PM PDT 24
Peak memory 204872 kb
Host smart-d80bd339-eee9-4f18-b6fe-837f2ab40c90
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181765797 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.4181765797
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.105853344
Short name T257
Test name
Test status
Simulation time 116611649 ps
CPU time 1.04 seconds
Started May 07 03:10:13 PM PDT 24
Finished May 07 03:10:18 PM PDT 24
Peak memory 204660 kb
Host smart-cc5c7a37-e4b3-4bde-881f-08d601090a80
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105853344 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_hw_reset.105853344
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.3459896206
Short name T177
Test name
Test status
Simulation time 269272172 ps
CPU time 0.69 seconds
Started May 07 03:10:15 PM PDT 24
Finished May 07 03:10:20 PM PDT 24
Peak memory 204652 kb
Host smart-9623d8f3-2564-47b6-a548-3dd6d81aacc3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459896206 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.3
459896206
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.29476987
Short name T174
Test name
Test status
Simulation time 106942221 ps
CPU time 0.66 seconds
Started May 07 03:10:11 PM PDT 24
Finished May 07 03:10:14 PM PDT 24
Peak memory 204604 kb
Host smart-beeceec6-da13-41f8-8bcd-5cd92a5127bd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29476987 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_parti
al_access.29476987
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.3901851441
Short name T183
Test name
Test status
Simulation time 20841758 ps
CPU time 0.7 seconds
Started May 07 03:10:13 PM PDT 24
Finished May 07 03:10:16 PM PDT 24
Peak memory 204664 kb
Host smart-08e917a9-33d7-483b-9b19-03d8db7dddc2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901851441 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.3901851441
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.1893478889
Short name T228
Test name
Test status
Simulation time 97763651 ps
CPU time 3.4 seconds
Started May 07 03:10:15 PM PDT 24
Finished May 07 03:10:22 PM PDT 24
Peak memory 205020 kb
Host smart-ac223584-4dd8-41c8-99fb-a4c0b9130780
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893478889 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.1893478889
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.2663435824
Short name T47
Test name
Test status
Simulation time 93711926 ps
CPU time 5.36 seconds
Started May 07 03:10:16 PM PDT 24
Finished May 07 03:10:25 PM PDT 24
Peak memory 213212 kb
Host smart-7011e3ec-be11-4ac8-99ce-cb5205ce3f9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663435824 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.2663435824
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/22.rv_dm_tap_fsm_rand_reset.1514107081
Short name T282
Test name
Test status
Simulation time 13933229294 ps
CPU time 45.91 seconds
Started May 07 03:10:44 PM PDT 24
Finished May 07 03:11:31 PM PDT 24
Peak memory 220728 kb
Host smart-db806c65-e871-4380-9cd3-cc9d00bb7d45
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514107081 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 22.rv_dm_tap_fsm_rand_reset.1514107081
Directory /workspace/22.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/23.rv_dm_tap_fsm_rand_reset.2532880767
Short name T284
Test name
Test status
Simulation time 5287101559 ps
CPU time 19.79 seconds
Started May 07 03:10:47 PM PDT 24
Finished May 07 03:11:08 PM PDT 24
Peak memory 220972 kb
Host smart-bab8030e-610e-4173-bee4-59e057dbff9f
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532880767 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 23.rv_dm_tap_fsm_rand_reset.2532880767
Directory /workspace/23.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.950591516
Short name T281
Test name
Test status
Simulation time 2342526055 ps
CPU time 26.76 seconds
Started May 07 03:10:15 PM PDT 24
Finished May 07 03:10:46 PM PDT 24
Peak memory 205028 kb
Host smart-80f220f8-fb85-40b9-a2cd-62867b5f9afa
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950591516 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.rv_dm_csr_aliasing.950591516
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.2073090787
Short name T78
Test name
Test status
Simulation time 16657247806 ps
CPU time 70.7 seconds
Started May 07 03:10:17 PM PDT 24
Finished May 07 03:11:31 PM PDT 24
Peak memory 213296 kb
Host smart-ec0d8e12-d74d-464d-8fbf-c6ffcc6cc30c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073090787 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.2073090787
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.2287795357
Short name T211
Test name
Test status
Simulation time 130401397 ps
CPU time 2.39 seconds
Started May 07 03:10:16 PM PDT 24
Finished May 07 03:10:22 PM PDT 24
Peak memory 213120 kb
Host smart-5f973664-ca54-4e89-8c3e-be2a0a8c60c8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287795357 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.2287795357
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1912447729
Short name T115
Test name
Test status
Simulation time 338127010 ps
CPU time 2.31 seconds
Started May 07 03:10:18 PM PDT 24
Finished May 07 03:10:23 PM PDT 24
Peak memory 221180 kb
Host smart-9a899ec8-49f4-4c79-9b55-9c3a8c880f24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912447729 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.1912447729
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2973062781
Short name T93
Test name
Test status
Simulation time 42146105 ps
CPU time 2.14 seconds
Started May 07 03:10:17 PM PDT 24
Finished May 07 03:10:23 PM PDT 24
Peak memory 219036 kb
Host smart-32e145c4-4033-4a82-bc77-89a1c97f460a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973062781 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.2973062781
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.3835153235
Short name T265
Test name
Test status
Simulation time 7267825309 ps
CPU time 19.84 seconds
Started May 07 03:10:18 PM PDT 24
Finished May 07 03:10:41 PM PDT 24
Peak memory 204996 kb
Host smart-9c483339-0830-45b3-b589-5558ed18e9a9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835153235 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.3835153235
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.518478932
Short name T184
Test name
Test status
Simulation time 42683598214 ps
CPU time 128.67 seconds
Started May 07 03:10:17 PM PDT 24
Finished May 07 03:12:29 PM PDT 24
Peak memory 204920 kb
Host smart-4ec6e4f9-8439-481e-8db5-46c3f8e2f1ed
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518478932 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr
_bit_bash.518478932
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.3900854469
Short name T89
Test name
Test status
Simulation time 676424257 ps
CPU time 1.72 seconds
Started May 07 03:10:21 PM PDT 24
Finished May 07 03:10:25 PM PDT 24
Peak memory 204920 kb
Host smart-f9028f4d-5cc1-47c7-909b-d4252d1bc895
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900854469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.3900854469
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.3745094169
Short name T219
Test name
Test status
Simulation time 338581847 ps
CPU time 1.84 seconds
Started May 07 03:10:18 PM PDT 24
Finished May 07 03:10:23 PM PDT 24
Peak memory 204880 kb
Host smart-f0459c66-e848-4970-9b93-d182c062fa2c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745094169 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.3
745094169
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.2891374467
Short name T207
Test name
Test status
Simulation time 82249165 ps
CPU time 0.84 seconds
Started May 07 03:10:18 PM PDT 24
Finished May 07 03:10:22 PM PDT 24
Peak memory 204592 kb
Host smart-5170f2ab-28b8-49bc-8918-cde17f79cba6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891374467 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.2891374467
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.636948471
Short name T271
Test name
Test status
Simulation time 1181297251 ps
CPU time 3.26 seconds
Started May 07 03:10:18 PM PDT 24
Finished May 07 03:10:24 PM PDT 24
Peak memory 204784 kb
Host smart-42e9b6c3-952f-46ef-b7e1-904a5c6a09ed
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636948471 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr
_bit_bash.636948471
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.2292081352
Short name T264
Test name
Test status
Simulation time 48598429 ps
CPU time 0.79 seconds
Started May 07 03:10:12 PM PDT 24
Finished May 07 03:10:16 PM PDT 24
Peak memory 204632 kb
Host smart-3b60b93d-01b2-47bc-a16d-d7c5cb076ca2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292081352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.2292081352
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.898827983
Short name T278
Test name
Test status
Simulation time 30098523 ps
CPU time 0.73 seconds
Started May 07 03:10:26 PM PDT 24
Finished May 07 03:10:28 PM PDT 24
Peak memory 204632 kb
Host smart-c9f8dfc0-ee7c-44c1-98f0-46ec65a51bf2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898827983 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.898827983
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.1108157241
Short name T173
Test name
Test status
Simulation time 42805646 ps
CPU time 0.68 seconds
Started May 07 03:10:26 PM PDT 24
Finished May 07 03:10:29 PM PDT 24
Peak memory 204640 kb
Host smart-5f0d8210-286e-4c16-ae17-931e235ec7db
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108157241 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.1108157241
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1050635527
Short name T268
Test name
Test status
Simulation time 49964303 ps
CPU time 0.77 seconds
Started May 07 03:10:18 PM PDT 24
Finished May 07 03:10:22 PM PDT 24
Peak memory 204240 kb
Host smart-400f5827-8668-43df-b3b0-62b8a7f1d964
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050635527 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.1050635527
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2116991542
Short name T97
Test name
Test status
Simulation time 821095545 ps
CPU time 4.11 seconds
Started May 07 03:10:20 PM PDT 24
Finished May 07 03:10:27 PM PDT 24
Peak memory 204936 kb
Host smart-4587e240-c5f6-427d-ad1c-150273c891d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116991542 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_
csr_outstanding.2116991542
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2501139004
Short name T237
Test name
Test status
Simulation time 404323426 ps
CPU time 5.47 seconds
Started May 07 03:10:18 PM PDT 24
Finished May 07 03:10:27 PM PDT 24
Peak memory 213188 kb
Host smart-04b7bc9e-116a-42a9-b0d1-b173fe972b2a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501139004 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.2501139004
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3559622608
Short name T134
Test name
Test status
Simulation time 458159912 ps
CPU time 8.68 seconds
Started May 07 03:10:17 PM PDT 24
Finished May 07 03:10:29 PM PDT 24
Peak memory 213176 kb
Host smart-7bf448ae-2747-4a42-a92e-3428a1b05c23
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559622608 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.3559622608
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_dm_tap_fsm_rand_reset.2664693782
Short name T233
Test name
Test status
Simulation time 16651007435 ps
CPU time 57.63 seconds
Started May 07 03:10:46 PM PDT 24
Finished May 07 03:11:45 PM PDT 24
Peak memory 221412 kb
Host smart-4fa0aaf6-51e1-4058-bb62-598cb6dce8d0
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664693782 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 30.rv_dm_tap_fsm_rand_reset.2664693782
Directory /workspace/30.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/32.rv_dm_tap_fsm_rand_reset.474724958
Short name T294
Test name
Test status
Simulation time 8729648144 ps
CPU time 15.75 seconds
Started May 07 03:10:44 PM PDT 24
Finished May 07 03:11:01 PM PDT 24
Peak memory 221032 kb
Host smart-3210189e-4520-4dd7-b906-538189ecd60a
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474724958 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 32.rv_dm_tap_fsm_rand_reset.474724958
Directory /workspace/32.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/35.rv_dm_tap_fsm_rand_reset.2294626123
Short name T227
Test name
Test status
Simulation time 5202602732 ps
CPU time 19.18 seconds
Started May 07 03:10:48 PM PDT 24
Finished May 07 03:11:08 PM PDT 24
Peak memory 217300 kb
Host smart-cb173124-7246-4881-8f6c-94318b636b0b
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294626123 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 35.rv_dm_tap_fsm_rand_reset.2294626123
Directory /workspace/35.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.273547353
Short name T274
Test name
Test status
Simulation time 3831726917 ps
CPU time 25.39 seconds
Started May 07 03:10:19 PM PDT 24
Finished May 07 03:10:47 PM PDT 24
Peak memory 205000 kb
Host smart-2934a24e-e26e-479d-bb55-6fb3e209ffb9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273547353 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.rv_dm_csr_aliasing.273547353
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.234225253
Short name T118
Test name
Test status
Simulation time 13247874410 ps
CPU time 66.69 seconds
Started May 07 03:10:22 PM PDT 24
Finished May 07 03:11:31 PM PDT 24
Peak memory 205092 kb
Host smart-ba86e74c-cfa4-4d30-a792-b34bd9aab4b0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234225253 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.234225253
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2391412947
Short name T65
Test name
Test status
Simulation time 1594243575 ps
CPU time 3.15 seconds
Started May 07 03:10:23 PM PDT 24
Finished May 07 03:10:28 PM PDT 24
Peak memory 218536 kb
Host smart-6599e504-615d-4d57-bf7b-f19d78ccd699
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391412947 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.2391412947
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.4228597434
Short name T292
Test name
Test status
Simulation time 85023601 ps
CPU time 1.52 seconds
Started May 07 03:10:20 PM PDT 24
Finished May 07 03:10:24 PM PDT 24
Peak memory 213060 kb
Host smart-8c1a80fa-cbce-4977-a7a3-2a24171a48ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228597434 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.4228597434
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.1488658256
Short name T208
Test name
Test status
Simulation time 5381409516 ps
CPU time 15.79 seconds
Started May 07 03:10:18 PM PDT 24
Finished May 07 03:10:37 PM PDT 24
Peak memory 204968 kb
Host smart-dac3e92a-9527-44c3-9ee8-27feea8cb745
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488658256 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.1488658256
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.2064841435
Short name T272
Test name
Test status
Simulation time 18817653624 ps
CPU time 67.06 seconds
Started May 07 03:10:20 PM PDT 24
Finished May 07 03:11:30 PM PDT 24
Peak memory 204988 kb
Host smart-bf837e15-0fb6-4882-a419-773c159a0e7b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064841435 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_bit_bash.2064841435
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2722059679
Short name T172
Test name
Test status
Simulation time 3476964379 ps
CPU time 10.22 seconds
Started May 07 03:10:17 PM PDT 24
Finished May 07 03:10:30 PM PDT 24
Peak memory 204964 kb
Host smart-7b78177e-ba28-4a90-945d-7cb6bac935f2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722059679 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.2722059679
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3956508806
Short name T262
Test name
Test status
Simulation time 269971274 ps
CPU time 1.86 seconds
Started May 07 03:10:20 PM PDT 24
Finished May 07 03:10:25 PM PDT 24
Peak memory 204836 kb
Host smart-42a51db6-bea5-4edc-9e81-9d318b35d589
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956508806 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.3
956508806
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.3577525059
Short name T190
Test name
Test status
Simulation time 271834973 ps
CPU time 0.79 seconds
Started May 07 03:10:16 PM PDT 24
Finished May 07 03:10:20 PM PDT 24
Peak memory 204632 kb
Host smart-93b1be3e-ac76-4d6a-878d-fcc93b109c02
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577525059 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.3577525059
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2635911833
Short name T215
Test name
Test status
Simulation time 3587006211 ps
CPU time 7.17 seconds
Started May 07 03:10:19 PM PDT 24
Finished May 07 03:10:29 PM PDT 24
Peak memory 204884 kb
Host smart-109ee835-314d-4950-ac91-c06578826d50
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635911833 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.2635911833
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.3293767418
Short name T277
Test name
Test status
Simulation time 41785183 ps
CPU time 0.73 seconds
Started May 07 03:10:20 PM PDT 24
Finished May 07 03:10:24 PM PDT 24
Peak memory 204684 kb
Host smart-10502c73-8e2a-4a75-ac26-6015a3cb9e26
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293767418 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.3293767418
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.4034332010
Short name T267
Test name
Test status
Simulation time 163184724 ps
CPU time 0.73 seconds
Started May 07 03:10:20 PM PDT 24
Finished May 07 03:10:23 PM PDT 24
Peak memory 204628 kb
Host smart-7c738518-18a3-43c7-b293-52b69bceee19
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034332010 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.4
034332010
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1454995021
Short name T202
Test name
Test status
Simulation time 30479425 ps
CPU time 0.7 seconds
Started May 07 03:10:19 PM PDT 24
Finished May 07 03:10:22 PM PDT 24
Peak memory 204608 kb
Host smart-0c11d2c9-0a06-43b2-9cb2-66b365e55904
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454995021 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.1454995021
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.1075238576
Short name T261
Test name
Test status
Simulation time 26587027 ps
CPU time 0.67 seconds
Started May 07 03:10:16 PM PDT 24
Finished May 07 03:10:20 PM PDT 24
Peak memory 204616 kb
Host smart-503ca420-d1e1-4543-a8f6-bd2cb1ddc9bb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075238576 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.1075238576
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3177889613
Short name T241
Test name
Test status
Simulation time 516406039 ps
CPU time 4.3 seconds
Started May 07 03:10:17 PM PDT 24
Finished May 07 03:10:25 PM PDT 24
Peak memory 204956 kb
Host smart-ca8d7499-265a-458b-bcdd-bae65fa6ecf6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177889613 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.3177889613
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.1749353957
Short name T121
Test name
Test status
Simulation time 144160540 ps
CPU time 4.47 seconds
Started May 07 03:10:20 PM PDT 24
Finished May 07 03:10:27 PM PDT 24
Peak memory 213196 kb
Host smart-35cda59b-c35f-40d2-b998-69d0f2c41ccb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749353957 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.1749353957
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1594799220
Short name T126
Test name
Test status
Simulation time 4066757238 ps
CPU time 18.43 seconds
Started May 07 03:10:24 PM PDT 24
Finished May 07 03:10:44 PM PDT 24
Peak memory 213208 kb
Host smart-33465a96-5180-4f23-9d66-4d9421f162a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594799220 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.1594799220
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.2446609218
Short name T44
Test name
Test status
Simulation time 1815526099 ps
CPU time 4.94 seconds
Started May 07 03:10:22 PM PDT 24
Finished May 07 03:10:29 PM PDT 24
Peak memory 213020 kb
Host smart-1d4acc3c-97c2-47b5-9e3f-d9d63c6dac12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446609218 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.2446609218
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.1836000194
Short name T77
Test name
Test status
Simulation time 165605569 ps
CPU time 2.14 seconds
Started May 07 03:10:20 PM PDT 24
Finished May 07 03:10:25 PM PDT 24
Peak memory 221256 kb
Host smart-2589011d-827f-4181-bcc2-1dfab47cf6ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836000194 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.1836000194
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3984299607
Short name T248
Test name
Test status
Simulation time 243246429 ps
CPU time 1.14 seconds
Started May 07 03:10:25 PM PDT 24
Finished May 07 03:10:28 PM PDT 24
Peak memory 204360 kb
Host smart-853dd20c-5f08-429b-993f-28c56d15c537
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984299607 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.3
984299607
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3138905635
Short name T180
Test name
Test status
Simulation time 22998339 ps
CPU time 0.7 seconds
Started May 07 03:10:17 PM PDT 24
Finished May 07 03:10:21 PM PDT 24
Peak memory 204664 kb
Host smart-3f874d81-c99d-4d80-85d2-076263bf5bca
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138905635 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.3
138905635
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.3887331215
Short name T108
Test name
Test status
Simulation time 2146374796 ps
CPU time 8.19 seconds
Started May 07 03:10:18 PM PDT 24
Finished May 07 03:10:29 PM PDT 24
Peak memory 205000 kb
Host smart-21154738-f5c8-41d8-be22-3ced126cc707
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887331215 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.3887331215
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.201076011
Short name T291
Test name
Test status
Simulation time 152206211 ps
CPU time 3.92 seconds
Started May 07 03:10:20 PM PDT 24
Finished May 07 03:10:27 PM PDT 24
Peak memory 213248 kb
Host smart-b44287de-f4f0-448a-ab0b-17718b1e77b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201076011 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.201076011
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2884622599
Short name T74
Test name
Test status
Simulation time 1128659153 ps
CPU time 10.3 seconds
Started May 07 03:10:19 PM PDT 24
Finished May 07 03:10:32 PM PDT 24
Peak memory 213184 kb
Host smart-b0db0cfd-1465-4ffc-a991-97b304a28d53
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884622599 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.2884622599
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.1506522035
Short name T204
Test name
Test status
Simulation time 1079453357 ps
CPU time 3.71 seconds
Started May 07 03:10:19 PM PDT 24
Finished May 07 03:10:25 PM PDT 24
Peak memory 217800 kb
Host smart-f72ff995-7afc-44ac-88a5-0b835c6baff2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506522035 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.1506522035
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.3723743237
Short name T253
Test name
Test status
Simulation time 112308184 ps
CPU time 2.34 seconds
Started May 07 03:10:17 PM PDT 24
Finished May 07 03:10:23 PM PDT 24
Peak memory 221280 kb
Host smart-e66afca7-a9f9-45b0-a22d-b56076f7a320
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723743237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.3723743237
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2389879317
Short name T188
Test name
Test status
Simulation time 969023226 ps
CPU time 3.93 seconds
Started May 07 03:10:22 PM PDT 24
Finished May 07 03:10:27 PM PDT 24
Peak memory 204808 kb
Host smart-36966a18-172c-49f1-a0df-1d0043402829
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389879317 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.2
389879317
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.702373294
Short name T297
Test name
Test status
Simulation time 61141404 ps
CPU time 0.87 seconds
Started May 07 03:10:18 PM PDT 24
Finished May 07 03:10:22 PM PDT 24
Peak memory 204624 kb
Host smart-c39003ff-aeeb-4952-a73a-94f0eac004e5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702373294 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.702373294
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2065263177
Short name T300
Test name
Test status
Simulation time 1051518218 ps
CPU time 7.74 seconds
Started May 07 03:10:20 PM PDT 24
Finished May 07 03:10:31 PM PDT 24
Peak memory 204936 kb
Host smart-161e5161-1c3c-4873-a7eb-fb53e0c6c62b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065263177 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.2065263177
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.3614983532
Short name T116
Test name
Test status
Simulation time 12607531832 ps
CPU time 41.27 seconds
Started May 07 03:10:20 PM PDT 24
Finished May 07 03:11:04 PM PDT 24
Peak memory 221404 kb
Host smart-196fe274-33ae-4cff-a2e8-6dfb06c68ab4
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614983532 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.3614983532
Directory /workspace/6.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.703903598
Short name T252
Test name
Test status
Simulation time 879128385 ps
CPU time 3.77 seconds
Started May 07 03:10:22 PM PDT 24
Finished May 07 03:10:28 PM PDT 24
Peak memory 213132 kb
Host smart-f839ec8b-8973-49a8-a5a7-ddb07df58add
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703903598 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.703903598
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2761822762
Short name T128
Test name
Test status
Simulation time 441692263 ps
CPU time 15.75 seconds
Started May 07 03:10:25 PM PDT 24
Finished May 07 03:10:42 PM PDT 24
Peak memory 220760 kb
Host smart-4a13d6c0-c210-4a80-a8f5-6f064932c7ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761822762 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.2761822762
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.2048335064
Short name T82
Test name
Test status
Simulation time 161874310 ps
CPU time 2.29 seconds
Started May 07 03:10:27 PM PDT 24
Finished May 07 03:10:32 PM PDT 24
Peak memory 213176 kb
Host smart-8b72d143-e6bd-4394-a596-164c5aff1125
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048335064 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.2048335064
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.1527721596
Short name T226
Test name
Test status
Simulation time 529937117 ps
CPU time 1.34 seconds
Started May 07 03:10:19 PM PDT 24
Finished May 07 03:10:23 PM PDT 24
Peak memory 204904 kb
Host smart-4a38c1b2-2858-410e-8dc3-d5c5cc4542e2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527721596 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.1
527721596
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.2374740565
Short name T175
Test name
Test status
Simulation time 99110077 ps
CPU time 0.73 seconds
Started May 07 03:10:20 PM PDT 24
Finished May 07 03:10:23 PM PDT 24
Peak memory 204652 kb
Host smart-44b44d3e-3303-4491-a5a1-a7785ce65015
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374740565 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.2
374740565
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.1034995699
Short name T109
Test name
Test status
Simulation time 1086336451 ps
CPU time 8.19 seconds
Started May 07 03:10:24 PM PDT 24
Finished May 07 03:10:34 PM PDT 24
Peak memory 204996 kb
Host smart-b95de456-9f65-48d9-aff1-07f675ba571e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034995699 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.1034995699
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.1397817831
Short name T249
Test name
Test status
Simulation time 5285459118 ps
CPU time 19.32 seconds
Started May 07 03:10:18 PM PDT 24
Finished May 07 03:10:40 PM PDT 24
Peak memory 218436 kb
Host smart-d60074e4-8262-4d0b-a530-89d36f8bcd8e
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397817831 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.1397817831
Directory /workspace/7.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.3131526090
Short name T275
Test name
Test status
Simulation time 50400936 ps
CPU time 2.12 seconds
Started May 07 03:10:22 PM PDT 24
Finished May 07 03:10:26 PM PDT 24
Peak memory 213264 kb
Host smart-596abc07-0e31-4e9d-931f-6a30fa64d889
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131526090 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.3131526090
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.3549232788
Short name T229
Test name
Test status
Simulation time 4254043047 ps
CPU time 9.65 seconds
Started May 07 03:10:26 PM PDT 24
Finished May 07 03:10:37 PM PDT 24
Peak memory 221388 kb
Host smart-c348a11e-9d25-4a99-8a78-1cfd4eb73b35
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549232788 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.3549232788
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1890240824
Short name T107
Test name
Test status
Simulation time 111899298 ps
CPU time 1.56 seconds
Started May 07 03:10:26 PM PDT 24
Finished May 07 03:10:29 PM PDT 24
Peak memory 213132 kb
Host smart-b26c435b-8bcb-4682-9652-916f1dfc489f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890240824 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.1890240824
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1748130966
Short name T217
Test name
Test status
Simulation time 341004207 ps
CPU time 1.55 seconds
Started May 07 03:10:25 PM PDT 24
Finished May 07 03:10:28 PM PDT 24
Peak memory 204836 kb
Host smart-2a9a9f08-2332-4931-b92f-b02e8bb8b2be
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748130966 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.1
748130966
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2987746172
Short name T192
Test name
Test status
Simulation time 22401584 ps
CPU time 0.74 seconds
Started May 07 03:10:26 PM PDT 24
Finished May 07 03:10:28 PM PDT 24
Peak memory 204612 kb
Host smart-acd2125d-e0f0-4d29-95ef-7d2b696c5b05
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987746172 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.2
987746172
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2280045771
Short name T83
Test name
Test status
Simulation time 1766141442 ps
CPU time 6.9 seconds
Started May 07 03:10:26 PM PDT 24
Finished May 07 03:10:35 PM PDT 24
Peak memory 204956 kb
Host smart-f5cc3300-c694-4dc4-8ccd-4127979dd6f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280045771 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_
csr_outstanding.2280045771
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.3343812936
Short name T285
Test name
Test status
Simulation time 100025093 ps
CPU time 2.13 seconds
Started May 07 03:10:26 PM PDT 24
Finished May 07 03:10:30 PM PDT 24
Peak memory 213272 kb
Host smart-7d9bcd20-daad-4141-9a54-ed5035eb5861
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343812936 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.3343812936
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3676772964
Short name T133
Test name
Test status
Simulation time 2450238384 ps
CPU time 9.56 seconds
Started May 07 03:10:28 PM PDT 24
Finished May 07 03:10:39 PM PDT 24
Peak memory 213196 kb
Host smart-ff4a5632-056a-42c3-a023-b99e2e08025e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676772964 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.3676772964
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.481452596
Short name T218
Test name
Test status
Simulation time 1077203074 ps
CPU time 2.74 seconds
Started May 07 03:10:24 PM PDT 24
Finished May 07 03:10:28 PM PDT 24
Peak memory 216924 kb
Host smart-72f92423-7012-47d6-b03c-4ddea4e14c20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481452596 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.481452596
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.2584884857
Short name T106
Test name
Test status
Simulation time 334035230 ps
CPU time 2.43 seconds
Started May 07 03:10:24 PM PDT 24
Finished May 07 03:10:28 PM PDT 24
Peak memory 221260 kb
Host smart-3d04eb87-4d0c-4beb-a7e8-83b9c8566f6a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584884857 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.2584884857
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.4206992162
Short name T203
Test name
Test status
Simulation time 2039640860 ps
CPU time 4.16 seconds
Started May 07 03:10:24 PM PDT 24
Finished May 07 03:10:30 PM PDT 24
Peak memory 204816 kb
Host smart-533ded18-c13e-4160-aee1-7df61b537b27
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206992162 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.4
206992162
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.2378420190
Short name T63
Test name
Test status
Simulation time 52125109 ps
CPU time 0.76 seconds
Started May 07 03:10:28 PM PDT 24
Finished May 07 03:10:30 PM PDT 24
Peak memory 204652 kb
Host smart-61999acf-aa7a-419b-8785-392488ef9a77
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378420190 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.2
378420190
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.1308821200
Short name T99
Test name
Test status
Simulation time 410141976 ps
CPU time 3.84 seconds
Started May 07 03:10:25 PM PDT 24
Finished May 07 03:10:31 PM PDT 24
Peak memory 204948 kb
Host smart-eb49a8a4-f702-4fb6-9ba4-db4ae7fce6cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308821200 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.1308821200
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.2832480898
Short name T258
Test name
Test status
Simulation time 339595345 ps
CPU time 3.39 seconds
Started May 07 03:10:25 PM PDT 24
Finished May 07 03:10:30 PM PDT 24
Peak memory 213232 kb
Host smart-fbe51bff-6030-45c2-99ca-6b516906ba4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832480898 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.2832480898
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.3293755935
Short name T129
Test name
Test status
Simulation time 3581506899 ps
CPU time 15.37 seconds
Started May 07 03:10:26 PM PDT 24
Finished May 07 03:10:44 PM PDT 24
Peak memory 221428 kb
Host smart-1934e2f0-8494-485c-83bc-2bfb9aee854f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293755935 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.3293755935
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.3314533406
Short name T10
Test name
Test status
Simulation time 24258584 ps
CPU time 0.77 seconds
Started May 07 03:22:18 PM PDT 24
Finished May 07 03:22:20 PM PDT 24
Peak memory 205184 kb
Host smart-e96928b1-d90e-4983-8700-5299e4515554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314533406 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.3314533406
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.2750945888
Short name T141
Test name
Test status
Simulation time 22370068 ps
CPU time 0.79 seconds
Started May 07 03:22:14 PM PDT 24
Finished May 07 03:22:16 PM PDT 24
Peak memory 205152 kb
Host smart-8f3fab32-c5ef-494b-ad65-f42268717a48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750945888 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.2750945888
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.581999449
Short name T5
Test name
Test status
Simulation time 1030349646 ps
CPU time 3.92 seconds
Started May 07 03:22:08 PM PDT 24
Finished May 07 03:22:14 PM PDT 24
Peak memory 205376 kb
Host smart-1ea5d1d3-232c-419c-81d8-093055a3ba68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581999449 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.581999449
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.1182918398
Short name T19
Test name
Test status
Simulation time 63110363 ps
CPU time 0.74 seconds
Started May 07 03:22:11 PM PDT 24
Finished May 07 03:22:13 PM PDT 24
Peak memory 205168 kb
Host smart-16517aef-b4ae-4449-9dfd-b54d5d67ed2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182918398 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.1182918398
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.3075893083
Short name T32
Test name
Test status
Simulation time 47327015 ps
CPU time 0.82 seconds
Started May 07 03:22:06 PM PDT 24
Finished May 07 03:22:09 PM PDT 24
Peak memory 205052 kb
Host smart-38f713e3-e427-437d-ad76-4271b97595af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075893083 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.3075893083
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.1429287576
Short name T165
Test name
Test status
Simulation time 263147927 ps
CPU time 0.86 seconds
Started May 07 03:22:09 PM PDT 24
Finished May 07 03:22:12 PM PDT 24
Peak memory 205068 kb
Host smart-2ab07cd2-5225-40cd-ae7d-cd58336705ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429287576 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.1429287576
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.1804342751
Short name T57
Test name
Test status
Simulation time 191726783 ps
CPU time 1.34 seconds
Started May 07 03:22:18 PM PDT 24
Finished May 07 03:22:20 PM PDT 24
Peak memory 205304 kb
Host smart-261b423b-f37f-404d-ba8a-961bd99e7204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804342751 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.1804342751
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.1313687463
Short name T52
Test name
Test status
Simulation time 364934369 ps
CPU time 1 seconds
Started May 07 03:22:13 PM PDT 24
Finished May 07 03:22:15 PM PDT 24
Peak memory 205316 kb
Host smart-fe5b595c-a826-4cbc-a094-9a2e13a70aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313687463 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.1313687463
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.2523888778
Short name T11
Test name
Test status
Simulation time 148157276 ps
CPU time 0.94 seconds
Started May 07 03:22:12 PM PDT 24
Finished May 07 03:22:14 PM PDT 24
Peak memory 205256 kb
Host smart-9c41c48b-52bc-4d65-9262-8aa13c60fcff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523888778 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.2523888778
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.3372848574
Short name T15
Test name
Test status
Simulation time 20681458 ps
CPU time 0.88 seconds
Started May 07 03:22:16 PM PDT 24
Finished May 07 03:22:18 PM PDT 24
Peak memory 213364 kb
Host smart-37c0d054-9e0f-4677-9356-7c9feaf1fa88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372848574 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.3372848574
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.3083869600
Short name T55
Test name
Test status
Simulation time 187835691 ps
CPU time 1.02 seconds
Started May 07 03:22:13 PM PDT 24
Finished May 07 03:22:15 PM PDT 24
Peak memory 237480 kb
Host smart-91f87de4-d3f3-43d3-9b9a-d780a221fc1e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083869600 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.3083869600
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.81136362
Short name T168
Test name
Test status
Simulation time 773381774 ps
CPU time 1.36 seconds
Started May 07 03:22:11 PM PDT 24
Finished May 07 03:22:14 PM PDT 24
Peak memory 205288 kb
Host smart-e0efb8bd-4e33-4fcc-980c-86874ed0ed0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81136362 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.81136362
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.3723987003
Short name T66
Test name
Test status
Simulation time 26301422 ps
CPU time 0.74 seconds
Started May 07 03:22:26 PM PDT 24
Finished May 07 03:22:28 PM PDT 24
Peak memory 205260 kb
Host smart-bcb79066-7b2d-4f14-a605-890589f12d13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723987003 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.3723987003
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.1928208455
Short name T27
Test name
Test status
Simulation time 6416753772 ps
CPU time 7.54 seconds
Started May 07 03:22:13 PM PDT 24
Finished May 07 03:22:22 PM PDT 24
Peak memory 205472 kb
Host smart-fda673c3-576a-40cf-8716-54ee5be9239a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928208455 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.1928208455
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.647497390
Short name T7
Test name
Test status
Simulation time 222914371 ps
CPU time 1.33 seconds
Started May 07 03:22:15 PM PDT 24
Finished May 07 03:22:18 PM PDT 24
Peak memory 205048 kb
Host smart-b0b0a924-d279-4c6c-b337-1071c53b4cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647497390 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.647497390
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.1848352994
Short name T9
Test name
Test status
Simulation time 2160854306 ps
CPU time 4.98 seconds
Started May 07 03:22:15 PM PDT 24
Finished May 07 03:22:21 PM PDT 24
Peak memory 205516 kb
Host smart-a8fc082c-8fba-4764-8a70-bd696427c3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848352994 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.1848352994
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.2785195141
Short name T18
Test name
Test status
Simulation time 42678836 ps
CPU time 0.8 seconds
Started May 07 03:22:15 PM PDT 24
Finished May 07 03:22:17 PM PDT 24
Peak memory 205176 kb
Host smart-947040b9-322d-42ef-bb49-0295d15ed869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785195141 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.2785195141
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.2709199824
Short name T164
Test name
Test status
Simulation time 204434401 ps
CPU time 0.75 seconds
Started May 07 03:22:14 PM PDT 24
Finished May 07 03:22:16 PM PDT 24
Peak memory 205064 kb
Host smart-e3e74a88-55f0-4c82-a5d4-c53acc12e2f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709199824 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.2709199824
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.4113824018
Short name T26
Test name
Test status
Simulation time 282088138 ps
CPU time 0.87 seconds
Started May 07 03:22:15 PM PDT 24
Finished May 07 03:22:17 PM PDT 24
Peak memory 205036 kb
Host smart-86459c65-b587-4013-b698-3220d5ae5481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113824018 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.4113824018
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.3031468624
Short name T31
Test name
Test status
Simulation time 132648570 ps
CPU time 1.07 seconds
Started May 07 03:22:16 PM PDT 24
Finished May 07 03:22:18 PM PDT 24
Peak memory 205028 kb
Host smart-0120bd7f-a3dc-4c3d-b605-0321e044a326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031468624 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.3031468624
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.3828457498
Short name T135
Test name
Test status
Simulation time 101184696 ps
CPU time 0.9 seconds
Started May 07 03:22:16 PM PDT 24
Finished May 07 03:22:18 PM PDT 24
Peak memory 205156 kb
Host smart-8b2d7fa4-c1fe-4dc2-abd3-6228e13ae57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828457498 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.3828457498
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.4136325795
Short name T12
Test name
Test status
Simulation time 355091988 ps
CPU time 1.76 seconds
Started May 07 03:22:18 PM PDT 24
Finished May 07 03:22:20 PM PDT 24
Peak memory 204892 kb
Host smart-eb52953c-577c-404e-8b0e-df332928cb8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136325795 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.4136325795
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.1419678553
Short name T25
Test name
Test status
Simulation time 423965378 ps
CPU time 1.93 seconds
Started May 07 03:22:15 PM PDT 24
Finished May 07 03:22:18 PM PDT 24
Peak memory 205348 kb
Host smart-d5597254-500c-4157-83de-8ef47ebe9a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419678553 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.1419678553
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.311146723
Short name T21
Test name
Test status
Simulation time 449337242 ps
CPU time 2.09 seconds
Started May 07 03:22:14 PM PDT 24
Finished May 07 03:22:17 PM PDT 24
Peak memory 205336 kb
Host smart-0b9f4788-4034-47fe-a177-d429ddee5577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311146723 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.311146723
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.3146537670
Short name T16
Test name
Test status
Simulation time 77716698 ps
CPU time 0.82 seconds
Started May 07 03:22:19 PM PDT 24
Finished May 07 03:22:20 PM PDT 24
Peak memory 205152 kb
Host smart-7e2b5ea5-fdcd-4f01-8cd3-d08637bf2597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146537670 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.3146537670
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.939562080
Short name T56
Test name
Test status
Simulation time 159671684 ps
CPU time 1 seconds
Started May 07 03:22:18 PM PDT 24
Finished May 07 03:22:20 PM PDT 24
Peak memory 229668 kb
Host smart-e86332c0-cb54-43d9-8568-3ee9be30d242
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939562080 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.939562080
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.267936056
Short name T24
Test name
Test status
Simulation time 591272851 ps
CPU time 1.15 seconds
Started May 07 03:22:15 PM PDT 24
Finished May 07 03:22:18 PM PDT 24
Peak memory 205280 kb
Host smart-760b31e9-e012-43a8-b0e2-58f0b42e324b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267936056 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.267936056
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.1534815634
Short name T119
Test name
Test status
Simulation time 65590260 ps
CPU time 0.73 seconds
Started May 07 03:22:54 PM PDT 24
Finished May 07 03:22:57 PM PDT 24
Peak memory 205216 kb
Host smart-0e0c4d56-8ffd-429b-badf-de0fcc9db878
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534815634 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.1534815634
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.2657018556
Short name T40
Test name
Test status
Simulation time 72230504 ps
CPU time 0.72 seconds
Started May 07 03:22:33 PM PDT 24
Finished May 07 03:22:34 PM PDT 24
Peak memory 205176 kb
Host smart-9be957ed-7234-4a8e-a668-fb95e082b34c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657018556 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.2657018556
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.2579647825
Short name T28
Test name
Test status
Simulation time 4694528012 ps
CPU time 7.56 seconds
Started May 07 03:22:40 PM PDT 24
Finished May 07 03:22:49 PM PDT 24
Peak memory 213780 kb
Host smart-21778b14-4ac9-4850-ad63-22bdbf30754f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2579647825 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.2579647825
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.2148844734
Short name T113
Test name
Test status
Simulation time 19217055 ps
CPU time 0.74 seconds
Started May 07 03:22:37 PM PDT 24
Finished May 07 03:22:44 PM PDT 24
Peak memory 205136 kb
Host smart-2b9225fb-7fdd-4063-9e04-bc012060bf26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148844734 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.2148844734
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.1495624646
Short name T158
Test name
Test status
Simulation time 18172315 ps
CPU time 0.72 seconds
Started May 07 03:22:44 PM PDT 24
Finished May 07 03:22:47 PM PDT 24
Peak memory 205096 kb
Host smart-5dc8b6cf-6ae7-4325-8d0e-b95114c2f7de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495624646 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.1495624646
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.2215379019
Short name T152
Test name
Test status
Simulation time 40755717 ps
CPU time 0.78 seconds
Started May 07 03:22:40 PM PDT 24
Finished May 07 03:22:42 PM PDT 24
Peak memory 205164 kb
Host smart-d097afbf-6e70-465b-8eec-e48923b73cad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215379019 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.2215379019
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.3434063832
Short name T70
Test name
Test status
Simulation time 23742500 ps
CPU time 0.78 seconds
Started May 07 03:22:40 PM PDT 24
Finished May 07 03:22:42 PM PDT 24
Peak memory 205136 kb
Host smart-dacc1be8-184e-40ba-8ed3-7a8cd5b1e6f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434063832 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.3434063832
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.173490554
Short name T162
Test name
Test status
Simulation time 55756911 ps
CPU time 0.73 seconds
Started May 07 03:22:43 PM PDT 24
Finished May 07 03:22:46 PM PDT 24
Peak memory 205164 kb
Host smart-96ed2908-b0d4-4e35-8684-5061f424e1d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173490554 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.173490554
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.465027169
Short name T87
Test name
Test status
Simulation time 5211816362 ps
CPU time 7.35 seconds
Started May 07 03:22:45 PM PDT 24
Finished May 07 03:22:54 PM PDT 24
Peak memory 213820 kb
Host smart-c3035c2e-eef2-4ca0-abbe-420dcc9e1e79
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=465027169 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_t
l_access.465027169
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.3243166212
Short name T112
Test name
Test status
Simulation time 35694767 ps
CPU time 0.67 seconds
Started May 07 03:22:48 PM PDT 24
Finished May 07 03:22:51 PM PDT 24
Peak memory 205128 kb
Host smart-1afcbccf-6a67-4c22-984d-7dd8eaa2a006
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243166212 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.3243166212
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.2369444914
Short name T49
Test name
Test status
Simulation time 19061811 ps
CPU time 0.73 seconds
Started May 07 03:22:20 PM PDT 24
Finished May 07 03:22:22 PM PDT 24
Peak memory 205168 kb
Host smart-6393c189-5996-429d-adfa-04faf9d9aa95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369444914 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.2369444914
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.4049691360
Short name T167
Test name
Test status
Simulation time 55726353 ps
CPU time 0.86 seconds
Started May 07 03:22:28 PM PDT 24
Finished May 07 03:22:29 PM PDT 24
Peak memory 205060 kb
Host smart-a38600e9-7645-4a0c-aec5-41a03afc9436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049691360 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.4049691360
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.4175186317
Short name T1
Test name
Test status
Simulation time 302849247 ps
CPU time 1.73 seconds
Started May 07 03:22:20 PM PDT 24
Finished May 07 03:22:23 PM PDT 24
Peak memory 229452 kb
Host smart-196b3202-1ccd-4924-b654-dcd40e3fc9aa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175186317 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.4175186317
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.1814947773
Short name T151
Test name
Test status
Simulation time 46269271 ps
CPU time 0.76 seconds
Started May 07 03:22:42 PM PDT 24
Finished May 07 03:22:45 PM PDT 24
Peak memory 205264 kb
Host smart-e7cc990a-5bbe-42c3-866e-a859b05fb142
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814947773 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.1814947773
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.2607225204
Short name T140
Test name
Test status
Simulation time 25916406 ps
CPU time 0.73 seconds
Started May 07 03:22:55 PM PDT 24
Finished May 07 03:22:59 PM PDT 24
Peak memory 205128 kb
Host smart-f78814dc-d75b-4fab-bf4f-0c4bf5348a87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607225204 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.2607225204
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.2985513438
Short name T67
Test name
Test status
Simulation time 57568010 ps
CPU time 0.7 seconds
Started May 07 03:22:44 PM PDT 24
Finished May 07 03:22:47 PM PDT 24
Peak memory 205140 kb
Host smart-a30c1c1d-fdb1-4605-9c3d-47d5434dff2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985513438 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.2985513438
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.1730261506
Short name T156
Test name
Test status
Simulation time 20151130 ps
CPU time 0.71 seconds
Started May 07 03:22:44 PM PDT 24
Finished May 07 03:22:47 PM PDT 24
Peak memory 205180 kb
Host smart-0b3f80e3-5fb2-42f0-96f2-74d3af378dd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730261506 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.1730261506
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.2876714767
Short name T148
Test name
Test status
Simulation time 20696281 ps
CPU time 0.74 seconds
Started May 07 03:22:53 PM PDT 24
Finished May 07 03:22:56 PM PDT 24
Peak memory 205116 kb
Host smart-2310baef-4c2a-469f-a75d-18675235429a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876714767 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.2876714767
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.3626202759
Short name T169
Test name
Test status
Simulation time 28735382 ps
CPU time 0.71 seconds
Started May 07 03:22:46 PM PDT 24
Finished May 07 03:22:49 PM PDT 24
Peak memory 205328 kb
Host smart-82edb4ca-0839-4559-bec5-6301aaddf6d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626202759 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.3626202759
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.3888087311
Short name T43
Test name
Test status
Simulation time 33509434 ps
CPU time 0.67 seconds
Started May 07 03:22:48 PM PDT 24
Finished May 07 03:22:51 PM PDT 24
Peak memory 205172 kb
Host smart-d8d69ae7-3c65-4b72-90e5-2d64b6f91674
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888087311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.3888087311
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.2626438140
Short name T163
Test name
Test status
Simulation time 42350157 ps
CPU time 0.7 seconds
Started May 07 03:22:50 PM PDT 24
Finished May 07 03:22:53 PM PDT 24
Peak memory 205116 kb
Host smart-80907149-8481-4f17-92dd-ec99f4497bc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626438140 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.2626438140
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.1082255610
Short name T53
Test name
Test status
Simulation time 33214567 ps
CPU time 0.77 seconds
Started May 07 03:22:46 PM PDT 24
Finished May 07 03:22:49 PM PDT 24
Peak memory 205168 kb
Host smart-81b281a3-cba3-4f53-b3a8-83fafb389a1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082255610 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.1082255610
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.3957365324
Short name T170
Test name
Test status
Simulation time 19130419 ps
CPU time 0.71 seconds
Started May 07 03:22:49 PM PDT 24
Finished May 07 03:23:04 PM PDT 24
Peak memory 205176 kb
Host smart-2060f1f5-8f8d-44f9-aecc-b7bd13179ffb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957365324 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.3957365324
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.4062388358
Short name T69
Test name
Test status
Simulation time 21184222 ps
CPU time 0.71 seconds
Started May 07 03:22:19 PM PDT 24
Finished May 07 03:22:21 PM PDT 24
Peak memory 205140 kb
Host smart-6d01ec76-053b-431e-b377-273c4280e087
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062388358 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.4062388358
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.1848931229
Short name T161
Test name
Test status
Simulation time 75259445 ps
CPU time 0.81 seconds
Started May 07 03:22:20 PM PDT 24
Finished May 07 03:22:22 PM PDT 24
Peak memory 204972 kb
Host smart-14b26883-fe66-4456-a0ea-5cc45a6e9f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848931229 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.1848931229
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.2147064335
Short name T150
Test name
Test status
Simulation time 47099914 ps
CPU time 0.7 seconds
Started May 07 03:22:42 PM PDT 24
Finished May 07 03:22:45 PM PDT 24
Peak memory 205160 kb
Host smart-70d035de-1e5b-4b28-9462-973752c0b665
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147064335 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.2147064335
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.1801040893
Short name T50
Test name
Test status
Simulation time 75068121 ps
CPU time 0.75 seconds
Started May 07 03:22:58 PM PDT 24
Finished May 07 03:23:03 PM PDT 24
Peak memory 205164 kb
Host smart-200f41b3-ee7f-4da2-9a59-2c6cc042db5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801040893 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.1801040893
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.3181414806
Short name T41
Test name
Test status
Simulation time 23579543 ps
CPU time 0.72 seconds
Started May 07 03:22:49 PM PDT 24
Finished May 07 03:22:53 PM PDT 24
Peak memory 205188 kb
Host smart-307b76cc-38cd-4a82-b0d7-b9981a8bd4fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181414806 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.3181414806
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.3850833870
Short name T38
Test name
Test status
Simulation time 65494531 ps
CPU time 0.69 seconds
Started May 07 03:22:45 PM PDT 24
Finished May 07 03:22:48 PM PDT 24
Peak memory 205136 kb
Host smart-3dcfc21d-e5c6-482a-922c-c1f9b2ac96f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850833870 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.3850833870
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.2879256614
Short name T71
Test name
Test status
Simulation time 37422196 ps
CPU time 0.71 seconds
Started May 07 03:22:43 PM PDT 24
Finished May 07 03:22:45 PM PDT 24
Peak memory 205124 kb
Host smart-2f616373-0b6d-408a-a6e5-069b3b0a4e19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879256614 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.2879256614
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.207555600
Short name T171
Test name
Test status
Simulation time 35935919 ps
CPU time 0.72 seconds
Started May 07 03:22:47 PM PDT 24
Finished May 07 03:22:50 PM PDT 24
Peak memory 205164 kb
Host smart-22ed9440-9664-4663-b792-ba4b7ab00b21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207555600 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.207555600
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.3994873855
Short name T155
Test name
Test status
Simulation time 18678765 ps
CPU time 0.72 seconds
Started May 07 03:22:50 PM PDT 24
Finished May 07 03:22:53 PM PDT 24
Peak memory 205180 kb
Host smart-be639dc1-b41d-4bf6-9ba5-ee05bd78b45a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994873855 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.3994873855
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.1706985711
Short name T149
Test name
Test status
Simulation time 59160166 ps
CPU time 0.73 seconds
Started May 07 03:22:54 PM PDT 24
Finished May 07 03:22:57 PM PDT 24
Peak memory 205164 kb
Host smart-92cb8dd5-dffd-4196-b083-65e7899ed050
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706985711 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.1706985711
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.2701021850
Short name T68
Test name
Test status
Simulation time 29641518 ps
CPU time 0.69 seconds
Started May 07 03:22:49 PM PDT 24
Finished May 07 03:22:53 PM PDT 24
Peak memory 205168 kb
Host smart-af892091-e00e-407a-8013-bd90a3cce44c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701021850 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.2701021850
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.3296162125
Short name T136
Test name
Test status
Simulation time 27960458 ps
CPU time 0.73 seconds
Started May 07 03:22:44 PM PDT 24
Finished May 07 03:22:47 PM PDT 24
Peak memory 205148 kb
Host smart-581939e6-c66a-4270-9183-58b2c5f6d9ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296162125 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.3296162125
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.2348213205
Short name T143
Test name
Test status
Simulation time 27786975 ps
CPU time 0.73 seconds
Started May 07 03:22:21 PM PDT 24
Finished May 07 03:22:23 PM PDT 24
Peak memory 205168 kb
Host smart-99455542-263c-455b-bddc-187b2f9a9f58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348213205 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.2348213205
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.2631014491
Short name T39
Test name
Test status
Simulation time 44668417 ps
CPU time 0.7 seconds
Started May 07 03:22:21 PM PDT 24
Finished May 07 03:22:23 PM PDT 24
Peak memory 205008 kb
Host smart-e48a4119-2f1d-4da5-b358-5ef4b05d7a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631014491 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.2631014491
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.2003999512
Short name T35
Test name
Test status
Simulation time 257800233 ps
CPU time 1.73 seconds
Started May 07 03:22:21 PM PDT 24
Finished May 07 03:22:24 PM PDT 24
Peak memory 229424 kb
Host smart-4d3e513a-bde0-481a-983a-649969260b0a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003999512 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.2003999512
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.1702191532
Short name T138
Test name
Test status
Simulation time 21430472 ps
CPU time 0.72 seconds
Started May 07 03:22:53 PM PDT 24
Finished May 07 03:22:57 PM PDT 24
Peak memory 205168 kb
Host smart-9c0f39a7-bb6e-45e4-bd6e-42b07a8e45f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702191532 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.1702191532
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.3795312168
Short name T137
Test name
Test status
Simulation time 29077187 ps
CPU time 0.73 seconds
Started May 07 03:22:44 PM PDT 24
Finished May 07 03:22:47 PM PDT 24
Peak memory 204800 kb
Host smart-75785886-e360-46a7-a365-f8ea5b703beb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795312168 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.3795312168
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.505508220
Short name T145
Test name
Test status
Simulation time 169336872 ps
CPU time 0.73 seconds
Started May 07 03:22:58 PM PDT 24
Finished May 07 03:23:03 PM PDT 24
Peak memory 205092 kb
Host smart-3a3a34c5-ef5d-4244-bd6e-c597bf61abca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505508220 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.505508220
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.2672227023
Short name T54
Test name
Test status
Simulation time 39225884 ps
CPU time 0.78 seconds
Started May 07 03:22:48 PM PDT 24
Finished May 07 03:22:52 PM PDT 24
Peak memory 205112 kb
Host smart-cf070268-f5de-49d6-9bdc-5848cad5acb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672227023 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.2672227023
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.440981413
Short name T160
Test name
Test status
Simulation time 44132255 ps
CPU time 0.74 seconds
Started May 07 03:22:58 PM PDT 24
Finished May 07 03:23:03 PM PDT 24
Peak memory 205092 kb
Host smart-efd8d3f1-7219-4d15-bb96-9479ce7c4345
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440981413 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.440981413
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.2720346058
Short name T42
Test name
Test status
Simulation time 173817972 ps
CPU time 0.73 seconds
Started May 07 03:22:51 PM PDT 24
Finished May 07 03:22:54 PM PDT 24
Peak memory 205160 kb
Host smart-16dd028f-deaf-4a39-bd7b-51391ac32ff8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720346058 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.2720346058
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.3869962356
Short name T157
Test name
Test status
Simulation time 34112692 ps
CPU time 0.72 seconds
Started May 07 03:22:48 PM PDT 24
Finished May 07 03:22:51 PM PDT 24
Peak memory 205172 kb
Host smart-97e00461-2ff9-433f-9a5d-85c3d0f8f60d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869962356 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.3869962356
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.3991170094
Short name T139
Test name
Test status
Simulation time 152468093 ps
CPU time 0.72 seconds
Started May 07 03:22:50 PM PDT 24
Finished May 07 03:22:54 PM PDT 24
Peak memory 205136 kb
Host smart-ffd459ba-85ab-4f36-a9a5-4e83cf9ed309
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991170094 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.3991170094
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.3004669020
Short name T153
Test name
Test status
Simulation time 29167183 ps
CPU time 0.71 seconds
Started May 07 03:22:56 PM PDT 24
Finished May 07 03:23:01 PM PDT 24
Peak memory 205132 kb
Host smart-61399844-09f8-4c1b-a923-4d595efd9ba1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004669020 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.3004669020
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.2347754191
Short name T166
Test name
Test status
Simulation time 23113492 ps
CPU time 0.7 seconds
Started May 07 03:22:59 PM PDT 24
Finished May 07 03:23:04 PM PDT 24
Peak memory 205160 kb
Host smart-eb0a95f3-28f6-47c2-81b3-2c2743eaeffc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347754191 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.2347754191
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.3658656071
Short name T159
Test name
Test status
Simulation time 23173203 ps
CPU time 0.73 seconds
Started May 07 03:22:20 PM PDT 24
Finished May 07 03:22:22 PM PDT 24
Peak memory 205164 kb
Host smart-0f16fe49-582a-42aa-aa9d-be1670477e52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658656071 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.3658656071
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.2368167160
Short name T37
Test name
Test status
Simulation time 26584811 ps
CPU time 0.7 seconds
Started May 07 03:22:39 PM PDT 24
Finished May 07 03:22:41 PM PDT 24
Peak memory 205112 kb
Host smart-f96e5a85-9e1f-4eb2-a20b-51e6183766ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368167160 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.2368167160
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.3777265346
Short name T29
Test name
Test status
Simulation time 3052295743 ps
CPU time 5.89 seconds
Started May 07 03:22:30 PM PDT 24
Finished May 07 03:22:37 PM PDT 24
Peak memory 215232 kb
Host smart-59aeb719-976d-4a41-b104-8183f6617250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777265346 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.3777265346
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.691178236
Short name T142
Test name
Test status
Simulation time 87627298 ps
CPU time 0.72 seconds
Started May 07 03:22:38 PM PDT 24
Finished May 07 03:22:40 PM PDT 24
Peak memory 205184 kb
Host smart-c3e04e9c-6f70-4ecb-a0a0-951278882527
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691178236 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.691178236
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.1277422020
Short name T154
Test name
Test status
Simulation time 20114637 ps
CPU time 0.71 seconds
Started May 07 03:22:32 PM PDT 24
Finished May 07 03:22:34 PM PDT 24
Peak memory 205152 kb
Host smart-310578f3-45c9-47cf-b040-cf17f39db5fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277422020 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.1277422020
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.1038847167
Short name T146
Test name
Test status
Simulation time 19535852 ps
CPU time 0.71 seconds
Started May 07 03:22:38 PM PDT 24
Finished May 07 03:22:40 PM PDT 24
Peak memory 205112 kb
Host smart-0d76e957-b9e9-4c4c-b471-aa456e2752da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038847167 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.1038847167
Directory /workspace/9.rv_dm_alert_test/latest
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