Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 183527 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 558069 1 T17 80 T6 1 T19 2



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 447279 1 T17 80 T27 8 T18 80
values[0x0] 144269 1 T6 4 T19 2 T7 24
values[0x1] 150048 1 T6 6 T7 23 T8 4



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 140858 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 600738 1 T17 80 T6 2 T19 2



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 3031 1 T14 1 T43 1 T40 37
valid_sources[0x01] 2524 1 T13 1 T43 3 T40 24
valid_sources[0x02] 2609 1 T14 1 T43 1 T40 48
valid_sources[0x03] 2591 1 T13 1 T24 5 T43 4
valid_sources[0x04] 3415 1 T6 1 T12 3 T43 3
valid_sources[0x05] 2501 1 T43 2 T40 15 T41 9
valid_sources[0x06] 2607 1 T38 1 T43 3 T40 51
valid_sources[0x07] 2783 1 T43 1 T40 80 T41 7
valid_sources[0x08] 3012 1 T14 1 T18 80 T67 1
valid_sources[0x09] 3305 1 T14 1 T40 36 T41 2
valid_sources[0x0a] 3256 1 T12 4 T13 1 T120 1
valid_sources[0x0b] 2556 1 T13 1 T43 4 T40 50
valid_sources[0x0c] 2893 1 T13 1 T43 3 T40 38
valid_sources[0x0d] 2851 1 T13 1 T43 1 T40 23
valid_sources[0x0e] 2809 1 T121 5 T43 2 T40 57
valid_sources[0x0f] 2960 1 T43 1 T40 43 T41 3
valid_sources[0x10] 2958 1 T12 1 T43 4 T40 43
valid_sources[0x11] 2790 1 T12 1 T43 3 T40 56
valid_sources[0x12] 2899 1 T13 1 T38 1 T43 4
valid_sources[0x13] 2656 1 T14 2 T43 2 T40 57
valid_sources[0x14] 3078 1 T13 1 T43 3 T40 36
valid_sources[0x15] 2869 1 T13 1 T43 3 T40 35
valid_sources[0x16] 2605 1 T43 1 T40 47 T41 6
valid_sources[0x17] 2573 1 T38 1 T43 2 T40 42
valid_sources[0x18] 3262 1 T15 7 T11 5 T13 1
valid_sources[0x19] 3073 1 T43 4 T40 52 T41 6
valid_sources[0x1a] 2886 1 T8 1 T43 2 T40 40
valid_sources[0x1b] 2834 1 T67 1 T43 2 T40 53
valid_sources[0x1c] 2893 1 T43 2 T40 44 T41 13
valid_sources[0x1d] 3272 1 T11 1 T12 2 T13 1
valid_sources[0x1e] 3341 1 T7 47 T12 1 T13 1
valid_sources[0x1f] 2524 1 T12 1 T120 1 T43 2
valid_sources[0x20] 2587 1 T38 1 T43 2 T40 42
valid_sources[0x21] 2566 1 T8 2 T38 1 T43 2
valid_sources[0x22] 3159 1 T12 1 T43 3 T40 47
valid_sources[0x23] 2744 1 T14 1 T13 2 T120 1
valid_sources[0x24] 2744 1 T43 2 T40 46 T41 7
valid_sources[0x25] 2655 1 T14 1 T67 1 T43 3
valid_sources[0x26] 2944 1 T12 2 T13 1 T38 1
valid_sources[0x27] 2743 1 T43 1 T40 67 T41 5
valid_sources[0x28] 2439 1 T16 14 T67 1 T43 1
valid_sources[0x29] 2566 1 T14 2 T43 2 T40 21
valid_sources[0x2a] 2912 1 T38 1 T120 2 T43 4
valid_sources[0x2b] 2731 1 T38 1 T43 5 T40 63
valid_sources[0x2c] 3045 1 T14 1 T40 42 T41 5
valid_sources[0x2d] 2678 1 T40 43 T41 7 T42 34
valid_sources[0x2e] 2885 1 T38 1 T40 32 T41 8
valid_sources[0x2f] 2653 1 T43 2 T40 33 T41 11
valid_sources[0x30] 2755 1 T14 1 T43 3 T40 53
valid_sources[0x31] 3294 1 T13 1 T43 1 T40 36
valid_sources[0x32] 3127 1 T6 1 T43 1 T40 54
valid_sources[0x33] 2781 1 T43 1 T40 32 T41 16
valid_sources[0x34] 3124 1 T13 1 T43 1 T40 44
valid_sources[0x35] 2705 1 T13 1 T43 1 T40 44
valid_sources[0x36] 2668 1 T43 3 T40 56 T41 7
valid_sources[0x37] 3253 1 T40 34 T41 3 T42 38
valid_sources[0x38] 2720 1 T38 1 T43 4 T40 45
valid_sources[0x39] 2810 1 T12 1 T43 3 T40 55
valid_sources[0x3a] 2822 1 T43 3 T40 74 T41 2
valid_sources[0x3b] 3323 1 T27 1 T38 1 T43 4
valid_sources[0x3c] 2851 1 T43 2 T40 36 T41 5
valid_sources[0x3d] 4191 1 T12 1 T43 1 T40 35
valid_sources[0x3e] 2546 1 T28 1 T29 11 T43 4
valid_sources[0x3f] 3165 1 T15 2 T13 1 T43 3
valid_sources[0x40] 2592 1 T43 5 T40 41 T41 8
valid_sources[0x41] 2861 1 T40 54 T41 6 T42 45
valid_sources[0x42] 4205 1 T20 1 T43 1 T40 46
valid_sources[0x43] 2534 1 T43 2 T40 33 T41 4
valid_sources[0x44] 2590 1 T15 2 T13 1 T120 1
valid_sources[0x45] 2851 1 T12 1 T67 1 T43 2
valid_sources[0x46] 2823 1 T12 4 T43 3 T40 29
valid_sources[0x47] 2640 1 T11 3 T13 1 T40 45
valid_sources[0x48] 2867 1 T12 5 T43 1 T40 49
valid_sources[0x49] 2622 1 T14 1 T38 1 T43 2
valid_sources[0x4a] 2806 1 T12 1 T38 1 T43 2
valid_sources[0x4b] 3111 1 T14 2 T12 4 T38 1
valid_sources[0x4c] 2973 1 T20 3 T43 2 T40 60
valid_sources[0x4d] 2664 1 T43 4 T40 45 T41 6
valid_sources[0x4e] 3161 1 T43 1 T40 42 T41 5
valid_sources[0x4f] 2938 1 T13 1 T43 3 T40 33
valid_sources[0x50] 2641 1 T27 1 T13 2 T120 1
valid_sources[0x51] 2894 1 T12 3 T40 40 T41 5
valid_sources[0x52] 2845 1 T23 1 T12 1 T43 3
valid_sources[0x53] 2948 1 T13 2 T38 1 T40 45
valid_sources[0x54] 2649 1 T43 2 T40 27 T41 4
valid_sources[0x55] 2460 1 T121 2 T43 2 T40 53
valid_sources[0x56] 2880 1 T14 1 T12 4 T13 1
valid_sources[0x57] 2933 1 T43 2 T40 51 T41 11
valid_sources[0x58] 2924 1 T43 2 T40 27 T41 8
valid_sources[0x59] 2574 1 T40 29 T41 7 T42 39
valid_sources[0x5a] 3372 1 T27 1 T12 5 T13 1
valid_sources[0x5b] 2843 1 T13 1 T24 2 T43 1
valid_sources[0x5c] 2835 1 T13 1 T28 7 T43 1
valid_sources[0x5d] 2740 1 T43 1 T40 39 T41 8
valid_sources[0x5e] 2657 1 T67 2 T40 31 T41 6
valid_sources[0x5f] 3427 1 T14 2 T12 2 T13 1
valid_sources[0x60] 2668 1 T14 1 T43 3 T40 45
valid_sources[0x61] 2551 1 T43 2 T40 36 T41 7
valid_sources[0x62] 2664 1 T14 3 T43 2 T40 25
valid_sources[0x63] 3064 1 T13 1 T43 3 T40 43
valid_sources[0x64] 2908 1 T12 4 T67 1 T38 1
valid_sources[0x65] 2546 1 T12 2 T13 1 T40 52
valid_sources[0x66] 2631 1 T19 2 T23 3 T43 3
valid_sources[0x67] 3636 1 T43 3 T40 44 T41 14
valid_sources[0x68] 3090 1 T12 2 T43 2 T40 39
valid_sources[0x69] 2608 1 T21 2 T38 1 T43 3
valid_sources[0x6a] 2847 1 T14 2 T67 1 T38 1
valid_sources[0x6b] 2753 1 T12 3 T43 1 T40 42
valid_sources[0x6c] 2880 1 T12 1 T43 2 T40 43
valid_sources[0x6d] 3377 1 T43 2 T40 54 T41 5
valid_sources[0x6e] 2642 1 T14 2 T12 1 T40 47
valid_sources[0x6f] 2602 1 T12 1 T43 3 T40 36
valid_sources[0x70] 2909 1 T40 26 T41 7 T42 27
valid_sources[0x71] 2769 1 T38 1 T43 4 T40 54
valid_sources[0x72] 2630 1 T43 2 T40 49 T41 6
valid_sources[0x73] 2726 1 T43 2 T40 24 T41 15
valid_sources[0x74] 3230 1 T14 1 T13 1 T43 4
valid_sources[0x75] 2594 1 T14 2 T43 1 T40 44
valid_sources[0x76] 2672 1 T13 1 T43 1 T40 48
valid_sources[0x77] 2873 1 T43 3 T40 46 T41 5
valid_sources[0x78] 2850 1 T67 1 T43 2 T40 42
valid_sources[0x79] 2792 1 T14 1 T12 4 T13 1
valid_sources[0x7a] 2656 1 T43 1 T40 47 T41 4
valid_sources[0x7b] 2584 1 T14 1 T40 56 T41 9
valid_sources[0x7c] 2887 1 T13 2 T40 46 T41 8
valid_sources[0x7d] 3413 1 T43 1 T40 33 T41 4
valid_sources[0x7e] 2625 1 T38 1 T43 1 T40 61
valid_sources[0x7f] 2834 1 T120 2 T43 2 T40 22
valid_sources[0x80] 2807 1 T14 1 T40 47 T41 7



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 272733 1 T17 80 T27 2 T18 80
values[0x0] all_enables biggest_size 142463 1 T6 1 T19 2 T7 7
values[0x1] all_enables biggest_size 142873 1 T7 3 T14 8 T20 9


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 4735 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 20191 1 T2 6 T5 5 T37 2



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 9351 1 T43 126 T40 69 T41 52
values[0x0] 7706 1 T2 5 T5 10 T37 5
values[0x1] 7869 1 T2 5 T5 11 T37 6



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 3581 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 21345 1 T2 6 T5 7 T37 3



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 127 1 T37 11 T61 2 T122 1
valid_sources[0x01] 64 1 T123 3 T43 2 T59 3
valid_sources[0x02] 73 1 T43 2 T40 2 T59 2
valid_sources[0x03] 79 1 T61 3 T124 1 T43 1
valid_sources[0x04] 66 1 T43 1 T59 3 T63 1
valid_sources[0x05] 68 1 T43 2 T40 1 T59 2
valid_sources[0x06] 72 1 T43 4 T42 1 T63 4
valid_sources[0x07] 112 1 T125 10 T40 1 T59 6
valid_sources[0x08] 69 1 T126 2 T43 2 T59 2
valid_sources[0x09] 86 1 T42 1 T63 1 T64 1
valid_sources[0x0a] 78 1 T43 3 T40 1 T59 3
valid_sources[0x0b] 66 1 T43 4 T59 2 T65 1
valid_sources[0x0c] 204 1 T40 1 T42 1 T59 2
valid_sources[0x0d] 98 1 T5 1 T45 4 T61 1
valid_sources[0x0e] 74 1 T43 2 T59 2 T63 2
valid_sources[0x0f] 81 1 T43 4 T63 1 T53 1
valid_sources[0x10] 93 1 T43 3 T69 1 T64 2
valid_sources[0x11] 61 1 T54 2 T43 1 T42 1
valid_sources[0x12] 84 1 T59 4 T63 2 T75 7
valid_sources[0x13] 236 1 T2 1 T43 2 T59 2
valid_sources[0x14] 72 1 T43 1 T59 1 T63 1
valid_sources[0x15] 63 1 T46 2 T43 3 T59 1
valid_sources[0x16] 83 1 T2 1 T127 1 T125 7
valid_sources[0x17] 97 1 T128 11 T129 5 T130 1
valid_sources[0x18] 65 1 T54 1 T43 2 T63 1
valid_sources[0x19] 54 1 T40 1 T42 1 T63 1
valid_sources[0x1a] 50 1 T43 2 T42 1 T59 1
valid_sources[0x1b] 83 1 T43 4 T42 1 T59 3
valid_sources[0x1c] 74 1 T43 4 T63 1 T65 2
valid_sources[0x1d] 63 1 T43 1 T41 11 T64 1
valid_sources[0x1e] 63 1 T43 2 T63 4 T68 4
valid_sources[0x1f] 126 1 T43 4 T59 2 T64 1
valid_sources[0x20] 312 1 T131 1 T43 2 T59 1
valid_sources[0x21] 114 1 T43 2 T40 2 T63 1
valid_sources[0x22] 81 1 T5 1 T132 3 T43 1
valid_sources[0x23] 51 1 T43 2 T40 1 T59 3
valid_sources[0x24] 117 1 T59 1 T64 1 T65 1
valid_sources[0x25] 52 1 T43 1 T42 1 T59 1
valid_sources[0x26] 858 1 T5 2 T43 5 T40 1
valid_sources[0x27] 288 1 T44 1 T43 2 T40 2
valid_sources[0x28] 223 1 T133 3 T43 1 T59 2
valid_sources[0x29] 127 1 T122 1 T134 13 T43 2
valid_sources[0x2a] 133 1 T135 2 T43 1 T59 2
valid_sources[0x2b] 53 1 T59 4 T63 1 T64 1
valid_sources[0x2c] 187 1 T43 2 T40 4 T42 1
valid_sources[0x2d] 61 1 T43 2 T40 3 T42 1
valid_sources[0x2e] 109 1 T2 1 T43 1 T59 1
valid_sources[0x2f] 75 1 T43 1 T59 2 T63 1
valid_sources[0x30] 111 1 T44 4 T136 2 T43 1
valid_sources[0x31] 91 1 T104 1 T126 1 T43 4
valid_sources[0x32] 190 1 T43 3 T42 3 T63 1
valid_sources[0x33] 87 1 T43 1 T59 4 T64 1
valid_sources[0x34] 139 1 T136 7 T54 1 T43 1
valid_sources[0x35] 147 1 T43 1 T59 4 T63 2
valid_sources[0x36] 82 1 T43 3 T40 1 T59 2
valid_sources[0x37] 80 1 T43 2 T59 3 T63 1
valid_sources[0x38] 129 1 T43 1 T59 1 T63 1
valid_sources[0x39] 70 1 T127 3 T43 2 T63 5
valid_sources[0x3a] 53 1 T39 1 T62 2 T137 3
valid_sources[0x3b] 79 1 T43 4 T40 2 T65 1
valid_sources[0x3c] 68 1 T122 1 T43 3 T42 1
valid_sources[0x3d] 101 1 T43 1 T40 4 T42 2
valid_sources[0x3e] 106 1 T43 4 T42 2 T59 2
valid_sources[0x3f] 152 1 T47 1 T43 3 T40 1
valid_sources[0x40] 78 1 T62 1 T43 2 T59 3
valid_sources[0x41] 57 1 T43 1 T42 1 T59 1
valid_sources[0x42] 119 1 T61 2 T122 2 T54 1
valid_sources[0x43] 184 1 T43 3 T40 2 T59 3
valid_sources[0x44] 60 1 T122 1 T63 1 T53 3
valid_sources[0x45] 85 1 T5 1 T43 4 T42 1
valid_sources[0x46] 87 1 T138 1 T139 4 T140 6
valid_sources[0x47] 80 1 T126 1 T43 3 T59 3
valid_sources[0x48] 126 1 T43 4 T40 2 T41 6
valid_sources[0x49] 91 1 T64 1 T75 4 T53 1
valid_sources[0x4a] 67 1 T43 1 T40 1 T59 4
valid_sources[0x4b] 103 1 T43 2 T40 3 T42 3
valid_sources[0x4c] 97 1 T43 4 T40 1 T59 1
valid_sources[0x4d] 97 1 T43 2 T42 1 T59 1
valid_sources[0x4e] 61 1 T141 2 T43 3 T40 1
valid_sources[0x4f] 87 1 T142 3 T43 3 T40 1
valid_sources[0x50] 100 1 T43 5 T42 2 T59 1
valid_sources[0x51] 131 1 T43 1 T42 2 T59 5
valid_sources[0x52] 284 1 T124 1 T43 2 T40 1
valid_sources[0x53] 164 1 T2 1 T43 2 T59 8
valid_sources[0x54] 199 1 T43 1 T59 4 T63 2
valid_sources[0x55] 51 1 T43 3 T59 2 T63 1
valid_sources[0x56] 237 1 T62 1 T43 1 T40 1
valid_sources[0x57] 59 1 T43 4 T59 2 T63 1
valid_sources[0x58] 59 1 T40 2 T42 1 T59 2
valid_sources[0x59] 87 1 T126 1 T43 2 T42 1
valid_sources[0x5a] 78 1 T43 1 T40 1 T59 2
valid_sources[0x5b] 212 1 T143 1 T59 3 T53 5
valid_sources[0x5c] 66 1 T60 8 T144 2 T130 1
valid_sources[0x5d] 161 1 T43 7 T59 2 T52 30
valid_sources[0x5e] 89 1 T43 1 T40 2 T63 1
valid_sources[0x5f] 67 1 T43 2 T40 1 T59 1
valid_sources[0x60] 51 1 T62 1 T43 2 T42 2
valid_sources[0x61] 145 1 T127 1 T43 1 T42 1
valid_sources[0x62] 94 1 T43 3 T59 6 T64 3
valid_sources[0x63] 66 1 T145 1 T43 4 T59 1
valid_sources[0x64] 71 1 T43 3 T59 2 T63 4
valid_sources[0x65] 51 1 T122 1 T142 1 T43 1
valid_sources[0x66] 73 1 T43 1 T63 2 T75 2
valid_sources[0x67] 58 1 T43 1 T42 4 T75 2
valid_sources[0x68] 64 1 T5 2 T43 2 T59 1
valid_sources[0x69] 97 1 T5 1 T43 2 T59 1
valid_sources[0x6a] 80 1 T59 5 T63 2 T65 1
valid_sources[0x6b] 82 1 T43 4 T42 3 T64 1
valid_sources[0x6c] 73 1 T61 1 T122 1 T43 2
valid_sources[0x6d] 153 1 T43 3 T42 1 T59 1
valid_sources[0x6e] 74 1 T42 1 T63 4 T64 1
valid_sources[0x6f] 77 1 T43 2 T42 1 T52 15
valid_sources[0x70] 109 1 T54 1 T43 2 T40 3
valid_sources[0x71] 143 1 T54 2 T43 1 T59 3
valid_sources[0x72] 89 1 T43 3 T41 3 T42 2
valid_sources[0x73] 104 1 T43 1 T59 5 T63 1
valid_sources[0x74] 45 1 T144 1 T43 5 T59 1
valid_sources[0x75] 81 1 T59 3 T63 1 T65 1
valid_sources[0x76] 53 1 T44 1 T43 1 T40 1
valid_sources[0x77] 304 1 T2 1 T141 1 T43 3
valid_sources[0x78] 50 1 T43 1 T40 3 T59 2
valid_sources[0x79] 69 1 T5 1 T129 1 T131 1
valid_sources[0x7a] 64 1 T61 2 T43 1 T42 1
valid_sources[0x7b] 89 1 T146 6 T40 4 T59 6
valid_sources[0x7c] 56 1 T43 1 T40 1 T59 4
valid_sources[0x7d] 58 1 T43 1 T40 1 T59 4
valid_sources[0x7e] 54 1 T147 2 T43 1 T40 1
valid_sources[0x7f] 65 1 T141 1 T43 3 T42 1
valid_sources[0x80] 55 1 T43 2 T59 5 T75 3



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 6698 1 T43 112 T40 23 T41 44
values[0x0] all_enables biggest_size 6904 1 T2 2 T5 4 T37 1
values[0x1] all_enables biggest_size 6589 1 T2 4 T5 1 T37 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%