Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	225256	1		T6	9		T7	37		T8	7
full_word	559724	1		T17	80		T6	1		T19	2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	784640	1		T17	80		T6	10		T19	2
auto[TlIntgErrCmd]	123	1		T40	7		T42	6		T65	4
auto[TlIntgErrData]	119	1		T40	6		T42	8		T65	8
auto[TlIntgErrBoth]	98	1		T40	7		T42	6		T65	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	449293	1		T17	80		T27	8		T18	80
auto[1]	335687	1		T6	10		T19	2		T7	47

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	176229	1		T27	6		T15	8		T20	10
auto[TlIntgErrNone]	partial	auto[1]	48722	1		T6	9		T7	37		T8	7
auto[TlIntgErrNone]	full_word	auto[0]	272924	1		T17	80		T27	2		T18	80
auto[TlIntgErrNone]	full_word	auto[1]	286765	1		T6	1		T19	2		T7	10
auto[TlIntgErrCmd]	partial	auto[0]	45	1		T40	3		T42	3		T65	2
auto[TlIntgErrCmd]	partial	auto[1]	67	1		T40	4		T42	3		T65	2
auto[TlIntgErrCmd]	full_word	auto[0]	6	1		T115	1		T116	1		T117	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1		T112	1		T116	2		T119	1
auto[TlIntgErrData]	partial	auto[0]	49	1		T40	1		T42	4		T65	3
auto[TlIntgErrData]	partial	auto[1]	53	1		T40	4		T42	2		T65	4
auto[TlIntgErrData]	full_word	auto[0]	9	1		T42	1		T65	1		T111	2
auto[TlIntgErrData]	full_word	auto[1]	8	1		T40	1		T42	1		T117	1
auto[TlIntgErrBoth]	partial	auto[0]	30	1		T40	2		T65	2		T106	3
auto[TlIntgErrBoth]	partial	auto[1]	61	1		T40	5		T42	6		T65	4
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T118	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1		T65	2		T112	1		T117	1