Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.35	87.88	61.70	87.54		57.14	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	25819027	15272	0	0
late_debug_enable_rd_A	25819027	1347	0	0
late_debug_enable_regwen_rd_A	25819027	3096	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25819027	15272	0	0
T40	31676	7	0	0
T41	209894	158	0	0
T42	93009	7	0	0
T43	6216	946	0	0
T52	297708	47	0	0
T53	752465	870	0	0
T59	17436	576	0	0
T63	19706	438	0	0
T64	7605	50	0	0
T65	36699	6	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25819027	1347	0	0
T63	19706	130	0	0
T69	9538	9	0	0
T76	19430	16	0	0
T85	10046	8	0	0
T88	26047	23	0	0
T89	9447	13	0	0
T91	8019	9	0	0
T93	23889	20	0	0
T94	26402	39	0	0
T105	9123	1	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25819027	3096	0	0
T63	19706	230	0	0
T69	9538	4	0	0
T75	335942	971	0	0
T76	19430	37	0	0
T85	10046	10	0	0
T88	26047	8	0	0
T91	8019	4	0	0
T93	23889	6	0	0
T94	26402	39	0	0
T106	57221	47	0	0