Line Coverage for Module :
prim_generic_clock_mux2
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Module :
prim_generic_clock_mux2
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Module :
prim_generic_clock_mux2
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
10895423 |
10894605 |
0 |
0 |
selKnown1 |
12438704 |
12437886 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10895423 |
10894605 |
0 |
0 |
T1 |
7234 |
7230 |
0 |
0 |
T2 |
312 |
308 |
0 |
0 |
T3 |
3898 |
3894 |
0 |
0 |
T4 |
358026 |
358022 |
0 |
0 |
T5 |
386 |
382 |
0 |
0 |
T12 |
0 |
8 |
0 |
0 |
T13 |
0 |
19 |
0 |
0 |
T17 |
364 |
360 |
0 |
0 |
T30 |
1248 |
1244 |
0 |
0 |
T31 |
0 |
68 |
0 |
0 |
T34 |
0 |
8 |
0 |
0 |
T35 |
0 |
40 |
0 |
0 |
T36 |
0 |
20 |
0 |
0 |
T37 |
340 |
336 |
0 |
0 |
T38 |
0 |
6 |
0 |
0 |
T39 |
388 |
384 |
0 |
0 |
T44 |
312 |
308 |
0 |
0 |
T48 |
0 |
40 |
0 |
0 |
T51 |
0 |
9 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
12438704 |
12437886 |
0 |
0 |
T1 |
19377 |
19373 |
0 |
0 |
T2 |
2265 |
2261 |
0 |
0 |
T3 |
9804 |
9800 |
0 |
0 |
T4 |
200688 |
200684 |
0 |
0 |
T5 |
1710 |
1706 |
0 |
0 |
T12 |
0 |
8 |
0 |
0 |
T13 |
0 |
12 |
0 |
0 |
T17 |
1968 |
1964 |
0 |
0 |
T30 |
2056 |
2052 |
0 |
0 |
T31 |
0 |
68 |
0 |
0 |
T35 |
0 |
40 |
0 |
0 |
T36 |
0 |
20 |
0 |
0 |
T37 |
1251 |
1247 |
0 |
0 |
T38 |
0 |
8 |
0 |
0 |
T39 |
1212 |
1208 |
0 |
0 |
T44 |
1378 |
1374 |
0 |
0 |
T48 |
0 |
40 |
0 |
0 |
T51 |
0 |
8 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
1506594 |
1506494 |
0 |
0 |
selKnown1 |
3049990 |
3049890 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1506594 |
1506494 |
0 |
0 |
T1 |
3596 |
3595 |
0 |
0 |
T2 |
155 |
154 |
0 |
0 |
T3 |
1948 |
1947 |
0 |
0 |
T4 |
178993 |
178992 |
0 |
0 |
T5 |
192 |
191 |
0 |
0 |
T17 |
181 |
180 |
0 |
0 |
T30 |
623 |
622 |
0 |
0 |
T37 |
169 |
168 |
0 |
0 |
T39 |
193 |
192 |
0 |
0 |
T44 |
155 |
154 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3049990 |
3049890 |
0 |
0 |
T1 |
15739 |
15738 |
0 |
0 |
T2 |
2108 |
2107 |
0 |
0 |
T3 |
7854 |
7853 |
0 |
0 |
T4 |
21657 |
21656 |
0 |
0 |
T5 |
1516 |
1515 |
0 |
0 |
T17 |
1785 |
1784 |
0 |
0 |
T30 |
1431 |
1430 |
0 |
0 |
T37 |
1080 |
1079 |
0 |
0 |
T39 |
1017 |
1016 |
0 |
0 |
T44 |
1221 |
1220 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
255 |
155 |
0 |
0 |
T1 |
21 |
20 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
21 |
20 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
0 |
6 |
0 |
0 |
T17 |
1 |
0 |
0 |
0 |
T30 |
1 |
0 |
0 |
0 |
T31 |
0 |
34 |
0 |
0 |
T35 |
0 |
20 |
0 |
0 |
T36 |
0 |
10 |
0 |
0 |
T37 |
1 |
0 |
0 |
0 |
T38 |
0 |
6 |
0 |
0 |
T39 |
1 |
0 |
0 |
0 |
T44 |
1 |
0 |
0 |
0 |
T48 |
0 |
20 |
0 |
0 |
T51 |
0 |
4 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
251 |
151 |
0 |
0 |
T1 |
21 |
20 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
19 |
18 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
0 |
6 |
0 |
0 |
T17 |
1 |
0 |
0 |
0 |
T30 |
1 |
0 |
0 |
0 |
T31 |
0 |
34 |
0 |
0 |
T35 |
0 |
20 |
0 |
0 |
T36 |
0 |
10 |
0 |
0 |
T37 |
1 |
0 |
0 |
0 |
T38 |
0 |
4 |
0 |
0 |
T39 |
1 |
0 |
0 |
0 |
T44 |
1 |
0 |
0 |
0 |
T48 |
0 |
20 |
0 |
0 |
T51 |
0 |
4 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
9386899 |
9386590 |
0 |
0 |
selKnown1 |
9386899 |
9386590 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9386899 |
9386590 |
0 |
0 |
T1 |
3596 |
3595 |
0 |
0 |
T2 |
155 |
154 |
0 |
0 |
T3 |
1948 |
1947 |
0 |
0 |
T4 |
178993 |
178992 |
0 |
0 |
T5 |
192 |
191 |
0 |
0 |
T17 |
181 |
180 |
0 |
0 |
T30 |
623 |
622 |
0 |
0 |
T37 |
169 |
168 |
0 |
0 |
T39 |
193 |
192 |
0 |
0 |
T44 |
155 |
154 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9386899 |
9386590 |
0 |
0 |
T1 |
3596 |
3595 |
0 |
0 |
T2 |
155 |
154 |
0 |
0 |
T3 |
1948 |
1947 |
0 |
0 |
T4 |
178993 |
178992 |
0 |
0 |
T5 |
192 |
191 |
0 |
0 |
T17 |
181 |
180 |
0 |
0 |
T30 |
623 |
622 |
0 |
0 |
T37 |
169 |
168 |
0 |
0 |
T39 |
193 |
192 |
0 |
0 |
T44 |
155 |
154 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
1675 |
1366 |
0 |
0 |
selKnown1 |
1564 |
1255 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1675 |
1366 |
0 |
0 |
T1 |
21 |
20 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
19 |
18 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
0 |
13 |
0 |
0 |
T17 |
1 |
0 |
0 |
0 |
T30 |
1 |
0 |
0 |
0 |
T31 |
0 |
34 |
0 |
0 |
T34 |
0 |
8 |
0 |
0 |
T35 |
0 |
20 |
0 |
0 |
T36 |
0 |
10 |
0 |
0 |
T37 |
1 |
0 |
0 |
0 |
T39 |
1 |
0 |
0 |
0 |
T44 |
1 |
0 |
0 |
0 |
T48 |
0 |
20 |
0 |
0 |
T51 |
0 |
5 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1564 |
1255 |
0 |
0 |
T1 |
21 |
20 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
19 |
18 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
0 |
6 |
0 |
0 |
T17 |
1 |
0 |
0 |
0 |
T30 |
1 |
0 |
0 |
0 |
T31 |
0 |
34 |
0 |
0 |
T35 |
0 |
20 |
0 |
0 |
T36 |
0 |
10 |
0 |
0 |
T37 |
1 |
0 |
0 |
0 |
T38 |
0 |
4 |
0 |
0 |
T39 |
1 |
0 |
0 |
0 |
T44 |
1 |
0 |
0 |
0 |
T48 |
0 |
20 |
0 |
0 |
T51 |
0 |
4 |
0 |
0 |