SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync_lc_hw_debug_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sync_lc_dft_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_en_sync_copies | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_pm_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
76.35 | 87.88 | 61.70 | 87.54 | 57.14 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
76.35 | 87.88 | 61.70 | 87.54 | 57.14 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
76.35 | 87.88 | 61.70 | 87.54 | 57.14 | 87.50 | dut |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
76.35 | 87.88 | 61.70 | 87.54 | 57.14 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
68.13 | 86.27 | 72.22 | 57.14 | 75.00 | 50.00 | u_tlul_lc_gate_sba |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
78.58 | 96.08 | 77.78 | 85.71 | 83.33 | 50.00 | u_tlul_lc_gate_rom |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 600 | 600 | 0 | 0 |
OutputsKnown_A | 18299940 | 18198540 | 0 | 0 |
gen_flops.OutputDelay_A | 9149970 | 9097011 | 0 | 900 |
gen_no_flops.OutputDelay_A | 9149970 | 9099270 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 600 | 600 | 0 | 0 |
T1 | 6 | 6 | 0 | 0 |
T2 | 6 | 6 | 0 | 0 |
T3 | 6 | 6 | 0 | 0 |
T4 | 6 | 6 | 0 | 0 |
T5 | 6 | 6 | 0 | 0 |
T17 | 6 | 6 | 0 | 0 |
T30 | 6 | 6 | 0 | 0 |
T37 | 6 | 6 | 0 | 0 |
T39 | 6 | 6 | 0 | 0 |
T44 | 6 | 6 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 18299940 | 18198540 | 0 | 0 |
T1 | 94434 | 85854 | 0 | 0 |
T2 | 12648 | 12300 | 0 | 0 |
T3 | 47124 | 46728 | 0 | 0 |
T4 | 129942 | 122292 | 0 | 0 |
T5 | 9096 | 8622 | 0 | 0 |
T17 | 10710 | 10272 | 0 | 0 |
T30 | 8586 | 8286 | 0 | 0 |
T37 | 6480 | 5982 | 0 | 0 |
T39 | 6102 | 5796 | 0 | 0 |
T44 | 7326 | 6990 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9149970 | 9097011 | 0 | 900 |
T1 | 47217 | 42738 | 0 | 9 |
T2 | 6324 | 6141 | 0 | 9 |
T3 | 23562 | 23355 | 0 | 9 |
T4 | 64971 | 60975 | 0 | 9 |
T5 | 4548 | 4302 | 0 | 9 |
T17 | 5355 | 5127 | 0 | 9 |
T30 | 4293 | 4134 | 0 | 9 |
T37 | 3240 | 2982 | 0 | 9 |
T39 | 3051 | 2889 | 0 | 9 |
T44 | 3663 | 3486 | 0 | 9 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9149970 | 9099270 | 0 | 0 |
T1 | 47217 | 42927 | 0 | 0 |
T2 | 6324 | 6150 | 0 | 0 |
T3 | 23562 | 23364 | 0 | 0 |
T4 | 64971 | 61146 | 0 | 0 |
T5 | 4548 | 4311 | 0 | 0 |
T17 | 5355 | 5136 | 0 | 0 |
T30 | 4293 | 4143 | 0 | 0 |
T37 | 3240 | 2991 | 0 | 0 |
T39 | 3051 | 2898 | 0 | 0 |
T44 | 3663 | 3495 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 100 | 100 | 0 | 0 |
OutputsKnown_A | 3049990 | 3033090 | 0 | 0 |
gen_flops.OutputDelay_A | 3049990 | 3032337 | 0 | 300 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 100 | 100 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
T37 | 1 | 1 | 0 | 0 |
T39 | 1 | 1 | 0 | 0 |
T44 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 3049990 | 3033090 | 0 | 0 |
T1 | 15739 | 14309 | 0 | 0 |
T2 | 2108 | 2050 | 0 | 0 |
T3 | 7854 | 7788 | 0 | 0 |
T4 | 21657 | 20382 | 0 | 0 |
T5 | 1516 | 1437 | 0 | 0 |
T17 | 1785 | 1712 | 0 | 0 |
T30 | 1431 | 1381 | 0 | 0 |
T37 | 1080 | 997 | 0 | 0 |
T39 | 1017 | 966 | 0 | 0 |
T44 | 1221 | 1165 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 3049990 | 3032337 | 0 | 300 |
T1 | 15739 | 14246 | 0 | 3 |
T2 | 2108 | 2047 | 0 | 3 |
T3 | 7854 | 7785 | 0 | 3 |
T4 | 21657 | 20325 | 0 | 3 |
T5 | 1516 | 1434 | 0 | 3 |
T17 | 1785 | 1709 | 0 | 3 |
T30 | 1431 | 1378 | 0 | 3 |
T37 | 1080 | 994 | 0 | 3 |
T39 | 1017 | 963 | 0 | 3 |
T44 | 1221 | 1162 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 100 | 100 | 0 | 0 |
OutputsKnown_A | 3049990 | 3033090 | 0 | 0 |
gen_flops.OutputDelay_A | 3049990 | 3032337 | 0 | 300 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 100 | 100 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
T37 | 1 | 1 | 0 | 0 |
T39 | 1 | 1 | 0 | 0 |
T44 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 3049990 | 3033090 | 0 | 0 |
T1 | 15739 | 14309 | 0 | 0 |
T2 | 2108 | 2050 | 0 | 0 |
T3 | 7854 | 7788 | 0 | 0 |
T4 | 21657 | 20382 | 0 | 0 |
T5 | 1516 | 1437 | 0 | 0 |
T17 | 1785 | 1712 | 0 | 0 |
T30 | 1431 | 1381 | 0 | 0 |
T37 | 1080 | 997 | 0 | 0 |
T39 | 1017 | 966 | 0 | 0 |
T44 | 1221 | 1165 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 3049990 | 3032337 | 0 | 300 |
T1 | 15739 | 14246 | 0 | 3 |
T2 | 2108 | 2047 | 0 | 3 |
T3 | 7854 | 7785 | 0 | 3 |
T4 | 21657 | 20325 | 0 | 3 |
T5 | 1516 | 1434 | 0 | 3 |
T17 | 1785 | 1709 | 0 | 3 |
T30 | 1431 | 1378 | 0 | 3 |
T37 | 1080 | 994 | 0 | 3 |
T39 | 1017 | 963 | 0 | 3 |
T44 | 1221 | 1162 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 100 | 100 | 0 | 0 |
OutputsKnown_A | 3049990 | 3033090 | 0 | 0 |
gen_no_flops.OutputDelay_A | 3049990 | 3033090 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 100 | 100 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
T37 | 1 | 1 | 0 | 0 |
T39 | 1 | 1 | 0 | 0 |
T44 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 3049990 | 3033090 | 0 | 0 |
T1 | 15739 | 14309 | 0 | 0 |
T2 | 2108 | 2050 | 0 | 0 |
T3 | 7854 | 7788 | 0 | 0 |
T4 | 21657 | 20382 | 0 | 0 |
T5 | 1516 | 1437 | 0 | 0 |
T17 | 1785 | 1712 | 0 | 0 |
T30 | 1431 | 1381 | 0 | 0 |
T37 | 1080 | 997 | 0 | 0 |
T39 | 1017 | 966 | 0 | 0 |
T44 | 1221 | 1165 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 3049990 | 3033090 | 0 | 0 |
T1 | 15739 | 14309 | 0 | 0 |
T2 | 2108 | 2050 | 0 | 0 |
T3 | 7854 | 7788 | 0 | 0 |
T4 | 21657 | 20382 | 0 | 0 |
T5 | 1516 | 1437 | 0 | 0 |
T17 | 1785 | 1712 | 0 | 0 |
T30 | 1431 | 1381 | 0 | 0 |
T37 | 1080 | 997 | 0 | 0 |
T39 | 1017 | 966 | 0 | 0 |
T44 | 1221 | 1165 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 100 | 100 | 0 | 0 |
OutputsKnown_A | 3049990 | 3033090 | 0 | 0 |
gen_flops.OutputDelay_A | 3049990 | 3032337 | 0 | 300 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 100 | 100 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
T37 | 1 | 1 | 0 | 0 |
T39 | 1 | 1 | 0 | 0 |
T44 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 3049990 | 3033090 | 0 | 0 |
T1 | 15739 | 14309 | 0 | 0 |
T2 | 2108 | 2050 | 0 | 0 |
T3 | 7854 | 7788 | 0 | 0 |
T4 | 21657 | 20382 | 0 | 0 |
T5 | 1516 | 1437 | 0 | 0 |
T17 | 1785 | 1712 | 0 | 0 |
T30 | 1431 | 1381 | 0 | 0 |
T37 | 1080 | 997 | 0 | 0 |
T39 | 1017 | 966 | 0 | 0 |
T44 | 1221 | 1165 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 3049990 | 3032337 | 0 | 300 |
T1 | 15739 | 14246 | 0 | 3 |
T2 | 2108 | 2047 | 0 | 3 |
T3 | 7854 | 7785 | 0 | 3 |
T4 | 21657 | 20325 | 0 | 3 |
T5 | 1516 | 1434 | 0 | 3 |
T17 | 1785 | 1709 | 0 | 3 |
T30 | 1431 | 1378 | 0 | 3 |
T37 | 1080 | 994 | 0 | 3 |
T39 | 1017 | 963 | 0 | 3 |
T44 | 1221 | 1162 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 100 | 100 | 0 | 0 |
OutputsKnown_A | 3049990 | 3033090 | 0 | 0 |
gen_no_flops.OutputDelay_A | 3049990 | 3033090 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 100 | 100 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
T37 | 1 | 1 | 0 | 0 |
T39 | 1 | 1 | 0 | 0 |
T44 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 3049990 | 3033090 | 0 | 0 |
T1 | 15739 | 14309 | 0 | 0 |
T2 | 2108 | 2050 | 0 | 0 |
T3 | 7854 | 7788 | 0 | 0 |
T4 | 21657 | 20382 | 0 | 0 |
T5 | 1516 | 1437 | 0 | 0 |
T17 | 1785 | 1712 | 0 | 0 |
T30 | 1431 | 1381 | 0 | 0 |
T37 | 1080 | 997 | 0 | 0 |
T39 | 1017 | 966 | 0 | 0 |
T44 | 1221 | 1165 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 3049990 | 3033090 | 0 | 0 |
T1 | 15739 | 14309 | 0 | 0 |
T2 | 2108 | 2050 | 0 | 0 |
T3 | 7854 | 7788 | 0 | 0 |
T4 | 21657 | 20382 | 0 | 0 |
T5 | 1516 | 1437 | 0 | 0 |
T17 | 1785 | 1712 | 0 | 0 |
T30 | 1431 | 1381 | 0 | 0 |
T37 | 1080 | 997 | 0 | 0 |
T39 | 1017 | 966 | 0 | 0 |
T44 | 1221 | 1165 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 100 | 100 | 0 | 0 |
OutputsKnown_A | 3049990 | 3033090 | 0 | 0 |
gen_no_flops.OutputDelay_A | 3049990 | 3033090 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 100 | 100 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
T37 | 1 | 1 | 0 | 0 |
T39 | 1 | 1 | 0 | 0 |
T44 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 3049990 | 3033090 | 0 | 0 |
T1 | 15739 | 14309 | 0 | 0 |
T2 | 2108 | 2050 | 0 | 0 |
T3 | 7854 | 7788 | 0 | 0 |
T4 | 21657 | 20382 | 0 | 0 |
T5 | 1516 | 1437 | 0 | 0 |
T17 | 1785 | 1712 | 0 | 0 |
T30 | 1431 | 1381 | 0 | 0 |
T37 | 1080 | 997 | 0 | 0 |
T39 | 1017 | 966 | 0 | 0 |
T44 | 1221 | 1165 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 3049990 | 3033090 | 0 | 0 |
T1 | 15739 | 14309 | 0 | 0 |
T2 | 2108 | 2050 | 0 | 0 |
T3 | 7854 | 7788 | 0 | 0 |
T4 | 21657 | 20382 | 0 | 0 |
T5 | 1516 | 1437 | 0 | 0 |
T17 | 1785 | 1712 | 0 | 0 |
T30 | 1431 | 1381 | 0 | 0 |
T37 | 1080 | 997 | 0 | 0 |
T39 | 1017 | 966 | 0 | 0 |
T44 | 1221 | 1165 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |