Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
78.32 93.71 78.85 87.05 73.08 82.50 98.42 34.62


Total test records in report: 304
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html
T261 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.2343538501 May 12 02:15:44 PM PDT 24 May 12 02:15:47 PM PDT 24 171340828 ps
T262 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2879205422 May 12 02:15:39 PM PDT 24 May 12 02:15:41 PM PDT 24 444242033 ps
T89 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2103877405 May 12 02:15:33 PM PDT 24 May 12 02:15:36 PM PDT 24 2458026148 ps
T263 /workspace/coverage/cover_reg_top/24.rv_dm_tap_fsm_rand_reset.2445085878 May 12 02:15:55 PM PDT 24 May 12 02:16:16 PM PDT 24 6000206967 ps
T264 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.889805422 May 12 02:15:47 PM PDT 24 May 12 02:15:51 PM PDT 24 947055076 ps
T265 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.129123340 May 12 02:15:42 PM PDT 24 May 12 02:15:46 PM PDT 24 826797541 ps
T266 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2116985534 May 12 02:15:14 PM PDT 24 May 12 02:15:17 PM PDT 24 167242628 ps
T267 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.2529761911 May 12 02:15:28 PM PDT 24 May 12 02:15:46 PM PDT 24 27936714850 ps
T268 /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.280126619 May 12 02:15:45 PM PDT 24 May 12 02:15:58 PM PDT 24 11652959691 ps
T269 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.1247536599 May 12 02:15:51 PM PDT 24 May 12 02:15:53 PM PDT 24 73059932 ps
T270 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.735898864 May 12 02:15:32 PM PDT 24 May 12 02:16:00 PM PDT 24 11406526590 ps
T271 /workspace/coverage/cover_reg_top/14.rv_dm_tap_fsm_rand_reset.827877684 May 12 02:15:47 PM PDT 24 May 12 02:16:01 PM PDT 24 15329648758 ps
T272 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.1283611995 May 12 02:15:31 PM PDT 24 May 12 02:15:32 PM PDT 24 241730807 ps
T121 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3199712519 May 12 02:15:41 PM PDT 24 May 12 02:16:01 PM PDT 24 2198722128 ps
T273 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.423693088 May 12 02:15:52 PM PDT 24 May 12 02:15:55 PM PDT 24 161806638 ps
T274 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.1470340789 May 12 02:15:47 PM PDT 24 May 12 02:15:50 PM PDT 24 103874884 ps
T275 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.2731093630 May 12 02:15:28 PM PDT 24 May 12 02:16:03 PM PDT 24 15170468804 ps
T276 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.3851829939 May 12 02:15:42 PM PDT 24 May 12 02:15:47 PM PDT 24 72842066 ps
T277 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.1542112481 May 12 02:15:44 PM PDT 24 May 12 02:15:48 PM PDT 24 222694761 ps
T102 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.739598393 May 12 02:15:27 PM PDT 24 May 12 02:15:29 PM PDT 24 57566835 ps
T103 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1710515247 May 12 02:15:48 PM PDT 24 May 12 02:15:53 PM PDT 24 278350067 ps
T278 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1716609155 May 12 02:15:36 PM PDT 24 May 12 02:15:40 PM PDT 24 4211372649 ps
T279 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.2096459363 May 12 02:15:44 PM PDT 24 May 12 02:15:52 PM PDT 24 434153434 ps
T280 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.1793049881 May 12 02:15:41 PM PDT 24 May 12 02:15:50 PM PDT 24 825791005 ps
T281 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1256330279 May 12 02:15:55 PM PDT 24 May 12 02:15:58 PM PDT 24 898519623 ps
T282 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.203656597 May 12 02:15:53 PM PDT 24 May 12 02:15:56 PM PDT 24 106508828 ps
T283 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.1522543444 May 12 02:15:53 PM PDT 24 May 12 02:15:57 PM PDT 24 748671175 ps
T284 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.852401951 May 12 02:15:50 PM PDT 24 May 12 02:15:55 PM PDT 24 437409802 ps
T285 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.1440275451 May 12 02:15:23 PM PDT 24 May 12 02:16:00 PM PDT 24 3324058024 ps
T286 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2479460434 May 12 02:15:48 PM PDT 24 May 12 02:16:09 PM PDT 24 1715920033 ps
T287 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.3689077374 May 12 02:15:31 PM PDT 24 May 12 02:15:32 PM PDT 24 27218011 ps
T288 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2014674748 May 12 02:15:44 PM PDT 24 May 12 02:15:46 PM PDT 24 104393683 ps
T289 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.748192483 May 12 02:15:15 PM PDT 24 May 12 02:15:32 PM PDT 24 20429300803 ps
T109 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.2613253257 May 12 02:15:54 PM PDT 24 May 12 02:15:57 PM PDT 24 313728482 ps
T290 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.2696727354 May 12 02:15:44 PM PDT 24 May 12 02:15:45 PM PDT 24 89673802 ps
T291 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.4010394355 May 12 02:15:34 PM PDT 24 May 12 02:15:36 PM PDT 24 208060183 ps
T292 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.3435857772 May 12 02:15:33 PM PDT 24 May 12 02:15:35 PM PDT 24 64364760 ps
T293 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2114127865 May 12 02:15:53 PM PDT 24 May 12 02:16:11 PM PDT 24 6254291278 ps
T294 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3769490210 May 12 02:15:33 PM PDT 24 May 12 02:15:52 PM PDT 24 1964049670 ps
T295 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.586183485 May 12 02:15:41 PM PDT 24 May 12 02:15:47 PM PDT 24 477823617 ps
T296 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.3370350954 May 12 02:15:41 PM PDT 24 May 12 02:15:46 PM PDT 24 321061775 ps
T110 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.3437835023 May 12 02:15:49 PM PDT 24 May 12 02:15:52 PM PDT 24 61833227 ps
T297 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.803790702 May 12 02:15:45 PM PDT 24 May 12 02:15:49 PM PDT 24 171694393 ps
T111 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.4016655018 May 12 02:15:36 PM PDT 24 May 12 02:16:48 PM PDT 24 8134267148 ps
T298 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.3983088319 May 12 02:15:40 PM PDT 24 May 12 02:15:42 PM PDT 24 25761357 ps
T299 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.1738947938 May 12 02:15:22 PM PDT 24 May 12 02:15:30 PM PDT 24 2546954085 ps
T300 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.2780804958 May 12 02:15:48 PM PDT 24 May 12 02:15:51 PM PDT 24 113244634 ps
T112 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.3760495987 May 12 02:15:34 PM PDT 24 May 12 02:16:31 PM PDT 24 2811583919 ps
T301 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3880438707 May 12 02:15:10 PM PDT 24 May 12 02:15:13 PM PDT 24 325574131 ps
T302 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2003111074 May 12 02:15:56 PM PDT 24 May 12 02:16:06 PM PDT 24 228707414 ps
T127 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.703170339 May 12 02:15:50 PM PDT 24 May 12 02:16:01 PM PDT 24 852352557 ps
T90 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.3746465735 May 12 02:15:31 PM PDT 24 May 12 02:15:34 PM PDT 24 3005163527 ps
T303 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.754535606 May 12 02:15:36 PM PDT 24 May 12 02:15:55 PM PDT 24 3063878178 ps
T304 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.3503979357 May 12 02:15:33 PM PDT 24 May 12 02:15:35 PM PDT 24 110888000 ps

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.4045414735
Short name T6
Test name
Test status
Simulation time 717434030 ps
CPU time 1.53 seconds
Started May 12 02:00:13 PM PDT 24
Finished May 12 02:00:15 PM PDT 24
Peak memory 205024 kb
Host smart-83697950-8462-4889-8eb7-b3c57480176b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045414735 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.4045414735
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.4165938089
Short name T1
Test name
Test status
Simulation time 30333417 ps
CPU time 0.71 seconds
Started May 12 02:01:28 PM PDT 24
Finished May 12 02:01:29 PM PDT 24
Peak memory 204744 kb
Host smart-86ef9351-2a33-44cf-9a5a-91a2426a19fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165938089 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.4165938089
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.905306155
Short name T34
Test name
Test status
Simulation time 3216551102 ps
CPU time 6.24 seconds
Started May 12 02:00:29 PM PDT 24
Finished May 12 02:00:36 PM PDT 24
Peak memory 221572 kb
Host smart-9fcb6279-7143-4245-aec3-5c5bddcb3069
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=905306155 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_tl
_access.905306155
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tap_fsm_rand_reset.2644643745
Short name T45
Test name
Test status
Simulation time 24977262818 ps
CPU time 30.73 seconds
Started May 12 02:15:50 PM PDT 24
Finished May 12 02:16:22 PM PDT 24
Peak memory 229564 kb
Host smart-f700ce74-ebb2-4c79-a626-92979122d0b0
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644643745 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rv_dm_tap_fsm_rand_reset.2644643745
Directory /workspace/18.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.512317845
Short name T20
Test name
Test status
Simulation time 151103966 ps
CPU time 0.95 seconds
Started May 12 02:00:20 PM PDT 24
Finished May 12 02:00:22 PM PDT 24
Peak memory 204720 kb
Host smart-ecad1eb1-1309-4163-88e9-5ed43b94f56d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512317845 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.512317845
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.3492791487
Short name T46
Test name
Test status
Simulation time 4730992909 ps
CPU time 19.59 seconds
Started May 12 02:15:47 PM PDT 24
Finished May 12 02:16:07 PM PDT 24
Peak memory 221424 kb
Host smart-a57cf6f8-7105-49b9-bbe1-acfe2842dcd3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492791487 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.3
492791487
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/31.rv_dm_stress_all.3122046784
Short name T12
Test name
Test status
Simulation time 3606002622 ps
CPU time 12.04 seconds
Started May 12 02:01:35 PM PDT 24
Finished May 12 02:01:47 PM PDT 24
Peak memory 205192 kb
Host smart-3afc48c7-27f0-4ab7-8431-06e12aeee72d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122046784 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.3122046784
Directory /workspace/31.rv_dm_stress_all/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.2306184270
Short name T35
Test name
Test status
Simulation time 502047705 ps
CPU time 2.21 seconds
Started May 12 02:01:01 PM PDT 24
Finished May 12 02:01:04 PM PDT 24
Peak memory 205052 kb
Host smart-0fd5a6d5-31de-4ee9-9ca5-15394b97f308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306184270 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.2306184270
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.2598337488
Short name T7
Test name
Test status
Simulation time 352065329 ps
CPU time 1.28 seconds
Started May 12 01:59:55 PM PDT 24
Finished May 12 01:59:56 PM PDT 24
Peak memory 204984 kb
Host smart-c1505867-77f5-4fc0-9e19-429e8ea85262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598337488 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.2598337488
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.3387189897
Short name T37
Test name
Test status
Simulation time 62814536 ps
CPU time 0.8 seconds
Started May 12 02:00:23 PM PDT 24
Finished May 12 02:00:24 PM PDT 24
Peak memory 204652 kb
Host smart-a533bd31-2fd8-4bb7-910a-37934b46fae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387189897 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.3387189897
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.2387866821
Short name T76
Test name
Test status
Simulation time 552899880 ps
CPU time 27.02 seconds
Started May 12 02:15:09 PM PDT 24
Finished May 12 02:15:36 PM PDT 24
Peak memory 204772 kb
Host smart-b980b3b3-cbc7-43b1-812b-00a83aca5151
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387866821 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.2387866821
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.87434528
Short name T4
Test name
Test status
Simulation time 504816226 ps
CPU time 1.01 seconds
Started May 12 02:00:14 PM PDT 24
Finished May 12 02:00:16 PM PDT 24
Peak memory 229160 kb
Host smart-6621ef17-b6c8-4adf-8cb8-f69560f95c83
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87434528 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.87434528
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.122860232
Short name T13
Test name
Test status
Simulation time 76771000 ps
CPU time 0.91 seconds
Started May 12 02:00:06 PM PDT 24
Finished May 12 02:00:07 PM PDT 24
Peak memory 204764 kb
Host smart-7a1a8f83-d8a4-4b06-9e80-083a3b1ba367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122860232 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.122860232
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2857391327
Short name T54
Test name
Test status
Simulation time 350117179 ps
CPU time 5.73 seconds
Started May 12 02:15:49 PM PDT 24
Finished May 12 02:15:55 PM PDT 24
Peak memory 213372 kb
Host smart-3023c1f5-c8f0-496e-adc2-395c8596e41a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857391327 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.2857391327
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.1278599246
Short name T85
Test name
Test status
Simulation time 3359427404 ps
CPU time 6.21 seconds
Started May 12 02:00:57 PM PDT 24
Finished May 12 02:01:03 PM PDT 24
Peak memory 213328 kb
Host smart-bbfeb999-8240-40d0-b46a-e0fa1fb2e730
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1278599246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.1278599246
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.3162281003
Short name T14
Test name
Test status
Simulation time 236903363 ps
CPU time 1.49 seconds
Started May 12 02:00:05 PM PDT 24
Finished May 12 02:00:07 PM PDT 24
Peak memory 204964 kb
Host smart-420f4d4a-5b75-4659-8842-1e1f5c41d157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162281003 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.3162281003
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.2824363463
Short name T17
Test name
Test status
Simulation time 83886536 ps
CPU time 0.81 seconds
Started May 12 02:00:06 PM PDT 24
Finished May 12 02:00:07 PM PDT 24
Peak memory 212960 kb
Host smart-76a1a5db-6c60-4d05-9b0a-94003516b5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824363463 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.2824363463
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.750921924
Short name T96
Test name
Test status
Simulation time 66233809 ps
CPU time 1.66 seconds
Started May 12 02:15:44 PM PDT 24
Finished May 12 02:15:46 PM PDT 24
Peak memory 213052 kb
Host smart-c2ccdee4-099b-463b-80ee-dc517ebd6e5e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750921924 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.750921924
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.3840829153
Short name T66
Test name
Test status
Simulation time 3369755186 ps
CPU time 18.85 seconds
Started May 12 02:15:36 PM PDT 24
Finished May 12 02:15:56 PM PDT 24
Peak memory 213228 kb
Host smart-31a55074-ae18-46d3-92f5-ee40b1224515
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840829153 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.3840829153
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3169312302
Short name T49
Test name
Test status
Simulation time 560920595 ps
CPU time 1.28 seconds
Started May 12 02:15:49 PM PDT 24
Finished May 12 02:15:52 PM PDT 24
Peak memory 204808 kb
Host smart-86d7ee87-439d-4c2a-a3ab-3e2bccd3fc1c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169312302 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
3169312302
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.238236456
Short name T28
Test name
Test status
Simulation time 141597874 ps
CPU time 0.85 seconds
Started May 12 02:00:08 PM PDT 24
Finished May 12 02:00:09 PM PDT 24
Peak memory 204736 kb
Host smart-8b198332-4806-43e1-9c1d-30eec39dec05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238236456 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.238236456
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.1835112713
Short name T178
Test name
Test status
Simulation time 92053258 ps
CPU time 0.73 seconds
Started May 12 02:15:45 PM PDT 24
Finished May 12 02:15:47 PM PDT 24
Peak memory 204604 kb
Host smart-c7b52cd4-a6d5-42af-a55c-35f6549870f0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835112713 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.
1835112713
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.703170339
Short name T127
Test name
Test status
Simulation time 852352557 ps
CPU time 9.58 seconds
Started May 12 02:15:50 PM PDT 24
Finished May 12 02:16:01 PM PDT 24
Peak memory 213132 kb
Host smart-c692d490-a77e-4ccd-b845-90da6e88e9ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703170339 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.703170339
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.1126026850
Short name T87
Test name
Test status
Simulation time 546982447 ps
CPU time 2.54 seconds
Started May 12 02:15:10 PM PDT 24
Finished May 12 02:15:14 PM PDT 24
Peak memory 204792 kb
Host smart-dfddbb58-c18f-4373-b0b3-0a542728ae5f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126026850 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.1126026850
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.635651381
Short name T72
Test name
Test status
Simulation time 315287372 ps
CPU time 3.55 seconds
Started May 12 02:15:10 PM PDT 24
Finished May 12 02:15:14 PM PDT 24
Peak memory 204892 kb
Host smart-ebfa998b-6129-494e-85ec-17fa84424f61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635651381 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_c
sr_outstanding.635651381
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.2320961024
Short name T56
Test name
Test status
Simulation time 65223908 ps
CPU time 0.69 seconds
Started May 12 02:01:37 PM PDT 24
Finished May 12 02:01:38 PM PDT 24
Peak memory 204728 kb
Host smart-975dad2b-8f40-425a-a00d-79718a85df87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320961024 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.2320961024
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.1617070598
Short name T9
Test name
Test status
Simulation time 280977313 ps
CPU time 1.58 seconds
Started May 12 02:00:03 PM PDT 24
Finished May 12 02:00:05 PM PDT 24
Peak memory 204652 kb
Host smart-0acf22cc-9258-466d-9725-cd27c57c4368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617070598 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.1617070598
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1067718638
Short name T124
Test name
Test status
Simulation time 95594815 ps
CPU time 4.14 seconds
Started May 12 02:15:45 PM PDT 24
Finished May 12 02:15:50 PM PDT 24
Peak memory 221448 kb
Host smart-bac302d6-9d57-48b7-9a15-119bb0f4631c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067718638 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.1067718638
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.1587927240
Short name T128
Test name
Test status
Simulation time 979373387 ps
CPU time 18.64 seconds
Started May 12 02:15:11 PM PDT 24
Finished May 12 02:15:31 PM PDT 24
Peak memory 221196 kb
Host smart-0b34cf7e-340c-430a-9653-b66f4513dc08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587927240 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.1587927240
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.520058362
Short name T247
Test name
Test status
Simulation time 18860538677 ps
CPU time 40.48 seconds
Started May 12 02:15:10 PM PDT 24
Finished May 12 02:15:52 PM PDT 24
Peak memory 204984 kb
Host smart-7aa43d02-26d8-4d0d-9592-423b093343e3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520058362 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.520058362
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.2286235388
Short name T104
Test name
Test status
Simulation time 714566150 ps
CPU time 1.57 seconds
Started May 12 02:15:10 PM PDT 24
Finished May 12 02:15:13 PM PDT 24
Peak memory 213104 kb
Host smart-10f034b2-c3da-4316-8a93-ad912fbba5ad
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286235388 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.2286235388
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.767600464
Short name T69
Test name
Test status
Simulation time 4762348619 ps
CPU time 7.91 seconds
Started May 12 02:15:12 PM PDT 24
Finished May 12 02:15:21 PM PDT 24
Peak memory 220108 kb
Host smart-98234d1b-69c8-426a-85cc-6c080037d981
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767600464 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.767600464
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.1660935249
Short name T75
Test name
Test status
Simulation time 97094421 ps
CPU time 2.4 seconds
Started May 12 02:15:11 PM PDT 24
Finished May 12 02:15:15 PM PDT 24
Peak memory 221224 kb
Host smart-6dd72343-d411-4799-b36c-ae2ff3371ba9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660935249 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.1660935249
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3753054569
Short name T213
Test name
Test status
Simulation time 5504703313 ps
CPU time 21.37 seconds
Started May 12 02:15:11 PM PDT 24
Finished May 12 02:15:33 PM PDT 24
Peak memory 204784 kb
Host smart-ca78fe32-2387-4258-9847-daed5e0026d7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753054569 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.3753054569
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3880438707
Short name T301
Test name
Test status
Simulation time 325574131 ps
CPU time 1.71 seconds
Started May 12 02:15:10 PM PDT 24
Finished May 12 02:15:13 PM PDT 24
Peak memory 204696 kb
Host smart-d316ecb3-f0f8-487d-8581-32f9ee8793aa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880438707 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.3
880438707
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3585006561
Short name T220
Test name
Test status
Simulation time 94260682 ps
CPU time 0.82 seconds
Started May 12 02:15:10 PM PDT 24
Finished May 12 02:15:12 PM PDT 24
Peak memory 204556 kb
Host smart-d16b3005-f8c9-4481-a5ee-0d7c792bb72d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585006561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.3585006561
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.2307043293
Short name T226
Test name
Test status
Simulation time 1680647816 ps
CPU time 3.59 seconds
Started May 12 02:15:11 PM PDT 24
Finished May 12 02:15:16 PM PDT 24
Peak memory 204804 kb
Host smart-49ffec0f-2a2b-4b0a-bcfb-65f55173698f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307043293 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.2307043293
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.1944051872
Short name T205
Test name
Test status
Simulation time 124458073 ps
CPU time 0.75 seconds
Started May 12 02:15:05 PM PDT 24
Finished May 12 02:15:07 PM PDT 24
Peak memory 204636 kb
Host smart-34d10a06-31e2-41aa-8668-06006a4db821
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944051872 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.1944051872
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.2075142945
Short name T209
Test name
Test status
Simulation time 44161545 ps
CPU time 0.67 seconds
Started May 12 02:15:06 PM PDT 24
Finished May 12 02:15:07 PM PDT 24
Peak memory 204564 kb
Host smart-efb5e2bc-fa22-4399-8af9-f0eeb2e178a0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075142945 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.2
075142945
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.2419347414
Short name T196
Test name
Test status
Simulation time 20980195 ps
CPU time 0.69 seconds
Started May 12 02:15:12 PM PDT 24
Finished May 12 02:15:14 PM PDT 24
Peak memory 204572 kb
Host smart-ba345cf9-d200-49cc-abc8-f5de229634af
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419347414 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.2419347414
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.2805986305
Short name T245
Test name
Test status
Simulation time 50171060 ps
CPU time 0.67 seconds
Started May 12 02:15:12 PM PDT 24
Finished May 12 02:15:14 PM PDT 24
Peak memory 204568 kb
Host smart-9f65a9c9-1f80-4084-b9dd-239636634487
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805986305 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.2805986305
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.2315674247
Short name T188
Test name
Test status
Simulation time 89925677 ps
CPU time 2.27 seconds
Started May 12 02:15:11 PM PDT 24
Finished May 12 02:15:15 PM PDT 24
Peak memory 213448 kb
Host smart-6d116d9d-b3df-46b1-889b-a54a30683981
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315674247 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.2315674247
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1426917599
Short name T225
Test name
Test status
Simulation time 9147719723 ps
CPU time 76.95 seconds
Started May 12 02:15:10 PM PDT 24
Finished May 12 02:16:28 PM PDT 24
Peak memory 217696 kb
Host smart-9151ade4-0dbe-45ed-9c04-f677161e63e2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426917599 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.1426917599
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.1440275451
Short name T285
Test name
Test status
Simulation time 3324058024 ps
CPU time 36.64 seconds
Started May 12 02:15:23 PM PDT 24
Finished May 12 02:16:00 PM PDT 24
Peak memory 213156 kb
Host smart-e2e0a066-6de7-4251-9b05-00d60a56c0dd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440275451 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.1440275451
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2116985534
Short name T266
Test name
Test status
Simulation time 167242628 ps
CPU time 2.28 seconds
Started May 12 02:15:14 PM PDT 24
Finished May 12 02:15:17 PM PDT 24
Peak memory 213168 kb
Host smart-21b68a8e-6b50-406b-acf3-dbe4eefecc4c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116985534 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.2116985534
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.1453972441
Short name T185
Test name
Test status
Simulation time 1873662443 ps
CPU time 5.12 seconds
Started May 12 02:15:22 PM PDT 24
Finished May 12 02:15:27 PM PDT 24
Peak memory 218560 kb
Host smart-82464e21-5974-4a3a-84fd-6d20e6278b93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453972441 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.1453972441
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.463370695
Short name T92
Test name
Test status
Simulation time 206554313 ps
CPU time 2.45 seconds
Started May 12 02:15:22 PM PDT 24
Finished May 12 02:15:25 PM PDT 24
Peak memory 213132 kb
Host smart-bdec5318-2c56-4dd1-bc1d-1ca8f1109008
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463370695 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.463370695
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.748192483
Short name T289
Test name
Test status
Simulation time 20429300803 ps
CPU time 17.07 seconds
Started May 12 02:15:15 PM PDT 24
Finished May 12 02:15:32 PM PDT 24
Peak memory 204932 kb
Host smart-356f3001-1398-48af-9718-63802c72d2b3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748192483 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr
_aliasing.748192483
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3857747422
Short name T180
Test name
Test status
Simulation time 18756709274 ps
CPU time 78.06 seconds
Started May 12 02:15:17 PM PDT 24
Finished May 12 02:16:35 PM PDT 24
Peak memory 204940 kb
Host smart-24bad321-85ae-4eff-acae-0f8c6c2401e8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857747422 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_bit_bash.3857747422
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.3063489048
Short name T88
Test name
Test status
Simulation time 527605703 ps
CPU time 1.73 seconds
Started May 12 02:15:11 PM PDT 24
Finished May 12 02:15:15 PM PDT 24
Peak memory 204844 kb
Host smart-37e018d1-1248-4294-905f-45c3a00d2733
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063489048 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.3063489048
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.2286438879
Short name T212
Test name
Test status
Simulation time 1205302850 ps
CPU time 1.85 seconds
Started May 12 02:15:12 PM PDT 24
Finished May 12 02:15:15 PM PDT 24
Peak memory 204620 kb
Host smart-37631d0d-6c5f-4734-b739-967caee33d61
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286438879 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.2
286438879
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2844670693
Short name T207
Test name
Test status
Simulation time 43657325 ps
CPU time 0.8 seconds
Started May 12 02:15:12 PM PDT 24
Finished May 12 02:15:14 PM PDT 24
Peak memory 204560 kb
Host smart-6299e0ab-6bd4-461c-8114-c05aea2c2e65
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844670693 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.2844670693
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.669748692
Short name T214
Test name
Test status
Simulation time 4426788007 ps
CPU time 13.91 seconds
Started May 12 02:15:11 PM PDT 24
Finished May 12 02:15:26 PM PDT 24
Peak memory 204740 kb
Host smart-b4b96b47-01d5-4771-b12a-76972621012e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669748692 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_bit_bash.669748692
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.4036654702
Short name T206
Test name
Test status
Simulation time 87398219 ps
CPU time 0.91 seconds
Started May 12 02:15:10 PM PDT 24
Finished May 12 02:15:11 PM PDT 24
Peak memory 204660 kb
Host smart-e25ce072-260c-455b-a1fb-04944934f921
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036654702 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.4036654702
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3980992672
Short name T239
Test name
Test status
Simulation time 47162272 ps
CPU time 0.7 seconds
Started May 12 02:15:10 PM PDT 24
Finished May 12 02:15:12 PM PDT 24
Peak memory 204544 kb
Host smart-ab5bcb68-57ef-4725-8f27-196d4777e457
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980992672 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.3
980992672
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3725507230
Short name T229
Test name
Test status
Simulation time 71605471 ps
CPU time 0.73 seconds
Started May 12 02:15:17 PM PDT 24
Finished May 12 02:15:18 PM PDT 24
Peak memory 204524 kb
Host smart-7f4871b4-48a8-451d-806b-4e3c9885faed
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725507230 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.3725507230
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.2622498367
Short name T182
Test name
Test status
Simulation time 51236176 ps
CPU time 0.69 seconds
Started May 12 02:15:16 PM PDT 24
Finished May 12 02:15:17 PM PDT 24
Peak memory 204556 kb
Host smart-e397640d-adea-4114-8dc1-eea7f6c48062
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622498367 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.2622498367
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.1738947938
Short name T299
Test name
Test status
Simulation time 2546954085 ps
CPU time 7.13 seconds
Started May 12 02:15:22 PM PDT 24
Finished May 12 02:15:30 PM PDT 24
Peak memory 204984 kb
Host smart-4e85edef-3298-4fba-bcd6-302ccdf9e0c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738947938 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_
csr_outstanding.1738947938
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.385220150
Short name T82
Test name
Test status
Simulation time 80411759 ps
CPU time 2.37 seconds
Started May 12 02:15:14 PM PDT 24
Finished May 12 02:15:17 PM PDT 24
Peak memory 213272 kb
Host smart-83dd7a3d-841b-4548-b11c-79b140c0d4b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385220150 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.385220150
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.1711395250
Short name T126
Test name
Test status
Simulation time 1096864834 ps
CPU time 19.94 seconds
Started May 12 02:15:16 PM PDT 24
Finished May 12 02:15:37 PM PDT 24
Peak memory 221160 kb
Host smart-d3e0181b-6243-4c28-99ed-a6c6cc75b095
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711395250 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.1711395250
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.724843088
Short name T258
Test name
Test status
Simulation time 3823000759 ps
CPU time 9.51 seconds
Started May 12 02:15:46 PM PDT 24
Finished May 12 02:15:57 PM PDT 24
Peak memory 217804 kb
Host smart-c69ed1a6-fb89-4298-a596-9acb8a229849
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724843088 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.724843088
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.2613253257
Short name T109
Test name
Test status
Simulation time 313728482 ps
CPU time 1.5 seconds
Started May 12 02:15:54 PM PDT 24
Finished May 12 02:15:57 PM PDT 24
Peak memory 213112 kb
Host smart-62b2a2fe-14de-4b06-9ae3-19786ca1f849
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613253257 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.2613253257
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.1320672449
Short name T241
Test name
Test status
Simulation time 331325438 ps
CPU time 1.01 seconds
Started May 12 02:15:40 PM PDT 24
Finished May 12 02:15:42 PM PDT 24
Peak memory 204796 kb
Host smart-9e8ff8a9-fb36-43e3-801b-f536e5778ce8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320672449 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
1320672449
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.2696727354
Short name T290
Test name
Test status
Simulation time 89673802 ps
CPU time 0.9 seconds
Started May 12 02:15:44 PM PDT 24
Finished May 12 02:15:45 PM PDT 24
Peak memory 204528 kb
Host smart-3ee39752-ce71-46c8-81ee-a002c8eed62c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696727354 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
2696727354
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.2096459363
Short name T279
Test name
Test status
Simulation time 434153434 ps
CPU time 6.51 seconds
Started May 12 02:15:44 PM PDT 24
Finished May 12 02:15:52 PM PDT 24
Peak memory 204888 kb
Host smart-cc70a6c8-c3f6-4a15-8364-51382c060caf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096459363 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same
_csr_outstanding.2096459363
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3778282725
Short name T120
Test name
Test status
Simulation time 132336693 ps
CPU time 2.36 seconds
Started May 12 02:15:46 PM PDT 24
Finished May 12 02:15:49 PM PDT 24
Peak memory 215252 kb
Host smart-efe7b277-ee19-45be-8c00-58efe21b496c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778282725 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.3778282725
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.3132169724
Short name T74
Test name
Test status
Simulation time 50099979 ps
CPU time 1.57 seconds
Started May 12 02:15:49 PM PDT 24
Finished May 12 02:15:51 PM PDT 24
Peak memory 213132 kb
Host smart-df88c1a9-2999-43ed-99cf-6f19628b3e91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132169724 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.3132169724
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3737098700
Short name T233
Test name
Test status
Simulation time 352119566 ps
CPU time 1.42 seconds
Started May 12 02:15:44 PM PDT 24
Finished May 12 02:15:46 PM PDT 24
Peak memory 204788 kb
Host smart-4952b77c-8324-4eab-bf5f-3a6fd10bd1b6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737098700 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
3737098700
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.651044515
Short name T101
Test name
Test status
Simulation time 148462635 ps
CPU time 3.53 seconds
Started May 12 02:15:50 PM PDT 24
Finished May 12 02:15:55 PM PDT 24
Peak memory 204928 kb
Host smart-0c783c80-1e83-4c1c-8d16-aae5213e211d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651044515 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same_
csr_outstanding.651044515
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.696111925
Short name T67
Test name
Test status
Simulation time 89797800 ps
CPU time 5.28 seconds
Started May 12 02:15:46 PM PDT 24
Finished May 12 02:15:52 PM PDT 24
Peak memory 213072 kb
Host smart-b4dcf7f5-76e5-4f94-bb40-d3807a638cd3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696111925 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.696111925
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.2304069804
Short name T132
Test name
Test status
Simulation time 995896554 ps
CPU time 10.4 seconds
Started May 12 02:15:46 PM PDT 24
Finished May 12 02:15:57 PM PDT 24
Peak memory 221140 kb
Host smart-3362a4b9-63bc-4a55-9adc-f7f16c7264be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304069804 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.2
304069804
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.3372672823
Short name T240
Test name
Test status
Simulation time 293707018 ps
CPU time 2.3 seconds
Started May 12 02:15:45 PM PDT 24
Finished May 12 02:15:48 PM PDT 24
Peak memory 216784 kb
Host smart-948e0f04-8c2f-4df4-8a2a-c1020063010e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372672823 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.3372672823
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.2780804958
Short name T300
Test name
Test status
Simulation time 113244634 ps
CPU time 1.61 seconds
Started May 12 02:15:48 PM PDT 24
Finished May 12 02:15:51 PM PDT 24
Peak memory 213016 kb
Host smart-4a8463b7-b1d9-4e7b-87d4-24679c7ed6ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780804958 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.2780804958
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1038872049
Short name T184
Test name
Test status
Simulation time 836764326 ps
CPU time 3.3 seconds
Started May 12 02:15:54 PM PDT 24
Finished May 12 02:15:59 PM PDT 24
Peak memory 204808 kb
Host smart-8949105e-ef52-4e42-b995-05f3c71b77c9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038872049 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
1038872049
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.2221457884
Short name T51
Test name
Test status
Simulation time 50423804 ps
CPU time 0.73 seconds
Started May 12 02:15:55 PM PDT 24
Finished May 12 02:15:57 PM PDT 24
Peak memory 204572 kb
Host smart-36e58a1e-c3f8-483f-b14a-e38b559a0088
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221457884 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
2221457884
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1710515247
Short name T103
Test name
Test status
Simulation time 278350067 ps
CPU time 3.73 seconds
Started May 12 02:15:48 PM PDT 24
Finished May 12 02:15:53 PM PDT 24
Peak memory 204820 kb
Host smart-6f0727ef-5f42-4023-ac2a-d398ab67083f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710515247 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.1710515247
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.3198646508
Short name T64
Test name
Test status
Simulation time 201256520 ps
CPU time 3.02 seconds
Started May 12 02:15:44 PM PDT 24
Finished May 12 02:15:48 PM PDT 24
Peak memory 213180 kb
Host smart-c7da1158-cfdb-4657-b75c-a55bd0f65c03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198646508 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.3198646508
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2424805063
Short name T191
Test name
Test status
Simulation time 718010004 ps
CPU time 10.93 seconds
Started May 12 02:15:48 PM PDT 24
Finished May 12 02:16:00 PM PDT 24
Peak memory 221208 kb
Host smart-2e6500c0-b0cf-4aae-93af-885cb0e0a4eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424805063 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.2
424805063
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.773499210
Short name T218
Test name
Test status
Simulation time 478764085 ps
CPU time 4.4 seconds
Started May 12 02:15:45 PM PDT 24
Finished May 12 02:15:50 PM PDT 24
Peak memory 218796 kb
Host smart-16992761-ef10-440f-8e44-915241cc1a71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773499210 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.773499210
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.4155513106
Short name T98
Test name
Test status
Simulation time 49430816 ps
CPU time 1.54 seconds
Started May 12 02:15:46 PM PDT 24
Finished May 12 02:15:48 PM PDT 24
Peak memory 213076 kb
Host smart-2fd97a20-99ee-44c7-9e05-b94224e85903
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155513106 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.4155513106
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.4008701033
Short name T236
Test name
Test status
Simulation time 373606390 ps
CPU time 1.13 seconds
Started May 12 02:15:48 PM PDT 24
Finished May 12 02:15:50 PM PDT 24
Peak memory 204772 kb
Host smart-ad517eaf-5dbe-499a-a5a1-6f012ce87c18
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008701033 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
4008701033
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1098694115
Short name T204
Test name
Test status
Simulation time 140667016 ps
CPU time 0.83 seconds
Started May 12 02:15:55 PM PDT 24
Finished May 12 02:15:57 PM PDT 24
Peak memory 204572 kb
Host smart-dad34237-c707-4ac8-b9e4-c97f610f2919
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098694115 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
1098694115
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.1798931012
Short name T100
Test name
Test status
Simulation time 534042288 ps
CPU time 4.19 seconds
Started May 12 02:15:55 PM PDT 24
Finished May 12 02:16:00 PM PDT 24
Peak memory 204896 kb
Host smart-90050d84-fad6-4da1-901f-52cf1ef84833
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798931012 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.1798931012
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tap_fsm_rand_reset.3760473012
Short name T210
Test name
Test status
Simulation time 8644544392 ps
CPU time 10.08 seconds
Started May 12 02:15:50 PM PDT 24
Finished May 12 02:16:01 PM PDT 24
Peak memory 218672 kb
Host smart-586d3097-b6da-4731-bdb9-bdcf37be3f6d
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760473012 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rv_dm_tap_fsm_rand_reset.3760473012
Directory /workspace/13.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.1470340789
Short name T274
Test name
Test status
Simulation time 103874884 ps
CPU time 1.93 seconds
Started May 12 02:15:47 PM PDT 24
Finished May 12 02:15:50 PM PDT 24
Peak memory 213216 kb
Host smart-6e52a285-c6d7-48b0-b9f2-3c2d3d4d5718
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470340789 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.1470340789
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.4174111494
Short name T68
Test name
Test status
Simulation time 1760572542 ps
CPU time 16.16 seconds
Started May 12 02:15:49 PM PDT 24
Finished May 12 02:16:06 PM PDT 24
Peak memory 213132 kb
Host smart-d2ce42b3-2ac5-4d4c-aaf5-eb33fac4c209
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174111494 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.4
174111494
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.4003317006
Short name T243
Test name
Test status
Simulation time 1227492248 ps
CPU time 3.71 seconds
Started May 12 02:15:46 PM PDT 24
Finished May 12 02:15:50 PM PDT 24
Peak memory 217864 kb
Host smart-a96a8def-c01c-4d1a-b6c0-84562841a281
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003317006 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.4003317006
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.1542112481
Short name T277
Test name
Test status
Simulation time 222694761 ps
CPU time 2.38 seconds
Started May 12 02:15:44 PM PDT 24
Finished May 12 02:15:48 PM PDT 24
Peak memory 218716 kb
Host smart-405aaab7-d9bc-4b29-93a6-cd356fe94127
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542112481 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.1542112481
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1256330279
Short name T281
Test name
Test status
Simulation time 898519623 ps
CPU time 2.47 seconds
Started May 12 02:15:55 PM PDT 24
Finished May 12 02:15:58 PM PDT 24
Peak memory 204756 kb
Host smart-5c29f7e6-f9e3-440c-8abd-764dd80f3f2d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256330279 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
1256330279
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.1641300421
Short name T217
Test name
Test status
Simulation time 161349130 ps
CPU time 0.72 seconds
Started May 12 02:15:46 PM PDT 24
Finished May 12 02:15:47 PM PDT 24
Peak memory 204792 kb
Host smart-e9413a81-b40e-4198-a051-4a964e79cd84
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641300421 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
1641300421
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.4129224815
Short name T73
Test name
Test status
Simulation time 1843288771 ps
CPU time 7.23 seconds
Started May 12 02:15:48 PM PDT 24
Finished May 12 02:15:56 PM PDT 24
Peak memory 204828 kb
Host smart-849ca920-761c-49a8-a082-f4887a49c3ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129224815 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.4129224815
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tap_fsm_rand_reset.827877684
Short name T271
Test name
Test status
Simulation time 15329648758 ps
CPU time 12.46 seconds
Started May 12 02:15:47 PM PDT 24
Finished May 12 02:16:01 PM PDT 24
Peak memory 217160 kb
Host smart-d9fae073-9791-423d-9466-371406f80254
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827877684 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.rv_dm_tap_fsm_rand_reset.827877684
Directory /workspace/14.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.803790702
Short name T297
Test name
Test status
Simulation time 171694393 ps
CPU time 3.84 seconds
Started May 12 02:15:45 PM PDT 24
Finished May 12 02:15:49 PM PDT 24
Peak memory 213136 kb
Host smart-bd915218-68ab-4235-81b7-00b5d5a424e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803790702 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.803790702
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1940808683
Short name T130
Test name
Test status
Simulation time 1094544661 ps
CPU time 18.62 seconds
Started May 12 02:15:50 PM PDT 24
Finished May 12 02:16:10 PM PDT 24
Peak memory 221280 kb
Host smart-949172cd-9848-4064-8263-17e55ecc8a16
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940808683 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.1
940808683
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1592063615
Short name T118
Test name
Test status
Simulation time 609010685 ps
CPU time 4.69 seconds
Started May 12 02:15:50 PM PDT 24
Finished May 12 02:15:56 PM PDT 24
Peak memory 221156 kb
Host smart-71d70a13-badd-4164-a4e5-cd6b39db08e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592063615 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.1592063615
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.283765493
Short name T246
Test name
Test status
Simulation time 66753017 ps
CPU time 1.63 seconds
Started May 12 02:15:50 PM PDT 24
Finished May 12 02:15:53 PM PDT 24
Peak memory 213176 kb
Host smart-fa3ca6cf-4b00-4732-a109-d2b2e5a29c04
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283765493 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.283765493
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.730015142
Short name T52
Test name
Test status
Simulation time 70477939 ps
CPU time 0.77 seconds
Started May 12 02:15:46 PM PDT 24
Finished May 12 02:15:48 PM PDT 24
Peak memory 204604 kb
Host smart-55d08af2-db46-4aaf-9bf0-f6a154e0b25b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730015142 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.730015142
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.2945488408
Short name T113
Test name
Test status
Simulation time 425856183 ps
CPU time 4.13 seconds
Started May 12 02:15:49 PM PDT 24
Finished May 12 02:15:55 PM PDT 24
Peak memory 204840 kb
Host smart-61f87885-0eb0-4902-b30f-8584f3e61371
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945488408 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.2945488408
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.423693088
Short name T273
Test name
Test status
Simulation time 161806638 ps
CPU time 2.64 seconds
Started May 12 02:15:52 PM PDT 24
Finished May 12 02:15:55 PM PDT 24
Peak memory 213060 kb
Host smart-ac010967-11c7-42f4-b5df-96138c36b133
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423693088 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.423693088
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2479460434
Short name T286
Test name
Test status
Simulation time 1715920033 ps
CPU time 19.91 seconds
Started May 12 02:15:48 PM PDT 24
Finished May 12 02:16:09 PM PDT 24
Peak memory 213068 kb
Host smart-5240951e-3cf3-4bbb-8770-555215863378
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479460434 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.2
479460434
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.3885113456
Short name T202
Test name
Test status
Simulation time 641905524 ps
CPU time 4.5 seconds
Started May 12 02:15:49 PM PDT 24
Finished May 12 02:15:55 PM PDT 24
Peak memory 218448 kb
Host smart-6c5d92f3-267d-4473-9ff0-0d376dabaf84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885113456 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.3885113456
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.3437835023
Short name T110
Test name
Test status
Simulation time 61833227 ps
CPU time 1.55 seconds
Started May 12 02:15:49 PM PDT 24
Finished May 12 02:15:52 PM PDT 24
Peak memory 213112 kb
Host smart-f4fdf543-90cf-4cb7-b5db-dbfeaf5a21d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437835023 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.3437835023
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.3775719640
Short name T250
Test name
Test status
Simulation time 840645395 ps
CPU time 3.01 seconds
Started May 12 02:15:50 PM PDT 24
Finished May 12 02:15:54 PM PDT 24
Peak memory 204816 kb
Host smart-03c059ff-d8b3-4a84-9900-360e2dedbcc2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775719640 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
3775719640
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3551454321
Short name T200
Test name
Test status
Simulation time 81033358 ps
CPU time 0.68 seconds
Started May 12 02:15:50 PM PDT 24
Finished May 12 02:15:52 PM PDT 24
Peak memory 204572 kb
Host smart-1dd5e07d-c3f3-4543-a696-0d961888ec96
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551454321 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
3551454321
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.852401951
Short name T284
Test name
Test status
Simulation time 437409802 ps
CPU time 4.08 seconds
Started May 12 02:15:50 PM PDT 24
Finished May 12 02:15:55 PM PDT 24
Peak memory 204864 kb
Host smart-8f75f639-59e0-4674-a603-73cab6996860
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852401951 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same_
csr_outstanding.852401951
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.203656597
Short name T282
Test name
Test status
Simulation time 106508828 ps
CPU time 1.88 seconds
Started May 12 02:15:53 PM PDT 24
Finished May 12 02:15:56 PM PDT 24
Peak memory 213180 kb
Host smart-3dc770b6-5e54-4961-9778-41b5e503ec1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203656597 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.203656597
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.4041426587
Short name T259
Test name
Test status
Simulation time 996103655 ps
CPU time 17.51 seconds
Started May 12 02:15:50 PM PDT 24
Finished May 12 02:16:09 PM PDT 24
Peak memory 213068 kb
Host smart-33269d41-d32a-4df4-84c4-b178154abcc1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041426587 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.4
041426587
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.1931941507
Short name T221
Test name
Test status
Simulation time 4373377274 ps
CPU time 4.9 seconds
Started May 12 02:15:53 PM PDT 24
Finished May 12 02:15:59 PM PDT 24
Peak memory 218496 kb
Host smart-499003cb-3bae-4a7d-87be-b91b704b68d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931941507 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.1931941507
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.4136837632
Short name T106
Test name
Test status
Simulation time 426947833 ps
CPU time 2.47 seconds
Started May 12 02:15:50 PM PDT 24
Finished May 12 02:15:54 PM PDT 24
Peak memory 213176 kb
Host smart-7a73af8c-e307-489c-9f49-4f4191eb8269
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136837632 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.4136837632
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.198392561
Short name T183
Test name
Test status
Simulation time 611165226 ps
CPU time 1.46 seconds
Started May 12 02:15:50 PM PDT 24
Finished May 12 02:15:53 PM PDT 24
Peak memory 204736 kb
Host smart-50581ed4-0784-4699-a65d-06a162f97d2e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198392561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.198392561
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.1247536599
Short name T269
Test name
Test status
Simulation time 73059932 ps
CPU time 0.8 seconds
Started May 12 02:15:51 PM PDT 24
Finished May 12 02:15:53 PM PDT 24
Peak memory 204628 kb
Host smart-df50c4a9-0735-4026-875d-4eb4ac665744
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247536599 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
1247536599
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.150363578
Short name T79
Test name
Test status
Simulation time 203861114 ps
CPU time 3.73 seconds
Started May 12 02:15:56 PM PDT 24
Finished May 12 02:16:00 PM PDT 24
Peak memory 204860 kb
Host smart-b11177d1-aa03-4edc-b7e1-ae401ee0d6ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150363578 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same_
csr_outstanding.150363578
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2114127865
Short name T293
Test name
Test status
Simulation time 6254291278 ps
CPU time 16.26 seconds
Started May 12 02:15:53 PM PDT 24
Finished May 12 02:16:11 PM PDT 24
Peak memory 215776 kb
Host smart-5d6df487-b60d-43f3-9b28-7e56f2157164
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114127865 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.2
114127865
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.410529804
Short name T63
Test name
Test status
Simulation time 4686469736 ps
CPU time 5.56 seconds
Started May 12 02:15:51 PM PDT 24
Finished May 12 02:15:58 PM PDT 24
Peak memory 219104 kb
Host smart-20b9e37a-d331-4587-b896-861e8acb9af0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410529804 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.410529804
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.1522543444
Short name T283
Test name
Test status
Simulation time 748671175 ps
CPU time 2.31 seconds
Started May 12 02:15:53 PM PDT 24
Finished May 12 02:15:57 PM PDT 24
Peak memory 213048 kb
Host smart-8e98ecaa-293a-4d04-8f70-5a55cec202e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522543444 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.1522543444
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2713036276
Short name T193
Test name
Test status
Simulation time 251309388 ps
CPU time 1.15 seconds
Started May 12 02:15:51 PM PDT 24
Finished May 12 02:15:53 PM PDT 24
Peak memory 204868 kb
Host smart-dd9a39fe-5fb3-48ce-b09f-47a495cfba02
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713036276 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
2713036276
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.3132062836
Short name T194
Test name
Test status
Simulation time 102703922 ps
CPU time 0.86 seconds
Started May 12 02:15:49 PM PDT 24
Finished May 12 02:15:50 PM PDT 24
Peak memory 204596 kb
Host smart-3960e58d-0cc0-49c6-8492-9f38ea1fc1fd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132062836 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
3132062836
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.4126710727
Short name T78
Test name
Test status
Simulation time 78388285 ps
CPU time 3.54 seconds
Started May 12 02:15:50 PM PDT 24
Finished May 12 02:15:55 PM PDT 24
Peak memory 204924 kb
Host smart-f566e8f1-67a0-4108-8143-f203c1816e7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126710727 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.4126710727
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.3050149173
Short name T224
Test name
Test status
Simulation time 3290205896 ps
CPU time 4.84 seconds
Started May 12 02:15:53 PM PDT 24
Finished May 12 02:15:59 PM PDT 24
Peak memory 213252 kb
Host smart-2253b210-d0bb-46ad-9250-d84a29010ee2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050149173 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.3050149173
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.1713435221
Short name T131
Test name
Test status
Simulation time 1166559375 ps
CPU time 20.14 seconds
Started May 12 02:15:53 PM PDT 24
Finished May 12 02:16:14 PM PDT 24
Peak memory 221508 kb
Host smart-5f8a3a17-3158-4bb4-9d23-58a7e125d669
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713435221 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.1
713435221
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3066304036
Short name T260
Test name
Test status
Simulation time 119459886 ps
CPU time 2.5 seconds
Started May 12 02:15:53 PM PDT 24
Finished May 12 02:15:57 PM PDT 24
Peak memory 221032 kb
Host smart-b437f707-6102-4cb0-aac5-33b79a81365b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066304036 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.3066304036
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.2660718702
Short name T93
Test name
Test status
Simulation time 1148002555 ps
CPU time 2.57 seconds
Started May 12 02:15:54 PM PDT 24
Finished May 12 02:15:58 PM PDT 24
Peak memory 218404 kb
Host smart-761875db-e180-40ac-b53e-4e3ba2645add
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660718702 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.2660718702
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.889805422
Short name T264
Test name
Test status
Simulation time 947055076 ps
CPU time 2.38 seconds
Started May 12 02:15:47 PM PDT 24
Finished May 12 02:15:51 PM PDT 24
Peak memory 204784 kb
Host smart-89412d9c-2202-48c3-a040-252889ea7967
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889805422 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.889805422
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.3982737152
Short name T189
Test name
Test status
Simulation time 42195739 ps
CPU time 0.79 seconds
Started May 12 02:15:53 PM PDT 24
Finished May 12 02:15:55 PM PDT 24
Peak memory 204560 kb
Host smart-5a1650e7-c991-4701-a4a6-3a4e4492297b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982737152 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
3982737152
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.2999795663
Short name T71
Test name
Test status
Simulation time 1840984483 ps
CPU time 6.69 seconds
Started May 12 02:15:54 PM PDT 24
Finished May 12 02:16:02 PM PDT 24
Peak memory 204948 kb
Host smart-bfe71539-de07-4663-a8eb-7db28de8c304
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999795663 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.2999795663
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.1561520551
Short name T242
Test name
Test status
Simulation time 73641628 ps
CPU time 5.15 seconds
Started May 12 02:15:53 PM PDT 24
Finished May 12 02:15:59 PM PDT 24
Peak memory 213376 kb
Host smart-e0c24758-557b-48a6-a9f9-e1bd6dc1186a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561520551 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.1561520551
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2003111074
Short name T302
Test name
Test status
Simulation time 228707414 ps
CPU time 8.66 seconds
Started May 12 02:15:56 PM PDT 24
Finished May 12 02:16:06 PM PDT 24
Peak memory 221296 kb
Host smart-4eb174e4-1c44-4b5d-9e96-68cf4bc0fb07
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003111074 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.2
003111074
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.1627042407
Short name T77
Test name
Test status
Simulation time 1134162950 ps
CPU time 26.85 seconds
Started May 12 02:15:23 PM PDT 24
Finished May 12 02:15:50 PM PDT 24
Peak memory 204896 kb
Host smart-fb0e6316-f9b0-4e08-a3c4-ddf277aca6d2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627042407 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.1627042407
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2647267025
Short name T186
Test name
Test status
Simulation time 13242708654 ps
CPU time 36.43 seconds
Started May 12 02:15:28 PM PDT 24
Finished May 12 02:16:05 PM PDT 24
Peak memory 204680 kb
Host smart-fe57e0ff-5b41-430b-8686-be7edc1f5c34
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647267025 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.2647267025
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.739598393
Short name T102
Test name
Test status
Simulation time 57566835 ps
CPU time 1.72 seconds
Started May 12 02:15:27 PM PDT 24
Finished May 12 02:15:29 PM PDT 24
Peak memory 213068 kb
Host smart-09fe56db-c243-4a64-bced-bda45a66df19
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739598393 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.739598393
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.1855952373
Short name T187
Test name
Test status
Simulation time 2039958195 ps
CPU time 4.31 seconds
Started May 12 02:15:30 PM PDT 24
Finished May 12 02:15:35 PM PDT 24
Peak memory 217652 kb
Host smart-bfad9bbf-b93c-4c48-af8f-c76f8ec1ea52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855952373 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.1855952373
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.2634249173
Short name T107
Test name
Test status
Simulation time 44590867 ps
CPU time 2.1 seconds
Started May 12 02:15:29 PM PDT 24
Finished May 12 02:15:32 PM PDT 24
Peak memory 213124 kb
Host smart-e9f8d6ca-8327-404f-b57d-364925c55280
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634249173 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.2634249173
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2916396659
Short name T244
Test name
Test status
Simulation time 13552894148 ps
CPU time 8.26 seconds
Started May 12 02:15:29 PM PDT 24
Finished May 12 02:15:38 PM PDT 24
Peak memory 204876 kb
Host smart-5dc24b7b-31c5-47c4-afa4-94b69566142c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916396659 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.2916396659
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.2731093630
Short name T275
Test name
Test status
Simulation time 15170468804 ps
CPU time 34.15 seconds
Started May 12 02:15:28 PM PDT 24
Finished May 12 02:16:03 PM PDT 24
Peak memory 204604 kb
Host smart-c6b1f831-5132-4723-a461-45b06b5da10f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731093630 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_bit_bash.2731093630
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.3746465735
Short name T90
Test name
Test status
Simulation time 3005163527 ps
CPU time 2.47 seconds
Started May 12 02:15:31 PM PDT 24
Finished May 12 02:15:34 PM PDT 24
Peak memory 204848 kb
Host smart-b4d3e3ae-f4d5-43eb-a889-046097281bc4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746465735 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.3746465735
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1500230857
Short name T173
Test name
Test status
Simulation time 874960635 ps
CPU time 1.49 seconds
Started May 12 02:15:27 PM PDT 24
Finished May 12 02:15:29 PM PDT 24
Peak memory 204696 kb
Host smart-7fb30e4f-d992-469a-9c66-3064d9747656
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500230857 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.1
500230857
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.1122128127
Short name T50
Test name
Test status
Simulation time 159619054 ps
CPU time 0.8 seconds
Started May 12 02:15:30 PM PDT 24
Finished May 12 02:15:31 PM PDT 24
Peak memory 204616 kb
Host smart-6ded2650-b5eb-4522-8a57-9c0b09fdffd3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122128127 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_aliasing.1122128127
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.2140880856
Short name T231
Test name
Test status
Simulation time 1378498389 ps
CPU time 2.53 seconds
Started May 12 02:15:31 PM PDT 24
Finished May 12 02:15:34 PM PDT 24
Peak memory 204724 kb
Host smart-339b7e40-7a12-440b-8976-c4118790043f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140880856 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.2140880856
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.942662613
Short name T201
Test name
Test status
Simulation time 441515992 ps
CPU time 0.76 seconds
Started May 12 02:15:26 PM PDT 24
Finished May 12 02:15:27 PM PDT 24
Peak memory 204600 kb
Host smart-bda57e2e-1418-459f-a056-536394a24397
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942662613 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_hw_reset.942662613
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.677474437
Short name T222
Test name
Test status
Simulation time 59925870 ps
CPU time 0.87 seconds
Started May 12 02:15:31 PM PDT 24
Finished May 12 02:15:32 PM PDT 24
Peak memory 204612 kb
Host smart-9e7d42c3-0ad5-486b-aa68-ffe5119a0ada
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677474437 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.677474437
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.3689077374
Short name T287
Test name
Test status
Simulation time 27218011 ps
CPU time 0.78 seconds
Started May 12 02:15:31 PM PDT 24
Finished May 12 02:15:32 PM PDT 24
Peak memory 204592 kb
Host smart-f8ec7995-4b22-4419-bbdf-373038fa419e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689077374 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.3689077374
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.2897971869
Short name T177
Test name
Test status
Simulation time 47048322 ps
CPU time 0.7 seconds
Started May 12 02:15:31 PM PDT 24
Finished May 12 02:15:32 PM PDT 24
Peak memory 204604 kb
Host smart-d9917469-7487-4b73-bf60-56c356b8c7d5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897971869 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.2897971869
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.1234866548
Short name T254
Test name
Test status
Simulation time 286187669 ps
CPU time 4.41 seconds
Started May 12 02:15:24 PM PDT 24
Finished May 12 02:15:29 PM PDT 24
Peak memory 204940 kb
Host smart-f0d17242-a911-4364-82e6-6830e83e7eba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234866548 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.1234866548
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.3094245226
Short name T133
Test name
Test status
Simulation time 8110569648 ps
CPU time 15.89 seconds
Started May 12 02:15:28 PM PDT 24
Finished May 12 02:15:44 PM PDT 24
Peak memory 218572 kb
Host smart-25a60a28-532f-4cd3-a3b9-50ee9fe1f254
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094245226 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.3094245226
Directory /workspace/2.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.3653578717
Short name T228
Test name
Test status
Simulation time 198336534 ps
CPU time 5.19 seconds
Started May 12 02:15:24 PM PDT 24
Finished May 12 02:15:29 PM PDT 24
Peak memory 213060 kb
Host smart-d1a246d9-e205-438c-b845-3837c95457b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653578717 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.3653578717
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.2499671737
Short name T53
Test name
Test status
Simulation time 975438632 ps
CPU time 9.74 seconds
Started May 12 02:15:31 PM PDT 24
Finished May 12 02:15:42 PM PDT 24
Peak memory 213104 kb
Host smart-4cf95edc-5bd8-408c-897c-1352312c9125
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499671737 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.2499671737
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/24.rv_dm_tap_fsm_rand_reset.2445085878
Short name T263
Test name
Test status
Simulation time 6000206967 ps
CPU time 20.14 seconds
Started May 12 02:15:55 PM PDT 24
Finished May 12 02:16:16 PM PDT 24
Peak memory 219312 kb
Host smart-0bb7f741-e4e7-4e13-b438-ef1e0260acf3
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445085878 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 24.rv_dm_tap_fsm_rand_reset.2445085878
Directory /workspace/24.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/25.rv_dm_tap_fsm_rand_reset.3141447052
Short name T47
Test name
Test status
Simulation time 23057514185 ps
CPU time 12.67 seconds
Started May 12 02:15:53 PM PDT 24
Finished May 12 02:16:07 PM PDT 24
Peak memory 216188 kb
Host smart-261497e6-5403-4439-8c72-e472750a363f
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141447052 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 25.rv_dm_tap_fsm_rand_reset.3141447052
Directory /workspace/25.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/29.rv_dm_tap_fsm_rand_reset.3532317717
Short name T134
Test name
Test status
Simulation time 13496063591 ps
CPU time 14.23 seconds
Started May 12 02:15:52 PM PDT 24
Finished May 12 02:16:07 PM PDT 24
Peak memory 213716 kb
Host smart-2641af1e-86c2-442a-a492-3a10d7f75c2f
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532317717 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 29.rv_dm_tap_fsm_rand_reset.3532317717
Directory /workspace/29.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.93822990
Short name T97
Test name
Test status
Simulation time 4533472676 ps
CPU time 75.85 seconds
Started May 12 02:15:29 PM PDT 24
Finished May 12 02:16:46 PM PDT 24
Peak memory 217844 kb
Host smart-0a3967e8-2c89-4192-b6ff-a65c17cdca9b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93822990 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UV
M_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 3.rv_dm_csr_aliasing.93822990
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.3760495987
Short name T112
Test name
Test status
Simulation time 2811583919 ps
CPU time 56.45 seconds
Started May 12 02:15:34 PM PDT 24
Finished May 12 02:16:31 PM PDT 24
Peak memory 204896 kb
Host smart-ee2bccbf-4238-490c-9b71-e77a09553f88
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760495987 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.3760495987
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.3503979357
Short name T304
Test name
Test status
Simulation time 110888000 ps
CPU time 1.54 seconds
Started May 12 02:15:33 PM PDT 24
Finished May 12 02:15:35 PM PDT 24
Peak memory 212972 kb
Host smart-62497b2b-899a-416b-a392-5a32ac010a8e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503979357 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.3503979357
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1716609155
Short name T278
Test name
Test status
Simulation time 4211372649 ps
CPU time 3.99 seconds
Started May 12 02:15:36 PM PDT 24
Finished May 12 02:15:40 PM PDT 24
Peak memory 218020 kb
Host smart-1aa55e81-64b6-4f6b-b9ed-702eeb02d798
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716609155 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.1716609155
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.4010394355
Short name T291
Test name
Test status
Simulation time 208060183 ps
CPU time 1.57 seconds
Started May 12 02:15:34 PM PDT 24
Finished May 12 02:15:36 PM PDT 24
Peak memory 217900 kb
Host smart-8d0ab14f-7b26-4241-b320-228a1ef837a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010394355 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.4010394355
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.735898864
Short name T270
Test name
Test status
Simulation time 11406526590 ps
CPU time 27.45 seconds
Started May 12 02:15:32 PM PDT 24
Finished May 12 02:16:00 PM PDT 24
Peak memory 204924 kb
Host smart-b8f2ae06-660d-4201-a100-c752d6ff6fe4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735898864 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr
_aliasing.735898864
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.2529761911
Short name T267
Test name
Test status
Simulation time 27936714850 ps
CPU time 16.47 seconds
Started May 12 02:15:28 PM PDT 24
Finished May 12 02:15:46 PM PDT 24
Peak memory 205012 kb
Host smart-11bed027-be7c-4fd5-af93-e7eafd462317
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529761911 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_bit_bash.2529761911
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2103877405
Short name T89
Test name
Test status
Simulation time 2458026148 ps
CPU time 2.69 seconds
Started May 12 02:15:33 PM PDT 24
Finished May 12 02:15:36 PM PDT 24
Peak memory 204924 kb
Host smart-7aed0378-6016-49ef-bc9d-baccab915d4c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103877405 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.2103877405
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.3750897196
Short name T176
Test name
Test status
Simulation time 425538825 ps
CPU time 1.41 seconds
Started May 12 02:15:33 PM PDT 24
Finished May 12 02:15:35 PM PDT 24
Peak memory 204124 kb
Host smart-7b44645c-67c1-4dbf-ad72-1fd7de7986dc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750897196 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.3
750897196
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.1283611995
Short name T272
Test name
Test status
Simulation time 241730807 ps
CPU time 0.81 seconds
Started May 12 02:15:31 PM PDT 24
Finished May 12 02:15:32 PM PDT 24
Peak memory 204532 kb
Host smart-bd787408-b62b-43e1-926b-02cbd07b8742
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283611995 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.1283611995
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.1344424915
Short name T215
Test name
Test status
Simulation time 376859958 ps
CPU time 2.46 seconds
Started May 12 02:15:31 PM PDT 24
Finished May 12 02:15:34 PM PDT 24
Peak memory 205032 kb
Host smart-17bcb156-981d-4972-a0e0-1b565e2bb628
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344424915 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.1344424915
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.2980053578
Short name T255
Test name
Test status
Simulation time 72643164 ps
CPU time 0.86 seconds
Started May 12 02:15:28 PM PDT 24
Finished May 12 02:15:30 PM PDT 24
Peak memory 204576 kb
Host smart-fd187119-6c69-4100-bc34-b52e827c1f57
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980053578 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.2980053578
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1877393243
Short name T208
Test name
Test status
Simulation time 50052052 ps
CPU time 0.76 seconds
Started May 12 02:15:28 PM PDT 24
Finished May 12 02:15:29 PM PDT 24
Peak memory 204552 kb
Host smart-ffe91699-0426-4b16-a2b0-6dfc4bdc53cb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877393243 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.1
877393243
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.1923643496
Short name T223
Test name
Test status
Simulation time 30612944 ps
CPU time 0.68 seconds
Started May 12 02:15:33 PM PDT 24
Finished May 12 02:15:34 PM PDT 24
Peak memory 204524 kb
Host smart-8d3c032f-f0be-4285-9cf3-4f62d31884f0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923643496 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.1923643496
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.4144783359
Short name T211
Test name
Test status
Simulation time 61549562 ps
CPU time 0.72 seconds
Started May 12 02:15:32 PM PDT 24
Finished May 12 02:15:33 PM PDT 24
Peak memory 204560 kb
Host smart-e1aa444d-51fb-4f6c-a1b4-bc8da67f9c7a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144783359 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.4144783359
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2328060473
Short name T80
Test name
Test status
Simulation time 82467977 ps
CPU time 3.66 seconds
Started May 12 02:15:32 PM PDT 24
Finished May 12 02:15:36 PM PDT 24
Peak memory 204848 kb
Host smart-e5429dbf-ec0d-4405-88dc-9e7081e655d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328060473 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_
csr_outstanding.2328060473
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2635128720
Short name T232
Test name
Test status
Simulation time 301990171 ps
CPU time 2.3 seconds
Started May 12 02:15:31 PM PDT 24
Finished May 12 02:15:34 PM PDT 24
Peak memory 213132 kb
Host smart-ad1f8f6d-62ec-42bc-aabf-e67a5a4d3691
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635128720 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.2635128720
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3769490210
Short name T294
Test name
Test status
Simulation time 1964049670 ps
CPU time 18.61 seconds
Started May 12 02:15:33 PM PDT 24
Finished May 12 02:15:52 PM PDT 24
Peak memory 213092 kb
Host smart-3b5f17cd-649b-40c9-8e03-96cae145ce0a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769490210 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.3769490210
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/35.rv_dm_tap_fsm_rand_reset.3471729804
Short name T230
Test name
Test status
Simulation time 21898421458 ps
CPU time 30.37 seconds
Started May 12 02:15:54 PM PDT 24
Finished May 12 02:16:25 PM PDT 24
Peak memory 235684 kb
Host smart-0feb95c0-89bb-4e5e-a7c8-29a84239232a
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471729804 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 35.rv_dm_tap_fsm_rand_reset.3471729804
Directory /workspace/35.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1774293702
Short name T108
Test name
Test status
Simulation time 4535372837 ps
CPU time 67.83 seconds
Started May 12 02:15:36 PM PDT 24
Finished May 12 02:16:45 PM PDT 24
Peak memory 217632 kb
Host smart-94a4c2f5-19df-476e-81d9-923ff6aacf63
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774293702 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.1774293702
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.4016655018
Short name T111
Test name
Test status
Simulation time 8134267148 ps
CPU time 71.25 seconds
Started May 12 02:15:36 PM PDT 24
Finished May 12 02:16:48 PM PDT 24
Peak memory 204992 kb
Host smart-60dcea15-2695-4ec5-b30a-2bc5c1ee3e7b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016655018 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.4016655018
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2014674748
Short name T288
Test name
Test status
Simulation time 104393683 ps
CPU time 1.54 seconds
Started May 12 02:15:44 PM PDT 24
Finished May 12 02:15:46 PM PDT 24
Peak memory 213140 kb
Host smart-5b583454-911b-4604-a6d1-c21bc146d6e4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014674748 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.2014674748
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.3370350954
Short name T296
Test name
Test status
Simulation time 321061775 ps
CPU time 3.85 seconds
Started May 12 02:15:41 PM PDT 24
Finished May 12 02:15:46 PM PDT 24
Peak memory 218756 kb
Host smart-4b3edd99-c860-45f8-8ffb-2d31940af2dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370350954 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.3370350954
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.108181510
Short name T252
Test name
Test status
Simulation time 315351171 ps
CPU time 2.42 seconds
Started May 12 02:15:44 PM PDT 24
Finished May 12 02:15:47 PM PDT 24
Peak memory 218580 kb
Host smart-4ef37375-a21a-47d8-aa59-18496d694f20
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108181510 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.108181510
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.400876659
Short name T179
Test name
Test status
Simulation time 16544583332 ps
CPU time 57.17 seconds
Started May 12 02:15:33 PM PDT 24
Finished May 12 02:16:30 PM PDT 24
Peak memory 204976 kb
Host smart-e821f9be-0a80-4ef2-9e38-3475d5f037d0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400876659 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr
_aliasing.400876659
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.1177454472
Short name T192
Test name
Test status
Simulation time 16304845438 ps
CPU time 38.12 seconds
Started May 12 02:15:36 PM PDT 24
Finished May 12 02:16:15 PM PDT 24
Peak memory 204888 kb
Host smart-df6e743d-14f3-4022-b4c5-1102235592fb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177454472 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_bit_bash.1177454472
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.864468605
Short name T86
Test name
Test status
Simulation time 1260701666 ps
CPU time 1.95 seconds
Started May 12 02:15:32 PM PDT 24
Finished May 12 02:15:35 PM PDT 24
Peak memory 204780 kb
Host smart-cc5d2d57-d0cd-493e-920d-33a275355a2c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864468605 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr
_hw_reset.864468605
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.136451382
Short name T174
Test name
Test status
Simulation time 563816284 ps
CPU time 2.56 seconds
Started May 12 02:15:35 PM PDT 24
Finished May 12 02:15:38 PM PDT 24
Peak memory 204848 kb
Host smart-05875c8b-50fc-4d0c-81d2-72d66055a3dc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136451382 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.136451382
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.3435857772
Short name T292
Test name
Test status
Simulation time 64364760 ps
CPU time 0.79 seconds
Started May 12 02:15:33 PM PDT 24
Finished May 12 02:15:35 PM PDT 24
Peak memory 204796 kb
Host smart-56e6eb6b-8dcd-4821-8861-633e26c90d34
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435857772 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.3435857772
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.3516931441
Short name T198
Test name
Test status
Simulation time 477201863 ps
CPU time 2.64 seconds
Started May 12 02:15:33 PM PDT 24
Finished May 12 02:15:36 PM PDT 24
Peak memory 204864 kb
Host smart-3b681d22-c99e-4e68-a88c-879de52eea28
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516931441 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.3516931441
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2719268756
Short name T199
Test name
Test status
Simulation time 117610564 ps
CPU time 1.07 seconds
Started May 12 02:15:36 PM PDT 24
Finished May 12 02:15:38 PM PDT 24
Peak memory 204828 kb
Host smart-e53f140b-b453-472a-9ea4-09cb5fa361a6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719268756 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.2719268756
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.4622407
Short name T237
Test name
Test status
Simulation time 23415047 ps
CPU time 0.72 seconds
Started May 12 02:15:35 PM PDT 24
Finished May 12 02:15:36 PM PDT 24
Peak memory 204580 kb
Host smart-54d4cae4-41b1-4952-a40e-1b60d813d4b3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4622407 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.4622407
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.3433897725
Short name T249
Test name
Test status
Simulation time 17588735 ps
CPU time 0.7 seconds
Started May 12 02:15:36 PM PDT 24
Finished May 12 02:15:38 PM PDT 24
Peak memory 204608 kb
Host smart-1f1b90d6-9b55-42ee-a94c-9eee684c261e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433897725 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.3433897725
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.2843199238
Short name T197
Test name
Test status
Simulation time 57907423 ps
CPU time 0.69 seconds
Started May 12 02:15:39 PM PDT 24
Finished May 12 02:15:40 PM PDT 24
Peak memory 204576 kb
Host smart-df1941e2-81c0-4473-b6d5-2cb28354b748
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843199238 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.2843199238
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.2507167603
Short name T99
Test name
Test status
Simulation time 2237374175 ps
CPU time 8.06 seconds
Started May 12 02:15:40 PM PDT 24
Finished May 12 02:15:49 PM PDT 24
Peak memory 204956 kb
Host smart-87dd156e-4c7d-49db-b2cf-e38508da0479
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507167603 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.2507167603
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.4192086469
Short name T219
Test name
Test status
Simulation time 12487077716 ps
CPU time 44.94 seconds
Started May 12 02:15:38 PM PDT 24
Finished May 12 02:16:24 PM PDT 24
Peak memory 221408 kb
Host smart-041e2d30-75e7-41e1-8e67-27164ca4b141
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192086469 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.4192086469
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2354819062
Short name T125
Test name
Test status
Simulation time 125214319 ps
CPU time 2.66 seconds
Started May 12 02:15:44 PM PDT 24
Finished May 12 02:15:47 PM PDT 24
Peak memory 213180 kb
Host smart-7a1cc3f8-ee8f-45a5-a9a9-7123e7aaf18e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354819062 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.2354819062
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.380467132
Short name T257
Test name
Test status
Simulation time 4473959321 ps
CPU time 4.7 seconds
Started May 12 02:15:38 PM PDT 24
Finished May 12 02:15:43 PM PDT 24
Peak memory 219288 kb
Host smart-87f23a26-4e7d-4e6e-8c26-a0300186fe76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380467132 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.380467132
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3645895915
Short name T181
Test name
Test status
Simulation time 176488786 ps
CPU time 1.44 seconds
Started May 12 02:15:39 PM PDT 24
Finished May 12 02:15:41 PM PDT 24
Peak memory 204700 kb
Host smart-4e0d4781-bc81-4b2e-9607-5d79854de540
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645895915 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.3
645895915
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3165478945
Short name T227
Test name
Test status
Simulation time 21575713 ps
CPU time 0.74 seconds
Started May 12 02:15:39 PM PDT 24
Finished May 12 02:15:41 PM PDT 24
Peak memory 204520 kb
Host smart-bb3e85c2-5c24-44c8-be12-5ed911265e4d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165478945 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.3
165478945
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.3674013659
Short name T115
Test name
Test status
Simulation time 500956882 ps
CPU time 4.15 seconds
Started May 12 02:15:39 PM PDT 24
Finished May 12 02:15:43 PM PDT 24
Peak memory 204920 kb
Host smart-30de277d-ae32-45b9-9e34-1e6e716c35e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674013659 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.3674013659
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.3154536147
Short name T70
Test name
Test status
Simulation time 695817876 ps
CPU time 5.85 seconds
Started May 12 02:15:39 PM PDT 24
Finished May 12 02:15:45 PM PDT 24
Peak memory 213228 kb
Host smart-cc5d4553-4df8-4386-8244-733168feae05
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154536147 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.3154536147
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.754535606
Short name T303
Test name
Test status
Simulation time 3063878178 ps
CPU time 18.47 seconds
Started May 12 02:15:36 PM PDT 24
Finished May 12 02:15:55 PM PDT 24
Peak memory 221352 kb
Host smart-4727bd69-b9a2-41f0-b3b5-858e2056e31d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754535606 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.754535606
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.129123340
Short name T265
Test name
Test status
Simulation time 826797541 ps
CPU time 3.28 seconds
Started May 12 02:15:42 PM PDT 24
Finished May 12 02:15:46 PM PDT 24
Peak memory 221184 kb
Host smart-472648bc-9963-4b99-9680-b664d844cfca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129123340 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.129123340
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1731873252
Short name T95
Test name
Test status
Simulation time 331557487 ps
CPU time 1.43 seconds
Started May 12 02:15:40 PM PDT 24
Finished May 12 02:15:43 PM PDT 24
Peak memory 213080 kb
Host smart-0e87439e-559b-4d92-a624-33d724a33065
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731873252 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.1731873252
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2879205422
Short name T262
Test name
Test status
Simulation time 444242033 ps
CPU time 1.57 seconds
Started May 12 02:15:39 PM PDT 24
Finished May 12 02:15:41 PM PDT 24
Peak memory 204704 kb
Host smart-c60d40bb-145e-4f11-acde-304a5fd3b8b5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879205422 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.2
879205422
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2782237262
Short name T248
Test name
Test status
Simulation time 77987561 ps
CPU time 0.89 seconds
Started May 12 02:15:40 PM PDT 24
Finished May 12 02:15:42 PM PDT 24
Peak memory 204568 kb
Host smart-9171981e-46ee-43d9-8cee-579b5b31ab57
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782237262 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.2
782237262
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.1793049881
Short name T280
Test name
Test status
Simulation time 825791005 ps
CPU time 7.69 seconds
Started May 12 02:15:41 PM PDT 24
Finished May 12 02:15:50 PM PDT 24
Peak memory 204884 kb
Host smart-3b571c4a-a2ec-479f-b8a7-ccd0285b4df2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793049881 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.1793049881
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.2723851096
Short name T123
Test name
Test status
Simulation time 279841676 ps
CPU time 3.98 seconds
Started May 12 02:15:39 PM PDT 24
Finished May 12 02:15:43 PM PDT 24
Peak memory 213188 kb
Host smart-33add7e8-b42e-4bd5-95d0-e68eea7774dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723851096 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.2723851096
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.3873002152
Short name T129
Test name
Test status
Simulation time 2184264940 ps
CPU time 19.42 seconds
Started May 12 02:15:43 PM PDT 24
Finished May 12 02:16:03 PM PDT 24
Peak memory 221264 kb
Host smart-d9b6ffaf-94a0-478e-bd21-e728dcce8c07
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873002152 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.3873002152
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2411841565
Short name T238
Test name
Test status
Simulation time 42469307 ps
CPU time 2.41 seconds
Started May 12 02:15:42 PM PDT 24
Finished May 12 02:15:45 PM PDT 24
Peak memory 217408 kb
Host smart-15e448c0-d81f-4e08-845b-1c8037e21e63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411841565 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.2411841565
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.2381477195
Short name T105
Test name
Test status
Simulation time 183054691 ps
CPU time 1.65 seconds
Started May 12 02:15:42 PM PDT 24
Finished May 12 02:15:44 PM PDT 24
Peak memory 218568 kb
Host smart-7d273324-f561-45d8-b568-9f9aeb512544
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381477195 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.2381477195
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2296450539
Short name T175
Test name
Test status
Simulation time 195099538 ps
CPU time 1.15 seconds
Started May 12 02:15:45 PM PDT 24
Finished May 12 02:15:47 PM PDT 24
Peak memory 204752 kb
Host smart-a3caeecf-dcf4-4bef-8fcf-41719549457d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296450539 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.2
296450539
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.409015379
Short name T251
Test name
Test status
Simulation time 85904663 ps
CPU time 0.7 seconds
Started May 12 02:15:49 PM PDT 24
Finished May 12 02:15:51 PM PDT 24
Peak memory 204628 kb
Host smart-a6bb88fc-e892-4893-b10a-cd8523d372e3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409015379 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.409015379
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.2466215828
Short name T91
Test name
Test status
Simulation time 90082051 ps
CPU time 3.81 seconds
Started May 12 02:15:43 PM PDT 24
Finished May 12 02:15:47 PM PDT 24
Peak memory 204960 kb
Host smart-6597bf6f-bc8d-4128-87df-6cd3bcd1a9cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466215828 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.2466215828
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.280126619
Short name T268
Test name
Test status
Simulation time 11652959691 ps
CPU time 12.33 seconds
Started May 12 02:15:45 PM PDT 24
Finished May 12 02:15:58 PM PDT 24
Peak memory 219748 kb
Host smart-fa95cd5d-0cd0-4c63-a6de-b8c4b4f4437f
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280126619 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.280126619
Directory /workspace/7.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.431280
Short name T235
Test name
Test status
Simulation time 71630748 ps
CPU time 2.34 seconds
Started May 12 02:15:40 PM PDT 24
Finished May 12 02:15:43 PM PDT 24
Peak memory 213212 kb
Host smart-8f75d4f5-418e-40ad-9bfd-616058cf515e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.431280
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.3510831220
Short name T203
Test name
Test status
Simulation time 126796183 ps
CPU time 4.12 seconds
Started May 12 02:15:45 PM PDT 24
Finished May 12 02:15:50 PM PDT 24
Peak memory 220740 kb
Host smart-fdeb9e8a-411f-42e9-8cd9-1754dec2559e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510831220 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.3510831220
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.2343538501
Short name T261
Test name
Test status
Simulation time 171340828 ps
CPU time 2.32 seconds
Started May 12 02:15:44 PM PDT 24
Finished May 12 02:15:47 PM PDT 24
Peak memory 221168 kb
Host smart-8cca0e4a-180a-4a49-ae9c-66025f0f794c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343538501 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.2343538501
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1286829469
Short name T190
Test name
Test status
Simulation time 659992546 ps
CPU time 1.78 seconds
Started May 12 02:15:42 PM PDT 24
Finished May 12 02:15:45 PM PDT 24
Peak memory 204796 kb
Host smart-5366a83c-a020-4af6-9622-203ebef4932a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286829469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.1
286829469
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.3581024129
Short name T195
Test name
Test status
Simulation time 70510547 ps
CPU time 0.86 seconds
Started May 12 02:15:45 PM PDT 24
Finished May 12 02:15:47 PM PDT 24
Peak memory 204508 kb
Host smart-120505ca-febd-44df-a813-fa3d07dfa9d0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581024129 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.3
581024129
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2393256459
Short name T234
Test name
Test status
Simulation time 158862547 ps
CPU time 3.66 seconds
Started May 12 02:15:43 PM PDT 24
Finished May 12 02:15:47 PM PDT 24
Peak memory 204896 kb
Host smart-1f4a5bad-34c4-42fa-8de0-d8c9eb892479
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393256459 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_
csr_outstanding.2393256459
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.586183485
Short name T295
Test name
Test status
Simulation time 477823617 ps
CPU time 5.54 seconds
Started May 12 02:15:41 PM PDT 24
Finished May 12 02:15:47 PM PDT 24
Peak memory 213204 kb
Host smart-e5d26bcb-42d1-4de7-8d79-fa204ecce373
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586183485 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.586183485
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3199712519
Short name T121
Test name
Test status
Simulation time 2198722128 ps
CPU time 19.61 seconds
Started May 12 02:15:41 PM PDT 24
Finished May 12 02:16:01 PM PDT 24
Peak memory 213192 kb
Host smart-944a506d-0578-4b7b-a7ed-3a5dce8433fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199712519 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.3199712519
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.4157971056
Short name T253
Test name
Test status
Simulation time 1994151487 ps
CPU time 5.46 seconds
Started May 12 02:15:49 PM PDT 24
Finished May 12 02:15:55 PM PDT 24
Peak memory 220760 kb
Host smart-f1e6e376-f4b4-4ab6-adce-df2f692b4bad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157971056 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.4157971056
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.2105551510
Short name T94
Test name
Test status
Simulation time 59198108 ps
CPU time 1.61 seconds
Started May 12 02:15:46 PM PDT 24
Finished May 12 02:15:48 PM PDT 24
Peak memory 213056 kb
Host smart-85736e3c-7939-4d2f-8512-dfabfefda217
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105551510 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.2105551510
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.1123509750
Short name T256
Test name
Test status
Simulation time 1550646868 ps
CPU time 2.38 seconds
Started May 12 02:15:49 PM PDT 24
Finished May 12 02:15:52 PM PDT 24
Peak memory 204780 kb
Host smart-b8aaf7ca-d2cb-404e-bcf9-014b4db85033
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123509750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.1
123509750
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.3983088319
Short name T298
Test name
Test status
Simulation time 25761357 ps
CPU time 0.73 seconds
Started May 12 02:15:40 PM PDT 24
Finished May 12 02:15:42 PM PDT 24
Peak memory 204616 kb
Host smart-e56010ba-c2db-42be-bd4d-19bbfc7f7ebd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983088319 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.3
983088319
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.3872362039
Short name T114
Test name
Test status
Simulation time 1785474958 ps
CPU time 7.7 seconds
Started May 12 02:15:43 PM PDT 24
Finished May 12 02:15:51 PM PDT 24
Peak memory 204920 kb
Host smart-a25d4c87-ebc9-4c5d-9761-206c5c507c3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872362039 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.3872362039
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.863753243
Short name T216
Test name
Test status
Simulation time 25188317126 ps
CPU time 25.27 seconds
Started May 12 02:15:41 PM PDT 24
Finished May 12 02:16:07 PM PDT 24
Peak memory 229640 kb
Host smart-0ac52597-ab79-4425-b6fe-95681af35e28
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863753243 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.863753243
Directory /workspace/9.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.3851829939
Short name T276
Test name
Test status
Simulation time 72842066 ps
CPU time 4.51 seconds
Started May 12 02:15:42 PM PDT 24
Finished May 12 02:15:47 PM PDT 24
Peak memory 213244 kb
Host smart-765e61a8-c8a3-45f8-9448-dfe917b6f815
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851829939 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.3851829939
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.1250245390
Short name T119
Test name
Test status
Simulation time 2904386223 ps
CPU time 18.52 seconds
Started May 12 02:15:43 PM PDT 24
Finished May 12 02:16:02 PM PDT 24
Peak memory 213152 kb
Host smart-db7c1801-3bb1-4a10-9439-f7b22c452aae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250245390 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.1250245390
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.1526270812
Short name T139
Test name
Test status
Simulation time 29223196 ps
CPU time 0.73 seconds
Started May 12 02:00:15 PM PDT 24
Finished May 12 02:00:16 PM PDT 24
Peak memory 204748 kb
Host smart-3c029682-72e0-4a7d-8ca0-409dbca2608d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526270812 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.1526270812
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.1703835570
Short name T33
Test name
Test status
Simulation time 2343033576 ps
CPU time 6.18 seconds
Started May 12 01:59:52 PM PDT 24
Finished May 12 01:59:58 PM PDT 24
Peak memory 205080 kb
Host smart-a0e2dba7-3f56-4dfd-8182-c959e44f9b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703835570 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.1703835570
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.84982444
Short name T23
Test name
Test status
Simulation time 310629905 ps
CPU time 1.59 seconds
Started May 12 01:59:56 PM PDT 24
Finished May 12 01:59:58 PM PDT 24
Peak memory 204928 kb
Host smart-2ca954c9-ca5d-42d5-8ed9-91ded67cf7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84982444 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.84982444
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.3823681839
Short name T11
Test name
Test status
Simulation time 6682247131 ps
CPU time 4.63 seconds
Started May 12 01:59:53 PM PDT 24
Finished May 12 01:59:58 PM PDT 24
Peak memory 205136 kb
Host smart-f476677b-926b-4af9-b908-e7a2bf4ec6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823681839 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.3823681839
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.2640529758
Short name T19
Test name
Test status
Simulation time 112068626 ps
CPU time 0.78 seconds
Started May 12 01:59:58 PM PDT 24
Finished May 12 01:59:59 PM PDT 24
Peak memory 204732 kb
Host smart-4f26cbb1-6026-48df-9474-55ef739964fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640529758 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.2640529758
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.3121487539
Short name T30
Test name
Test status
Simulation time 82583012 ps
CPU time 0.9 seconds
Started May 12 02:00:00 PM PDT 24
Finished May 12 02:00:01 PM PDT 24
Peak memory 204636 kb
Host smart-eba0c179-b9ee-4b6d-a2fd-8e9e1bbfd23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121487539 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.3121487539
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.1722412586
Short name T18
Test name
Test status
Simulation time 110388536 ps
CPU time 1.01 seconds
Started May 12 01:59:59 PM PDT 24
Finished May 12 02:00:01 PM PDT 24
Peak memory 204592 kb
Host smart-b23394be-a2b4-4e06-8a90-2fa2e9820923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722412586 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.1722412586
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.1279538216
Short name T43
Test name
Test status
Simulation time 209476437 ps
CPU time 0.85 seconds
Started May 12 02:00:03 PM PDT 24
Finished May 12 02:00:04 PM PDT 24
Peak memory 204608 kb
Host smart-e3e6faac-8174-433e-bd28-8abb394d8421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279538216 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.1279538216
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.1729572384
Short name T135
Test name
Test status
Simulation time 173267679 ps
CPU time 1.22 seconds
Started May 12 01:59:54 PM PDT 24
Finished May 12 01:59:56 PM PDT 24
Peak memory 204704 kb
Host smart-bef8d82b-2608-4113-bb5a-a4b74ac45b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729572384 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.1729572384
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.49858189
Short name T26
Test name
Test status
Simulation time 1710477965 ps
CPU time 1.45 seconds
Started May 12 01:59:59 PM PDT 24
Finished May 12 02:00:01 PM PDT 24
Peak memory 204940 kb
Host smart-1573c736-8423-450f-81e9-4900ac86cd30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49858189 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.49858189
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.138316911
Short name T84
Test name
Test status
Simulation time 2746714901 ps
CPU time 7.37 seconds
Started May 12 01:59:46 PM PDT 24
Finished May 12 01:59:53 PM PDT 24
Peak memory 205220 kb
Host smart-e6b32617-c87a-4544-b8e8-5a06d94c91c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138316911 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.138316911
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.4126922848
Short name T25
Test name
Test status
Simulation time 195207113 ps
CPU time 1.34 seconds
Started May 12 01:59:45 PM PDT 24
Finished May 12 01:59:47 PM PDT 24
Peak memory 204648 kb
Host smart-ef490dbe-4c12-444b-af50-2377d5e0c625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126922848 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.4126922848
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.3655692436
Short name T24
Test name
Test status
Simulation time 3907653271 ps
CPU time 4.5 seconds
Started May 12 01:59:45 PM PDT 24
Finished May 12 01:59:50 PM PDT 24
Peak memory 205084 kb
Host smart-b5f48bd7-6ed3-4082-927d-c79850327787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655692436 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.3655692436
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.3007153698
Short name T29
Test name
Test status
Simulation time 36994216 ps
CPU time 0.74 seconds
Started May 12 02:00:23 PM PDT 24
Finished May 12 02:00:25 PM PDT 24
Peak memory 204768 kb
Host smart-4e404b69-56a3-409c-87f2-4ab0046dc035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007153698 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.3007153698
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.3738532362
Short name T172
Test name
Test status
Simulation time 57782418 ps
CPU time 0.73 seconds
Started May 12 02:00:22 PM PDT 24
Finished May 12 02:00:23 PM PDT 24
Peak memory 204600 kb
Host smart-b18b16cc-ba47-4644-ba24-aacd2b773eb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738532362 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.3738532362
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.2559198082
Short name T32
Test name
Test status
Simulation time 2344151692 ps
CPU time 3.6 seconds
Started May 12 02:00:14 PM PDT 24
Finished May 12 02:00:18 PM PDT 24
Peak memory 205084 kb
Host smart-836a828b-2efb-46e5-8de2-04d8b8d1ca63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559198082 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.2559198082
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.1420447192
Short name T8
Test name
Test status
Simulation time 108599846 ps
CPU time 0.76 seconds
Started May 12 02:00:17 PM PDT 24
Finished May 12 02:00:19 PM PDT 24
Peak memory 204824 kb
Host smart-b71efd21-7426-4891-911e-35ecd2a3cae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420447192 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.1420447192
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.2152626573
Short name T10
Test name
Test status
Simulation time 2055482584 ps
CPU time 2.71 seconds
Started May 12 02:00:14 PM PDT 24
Finished May 12 02:00:17 PM PDT 24
Peak memory 205020 kb
Host smart-0611111f-c70d-4120-98f9-0411d9e6654e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152626573 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.2152626573
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.3450130034
Short name T21
Test name
Test status
Simulation time 74018997 ps
CPU time 0.73 seconds
Started May 12 02:00:17 PM PDT 24
Finished May 12 02:00:18 PM PDT 24
Peak memory 204732 kb
Host smart-d68c38e8-2205-4a45-a7dd-1ac8fa23cdef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450130034 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.3450130034
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.1443585466
Short name T168
Test name
Test status
Simulation time 38223398 ps
CPU time 0.71 seconds
Started May 12 02:00:15 PM PDT 24
Finished May 12 02:00:17 PM PDT 24
Peak memory 204576 kb
Host smart-33a078df-c0d8-4823-b060-08fe33a07d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443585466 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.1443585466
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.457573990
Short name T3
Test name
Test status
Simulation time 198518242 ps
CPU time 0.83 seconds
Started May 12 02:00:22 PM PDT 24
Finished May 12 02:00:23 PM PDT 24
Peak memory 204612 kb
Host smart-cb1a2b38-f926-4960-a4d6-5a9abefa2727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457573990 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.457573990
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.1356750424
Short name T41
Test name
Test status
Simulation time 1170640171 ps
CPU time 2.75 seconds
Started May 12 02:00:23 PM PDT 24
Finished May 12 02:00:27 PM PDT 24
Peak memory 204872 kb
Host smart-397e9f95-eaa0-4f4b-8ef4-d9252ccb665b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356750424 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.1356750424
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.3407293322
Short name T5
Test name
Test status
Simulation time 114857173 ps
CPU time 1.01 seconds
Started May 12 02:00:17 PM PDT 24
Finished May 12 02:00:19 PM PDT 24
Peak memory 204744 kb
Host smart-c7df4464-29e6-4147-8416-66edbdec293e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407293322 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.3407293322
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.2168554909
Short name T15
Test name
Test status
Simulation time 969942484 ps
CPU time 3.15 seconds
Started May 12 02:00:18 PM PDT 24
Finished May 12 02:00:21 PM PDT 24
Peak memory 205004 kb
Host smart-cfba50a0-f1f5-4cf8-a7d7-f329c4625b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168554909 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.2168554909
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.131413838
Short name T22
Test name
Test status
Simulation time 40629445 ps
CPU time 0.73 seconds
Started May 12 02:00:25 PM PDT 24
Finished May 12 02:00:26 PM PDT 24
Peak memory 204764 kb
Host smart-3335c27d-7142-4aa7-86b6-3b94cbc02a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131413838 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.131413838
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.2930701111
Short name T27
Test name
Test status
Simulation time 64607709 ps
CPU time 0.75 seconds
Started May 12 02:00:23 PM PDT 24
Finished May 12 02:00:24 PM PDT 24
Peak memory 204780 kb
Host smart-0add9f5b-13b4-4f4e-aef7-2a5fc8c7331d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930701111 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.2930701111
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.329420887
Short name T16
Test name
Test status
Simulation time 74666667 ps
CPU time 0.82 seconds
Started May 12 02:00:20 PM PDT 24
Finished May 12 02:00:21 PM PDT 24
Peak memory 212900 kb
Host smart-dc3b2c96-ae94-410c-99c9-fe40a7c939be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329420887 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.329420887
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.1135105735
Short name T2
Test name
Test status
Simulation time 3648745914 ps
CPU time 3.47 seconds
Started May 12 02:00:21 PM PDT 24
Finished May 12 02:00:25 PM PDT 24
Peak memory 228824 kb
Host smart-7f463cb9-fbc5-4116-a920-3adde6aa33a5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135105735 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.1135105735
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.1747378007
Short name T48
Test name
Test status
Simulation time 445491295 ps
CPU time 2.13 seconds
Started May 12 02:00:09 PM PDT 24
Finished May 12 02:00:12 PM PDT 24
Peak memory 204808 kb
Host smart-54d67173-5bdc-4239-9fcd-56c3756185d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747378007 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.1747378007
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.3296194454
Short name T59
Test name
Test status
Simulation time 28607749 ps
CPU time 0.73 seconds
Started May 12 02:00:59 PM PDT 24
Finished May 12 02:01:00 PM PDT 24
Peak memory 204748 kb
Host smart-0ac00070-ab1d-468c-8f6a-8b7e26b57566
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296194454 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.3296194454
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.4127066304
Short name T160
Test name
Test status
Simulation time 32745408 ps
CPU time 0.81 seconds
Started May 12 02:01:01 PM PDT 24
Finished May 12 02:01:02 PM PDT 24
Peak memory 204752 kb
Host smart-d9515592-5634-4a25-8da6-6a6b49ca05ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127066304 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.4127066304
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.1065686785
Short name T122
Test name
Test status
Simulation time 59200159 ps
CPU time 0.7 seconds
Started May 12 02:01:00 PM PDT 24
Finished May 12 02:01:01 PM PDT 24
Peak memory 204712 kb
Host smart-cfb06f88-7417-4e7b-9790-808b983059ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065686785 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.1065686785
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.2684264786
Short name T116
Test name
Test status
Simulation time 50850037 ps
CPU time 0.73 seconds
Started May 12 02:01:03 PM PDT 24
Finished May 12 02:01:04 PM PDT 24
Peak memory 204764 kb
Host smart-b933226d-f266-4a4e-885f-3f8d8baa661c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684264786 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.2684264786
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.1418151699
Short name T36
Test name
Test status
Simulation time 696674067 ps
CPU time 1.16 seconds
Started May 12 02:01:02 PM PDT 24
Finished May 12 02:01:04 PM PDT 24
Peak memory 204968 kb
Host smart-7bc6207e-f639-4bdf-b1a9-64084e60172b
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1418151699 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_
tl_access.1418151699
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.1942374140
Short name T62
Test name
Test status
Simulation time 30649245 ps
CPU time 0.73 seconds
Started May 12 02:01:06 PM PDT 24
Finished May 12 02:01:07 PM PDT 24
Peak memory 204668 kb
Host smart-40e8fa41-c0d4-446e-b05b-2d1f7aecb96f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942374140 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.1942374140
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.2090230942
Short name T159
Test name
Test status
Simulation time 35071226 ps
CPU time 0.73 seconds
Started May 12 02:01:14 PM PDT 24
Finished May 12 02:01:15 PM PDT 24
Peak memory 204752 kb
Host smart-eb7ddb37-2c4d-4676-8ad6-eb85b4262a71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090230942 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.2090230942
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.69616785
Short name T142
Test name
Test status
Simulation time 58994488 ps
CPU time 0.72 seconds
Started May 12 02:01:12 PM PDT 24
Finished May 12 02:01:13 PM PDT 24
Peak memory 204672 kb
Host smart-5f1035e5-4b67-4411-9d00-4eafb047b4b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69616785 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.69616785
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.1862791499
Short name T140
Test name
Test status
Simulation time 166013197 ps
CPU time 0.66 seconds
Started May 12 02:01:20 PM PDT 24
Finished May 12 02:01:21 PM PDT 24
Peak memory 204752 kb
Host smart-3d4175c3-bb43-4183-8d2e-3caeb3a51723
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862791499 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.1862791499
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.1922775397
Short name T149
Test name
Test status
Simulation time 19484102 ps
CPU time 0.72 seconds
Started May 12 02:01:24 PM PDT 24
Finished May 12 02:01:25 PM PDT 24
Peak memory 204720 kb
Host smart-9483a42c-dee3-44d9-89a2-85f1d597ba37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922775397 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.1922775397
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.226580368
Short name T83
Test name
Test status
Simulation time 2806396635 ps
CPU time 4.63 seconds
Started May 12 02:01:21 PM PDT 24
Finished May 12 02:01:26 PM PDT 24
Peak memory 205120 kb
Host smart-b9ce08cf-21cc-441a-8a1b-55c255c1c167
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=226580368 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_t
l_access.226580368
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.2235274662
Short name T152
Test name
Test status
Simulation time 29407406 ps
CPU time 0.74 seconds
Started May 12 02:01:26 PM PDT 24
Finished May 12 02:01:27 PM PDT 24
Peak memory 204952 kb
Host smart-6d6b1fd6-8e85-4f2f-937b-712c80e306c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235274662 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.2235274662
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.3862300260
Short name T137
Test name
Test status
Simulation time 35095232 ps
CPU time 0.74 seconds
Started May 12 02:00:31 PM PDT 24
Finished May 12 02:00:32 PM PDT 24
Peak memory 204668 kb
Host smart-55a1f6bc-1e2f-4869-8629-09b5c60e20dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862300260 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.3862300260
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.2047008222
Short name T31
Test name
Test status
Simulation time 62744259 ps
CPU time 0.74 seconds
Started May 12 02:00:27 PM PDT 24
Finished May 12 02:00:28 PM PDT 24
Peak memory 204504 kb
Host smart-e4af0ca2-595f-4e80-88b4-f8072c65daf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047008222 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.2047008222
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.637687443
Short name T42
Test name
Test status
Simulation time 139602309 ps
CPU time 1.07 seconds
Started May 12 02:00:28 PM PDT 24
Finished May 12 02:00:30 PM PDT 24
Peak memory 229352 kb
Host smart-d3bbb984-fa2b-4214-b30a-a5ceff72aecb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637687443 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.637687443
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.3957970993
Short name T154
Test name
Test status
Simulation time 54644080 ps
CPU time 0.72 seconds
Started May 12 02:01:25 PM PDT 24
Finished May 12 02:01:26 PM PDT 24
Peak memory 204740 kb
Host smart-c467e9da-d702-47dd-ac1c-b417221f5b39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957970993 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.3957970993
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.3655978789
Short name T151
Test name
Test status
Simulation time 105813608 ps
CPU time 0.7 seconds
Started May 12 02:01:24 PM PDT 24
Finished May 12 02:01:25 PM PDT 24
Peak memory 204692 kb
Host smart-4bc50ebe-874a-466f-b5c2-3029fe8b6b3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655978789 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.3655978789
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.3281366884
Short name T65
Test name
Test status
Simulation time 31951648 ps
CPU time 0.72 seconds
Started May 12 02:01:28 PM PDT 24
Finished May 12 02:01:30 PM PDT 24
Peak memory 204728 kb
Host smart-5b2c5fae-9887-4608-99fc-85cc614cd3e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281366884 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.3281366884
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.3353894855
Short name T162
Test name
Test status
Simulation time 30132685 ps
CPU time 0.71 seconds
Started May 12 02:01:32 PM PDT 24
Finished May 12 02:01:33 PM PDT 24
Peak memory 204692 kb
Host smart-65d30cf2-9154-4361-a7eb-443159d6b5fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353894855 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.3353894855
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.3097433386
Short name T146
Test name
Test status
Simulation time 34332461 ps
CPU time 0.77 seconds
Started May 12 02:01:28 PM PDT 24
Finished May 12 02:01:30 PM PDT 24
Peak memory 204612 kb
Host smart-d6e1203d-fe9f-4225-a5f2-45db64609a63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097433386 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.3097433386
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.3643800493
Short name T167
Test name
Test status
Simulation time 24844232 ps
CPU time 0.74 seconds
Started May 12 02:01:31 PM PDT 24
Finished May 12 02:01:32 PM PDT 24
Peak memory 204656 kb
Host smart-d6d550a8-68fa-401b-a5df-a871e31265c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643800493 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.3643800493
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.1966927429
Short name T150
Test name
Test status
Simulation time 73731875 ps
CPU time 0.74 seconds
Started May 12 02:01:33 PM PDT 24
Finished May 12 02:01:34 PM PDT 24
Peak memory 204748 kb
Host smart-8636c52f-87e5-4aa2-8e1d-efecf922644d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966927429 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.1966927429
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.3226388093
Short name T157
Test name
Test status
Simulation time 74481416 ps
CPU time 0.72 seconds
Started May 12 02:01:33 PM PDT 24
Finished May 12 02:01:34 PM PDT 24
Peak memory 204724 kb
Host smart-6f90c10e-b438-42dd-bd57-9b874308a11c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226388093 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.3226388093
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.819903815
Short name T164
Test name
Test status
Simulation time 25185809 ps
CPU time 0.71 seconds
Started May 12 02:00:33 PM PDT 24
Finished May 12 02:00:34 PM PDT 24
Peak memory 204744 kb
Host smart-52f7dab1-ed44-4b8e-9e3d-7a09a00ffb38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819903815 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.819903815
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.922198117
Short name T81
Test name
Test status
Simulation time 42304756 ps
CPU time 0.87 seconds
Started May 12 02:00:32 PM PDT 24
Finished May 12 02:00:33 PM PDT 24
Peak memory 204600 kb
Host smart-e5746e42-ca5f-493e-ba84-ac51a874343c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922198117 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.922198117
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.3058423052
Short name T38
Test name
Test status
Simulation time 157955362 ps
CPU time 1.48 seconds
Started May 12 02:00:35 PM PDT 24
Finished May 12 02:00:37 PM PDT 24
Peak memory 228808 kb
Host smart-6b6afb82-6a16-41ec-8000-30e6a20bdcd6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058423052 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.3058423052
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.3810872644
Short name T171
Test name
Test status
Simulation time 32652953 ps
CPU time 0.73 seconds
Started May 12 02:01:42 PM PDT 24
Finished May 12 02:01:43 PM PDT 24
Peak memory 204760 kb
Host smart-5da9f3ca-c0f1-4569-854d-d5473db6eefc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810872644 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.3810872644
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.2635371565
Short name T156
Test name
Test status
Simulation time 30887834 ps
CPU time 0.76 seconds
Started May 12 02:01:38 PM PDT 24
Finished May 12 02:01:40 PM PDT 24
Peak memory 204952 kb
Host smart-3076f085-58b9-42b0-b904-905641d738aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635371565 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.2635371565
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.3113216181
Short name T136
Test name
Test status
Simulation time 24671068 ps
CPU time 0.77 seconds
Started May 12 02:01:35 PM PDT 24
Finished May 12 02:01:36 PM PDT 24
Peak memory 204712 kb
Host smart-d3d90d8c-b368-4b0e-af6f-aae6479bb3e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113216181 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.3113216181
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.2462244341
Short name T141
Test name
Test status
Simulation time 53265220 ps
CPU time 0.71 seconds
Started May 12 02:01:41 PM PDT 24
Finished May 12 02:01:43 PM PDT 24
Peak memory 204764 kb
Host smart-ca6b0965-f9ba-4ef0-ad56-17567fe50f71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462244341 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.2462244341
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.1222718904
Short name T166
Test name
Test status
Simulation time 38677814 ps
CPU time 0.74 seconds
Started May 12 02:01:35 PM PDT 24
Finished May 12 02:01:37 PM PDT 24
Peak memory 204672 kb
Host smart-257a7af0-474a-4a54-8a72-51f3ff365ab0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222718904 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.1222718904
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.2223360416
Short name T148
Test name
Test status
Simulation time 31196666 ps
CPU time 0.76 seconds
Started May 12 02:01:43 PM PDT 24
Finished May 12 02:01:44 PM PDT 24
Peak memory 204764 kb
Host smart-28423e7a-2cbf-421d-8a25-7771a009de91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223360416 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.2223360416
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.3905514690
Short name T138
Test name
Test status
Simulation time 33132638 ps
CPU time 0.84 seconds
Started May 12 02:01:41 PM PDT 24
Finished May 12 02:01:42 PM PDT 24
Peak memory 204952 kb
Host smart-f905d234-deab-47b0-98eb-e3d6b06b434c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905514690 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.3905514690
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.1439887647
Short name T60
Test name
Test status
Simulation time 59205678 ps
CPU time 0.69 seconds
Started May 12 02:01:43 PM PDT 24
Finished May 12 02:01:44 PM PDT 24
Peak memory 204688 kb
Host smart-3ddd2fbd-4242-4416-9f05-e8f2cb50e3f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439887647 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.1439887647
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.2415459009
Short name T117
Test name
Test status
Simulation time 28846739 ps
CPU time 0.72 seconds
Started May 12 02:01:44 PM PDT 24
Finished May 12 02:01:45 PM PDT 24
Peak memory 204668 kb
Host smart-3e1bca58-b8a8-4849-8545-ab4195791f12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415459009 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.2415459009
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.4086229054
Short name T163
Test name
Test status
Simulation time 41030656 ps
CPU time 0.75 seconds
Started May 12 02:01:44 PM PDT 24
Finished May 12 02:01:45 PM PDT 24
Peak memory 204752 kb
Host smart-9f03430a-67c9-442f-a7b3-e065f371f0e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086229054 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.4086229054
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.3206955818
Short name T161
Test name
Test status
Simulation time 28389318 ps
CPU time 0.69 seconds
Started May 12 02:00:39 PM PDT 24
Finished May 12 02:00:40 PM PDT 24
Peak memory 204732 kb
Host smart-5cb8a060-be90-40ea-9353-9d4fb2163f38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206955818 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.3206955818
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.144256438
Short name T170
Test name
Test status
Simulation time 39540764 ps
CPU time 0.83 seconds
Started May 12 02:00:36 PM PDT 24
Finished May 12 02:00:37 PM PDT 24
Peak memory 204572 kb
Host smart-6736291e-e281-40a0-b566-10b0643c0079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144256438 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.144256438
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.2996600477
Short name T44
Test name
Test status
Simulation time 241624801 ps
CPU time 1.59 seconds
Started May 12 02:00:40 PM PDT 24
Finished May 12 02:00:42 PM PDT 24
Peak memory 229424 kb
Host smart-8f6984a4-5ba9-47fe-b3ae-8205f3ee3174
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996600477 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.2996600477
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.3570186359
Short name T153
Test name
Test status
Simulation time 40118503 ps
CPU time 0.72 seconds
Started May 12 02:01:47 PM PDT 24
Finished May 12 02:01:49 PM PDT 24
Peak memory 204672 kb
Host smart-71910f3b-7c7f-4524-b562-b303bb590265
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570186359 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.3570186359
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.2728376636
Short name T155
Test name
Test status
Simulation time 62299787 ps
CPU time 0.76 seconds
Started May 12 02:01:47 PM PDT 24
Finished May 12 02:01:49 PM PDT 24
Peak memory 204748 kb
Host smart-8785edd8-c5e0-4d21-98ec-ef3b9f2cd568
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728376636 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.2728376636
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.1805989516
Short name T158
Test name
Test status
Simulation time 142524368 ps
CPU time 0.69 seconds
Started May 12 02:01:49 PM PDT 24
Finished May 12 02:01:50 PM PDT 24
Peak memory 204752 kb
Host smart-b27abe57-05ef-4fea-b94e-17ac7e05d7de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805989516 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.1805989516
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.93859738
Short name T40
Test name
Test status
Simulation time 196496748 ps
CPU time 0.79 seconds
Started May 12 02:01:55 PM PDT 24
Finished May 12 02:01:56 PM PDT 24
Peak memory 204752 kb
Host smart-df4b6c43-21e9-4b8a-903b-a6ccebe64da1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93859738 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.93859738
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.3303607590
Short name T58
Test name
Test status
Simulation time 36028280 ps
CPU time 0.74 seconds
Started May 12 02:01:51 PM PDT 24
Finished May 12 02:01:52 PM PDT 24
Peak memory 204748 kb
Host smart-72e33e45-3faa-4ee2-85a0-f19fbc27b4bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303607590 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.3303607590
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.897704822
Short name T165
Test name
Test status
Simulation time 47533621 ps
CPU time 0.75 seconds
Started May 12 02:01:54 PM PDT 24
Finished May 12 02:01:55 PM PDT 24
Peak memory 204748 kb
Host smart-a40e1bfd-972d-426f-ad09-77b0cb28067e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897704822 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.897704822
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.1319470508
Short name T145
Test name
Test status
Simulation time 30660091 ps
CPU time 0.75 seconds
Started May 12 02:01:55 PM PDT 24
Finished May 12 02:01:56 PM PDT 24
Peak memory 204664 kb
Host smart-b6cd3e5e-096f-4865-96bd-58678c56382f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319470508 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.1319470508
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.2150456057
Short name T169
Test name
Test status
Simulation time 26780569 ps
CPU time 0.7 seconds
Started May 12 02:01:55 PM PDT 24
Finished May 12 02:01:56 PM PDT 24
Peak memory 204756 kb
Host smart-97f72fa5-9ef3-4fc7-97b1-f8342dec9556
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150456057 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.2150456057
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.3953100134
Short name T55
Test name
Test status
Simulation time 134648912 ps
CPU time 0.7 seconds
Started May 12 02:01:58 PM PDT 24
Finished May 12 02:01:59 PM PDT 24
Peak memory 204752 kb
Host smart-00d57f0a-a9e3-4dff-8e1b-904ee4f041e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953100134 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.3953100134
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.3216200916
Short name T147
Test name
Test status
Simulation time 34797427 ps
CPU time 0.71 seconds
Started May 12 02:01:58 PM PDT 24
Finished May 12 02:02:00 PM PDT 24
Peak memory 204752 kb
Host smart-25c5bdc6-c36a-4b37-b68c-9aa396023eb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216200916 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.3216200916
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.1963175068
Short name T39
Test name
Test status
Simulation time 65151083 ps
CPU time 0.73 seconds
Started May 12 02:00:44 PM PDT 24
Finished May 12 02:00:45 PM PDT 24
Peak memory 204608 kb
Host smart-be9d1a02-2741-4422-b735-f85521fe400e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963175068 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.1963175068
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.2852416660
Short name T143
Test name
Test status
Simulation time 80154121 ps
CPU time 0.77 seconds
Started May 12 02:00:48 PM PDT 24
Finished May 12 02:00:49 PM PDT 24
Peak memory 204580 kb
Host smart-d58ff3ac-464f-4131-abef-c2c90f042524
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852416660 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.2852416660
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.5337878
Short name T57
Test name
Test status
Simulation time 22638038 ps
CPU time 0.75 seconds
Started May 12 02:00:49 PM PDT 24
Finished May 12 02:00:51 PM PDT 24
Peak memory 204688 kb
Host smart-fc023d07-0223-4f01-8224-70fa920f5a5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5337878 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.5337878
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.3782909791
Short name T61
Test name
Test status
Simulation time 45796015 ps
CPU time 0.75 seconds
Started May 12 02:00:54 PM PDT 24
Finished May 12 02:00:55 PM PDT 24
Peak memory 204720 kb
Host smart-3f54ea2d-439e-4f14-985f-06093f1c12b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782909791 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.3782909791
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.3462231098
Short name T144
Test name
Test status
Simulation time 252362758 ps
CPU time 0.71 seconds
Started May 12 02:00:54 PM PDT 24
Finished May 12 02:00:55 PM PDT 24
Peak memory 204744 kb
Host smart-efa69516-17a0-4101-aff8-38a4f4a8d1d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462231098 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.3462231098
Directory /workspace/9.rv_dm_alert_test/latest
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