SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
73.98 | 90.58 | 76.37 | 86.09 | 58.97 | 77.00 | 98.31 | 30.55 |
T55 | /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.3956959793 | May 14 12:44:55 PM PDT 24 | May 14 12:45:07 PM PDT 24 | 4184576895 ps | ||
T257 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.4119869675 | May 14 12:45:11 PM PDT 24 | May 14 12:48:14 PM PDT 24 | 56836139265 ps | ||
T258 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.652433841 | May 14 12:44:51 PM PDT 24 | May 14 12:45:24 PM PDT 24 | 12415930931 ps | ||
T113 | /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.4134620438 | May 14 12:45:19 PM PDT 24 | May 14 12:45:40 PM PDT 24 | 2051554872 ps | ||
T91 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.3112514079 | May 14 12:44:46 PM PDT 24 | May 14 12:44:51 PM PDT 24 | 53271592 ps | ||
T259 | /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.2324202120 | May 14 12:44:49 PM PDT 24 | May 14 12:44:55 PM PDT 24 | 685203519 ps | ||
T42 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.974707416 | May 14 12:44:47 PM PDT 24 | May 14 12:44:56 PM PDT 24 | 1203456366 ps | ||
T260 | /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.879771595 | May 14 12:45:22 PM PDT 24 | May 14 12:45:32 PM PDT 24 | 2536186858 ps | ||
T261 | /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.4083874720 | May 14 12:45:12 PM PDT 24 | May 14 12:45:18 PM PDT 24 | 346967098 ps | ||
T262 | /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1309518258 | May 14 12:45:20 PM PDT 24 | May 14 12:45:25 PM PDT 24 | 79760147 ps | ||
T263 | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.905228357 | May 14 12:45:06 PM PDT 24 | May 14 12:45:09 PM PDT 24 | 533858960 ps | ||
T264 | /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.1691689412 | May 14 12:45:14 PM PDT 24 | May 14 12:45:20 PM PDT 24 | 640181240 ps | ||
T265 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.154467830 | May 14 12:45:06 PM PDT 24 | May 14 12:45:07 PM PDT 24 | 48961131 ps | ||
T266 | /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2958838163 | May 14 12:44:45 PM PDT 24 | May 14 12:44:55 PM PDT 24 | 835670830 ps | ||
T56 | /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1804397121 | May 14 12:45:15 PM PDT 24 | May 14 12:45:28 PM PDT 24 | 2273402591 ps | ||
T267 | /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.3125359487 | May 14 12:44:59 PM PDT 24 | May 14 12:45:05 PM PDT 24 | 736063198 ps | ||
T268 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.2830434170 | May 14 12:44:54 PM PDT 24 | May 14 12:44:58 PM PDT 24 | 179260672 ps | ||
T101 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.3917836168 | May 14 12:44:46 PM PDT 24 | May 14 12:44:52 PM PDT 24 | 338506219 ps | ||
T269 | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.1330327622 | May 14 12:45:15 PM PDT 24 | May 14 12:45:19 PM PDT 24 | 954081533 ps | ||
T270 | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.4161356666 | May 14 12:45:12 PM PDT 24 | May 14 12:45:15 PM PDT 24 | 62079957 ps | ||
T271 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.57011509 | May 14 12:44:53 PM PDT 24 | May 14 12:45:26 PM PDT 24 | 7445583039 ps | ||
T272 | /workspace/coverage/cover_reg_top/15.rv_dm_tap_fsm_rand_reset.3590947129 | May 14 12:45:12 PM PDT 24 | May 14 12:45:33 PM PDT 24 | 9952627479 ps | ||
T273 | /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.3484049654 | May 14 12:45:18 PM PDT 24 | May 14 12:45:25 PM PDT 24 | 89400462 ps | ||
T274 | /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.3723111924 | May 14 12:45:00 PM PDT 24 | May 14 12:45:07 PM PDT 24 | 410277238 ps | ||
T275 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.1137513269 | May 14 12:44:50 PM PDT 24 | May 14 12:45:32 PM PDT 24 | 17674609212 ps | ||
T276 | /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.2589725644 | May 14 12:45:05 PM PDT 24 | May 14 12:45:10 PM PDT 24 | 505249515 ps | ||
T277 | /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.2914486854 | May 14 12:45:07 PM PDT 24 | May 14 12:45:11 PM PDT 24 | 295306128 ps |
Test location | /workspace/coverage/default/45.rv_dm_alert_test.3213817188 |
Short name | T17 |
Test name | |
Test status | |
Simulation time | 23931313 ps |
CPU time | 0.73 seconds |
Started | May 14 12:50:48 PM PDT 24 |
Finished | May 14 12:50:50 PM PDT 24 |
Peak memory | 204352 kb |
Host | smart-d27b3974-348c-4cf0-97a8-005436459958 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213817188 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.3213817188 |
Directory | /workspace/45.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/23.rv_dm_stress_all.3958626819 |
Short name | T4 |
Test name | |
Test status | |
Simulation time | 3868379257 ps |
CPU time | 14.3 seconds |
Started | May 14 12:50:12 PM PDT 24 |
Finished | May 14 12:50:28 PM PDT 24 |
Peak memory | 204544 kb |
Host | smart-303f1116-69ac-4288-95a4-5aed5fea513f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958626819 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.3958626819 |
Directory | /workspace/23.rv_dm_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3660770016 |
Short name | T26 |
Test name | |
Test status | |
Simulation time | 3309835808 ps |
CPU time | 6.78 seconds |
Started | May 14 12:44:56 PM PDT 24 |
Finished | May 14 12:45:04 PM PDT 24 |
Peak memory | 220076 kb |
Host | smart-45f6f870-a41e-4843-94d7-dcac82e64251 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660770016 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.3660770016 |
Directory | /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/default/0.rv_dm_tap_fsm.2228234532 |
Short name | T9 |
Test name | |
Test status | |
Simulation time | 2805371334 ps |
CPU time | 3.3 seconds |
Started | May 14 12:49:39 PM PDT 24 |
Finished | May 14 12:49:44 PM PDT 24 |
Peak memory | 204444 kb |
Host | smart-6574db2c-8bd2-4a45-87a8-030ce4517c89 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2228234532 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.2228234532 |
Directory | /workspace/0.rv_dm_tap_fsm/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.2506584563 |
Short name | T81 |
Test name | |
Test status | |
Simulation time | 2290637825 ps |
CPU time | 67.94 seconds |
Started | May 14 12:44:46 PM PDT 24 |
Finished | May 14 12:45:58 PM PDT 24 |
Peak memory | 218572 kb |
Host | smart-ae392612-7461-4d00-9ba6-3a480332c0b2 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506584563 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 0.rv_dm_csr_aliasing.2506584563 |
Directory | /workspace/0.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.212487520 |
Short name | T35 |
Test name | |
Test status | |
Simulation time | 828518549 ps |
CPU time | 2.51 seconds |
Started | May 14 12:44:53 PM PDT 24 |
Finished | May 14 12:44:58 PM PDT 24 |
Peak memory | 204564 kb |
Host | smart-165d9942-62de-4157-9f66-815b13753e62 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212487520 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr _hw_reset.212487520 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.1273604194 |
Short name | T66 |
Test name | |
Test status | |
Simulation time | 2100953493 ps |
CPU time | 10.61 seconds |
Started | May 14 12:45:18 PM PDT 24 |
Finished | May 14 12:45:30 PM PDT 24 |
Peak memory | 212812 kb |
Host | smart-5a1e4ca3-4b7e-4694-adaa-14b0a472540a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273604194 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.1 273604194 |
Directory | /workspace/15.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/40.rv_dm_stress_all.1259420541 |
Short name | T5 |
Test name | |
Test status | |
Simulation time | 1316773560 ps |
CPU time | 4.55 seconds |
Started | May 14 12:50:20 PM PDT 24 |
Finished | May 14 12:50:26 PM PDT 24 |
Peak memory | 204428 kb |
Host | smart-134a0b75-777f-47c5-91c4-bf125a35a32e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259420541 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.1259420541 |
Directory | /workspace/40.rv_dm_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/22.rv_dm_tap_fsm_rand_reset.1439665132 |
Short name | T53 |
Test name | |
Test status | |
Simulation time | 12920057678 ps |
CPU time | 13.61 seconds |
Started | May 14 12:45:32 PM PDT 24 |
Finished | May 14 12:45:48 PM PDT 24 |
Peak memory | 220008 kb |
Host | smart-2a7d0b01-1387-4d67-9b6c-6f90b2805c6a |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439665132 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 22.rv_dm_tap_fsm_rand_reset.1439665132 |
Directory | /workspace/22.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2710228075 |
Short name | T39 |
Test name | |
Test status | |
Simulation time | 71986679526 ps |
CPU time | 121.64 seconds |
Started | May 14 12:44:47 PM PDT 24 |
Finished | May 14 12:46:52 PM PDT 24 |
Peak memory | 204524 kb |
Host | smart-5153c13a-fc53-4841-8a84-72a202b287f3 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710228075 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_bit_bash.2710228075 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.4239275453 |
Short name | T54 |
Test name | |
Test status | |
Simulation time | 4397980651 ps |
CPU time | 20.02 seconds |
Started | May 14 12:44:47 PM PDT 24 |
Finished | May 14 12:45:11 PM PDT 24 |
Peak memory | 220952 kb |
Host | smart-550853ea-d67e-4505-9866-5dd2d26f6f6d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239275453 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.4239275453 |
Directory | /workspace/1.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.2076499493 |
Short name | T115 |
Test name | |
Test status | |
Simulation time | 2210190470 ps |
CPU time | 17.75 seconds |
Started | May 14 12:45:05 PM PDT 24 |
Finished | May 14 12:45:24 PM PDT 24 |
Peak memory | 212776 kb |
Host | smart-d7e90ef5-7486-414f-8bc3-8e1ff0f75e8b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076499493 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.2 076499493 |
Directory | /workspace/11.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.rv_dm_sec_cm.2222482608 |
Short name | T49 |
Test name | |
Test status | |
Simulation time | 219870952 ps |
CPU time | 1.65 seconds |
Started | May 14 12:49:43 PM PDT 24 |
Finished | May 14 12:49:47 PM PDT 24 |
Peak memory | 228488 kb |
Host | smart-813dd19e-4f80-4843-8dbb-77660a4992b4 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222482608 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.2222482608 |
Directory | /workspace/0.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/0.rv_dm_rom_read_access.1024547460 |
Short name | T13 |
Test name | |
Test status | |
Simulation time | 138254274 ps |
CPU time | 0.85 seconds |
Started | May 14 12:49:44 PM PDT 24 |
Finished | May 14 12:49:47 PM PDT 24 |
Peak memory | 212604 kb |
Host | smart-f239ec92-f280-494d-97ff-49e3b71b0a98 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1024547460 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.1024547460 |
Directory | /workspace/0.rv_dm_rom_read_access/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.4134620438 |
Short name | T113 |
Test name | |
Test status | |
Simulation time | 2051554872 ps |
CPU time | 18.89 seconds |
Started | May 14 12:45:19 PM PDT 24 |
Finished | May 14 12:45:40 PM PDT 24 |
Peak memory | 220876 kb |
Host | smart-78ec8981-298d-4988-b65f-ce610d895fdd |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134620438 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.4 134620438 |
Directory | /workspace/19.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3565227453 |
Short name | T57 |
Test name | |
Test status | |
Simulation time | 1689634241 ps |
CPU time | 8.16 seconds |
Started | May 14 12:45:14 PM PDT 24 |
Finished | May 14 12:45:25 PM PDT 24 |
Peak memory | 204608 kb |
Host | smart-51a7de82-75ec-4ea4-8343-62b2916e0a28 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565227453 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same _csr_outstanding.3565227453 |
Directory | /workspace/14.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_tap_fsm_rand_reset.1352964005 |
Short name | T105 |
Test name | |
Test status | |
Simulation time | 12744318094 ps |
CPU time | 18.85 seconds |
Started | May 14 12:45:13 PM PDT 24 |
Finished | May 14 12:45:35 PM PDT 24 |
Peak memory | 213824 kb |
Host | smart-eead0ae3-66cc-47eb-8fe4-83dd19197343 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352964005 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 16.rv_dm_tap_fsm_rand_reset.1352964005 |
Directory | /workspace/16.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/default/42.rv_dm_alert_test.3234942078 |
Short name | T44 |
Test name | |
Test status | |
Simulation time | 39412736 ps |
CPU time | 0.7 seconds |
Started | May 14 12:50:27 PM PDT 24 |
Finished | May 14 12:50:29 PM PDT 24 |
Peak memory | 204344 kb |
Host | smart-41aae368-8bf0-433a-9deb-b222e6dfb626 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234942078 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.3234942078 |
Directory | /workspace/42.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.3293149492 |
Short name | T7 |
Test name | |
Test status | |
Simulation time | 150588819 ps |
CPU time | 0.89 seconds |
Started | May 14 12:49:42 PM PDT 24 |
Finished | May 14 12:49:45 PM PDT 24 |
Peak memory | 204352 kb |
Host | smart-398ed7b7-98df-45d5-b9d4-193051a31b53 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3293149492 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.3293149492 |
Directory | /workspace/0.rv_dm_progbuf_read_write_execute/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.3112514079 |
Short name | T91 |
Test name | |
Test status | |
Simulation time | 53271592 ps |
CPU time | 1.52 seconds |
Started | May 14 12:44:46 PM PDT 24 |
Finished | May 14 12:44:51 PM PDT 24 |
Peak memory | 217996 kb |
Host | smart-6a7e4866-9271-4758-9d9c-0b507f7005de |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112514079 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.3112514079 |
Directory | /workspace/0.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.31734698 |
Short name | T34 |
Test name | |
Test status | |
Simulation time | 1480032205 ps |
CPU time | 1.63 seconds |
Started | May 14 12:44:46 PM PDT 24 |
Finished | May 14 12:44:51 PM PDT 24 |
Peak memory | 204368 kb |
Host | smart-7545031c-7e75-4eca-87a1-8ec96320fe03 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31734698 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_ hw_reset.31734698 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/default/31.rv_dm_stress_all.1707135803 |
Short name | T10 |
Test name | |
Test status | |
Simulation time | 7478188735 ps |
CPU time | 8.03 seconds |
Started | May 14 12:50:14 PM PDT 24 |
Finished | May 14 12:50:25 PM PDT 24 |
Peak memory | 212764 kb |
Host | smart-83239592-4511-4709-b6ad-d8bb6d2e5dfa |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707135803 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.1707135803 |
Directory | /workspace/31.rv_dm_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/39.rv_dm_tap_fsm_rand_reset.44705851 |
Short name | T58 |
Test name | |
Test status | |
Simulation time | 11788617354 ps |
CPU time | 40.3 seconds |
Started | May 14 12:45:34 PM PDT 24 |
Finished | May 14 12:46:18 PM PDT 24 |
Peak memory | 220388 kb |
Host | smart-c545c8cb-0e52-4cd1-90be-35a7a0c4df09 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44705851 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 39.rv_dm_tap_fsm_rand_reset.44705851 |
Directory | /workspace/39.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.2120631748 |
Short name | T111 |
Test name | |
Test status | |
Simulation time | 982428443 ps |
CPU time | 19.1 seconds |
Started | May 14 12:45:17 PM PDT 24 |
Finished | May 14 12:45:38 PM PDT 24 |
Peak memory | 221052 kb |
Host | smart-52e0f622-d501-4dae-b0c4-c3495db8d57c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120631748 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.2 120631748 |
Directory | /workspace/18.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.3799196104 |
Short name | T154 |
Test name | |
Test status | |
Simulation time | 4710910745 ps |
CPU time | 14.5 seconds |
Started | May 14 12:44:48 PM PDT 24 |
Finished | May 14 12:45:07 PM PDT 24 |
Peak memory | 204492 kb |
Host | smart-47b3ca30-4d3e-433c-9fc1-5f5e666d3044 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799196104 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_bit_bash.3799196104 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.3956959793 |
Short name | T55 |
Test name | |
Test status | |
Simulation time | 4184576895 ps |
CPU time | 10.09 seconds |
Started | May 14 12:44:55 PM PDT 24 |
Finished | May 14 12:45:07 PM PDT 24 |
Peak memory | 212736 kb |
Host | smart-f1de96ce-79bc-4888-9384-c11e7a2af2b7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956959793 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.3956959793 |
Directory | /workspace/6.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.296814355 |
Short name | T90 |
Test name | |
Test status | |
Simulation time | 207245273 ps |
CPU time | 1.6 seconds |
Started | May 14 12:45:16 PM PDT 24 |
Finished | May 14 12:45:20 PM PDT 24 |
Peak memory | 218320 kb |
Host | smart-0b95aa79-6c0a-4e59-b821-0f8f5d3c8a79 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296814355 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.296814355 |
Directory | /workspace/16.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.4083874720 |
Short name | T261 |
Test name | |
Test status | |
Simulation time | 346967098 ps |
CPU time | 3.95 seconds |
Started | May 14 12:45:12 PM PDT 24 |
Finished | May 14 12:45:18 PM PDT 24 |
Peak memory | 218260 kb |
Host | smart-73fc178e-43b6-4edb-8442-5ba7b110b13a |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083874720 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.4083874720 |
Directory | /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1804397121 |
Short name | T56 |
Test name | |
Test status | |
Simulation time | 2273402591 ps |
CPU time | 10.18 seconds |
Started | May 14 12:45:15 PM PDT 24 |
Finished | May 14 12:45:28 PM PDT 24 |
Peak memory | 220860 kb |
Host | smart-3c9936f6-9ced-4032-91e3-a57bd2d3fa85 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804397121 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.1 804397121 |
Directory | /workspace/13.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.1630590105 |
Short name | T254 |
Test name | |
Test status | |
Simulation time | 99734382 ps |
CPU time | 3.26 seconds |
Started | May 14 12:45:14 PM PDT 24 |
Finished | May 14 12:45:20 PM PDT 24 |
Peak memory | 212948 kb |
Host | smart-4cb64cee-1090-41cc-95d2-580e6ee53ae6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630590105 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.1630590105 |
Directory | /workspace/10.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.421383428 |
Short name | T106 |
Test name | |
Test status | |
Simulation time | 1256476015 ps |
CPU time | 9.99 seconds |
Started | May 14 12:45:09 PM PDT 24 |
Finished | May 14 12:45:27 PM PDT 24 |
Peak memory | 220940 kb |
Host | smart-832922c3-4027-4c52-ac47-f019c2bfeccd |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421383428 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.421383428 |
Directory | /workspace/14.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.1058874773 |
Short name | T93 |
Test name | |
Test status | |
Simulation time | 206454850 ps |
CPU time | 2.32 seconds |
Started | May 14 12:44:45 PM PDT 24 |
Finished | May 14 12:44:50 PM PDT 24 |
Peak memory | 212720 kb |
Host | smart-8444a0ca-4da8-4c2b-90e9-c09e79b65625 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058874773 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.1058874773 |
Directory | /workspace/0.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.863500431 |
Short name | T70 |
Test name | |
Test status | |
Simulation time | 274962064 ps |
CPU time | 3.67 seconds |
Started | May 14 12:44:49 PM PDT 24 |
Finished | May 14 12:44:56 PM PDT 24 |
Peak memory | 218032 kb |
Host | smart-3cd0cb35-5231-4ded-b3dc-ce36f6b452cd |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863500431 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.863500431 |
Directory | /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.749111471 |
Short name | T230 |
Test name | |
Test status | |
Simulation time | 8077385875 ps |
CPU time | 25.05 seconds |
Started | May 14 12:44:48 PM PDT 24 |
Finished | May 14 12:45:17 PM PDT 24 |
Peak memory | 204572 kb |
Host | smart-ae854082-7501-4c05-ba24-b3ebc8edd19f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749111471 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr _aliasing.749111471 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.3316833108 |
Short name | T207 |
Test name | |
Test status | |
Simulation time | 42666623348 ps |
CPU time | 41.4 seconds |
Started | May 14 12:44:46 PM PDT 24 |
Finished | May 14 12:45:31 PM PDT 24 |
Peak memory | 204532 kb |
Host | smart-74379938-4025-484e-a133-3f423d71fef9 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316833108 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_bit_bash.3316833108 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.4279171685 |
Short name | T37 |
Test name | |
Test status | |
Simulation time | 1692650369 ps |
CPU time | 2.87 seconds |
Started | May 14 12:44:50 PM PDT 24 |
Finished | May 14 12:44:57 PM PDT 24 |
Peak memory | 204576 kb |
Host | smart-3720dc9f-76fa-4463-b226-4cb3087510be |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279171685 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs r_hw_reset.4279171685 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.4244267588 |
Short name | T232 |
Test name | |
Test status | |
Simulation time | 298816865 ps |
CPU time | 1.06 seconds |
Started | May 14 12:44:50 PM PDT 24 |
Finished | May 14 12:44:55 PM PDT 24 |
Peak memory | 204408 kb |
Host | smart-fd1d8237-9b2b-4964-b46d-0707a0aaa40c |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244267588 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.4 244267588 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.1470833237 |
Short name | T212 |
Test name | |
Test status | |
Simulation time | 289206093 ps |
CPU time | 1.14 seconds |
Started | May 14 12:44:49 PM PDT 24 |
Finished | May 14 12:44:54 PM PDT 24 |
Peak memory | 204196 kb |
Host | smart-1d6f0ec4-fd42-49ec-bc7c-abea6bf45c6d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470833237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_aliasing.1470833237 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3940943412 |
Short name | T248 |
Test name | |
Test status | |
Simulation time | 60840927 ps |
CPU time | 0.8 seconds |
Started | May 14 12:44:47 PM PDT 24 |
Finished | May 14 12:44:52 PM PDT 24 |
Peak memory | 204252 kb |
Host | smart-5d6192c8-0d14-4831-9c84-a3a0b80de8dd |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940943412 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_hw_reset.3940943412 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.2991915010 |
Short name | T159 |
Test name | |
Test status | |
Simulation time | 45901527 ps |
CPU time | 0.7 seconds |
Started | May 14 12:44:50 PM PDT 24 |
Finished | May 14 12:44:54 PM PDT 24 |
Peak memory | 204220 kb |
Host | smart-17837759-f6de-4101-a39b-dcfff6b5dc2c |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991915010 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.2 991915010 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.2399942938 |
Short name | T203 |
Test name | |
Test status | |
Simulation time | 24799784 ps |
CPU time | 0.71 seconds |
Started | May 14 12:44:44 PM PDT 24 |
Finished | May 14 12:44:47 PM PDT 24 |
Peak memory | 204156 kb |
Host | smart-cfeb75cd-346f-4baa-a9b3-25234ab74bed |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399942938 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par tial_access.2399942938 |
Directory | /workspace/0.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.3867525725 |
Short name | T242 |
Test name | |
Test status | |
Simulation time | 174429263 ps |
CPU time | 0.67 seconds |
Started | May 14 12:44:48 PM PDT 24 |
Finished | May 14 12:44:52 PM PDT 24 |
Peak memory | 204256 kb |
Host | smart-f50be786-859b-4c2c-8317-0e920b840a89 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867525725 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.3867525725 |
Directory | /workspace/0.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.839254963 |
Short name | T201 |
Test name | |
Test status | |
Simulation time | 487809542 ps |
CPU time | 4 seconds |
Started | May 14 12:44:48 PM PDT 24 |
Finished | May 14 12:44:56 PM PDT 24 |
Peak memory | 204540 kb |
Host | smart-dcc530fa-f60a-4fee-8de5-4051acfdf301 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839254963 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_c sr_outstanding.839254963 |
Directory | /workspace/0.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.2324202120 |
Short name | T259 |
Test name | |
Test status | |
Simulation time | 685203519 ps |
CPU time | 2.43 seconds |
Started | May 14 12:44:49 PM PDT 24 |
Finished | May 14 12:44:55 PM PDT 24 |
Peak memory | 212784 kb |
Host | smart-6515019e-0953-49ea-b754-fc1af873576d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324202120 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.2324202120 |
Directory | /workspace/0.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.323771592 |
Short name | T71 |
Test name | |
Test status | |
Simulation time | 625756373 ps |
CPU time | 8.39 seconds |
Started | May 14 12:44:47 PM PDT 24 |
Finished | May 14 12:45:03 PM PDT 24 |
Peak memory | 220976 kb |
Host | smart-4674368a-d4f4-4b31-a713-b61027db7a0e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323771592 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.323771592 |
Directory | /workspace/0.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1236443721 |
Short name | T74 |
Test name | |
Test status | |
Simulation time | 560720998 ps |
CPU time | 25.16 seconds |
Started | May 14 12:44:49 PM PDT 24 |
Finished | May 14 12:45:17 PM PDT 24 |
Peak memory | 212724 kb |
Host | smart-9dbce064-a127-465c-9db0-3277d3804ece |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236443721 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 1.rv_dm_csr_aliasing.1236443721 |
Directory | /workspace/1.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.3304247484 |
Short name | T140 |
Test name | |
Test status | |
Simulation time | 12881661047 ps |
CPU time | 33.97 seconds |
Started | May 14 12:44:46 PM PDT 24 |
Finished | May 14 12:45:22 PM PDT 24 |
Peak memory | 204668 kb |
Host | smart-58e95add-8b30-4cea-a2d9-a731cfb5b2ba |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304247484 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.3304247484 |
Directory | /workspace/1.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.3308845832 |
Short name | T94 |
Test name | |
Test status | |
Simulation time | 352226370 ps |
CPU time | 2.57 seconds |
Started | May 14 12:44:47 PM PDT 24 |
Finished | May 14 12:44:53 PM PDT 24 |
Peak memory | 212744 kb |
Host | smart-dac2a12e-5c2b-4039-998d-d193f2d68c5d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308845832 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.3308845832 |
Directory | /workspace/1.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.861710698 |
Short name | T237 |
Test name | |
Test status | |
Simulation time | 673229770 ps |
CPU time | 3.76 seconds |
Started | May 14 12:44:50 PM PDT 24 |
Finished | May 14 12:44:57 PM PDT 24 |
Peak memory | 218120 kb |
Host | smart-b0d8b10b-76f3-45f7-8061-ed2fdcb9389e |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861710698 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.861710698 |
Directory | /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.3269997275 |
Short name | T31 |
Test name | |
Test status | |
Simulation time | 43607794 ps |
CPU time | 2.12 seconds |
Started | May 14 12:44:50 PM PDT 24 |
Finished | May 14 12:44:56 PM PDT 24 |
Peak memory | 212764 kb |
Host | smart-6e0e5b65-7e4e-4824-8734-f4592889f435 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269997275 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.3269997275 |
Directory | /workspace/1.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1086689322 |
Short name | T161 |
Test name | |
Test status | |
Simulation time | 8943472354 ps |
CPU time | 32.53 seconds |
Started | May 14 12:44:47 PM PDT 24 |
Finished | May 14 12:45:24 PM PDT 24 |
Peak memory | 204584 kb |
Host | smart-9d2ab29d-9c31-4f60-818a-14cd4ee3ca83 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086689322 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs r_aliasing.1086689322 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.3107995141 |
Short name | T233 |
Test name | |
Test status | |
Simulation time | 253236672 ps |
CPU time | 1.27 seconds |
Started | May 14 12:44:47 PM PDT 24 |
Finished | May 14 12:44:52 PM PDT 24 |
Peak memory | 204504 kb |
Host | smart-cc3cf2ac-f4c6-4ccd-8265-b72274dc0d0b |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107995141 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.3 107995141 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2825058273 |
Short name | T179 |
Test name | |
Test status | |
Simulation time | 78489485 ps |
CPU time | 0.71 seconds |
Started | May 14 12:44:46 PM PDT 24 |
Finished | May 14 12:44:51 PM PDT 24 |
Peak memory | 204576 kb |
Host | smart-903e106e-ade4-483c-b803-fdd413e927e8 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825058273 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_aliasing.2825058273 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2319734191 |
Short name | T153 |
Test name | |
Test status | |
Simulation time | 2638851717 ps |
CPU time | 3.6 seconds |
Started | May 14 12:44:47 PM PDT 24 |
Finished | May 14 12:44:54 PM PDT 24 |
Peak memory | 204428 kb |
Host | smart-15e35672-1387-45b4-9ace-04b26a20b0a5 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319734191 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_bit_bash.2319734191 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2575865879 |
Short name | T226 |
Test name | |
Test status | |
Simulation time | 116579293 ps |
CPU time | 0.75 seconds |
Started | May 14 12:44:53 PM PDT 24 |
Finished | May 14 12:44:56 PM PDT 24 |
Peak memory | 204264 kb |
Host | smart-83007127-7b04-4a34-83ff-ae7f0dfb5dfe |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575865879 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_hw_reset.2575865879 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3920483579 |
Short name | T228 |
Test name | |
Test status | |
Simulation time | 125559479 ps |
CPU time | 0.72 seconds |
Started | May 14 12:44:46 PM PDT 24 |
Finished | May 14 12:44:51 PM PDT 24 |
Peak memory | 204184 kb |
Host | smart-d35bab71-e95f-4c39-a789-6b3bc4bcfbb9 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920483579 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.3 920483579 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1435435360 |
Short name | T174 |
Test name | |
Test status | |
Simulation time | 31834031 ps |
CPU time | 0.71 seconds |
Started | May 14 12:44:51 PM PDT 24 |
Finished | May 14 12:44:55 PM PDT 24 |
Peak memory | 204260 kb |
Host | smart-294a9f22-548f-458b-8c28-29b03fd95df6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435435360 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par tial_access.1435435360 |
Directory | /workspace/1.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.2433888102 |
Short name | T222 |
Test name | |
Test status | |
Simulation time | 29152084 ps |
CPU time | 0.65 seconds |
Started | May 14 12:44:48 PM PDT 24 |
Finished | May 14 12:44:52 PM PDT 24 |
Peak memory | 204168 kb |
Host | smart-88bb957a-1556-4e93-a501-bd8d005666eb |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433888102 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.2433888102 |
Directory | /workspace/1.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2958838163 |
Short name | T266 |
Test name | |
Test status | |
Simulation time | 835670830 ps |
CPU time | 7.17 seconds |
Started | May 14 12:44:45 PM PDT 24 |
Finished | May 14 12:44:55 PM PDT 24 |
Peak memory | 204488 kb |
Host | smart-26c96003-06bd-4f88-9ef0-3c55139a02e0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958838163 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_ csr_outstanding.2958838163 |
Directory | /workspace/1.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.2030683102 |
Short name | T183 |
Test name | |
Test status | |
Simulation time | 777642586 ps |
CPU time | 4.8 seconds |
Started | May 14 12:44:48 PM PDT 24 |
Finished | May 14 12:44:56 PM PDT 24 |
Peak memory | 215292 kb |
Host | smart-dacba08b-5335-4863-8c9c-0b8c53bce7a2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030683102 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.2030683102 |
Directory | /workspace/1.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.1057366513 |
Short name | T221 |
Test name | |
Test status | |
Simulation time | 1837292719 ps |
CPU time | 3.9 seconds |
Started | May 14 12:45:10 PM PDT 24 |
Finished | May 14 12:45:17 PM PDT 24 |
Peak memory | 212820 kb |
Host | smart-6d81877d-ac3e-42db-bbd9-f7838b2484cc |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057366513 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.1057366513 |
Directory | /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.3759774785 |
Short name | T171 |
Test name | |
Test status | |
Simulation time | 275664376 ps |
CPU time | 1.73 seconds |
Started | May 14 12:44:57 PM PDT 24 |
Finished | May 14 12:45:01 PM PDT 24 |
Peak memory | 217636 kb |
Host | smart-9e9e0b91-e222-41e5-9638-6211aa0fb0b1 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759774785 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.3759774785 |
Directory | /workspace/10.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.905228357 |
Short name | T263 |
Test name | |
Test status | |
Simulation time | 533858960 ps |
CPU time | 2.56 seconds |
Started | May 14 12:45:06 PM PDT 24 |
Finished | May 14 12:45:09 PM PDT 24 |
Peak memory | 204388 kb |
Host | smart-3002873c-ed75-4631-b706-a032f5087fa4 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905228357 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.905228357 |
Directory | /workspace/10.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.4031994930 |
Short name | T152 |
Test name | |
Test status | |
Simulation time | 231629050 ps |
CPU time | 0.71 seconds |
Started | May 14 12:45:07 PM PDT 24 |
Finished | May 14 12:45:09 PM PDT 24 |
Peak memory | 204292 kb |
Host | smart-d4649f92-4652-4ae1-b5a5-e2e25e2b78f1 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031994930 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw. 4031994930 |
Directory | /workspace/10.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3588426607 |
Short name | T256 |
Test name | |
Test status | |
Simulation time | 257690830 ps |
CPU time | 4 seconds |
Started | May 14 12:45:07 PM PDT 24 |
Finished | May 14 12:45:12 PM PDT 24 |
Peak memory | 204608 kb |
Host | smart-ece60653-ef19-451f-8bbe-a53379394a21 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588426607 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same _csr_outstanding.3588426607 |
Directory | /workspace/10.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_tap_fsm_rand_reset.518979922 |
Short name | T238 |
Test name | |
Test status | |
Simulation time | 11344520102 ps |
CPU time | 18.95 seconds |
Started | May 14 12:45:14 PM PDT 24 |
Finished | May 14 12:45:35 PM PDT 24 |
Peak memory | 214920 kb |
Host | smart-ad6da699-c0f2-4aa4-93e3-1c82916a6229 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518979922 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 10.rv_dm_tap_fsm_rand_reset.518979922 |
Directory | /workspace/10.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1458803374 |
Short name | T112 |
Test name | |
Test status | |
Simulation time | 467971294 ps |
CPU time | 15.82 seconds |
Started | May 14 12:44:56 PM PDT 24 |
Finished | May 14 12:45:13 PM PDT 24 |
Peak memory | 220880 kb |
Host | smart-5e0eae87-4dce-4984-9421-5bbb993d752a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458803374 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.1 458803374 |
Directory | /workspace/10.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3673597993 |
Short name | T163 |
Test name | |
Test status | |
Simulation time | 3216965868 ps |
CPU time | 4.68 seconds |
Started | May 14 12:45:11 PM PDT 24 |
Finished | May 14 12:45:18 PM PDT 24 |
Peak memory | 221164 kb |
Host | smart-2c75b1e2-097d-4ae9-8c49-b3b4fee1e5a1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673597993 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.3673597993 |
Directory | /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.1779409790 |
Short name | T251 |
Test name | |
Test status | |
Simulation time | 192854870 ps |
CPU time | 1.45 seconds |
Started | May 14 12:45:05 PM PDT 24 |
Finished | May 14 12:45:08 PM PDT 24 |
Peak memory | 218064 kb |
Host | smart-4f52326d-f391-4afa-8098-0ec0c56e5a1a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779409790 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.1779409790 |
Directory | /workspace/11.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.2872347061 |
Short name | T41 |
Test name | |
Test status | |
Simulation time | 421658153 ps |
CPU time | 1.7 seconds |
Started | May 14 12:45:05 PM PDT 24 |
Finished | May 14 12:45:08 PM PDT 24 |
Peak memory | 204452 kb |
Host | smart-6e8a06ef-d5c6-4ff2-bed8-1d903f314556 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872347061 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw. 2872347061 |
Directory | /workspace/11.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.2396993580 |
Short name | T243 |
Test name | |
Test status | |
Simulation time | 95530426 ps |
CPU time | 0.96 seconds |
Started | May 14 12:45:07 PM PDT 24 |
Finished | May 14 12:45:09 PM PDT 24 |
Peak memory | 204244 kb |
Host | smart-e78e0749-eab9-415d-8bb9-e19f45be43f8 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396993580 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw. 2396993580 |
Directory | /workspace/11.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.780215464 |
Short name | T255 |
Test name | |
Test status | |
Simulation time | 276018775 ps |
CPU time | 4.15 seconds |
Started | May 14 12:44:58 PM PDT 24 |
Finished | May 14 12:45:05 PM PDT 24 |
Peak memory | 204512 kb |
Host | smart-bd45e6d5-26b6-4a2e-b952-c03303a73f2a |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780215464 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same_ csr_outstanding.780215464 |
Directory | /workspace/11.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.2589725644 |
Short name | T276 |
Test name | |
Test status | |
Simulation time | 505249515 ps |
CPU time | 3.75 seconds |
Started | May 14 12:45:05 PM PDT 24 |
Finished | May 14 12:45:10 PM PDT 24 |
Peak memory | 212796 kb |
Host | smart-90212795-349d-4ee4-949b-cff986f3d4e1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589725644 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.2589725644 |
Directory | /workspace/11.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.2650722674 |
Short name | T229 |
Test name | |
Test status | |
Simulation time | 179410013 ps |
CPU time | 2.14 seconds |
Started | May 14 12:45:11 PM PDT 24 |
Finished | May 14 12:45:15 PM PDT 24 |
Peak memory | 212788 kb |
Host | smart-75c5ebb2-b62b-4081-a14b-3a855b92eb55 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650722674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.2650722674 |
Directory | /workspace/12.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.3463569373 |
Short name | T38 |
Test name | |
Test status | |
Simulation time | 1082743742 ps |
CPU time | 4.14 seconds |
Started | May 14 12:45:17 PM PDT 24 |
Finished | May 14 12:45:24 PM PDT 24 |
Peak memory | 204424 kb |
Host | smart-bd4ec6cc-332c-49cf-83fc-a2f1da3e9ab1 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463569373 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw. 3463569373 |
Directory | /workspace/12.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.370984491 |
Short name | T240 |
Test name | |
Test status | |
Simulation time | 53253577 ps |
CPU time | 0.68 seconds |
Started | May 14 12:45:10 PM PDT 24 |
Finished | May 14 12:45:14 PM PDT 24 |
Peak memory | 204236 kb |
Host | smart-41908bf4-7419-40af-a5f5-ada32b4e58a8 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370984491 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.370984491 |
Directory | /workspace/12.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.2624988749 |
Short name | T85 |
Test name | |
Test status | |
Simulation time | 213600639 ps |
CPU time | 4.03 seconds |
Started | May 14 12:45:27 PM PDT 24 |
Finished | May 14 12:45:32 PM PDT 24 |
Peak memory | 204520 kb |
Host | smart-c578be01-c405-463f-a714-6e98f09b6bba |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624988749 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same _csr_outstanding.2624988749 |
Directory | /workspace/12.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_tap_fsm_rand_reset.863649499 |
Short name | T189 |
Test name | |
Test status | |
Simulation time | 25929953748 ps |
CPU time | 27.93 seconds |
Started | May 14 12:45:33 PM PDT 24 |
Finished | May 14 12:46:03 PM PDT 24 |
Peak memory | 229232 kb |
Host | smart-ca78fd29-552e-45bd-8612-e72f8fe10c75 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863649499 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 12.rv_dm_tap_fsm_rand_reset.863649499 |
Directory | /workspace/12.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.1297384125 |
Short name | T245 |
Test name | |
Test status | |
Simulation time | 908271178 ps |
CPU time | 3.48 seconds |
Started | May 14 12:45:15 PM PDT 24 |
Finished | May 14 12:45:21 PM PDT 24 |
Peak memory | 212844 kb |
Host | smart-74630cad-e748-4fbd-92b8-6d6198c413b8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297384125 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.1297384125 |
Directory | /workspace/12.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2111506067 |
Short name | T114 |
Test name | |
Test status | |
Simulation time | 431715113 ps |
CPU time | 8.53 seconds |
Started | May 14 12:45:06 PM PDT 24 |
Finished | May 14 12:45:16 PM PDT 24 |
Peak memory | 221088 kb |
Host | smart-ac063363-77c2-4d17-99f3-6b6410d8a141 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111506067 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.2 111506067 |
Directory | /workspace/12.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.1323982602 |
Short name | T78 |
Test name | |
Test status | |
Simulation time | 259444308 ps |
CPU time | 3.57 seconds |
Started | May 14 12:45:13 PM PDT 24 |
Finished | May 14 12:45:20 PM PDT 24 |
Peak memory | 217836 kb |
Host | smart-f6925068-29f9-48da-a4b0-6ac4ce0c3d9f |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323982602 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.1323982602 |
Directory | /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.621873456 |
Short name | T82 |
Test name | |
Test status | |
Simulation time | 52618343 ps |
CPU time | 1.51 seconds |
Started | May 14 12:45:08 PM PDT 24 |
Finished | May 14 12:45:12 PM PDT 24 |
Peak memory | 212776 kb |
Host | smart-7dc6935e-7511-46ab-aefc-975fa70c4e47 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621873456 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.621873456 |
Directory | /workspace/13.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.1330327622 |
Short name | T269 |
Test name | |
Test status | |
Simulation time | 954081533 ps |
CPU time | 1.56 seconds |
Started | May 14 12:45:15 PM PDT 24 |
Finished | May 14 12:45:19 PM PDT 24 |
Peak memory | 204568 kb |
Host | smart-5c8dc17c-09a0-49d6-a1c0-372fcb424867 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330327622 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw. 1330327622 |
Directory | /workspace/13.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1432485961 |
Short name | T158 |
Test name | |
Test status | |
Simulation time | 57193689 ps |
CPU time | 0.78 seconds |
Started | May 14 12:45:07 PM PDT 24 |
Finished | May 14 12:45:10 PM PDT 24 |
Peak memory | 204168 kb |
Host | smart-abd4069b-9ff1-41d7-ac34-8590895f505b |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432485961 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw. 1432485961 |
Directory | /workspace/13.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2692642669 |
Short name | T87 |
Test name | |
Test status | |
Simulation time | 2062017272 ps |
CPU time | 7.61 seconds |
Started | May 14 12:45:32 PM PDT 24 |
Finished | May 14 12:45:41 PM PDT 24 |
Peak memory | 204660 kb |
Host | smart-7cc86c09-4b40-4af5-b2e8-fe8d84c002dd |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692642669 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same _csr_outstanding.2692642669 |
Directory | /workspace/13.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.3306102830 |
Short name | T79 |
Test name | |
Test status | |
Simulation time | 254076291 ps |
CPU time | 5.17 seconds |
Started | May 14 12:45:23 PM PDT 24 |
Finished | May 14 12:45:31 PM PDT 24 |
Peak memory | 212732 kb |
Host | smart-bbbb2873-a0c4-4d0c-9c7b-17b52c9d7c53 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306102830 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.3306102830 |
Directory | /workspace/13.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.869331233 |
Short name | T195 |
Test name | |
Test status | |
Simulation time | 347803357 ps |
CPU time | 3.94 seconds |
Started | May 14 12:45:27 PM PDT 24 |
Finished | May 14 12:45:32 PM PDT 24 |
Peak memory | 220952 kb |
Host | smart-942dfa0b-4fb2-4c72-947c-dbadc9b9c943 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869331233 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.869331233 |
Directory | /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.4150041828 |
Short name | T98 |
Test name | |
Test status | |
Simulation time | 154519252 ps |
CPU time | 2.29 seconds |
Started | May 14 12:45:26 PM PDT 24 |
Finished | May 14 12:45:29 PM PDT 24 |
Peak memory | 212716 kb |
Host | smart-07d43fd7-751e-465a-b7e0-e2fb7235f382 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150041828 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.4150041828 |
Directory | /workspace/14.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.152676310 |
Short name | T151 |
Test name | |
Test status | |
Simulation time | 746579270 ps |
CPU time | 1.97 seconds |
Started | May 14 12:45:20 PM PDT 24 |
Finished | May 14 12:45:23 PM PDT 24 |
Peak memory | 204264 kb |
Host | smart-9738da16-bd36-419c-9224-938f26276131 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152676310 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.152676310 |
Directory | /workspace/14.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.15718314 |
Short name | T241 |
Test name | |
Test status | |
Simulation time | 36544652 ps |
CPU time | 0.74 seconds |
Started | May 14 12:45:19 PM PDT 24 |
Finished | May 14 12:45:22 PM PDT 24 |
Peak memory | 204240 kb |
Host | smart-20bb8f13-99fa-4889-9800-48c98d3a727a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15718314 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.15718314 |
Directory | /workspace/14.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.1853040078 |
Short name | T224 |
Test name | |
Test status | |
Simulation time | 52862255 ps |
CPU time | 2.55 seconds |
Started | May 14 12:45:18 PM PDT 24 |
Finished | May 14 12:45:22 PM PDT 24 |
Peak memory | 212916 kb |
Host | smart-0357545e-8c4c-4f5e-98c4-ad735ace4b4b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853040078 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.1853040078 |
Directory | /workspace/14.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1975316516 |
Short name | T28 |
Test name | |
Test status | |
Simulation time | 2060550096 ps |
CPU time | 6.38 seconds |
Started | May 14 12:45:16 PM PDT 24 |
Finished | May 14 12:45:25 PM PDT 24 |
Peak memory | 217188 kb |
Host | smart-dab4994c-01b7-4a03-9aee-816d32e7393b |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975316516 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.1975316516 |
Directory | /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.1350041661 |
Short name | T227 |
Test name | |
Test status | |
Simulation time | 62700603 ps |
CPU time | 1.51 seconds |
Started | May 14 12:45:18 PM PDT 24 |
Finished | May 14 12:45:21 PM PDT 24 |
Peak memory | 220856 kb |
Host | smart-070278c4-fadd-4803-8c13-b5ba1fd4fcdd |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350041661 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.1350041661 |
Directory | /workspace/15.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.1717136319 |
Short name | T236 |
Test name | |
Test status | |
Simulation time | 307973036 ps |
CPU time | 1.66 seconds |
Started | May 14 12:45:12 PM PDT 24 |
Finished | May 14 12:45:17 PM PDT 24 |
Peak memory | 204476 kb |
Host | smart-c459dd23-6113-4dc6-85fc-bffe2b4e5c55 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717136319 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw. 1717136319 |
Directory | /workspace/15.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3672555726 |
Short name | T168 |
Test name | |
Test status | |
Simulation time | 29894509 ps |
CPU time | 0.75 seconds |
Started | May 14 12:45:20 PM PDT 24 |
Finished | May 14 12:45:22 PM PDT 24 |
Peak memory | 204572 kb |
Host | smart-347b8c4b-b8be-4798-aedc-027b08d5dcc2 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672555726 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw. 3672555726 |
Directory | /workspace/15.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.1889832441 |
Short name | T204 |
Test name | |
Test status | |
Simulation time | 810661877 ps |
CPU time | 4.31 seconds |
Started | May 14 12:45:08 PM PDT 24 |
Finished | May 14 12:45:16 PM PDT 24 |
Peak memory | 204628 kb |
Host | smart-d456e6ce-b6b2-44da-af2d-e80fa95b9d67 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889832441 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same _csr_outstanding.1889832441 |
Directory | /workspace/15.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_tap_fsm_rand_reset.3590947129 |
Short name | T272 |
Test name | |
Test status | |
Simulation time | 9952627479 ps |
CPU time | 18.17 seconds |
Started | May 14 12:45:12 PM PDT 24 |
Finished | May 14 12:45:33 PM PDT 24 |
Peak memory | 214716 kb |
Host | smart-89ab6e79-73b7-44fa-a6d4-9d0dec71f9eb |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590947129 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 15.rv_dm_tap_fsm_rand_reset.3590947129 |
Directory | /workspace/15.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.491561782 |
Short name | T244 |
Test name | |
Test status | |
Simulation time | 110047162 ps |
CPU time | 3.18 seconds |
Started | May 14 12:45:14 PM PDT 24 |
Finished | May 14 12:45:20 PM PDT 24 |
Peak memory | 212804 kb |
Host | smart-c24437d6-455a-4201-bd60-e76bfc229f63 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491561782 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.491561782 |
Directory | /workspace/15.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.966578515 |
Short name | T176 |
Test name | |
Test status | |
Simulation time | 945586084 ps |
CPU time | 3.38 seconds |
Started | May 14 12:45:18 PM PDT 24 |
Finished | May 14 12:45:24 PM PDT 24 |
Peak memory | 218376 kb |
Host | smart-81fa7344-3eba-4807-9624-826a579f5fdc |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966578515 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.966578515 |
Directory | /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.3427090138 |
Short name | T166 |
Test name | |
Test status | |
Simulation time | 2370806107 ps |
CPU time | 1.75 seconds |
Started | May 14 12:45:11 PM PDT 24 |
Finished | May 14 12:45:16 PM PDT 24 |
Peak memory | 204604 kb |
Host | smart-83bcb9de-4ee3-4bb6-a346-52664f6f6a7f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427090138 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw. 3427090138 |
Directory | /workspace/16.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.1853985241 |
Short name | T197 |
Test name | |
Test status | |
Simulation time | 59240326 ps |
CPU time | 0.84 seconds |
Started | May 14 12:45:13 PM PDT 24 |
Finished | May 14 12:45:17 PM PDT 24 |
Peak memory | 204256 kb |
Host | smart-48fa8729-0165-41bd-8299-d4f817c9670f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853985241 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw. 1853985241 |
Directory | /workspace/16.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1309518258 |
Short name | T262 |
Test name | |
Test status | |
Simulation time | 79760147 ps |
CPU time | 3.45 seconds |
Started | May 14 12:45:20 PM PDT 24 |
Finished | May 14 12:45:25 PM PDT 24 |
Peak memory | 204484 kb |
Host | smart-1a4fa918-6f10-42ed-ac02-fd3605f349ee |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309518258 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same _csr_outstanding.1309518258 |
Directory | /workspace/16.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.997345908 |
Short name | T225 |
Test name | |
Test status | |
Simulation time | 610936329 ps |
CPU time | 4.24 seconds |
Started | May 14 12:45:15 PM PDT 24 |
Finished | May 14 12:45:22 PM PDT 24 |
Peak memory | 212764 kb |
Host | smart-2e9f250f-3f3b-4d6b-8bf4-607b049c1b4b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997345908 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.997345908 |
Directory | /workspace/16.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.1675950729 |
Short name | T116 |
Test name | |
Test status | |
Simulation time | 1676916028 ps |
CPU time | 17.77 seconds |
Started | May 14 12:45:08 PM PDT 24 |
Finished | May 14 12:45:29 PM PDT 24 |
Peak memory | 221320 kb |
Host | smart-7132e617-89fa-4a7d-852e-0092c662ff15 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675950729 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.1 675950729 |
Directory | /workspace/16.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2197082145 |
Short name | T198 |
Test name | |
Test status | |
Simulation time | 1213710100 ps |
CPU time | 4.6 seconds |
Started | May 14 12:45:15 PM PDT 24 |
Finished | May 14 12:45:22 PM PDT 24 |
Peak memory | 217748 kb |
Host | smart-ea9a76de-2457-4794-92c3-02faa83f090b |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197082145 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.2197082145 |
Directory | /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.3500239219 |
Short name | T77 |
Test name | |
Test status | |
Simulation time | 234729989 ps |
CPU time | 1.6 seconds |
Started | May 14 12:45:08 PM PDT 24 |
Finished | May 14 12:45:11 PM PDT 24 |
Peak memory | 212832 kb |
Host | smart-8479572b-b32c-468d-8892-a10310fb5e5f |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500239219 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.3500239219 |
Directory | /workspace/17.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.174258078 |
Short name | T172 |
Test name | |
Test status | |
Simulation time | 325762573 ps |
CPU time | 1.01 seconds |
Started | May 14 12:45:16 PM PDT 24 |
Finished | May 14 12:45:20 PM PDT 24 |
Peak memory | 204460 kb |
Host | smart-0adc45eb-ac61-4f1e-8d9a-295ac7b4946f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174258078 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.174258078 |
Directory | /workspace/17.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.648339905 |
Short name | T223 |
Test name | |
Test status | |
Simulation time | 62812339 ps |
CPU time | 0.71 seconds |
Started | May 14 12:45:28 PM PDT 24 |
Finished | May 14 12:45:30 PM PDT 24 |
Peak memory | 204336 kb |
Host | smart-afad9494-badf-4dfa-ae75-f3cb81e5bcfd |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648339905 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.648339905 |
Directory | /workspace/17.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.1691689412 |
Short name | T264 |
Test name | |
Test status | |
Simulation time | 640181240 ps |
CPU time | 3.75 seconds |
Started | May 14 12:45:14 PM PDT 24 |
Finished | May 14 12:45:20 PM PDT 24 |
Peak memory | 204640 kb |
Host | smart-5116be78-7693-4a43-9dbd-c1d1e8c347ca |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691689412 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same _csr_outstanding.1691689412 |
Directory | /workspace/17.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_tap_fsm_rand_reset.3865962925 |
Short name | T205 |
Test name | |
Test status | |
Simulation time | 9108550099 ps |
CPU time | 16.59 seconds |
Started | May 14 12:45:17 PM PDT 24 |
Finished | May 14 12:45:36 PM PDT 24 |
Peak memory | 213700 kb |
Host | smart-67a5d07c-d171-4a80-8126-447849361608 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865962925 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 17.rv_dm_tap_fsm_rand_reset.3865962925 |
Directory | /workspace/17.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.3484049654 |
Short name | T273 |
Test name | |
Test status | |
Simulation time | 89400462 ps |
CPU time | 4.3 seconds |
Started | May 14 12:45:18 PM PDT 24 |
Finished | May 14 12:45:25 PM PDT 24 |
Peak memory | 212760 kb |
Host | smart-6648f3c2-b4b5-481b-aa0a-09801cacd250 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484049654 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.3484049654 |
Directory | /workspace/17.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.99011612 |
Short name | T103 |
Test name | |
Test status | |
Simulation time | 4255611130 ps |
CPU time | 19.08 seconds |
Started | May 14 12:45:15 PM PDT 24 |
Finished | May 14 12:45:37 PM PDT 24 |
Peak memory | 212836 kb |
Host | smart-e17fc773-6192-47c6-8132-60542f078d7b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99011612 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.99011612 |
Directory | /workspace/17.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.1876147864 |
Short name | T231 |
Test name | |
Test status | |
Simulation time | 191643993 ps |
CPU time | 3.24 seconds |
Started | May 14 12:45:22 PM PDT 24 |
Finished | May 14 12:45:27 PM PDT 24 |
Peak memory | 218048 kb |
Host | smart-0bc46572-3e09-4b0f-8b62-0a171f8d77b9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876147864 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.1876147864 |
Directory | /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2750029911 |
Short name | T30 |
Test name | |
Test status | |
Simulation time | 226474860 ps |
CPU time | 1.67 seconds |
Started | May 14 12:45:26 PM PDT 24 |
Finished | May 14 12:45:29 PM PDT 24 |
Peak memory | 212788 kb |
Host | smart-979d24c8-031e-4f51-859c-9b162b384e67 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750029911 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.2750029911 |
Directory | /workspace/18.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.3974743199 |
Short name | T160 |
Test name | |
Test status | |
Simulation time | 313240944 ps |
CPU time | 1.51 seconds |
Started | May 14 12:45:13 PM PDT 24 |
Finished | May 14 12:45:17 PM PDT 24 |
Peak memory | 204528 kb |
Host | smart-fadbe903-3c35-4610-ad53-4dbaea0fbee4 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974743199 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw. 3974743199 |
Directory | /workspace/18.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.4161356666 |
Short name | T270 |
Test name | |
Test status | |
Simulation time | 62079957 ps |
CPU time | 0.66 seconds |
Started | May 14 12:45:12 PM PDT 24 |
Finished | May 14 12:45:15 PM PDT 24 |
Peak memory | 204176 kb |
Host | smart-06e191d3-56b5-4a00-8e1b-a7d69230bea4 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161356666 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw. 4161356666 |
Directory | /workspace/18.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.879771595 |
Short name | T260 |
Test name | |
Test status | |
Simulation time | 2536186858 ps |
CPU time | 8.79 seconds |
Started | May 14 12:45:22 PM PDT 24 |
Finished | May 14 12:45:32 PM PDT 24 |
Peak memory | 204584 kb |
Host | smart-723ac110-b55f-4d7b-b79c-178c4a607679 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879771595 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same_ csr_outstanding.879771595 |
Directory | /workspace/18.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.979444176 |
Short name | T29 |
Test name | |
Test status | |
Simulation time | 74649253 ps |
CPU time | 4.08 seconds |
Started | May 14 12:45:29 PM PDT 24 |
Finished | May 14 12:45:34 PM PDT 24 |
Peak memory | 212808 kb |
Host | smart-0a8e5570-6a4f-4162-a96c-7813066ecdb1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979444176 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.979444176 |
Directory | /workspace/18.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1950342968 |
Short name | T68 |
Test name | |
Test status | |
Simulation time | 9009971557 ps |
CPU time | 5.59 seconds |
Started | May 14 12:45:13 PM PDT 24 |
Finished | May 14 12:45:22 PM PDT 24 |
Peak memory | 218788 kb |
Host | smart-ce8b5345-e5b2-4b29-9995-caf02e6f54b8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950342968 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.1950342968 |
Directory | /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.523795785 |
Short name | T95 |
Test name | |
Test status | |
Simulation time | 40053807 ps |
CPU time | 2.08 seconds |
Started | May 14 12:45:34 PM PDT 24 |
Finished | May 14 12:45:39 PM PDT 24 |
Peak memory | 220908 kb |
Host | smart-36bb4873-cc7a-46c0-b66c-c10d50878eaa |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523795785 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.523795785 |
Directory | /workspace/19.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2052479737 |
Short name | T178 |
Test name | |
Test status | |
Simulation time | 247107806 ps |
CPU time | 1.06 seconds |
Started | May 14 12:45:17 PM PDT 24 |
Finished | May 14 12:45:20 PM PDT 24 |
Peak memory | 204464 kb |
Host | smart-a9d9aa22-adaa-4766-9c31-557f7f8e1872 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052479737 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw. 2052479737 |
Directory | /workspace/19.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2019851375 |
Short name | T191 |
Test name | |
Test status | |
Simulation time | 131942007 ps |
CPU time | 0.98 seconds |
Started | May 14 12:45:21 PM PDT 24 |
Finished | May 14 12:45:24 PM PDT 24 |
Peak memory | 204276 kb |
Host | smart-3af4fc7b-1afc-458c-b6c5-9a5c150826a2 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019851375 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw. 2019851375 |
Directory | /workspace/19.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1115173733 |
Short name | T88 |
Test name | |
Test status | |
Simulation time | 524821528 ps |
CPU time | 6.08 seconds |
Started | May 14 12:45:23 PM PDT 24 |
Finished | May 14 12:45:31 PM PDT 24 |
Peak memory | 204616 kb |
Host | smart-e5f3de2d-73c3-4df3-bb16-9a6dc7a4923e |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115173733 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same _csr_outstanding.1115173733 |
Directory | /workspace/19.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_tap_fsm_rand_reset.720623202 |
Short name | T215 |
Test name | |
Test status | |
Simulation time | 15220537803 ps |
CPU time | 48.61 seconds |
Started | May 14 12:45:20 PM PDT 24 |
Finished | May 14 12:46:10 PM PDT 24 |
Peak memory | 221012 kb |
Host | smart-e166602f-4e70-46a0-b547-274d983da193 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720623202 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 19.rv_dm_tap_fsm_rand_reset.720623202 |
Directory | /workspace/19.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.884396338 |
Short name | T110 |
Test name | |
Test status | |
Simulation time | 87237101 ps |
CPU time | 5.23 seconds |
Started | May 14 12:45:19 PM PDT 24 |
Finished | May 14 12:45:26 PM PDT 24 |
Peak memory | 212776 kb |
Host | smart-1491dbe1-bfed-4c6b-8888-d0e16b847232 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884396338 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.884396338 |
Directory | /workspace/19.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.1534211972 |
Short name | T206 |
Test name | |
Test status | |
Simulation time | 1949764476 ps |
CPU time | 65.7 seconds |
Started | May 14 12:44:48 PM PDT 24 |
Finished | May 14 12:45:57 PM PDT 24 |
Peak memory | 204524 kb |
Host | smart-5d4b2cd0-521d-491b-9281-f2cae08ff059 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534211972 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 2.rv_dm_csr_aliasing.1534211972 |
Directory | /workspace/2.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.3941861857 |
Short name | T186 |
Test name | |
Test status | |
Simulation time | 723181959 ps |
CPU time | 28.21 seconds |
Started | May 14 12:44:45 PM PDT 24 |
Finished | May 14 12:45:17 PM PDT 24 |
Peak memory | 204628 kb |
Host | smart-e868f196-6ebc-4c02-aac3-708a1ebb7a79 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941861857 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.3941861857 |
Directory | /workspace/2.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3961857275 |
Short name | T80 |
Test name | |
Test status | |
Simulation time | 549186083 ps |
CPU time | 2.49 seconds |
Started | May 14 12:44:49 PM PDT 24 |
Finished | May 14 12:44:55 PM PDT 24 |
Peak memory | 212824 kb |
Host | smart-5ced598c-bc80-452e-b097-e3a165369c20 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961857275 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.3961857275 |
Directory | /workspace/2.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.2477911690 |
Short name | T177 |
Test name | |
Test status | |
Simulation time | 6291608897 ps |
CPU time | 5.28 seconds |
Started | May 14 12:44:49 PM PDT 24 |
Finished | May 14 12:44:58 PM PDT 24 |
Peak memory | 215812 kb |
Host | smart-8b564619-0937-490e-b085-948c093cce25 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477911690 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.2477911690 |
Directory | /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.3917836168 |
Short name | T101 |
Test name | |
Test status | |
Simulation time | 338506219 ps |
CPU time | 2.37 seconds |
Started | May 14 12:44:46 PM PDT 24 |
Finished | May 14 12:44:52 PM PDT 24 |
Peak memory | 221004 kb |
Host | smart-dbe0dbdf-f394-400c-b979-057582b29d86 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917836168 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.3917836168 |
Directory | /workspace/2.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.1137513269 |
Short name | T275 |
Test name | |
Test status | |
Simulation time | 17674609212 ps |
CPU time | 38.63 seconds |
Started | May 14 12:44:50 PM PDT 24 |
Finished | May 14 12:45:32 PM PDT 24 |
Peak memory | 204492 kb |
Host | smart-66843f9a-0369-490e-b5f4-d55ae7cc8556 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137513269 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs r_aliasing.1137513269 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.60177178 |
Short name | T194 |
Test name | |
Test status | |
Simulation time | 79933679931 ps |
CPU time | 222.24 seconds |
Started | May 14 12:44:49 PM PDT 24 |
Finished | May 14 12:48:35 PM PDT 24 |
Peak memory | 204600 kb |
Host | smart-f7f7a3b5-5ece-4509-b6b3-70689ebabd92 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60177178 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UV M_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null - cm_name 2.rv_dm_jtag_dmi_csr_bit_bash.60177178 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.974707416 |
Short name | T42 |
Test name | |
Test status | |
Simulation time | 1203456366 ps |
CPU time | 5.02 seconds |
Started | May 14 12:44:47 PM PDT 24 |
Finished | May 14 12:44:56 PM PDT 24 |
Peak memory | 204484 kb |
Host | smart-5551256f-8133-4f74-ad42-61710255f1c3 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974707416 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr _hw_reset.974707416 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1515680146 |
Short name | T155 |
Test name | |
Test status | |
Simulation time | 1460797377 ps |
CPU time | 5.22 seconds |
Started | May 14 12:44:48 PM PDT 24 |
Finished | May 14 12:44:57 PM PDT 24 |
Peak memory | 204492 kb |
Host | smart-716143b4-b184-4436-ab1a-becfb1533df3 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515680146 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.1 515680146 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.336397210 |
Short name | T188 |
Test name | |
Test status | |
Simulation time | 427403557 ps |
CPU time | 0.97 seconds |
Started | May 14 12:44:57 PM PDT 24 |
Finished | May 14 12:45:00 PM PDT 24 |
Peak memory | 204232 kb |
Host | smart-10fd8f6a-dbdd-453e-ac07-1a54f4a44e86 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336397210 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr _aliasing.336397210 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.2783141105 |
Short name | T184 |
Test name | |
Test status | |
Simulation time | 1224342055 ps |
CPU time | 3.35 seconds |
Started | May 14 12:44:44 PM PDT 24 |
Finished | May 14 12:44:50 PM PDT 24 |
Peak memory | 204488 kb |
Host | smart-e4166f2c-cddf-4cf3-8764-d3a40f27e3ae |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783141105 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_bit_bash.2783141105 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2147187010 |
Short name | T234 |
Test name | |
Test status | |
Simulation time | 237926609 ps |
CPU time | 0.7 seconds |
Started | May 14 12:44:47 PM PDT 24 |
Finished | May 14 12:44:52 PM PDT 24 |
Peak memory | 204224 kb |
Host | smart-a9b8187d-751d-4f2c-b6b5-8fb807e036e4 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147187010 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_hw_reset.2147187010 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.1452465084 |
Short name | T235 |
Test name | |
Test status | |
Simulation time | 27681913 ps |
CPU time | 0.69 seconds |
Started | May 14 12:44:59 PM PDT 24 |
Finished | May 14 12:45:02 PM PDT 24 |
Peak memory | 204212 kb |
Host | smart-36b2597e-2089-439d-9d4c-b7efdde10f59 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452465084 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.1 452465084 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.3794646843 |
Short name | T220 |
Test name | |
Test status | |
Simulation time | 39353759 ps |
CPU time | 0.66 seconds |
Started | May 14 12:44:50 PM PDT 24 |
Finished | May 14 12:44:54 PM PDT 24 |
Peak memory | 204224 kb |
Host | smart-d3362392-e8c1-4a03-8ca8-d9314e48f508 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794646843 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par tial_access.3794646843 |
Directory | /workspace/2.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.2991408262 |
Short name | T182 |
Test name | |
Test status | |
Simulation time | 119684874 ps |
CPU time | 0.66 seconds |
Started | May 14 12:44:57 PM PDT 24 |
Finished | May 14 12:44:59 PM PDT 24 |
Peak memory | 204232 kb |
Host | smart-81766bbc-4aa4-489a-8da0-b53ce01197d3 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991408262 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.2991408262 |
Directory | /workspace/2.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.130209502 |
Short name | T86 |
Test name | |
Test status | |
Simulation time | 282163525 ps |
CPU time | 6.44 seconds |
Started | May 14 12:44:48 PM PDT 24 |
Finished | May 14 12:44:59 PM PDT 24 |
Peak memory | 204652 kb |
Host | smart-c6883ff0-2f57-4670-b422-42101fd0e25b |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130209502 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_c sr_outstanding.130209502 |
Directory | /workspace/2.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.1186428623 |
Short name | T185 |
Test name | |
Test status | |
Simulation time | 138902124 ps |
CPU time | 2.55 seconds |
Started | May 14 12:44:47 PM PDT 24 |
Finished | May 14 12:44:54 PM PDT 24 |
Peak memory | 212904 kb |
Host | smart-8b39ca3e-f6db-42f2-a63e-2d611dadf763 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186428623 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.1186428623 |
Directory | /workspace/2.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.1051048555 |
Short name | T107 |
Test name | |
Test status | |
Simulation time | 4443467770 ps |
CPU time | 18.33 seconds |
Started | May 14 12:44:47 PM PDT 24 |
Finished | May 14 12:45:09 PM PDT 24 |
Peak memory | 212864 kb |
Host | smart-60293b2e-401d-4234-b7b2-8dfdf8917646 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051048555 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.1051048555 |
Directory | /workspace/2.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/27.rv_dm_tap_fsm_rand_reset.1443690721 |
Short name | T249 |
Test name | |
Test status | |
Simulation time | 7190177799 ps |
CPU time | 24.18 seconds |
Started | May 14 12:45:21 PM PDT 24 |
Finished | May 14 12:45:46 PM PDT 24 |
Peak memory | 220100 kb |
Host | smart-84fb87e0-f8b8-4ed4-aa0d-1aa5e98ef7a9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443690721 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 27.rv_dm_tap_fsm_rand_reset.1443690721 |
Directory | /workspace/27.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/28.rv_dm_tap_fsm_rand_reset.2464017181 |
Short name | T181 |
Test name | |
Test status | |
Simulation time | 7986224324 ps |
CPU time | 15.91 seconds |
Started | May 14 12:45:30 PM PDT 24 |
Finished | May 14 12:45:46 PM PDT 24 |
Peak memory | 217776 kb |
Host | smart-7bdd2489-6a31-4ab5-9724-1c048a38eccf |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464017181 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 28.rv_dm_tap_fsm_rand_reset.2464017181 |
Directory | /workspace/28.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.6663865 |
Short name | T75 |
Test name | |
Test status | |
Simulation time | 1179623918 ps |
CPU time | 68.83 seconds |
Started | May 14 12:44:47 PM PDT 24 |
Finished | May 14 12:46:00 PM PDT 24 |
Peak memory | 204504 kb |
Host | smart-8473b675-3fc3-49cf-842f-7e931da72bd1 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6663865 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM _TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_aliasing.6663865 |
Directory | /workspace/3.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.2350901572 |
Short name | T97 |
Test name | |
Test status | |
Simulation time | 10516706990 ps |
CPU time | 35.18 seconds |
Started | May 14 12:45:11 PM PDT 24 |
Finished | May 14 12:45:49 PM PDT 24 |
Peak memory | 204728 kb |
Host | smart-b0200b70-abbd-400f-834e-c1fca8f99e01 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350901572 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.2350901572 |
Directory | /workspace/3.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.2378923466 |
Short name | T217 |
Test name | |
Test status | |
Simulation time | 94309287 ps |
CPU time | 2.4 seconds |
Started | May 14 12:44:55 PM PDT 24 |
Finished | May 14 12:45:00 PM PDT 24 |
Peak memory | 212716 kb |
Host | smart-66be89b3-c42f-4c4c-be83-bbc0e5e78f35 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378923466 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.2378923466 |
Directory | /workspace/3.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1913102048 |
Short name | T202 |
Test name | |
Test status | |
Simulation time | 529101656 ps |
CPU time | 2.18 seconds |
Started | May 14 12:44:57 PM PDT 24 |
Finished | May 14 12:45:00 PM PDT 24 |
Peak memory | 213384 kb |
Host | smart-952ba7ed-e1f1-40dc-9dee-793e8dde9349 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913102048 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.1913102048 |
Directory | /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.1304239777 |
Short name | T72 |
Test name | |
Test status | |
Simulation time | 96195205 ps |
CPU time | 2.31 seconds |
Started | May 14 12:44:54 PM PDT 24 |
Finished | May 14 12:44:59 PM PDT 24 |
Peak memory | 217876 kb |
Host | smart-9322881f-d68b-4157-b2fc-35c90c55b3c7 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304239777 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.1304239777 |
Directory | /workspace/3.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.57011509 |
Short name | T271 |
Test name | |
Test status | |
Simulation time | 7445583039 ps |
CPU time | 30.2 seconds |
Started | May 14 12:44:53 PM PDT 24 |
Finished | May 14 12:45:26 PM PDT 24 |
Peak memory | 204516 kb |
Host | smart-9b3a5bdf-ad2b-4dee-bf43-163565a6f2c6 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57011509 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_ aliasing.57011509 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.904454124 |
Short name | T170 |
Test name | |
Test status | |
Simulation time | 16023146124 ps |
CPU time | 58.72 seconds |
Started | May 14 12:45:10 PM PDT 24 |
Finished | May 14 12:46:12 PM PDT 24 |
Peak memory | 204624 kb |
Host | smart-38d7fcf0-ce60-4d7e-83bd-9167aeb6bc94 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904454124 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U VM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_bit_bash.904454124 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1162286043 |
Short name | T253 |
Test name | |
Test status | |
Simulation time | 1071808717 ps |
CPU time | 1.8 seconds |
Started | May 14 12:44:59 PM PDT 24 |
Finished | May 14 12:45:03 PM PDT 24 |
Peak memory | 204372 kb |
Host | smart-9383d942-0b1f-49e5-8599-b86a3faf9c0a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162286043 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.1 162286043 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.413524969 |
Short name | T175 |
Test name | |
Test status | |
Simulation time | 156247573 ps |
CPU time | 0.79 seconds |
Started | May 14 12:45:02 PM PDT 24 |
Finished | May 14 12:45:04 PM PDT 24 |
Peak memory | 204224 kb |
Host | smart-ce19b896-0cf4-4788-94ef-8f170cebf708 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413524969 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr _aliasing.413524969 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.3716887285 |
Short name | T196 |
Test name | |
Test status | |
Simulation time | 1099544068 ps |
CPU time | 3.67 seconds |
Started | May 14 12:44:52 PM PDT 24 |
Finished | May 14 12:44:59 PM PDT 24 |
Peak memory | 204484 kb |
Host | smart-261952ab-b182-4552-81d1-a2def83acf6c |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716887285 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_bit_bash.3716887285 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.675413380 |
Short name | T193 |
Test name | |
Test status | |
Simulation time | 55950011 ps |
CPU time | 0.76 seconds |
Started | May 14 12:44:50 PM PDT 24 |
Finished | May 14 12:44:54 PM PDT 24 |
Peak memory | 204228 kb |
Host | smart-f7bd5680-41de-469b-917d-4753089f60b8 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675413380 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr _hw_reset.675413380 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.315008398 |
Short name | T180 |
Test name | |
Test status | |
Simulation time | 43276988 ps |
CPU time | 0.8 seconds |
Started | May 14 12:44:51 PM PDT 24 |
Finished | May 14 12:44:55 PM PDT 24 |
Peak memory | 204248 kb |
Host | smart-4dc2c8bb-fb5b-4101-ab32-14b4d08c43ba |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315008398 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.315008398 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.1733507611 |
Short name | T167 |
Test name | |
Test status | |
Simulation time | 53668779 ps |
CPU time | 0.67 seconds |
Started | May 14 12:45:08 PM PDT 24 |
Finished | May 14 12:45:10 PM PDT 24 |
Peak memory | 204260 kb |
Host | smart-3ad70b0a-e38b-4349-b27a-57c9efd5d146 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733507611 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par tial_access.1733507611 |
Directory | /workspace/3.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.2666621630 |
Short name | T210 |
Test name | |
Test status | |
Simulation time | 83998648 ps |
CPU time | 0.67 seconds |
Started | May 14 12:45:08 PM PDT 24 |
Finished | May 14 12:45:10 PM PDT 24 |
Peak memory | 204084 kb |
Host | smart-9a0328b7-a620-493c-a60e-4d10271d3921 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666621630 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.2666621630 |
Directory | /workspace/3.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.3858134700 |
Short name | T89 |
Test name | |
Test status | |
Simulation time | 509717636 ps |
CPU time | 4.35 seconds |
Started | May 14 12:44:58 PM PDT 24 |
Finished | May 14 12:45:04 PM PDT 24 |
Peak memory | 204528 kb |
Host | smart-f72b38a7-8854-46f1-9d8e-4120832da3a4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858134700 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_ csr_outstanding.3858134700 |
Directory | /workspace/3.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.4187779690 |
Short name | T192 |
Test name | |
Test status | |
Simulation time | 337720136 ps |
CPU time | 2.42 seconds |
Started | May 14 12:45:10 PM PDT 24 |
Finished | May 14 12:45:15 PM PDT 24 |
Peak memory | 214748 kb |
Host | smart-00eda8a0-5157-42a2-89a9-ddf7de650f7c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187779690 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.4187779690 |
Directory | /workspace/3.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2713106753 |
Short name | T67 |
Test name | |
Test status | |
Simulation time | 2283170673 ps |
CPU time | 19.43 seconds |
Started | May 14 12:45:09 PM PDT 24 |
Finished | May 14 12:45:31 PM PDT 24 |
Peak memory | 220808 kb |
Host | smart-c856267d-7031-42db-8ee4-808b9403edbb |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713106753 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.2713106753 |
Directory | /workspace/3.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/33.rv_dm_tap_fsm_rand_reset.3883494730 |
Short name | T109 |
Test name | |
Test status | |
Simulation time | 37923114487 ps |
CPU time | 22.41 seconds |
Started | May 14 12:45:21 PM PDT 24 |
Finished | May 14 12:45:45 PM PDT 24 |
Peak memory | 221060 kb |
Host | smart-9b93f183-8d77-4e80-b8f9-64fa3f1cb087 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883494730 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 33.rv_dm_tap_fsm_rand_reset.3883494730 |
Directory | /workspace/33.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/36.rv_dm_tap_fsm_rand_reset.2976554879 |
Short name | T187 |
Test name | |
Test status | |
Simulation time | 9317332785 ps |
CPU time | 15.61 seconds |
Started | May 14 12:45:24 PM PDT 24 |
Finished | May 14 12:45:41 PM PDT 24 |
Peak memory | 219720 kb |
Host | smart-3b421426-2882-4956-aeb2-fb5bda46a7bf |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976554879 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 36.rv_dm_tap_fsm_rand_reset.2976554879 |
Directory | /workspace/36.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.652433841 |
Short name | T258 |
Test name | |
Test status | |
Simulation time | 12415930931 ps |
CPU time | 29.62 seconds |
Started | May 14 12:44:51 PM PDT 24 |
Finished | May 14 12:45:24 PM PDT 24 |
Peak memory | 214016 kb |
Host | smart-d17c8b80-f39f-430d-afcb-64511cb5ea5b |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652433841 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 4.rv_dm_csr_aliasing.652433841 |
Directory | /workspace/4.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.2088007050 |
Short name | T83 |
Test name | |
Test status | |
Simulation time | 2566581148 ps |
CPU time | 32.65 seconds |
Started | May 14 12:44:57 PM PDT 24 |
Finished | May 14 12:45:32 PM PDT 24 |
Peak memory | 204604 kb |
Host | smart-da02673e-1448-48f1-8d55-714add8660d4 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088007050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.2088007050 |
Directory | /workspace/4.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.446263881 |
Short name | T208 |
Test name | |
Test status | |
Simulation time | 188507307 ps |
CPU time | 1.57 seconds |
Started | May 14 12:44:57 PM PDT 24 |
Finished | May 14 12:45:05 PM PDT 24 |
Peak memory | 212804 kb |
Host | smart-de916a21-d32a-4b46-a9a6-bd9e2c0f8134 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446263881 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.446263881 |
Directory | /workspace/4.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.1212832667 |
Short name | T246 |
Test name | |
Test status | |
Simulation time | 143488716 ps |
CPU time | 3.66 seconds |
Started | May 14 12:45:00 PM PDT 24 |
Finished | May 14 12:45:05 PM PDT 24 |
Peak memory | 217220 kb |
Host | smart-af74af6e-edb9-4f29-80f1-dd0ea6dc8fd5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212832667 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.1212832667 |
Directory | /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.2830434170 |
Short name | T268 |
Test name | |
Test status | |
Simulation time | 179260672 ps |
CPU time | 1.49 seconds |
Started | May 14 12:44:54 PM PDT 24 |
Finished | May 14 12:44:58 PM PDT 24 |
Peak memory | 217840 kb |
Host | smart-6a6cbbf9-1376-4123-8a11-81995ad45dab |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830434170 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.2830434170 |
Directory | /workspace/4.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.965544607 |
Short name | T252 |
Test name | |
Test status | |
Simulation time | 15008057477 ps |
CPU time | 33.18 seconds |
Started | May 14 12:44:54 PM PDT 24 |
Finished | May 14 12:45:30 PM PDT 24 |
Peak memory | 204496 kb |
Host | smart-ed45574f-a933-4e05-be94-19b14b581cba |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965544607 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr _aliasing.965544607 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.4119869675 |
Short name | T257 |
Test name | |
Test status | |
Simulation time | 56836139265 ps |
CPU time | 179.92 seconds |
Started | May 14 12:45:11 PM PDT 24 |
Finished | May 14 12:48:14 PM PDT 24 |
Peak memory | 204404 kb |
Host | smart-af6d9efe-1bb4-4f7b-bd1c-788ac642fcc2 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119869675 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_bit_bash.4119869675 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.3616237347 |
Short name | T36 |
Test name | |
Test status | |
Simulation time | 1532519730 ps |
CPU time | 2 seconds |
Started | May 14 12:44:58 PM PDT 24 |
Finished | May 14 12:45:01 PM PDT 24 |
Peak memory | 204420 kb |
Host | smart-d36e227c-8141-44b2-b315-06dd961bff67 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616237347 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs r_hw_reset.3616237347 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.1470120051 |
Short name | T247 |
Test name | |
Test status | |
Simulation time | 424742342 ps |
CPU time | 2.23 seconds |
Started | May 14 12:44:53 PM PDT 24 |
Finished | May 14 12:44:58 PM PDT 24 |
Peak memory | 204416 kb |
Host | smart-51f4a1da-99b3-4914-bfd6-3a80521c2cb3 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470120051 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.1 470120051 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.154467830 |
Short name | T265 |
Test name | |
Test status | |
Simulation time | 48961131 ps |
CPU time | 0.84 seconds |
Started | May 14 12:45:06 PM PDT 24 |
Finished | May 14 12:45:07 PM PDT 24 |
Peak memory | 204108 kb |
Host | smart-3aaabada-1275-4146-8ca2-8c4dbbad9383 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154467830 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr _aliasing.154467830 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.1406793833 |
Short name | T60 |
Test name | |
Test status | |
Simulation time | 5636673712 ps |
CPU time | 10.47 seconds |
Started | May 14 12:45:04 PM PDT 24 |
Finished | May 14 12:45:16 PM PDT 24 |
Peak memory | 204516 kb |
Host | smart-62b455c7-df8c-45ab-b5d2-7fd69e45584b |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406793833 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs r_bit_bash.1406793833 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.1472779008 |
Short name | T157 |
Test name | |
Test status | |
Simulation time | 172563711 ps |
CPU time | 0.75 seconds |
Started | May 14 12:44:54 PM PDT 24 |
Finished | May 14 12:44:57 PM PDT 24 |
Peak memory | 204156 kb |
Host | smart-1e39625c-5dde-46c4-bc78-9714c9222cf2 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472779008 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs r_hw_reset.1472779008 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.1866837811 |
Short name | T169 |
Test name | |
Test status | |
Simulation time | 83486365 ps |
CPU time | 0.94 seconds |
Started | May 14 12:44:58 PM PDT 24 |
Finished | May 14 12:45:01 PM PDT 24 |
Peak memory | 204064 kb |
Host | smart-e679dcef-b869-4fd5-8413-de7f535ec647 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866837811 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.1 866837811 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.614887138 |
Short name | T214 |
Test name | |
Test status | |
Simulation time | 30913656 ps |
CPU time | 0.73 seconds |
Started | May 14 12:44:52 PM PDT 24 |
Finished | May 14 12:44:56 PM PDT 24 |
Peak memory | 204208 kb |
Host | smart-dd5971e9-dce0-46c4-a09e-ab92a603d967 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614887138 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_part ial_access.614887138 |
Directory | /workspace/4.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.1105429056 |
Short name | T173 |
Test name | |
Test status | |
Simulation time | 24748851 ps |
CPU time | 0.71 seconds |
Started | May 14 12:45:04 PM PDT 24 |
Finished | May 14 12:45:06 PM PDT 24 |
Peak memory | 204136 kb |
Host | smart-2a537ac7-bb58-4da8-a7c6-e96702441bbb |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105429056 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.1105429056 |
Directory | /workspace/4.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1193418 |
Short name | T102 |
Test name | |
Test status | |
Simulation time | 303343047 ps |
CPU time | 3.54 seconds |
Started | May 14 12:45:03 PM PDT 24 |
Finished | May 14 12:45:08 PM PDT 24 |
Peak memory | 204656 kb |
Host | smart-c282f8b2-f3ba-4324-97e0-9c353a40a7d8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193418 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_csr _outstanding.1193418 |
Directory | /workspace/4.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.1879321522 |
Short name | T165 |
Test name | |
Test status | |
Simulation time | 80076827 ps |
CPU time | 2.9 seconds |
Started | May 14 12:44:55 PM PDT 24 |
Finished | May 14 12:45:00 PM PDT 24 |
Peak memory | 212740 kb |
Host | smart-67926602-c0f4-4de4-8bd8-3eb6d0109171 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879321522 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.1879321522 |
Directory | /workspace/4.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.711153002 |
Short name | T209 |
Test name | |
Test status | |
Simulation time | 485935372 ps |
CPU time | 9.12 seconds |
Started | May 14 12:44:57 PM PDT 24 |
Finished | May 14 12:45:08 PM PDT 24 |
Peak memory | 212764 kb |
Host | smart-102b07c4-0d65-4403-94e0-7b7dc3e1a780 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711153002 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.711153002 |
Directory | /workspace/4.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.394234633 |
Short name | T96 |
Test name | |
Test status | |
Simulation time | 169353019 ps |
CPU time | 2.3 seconds |
Started | May 14 12:45:00 PM PDT 24 |
Finished | May 14 12:45:04 PM PDT 24 |
Peak memory | 212648 kb |
Host | smart-a6907293-8994-47bf-ae6f-68eef65a40e9 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394234633 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.394234633 |
Directory | /workspace/5.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.4279976318 |
Short name | T156 |
Test name | |
Test status | |
Simulation time | 784755449 ps |
CPU time | 2.09 seconds |
Started | May 14 12:44:59 PM PDT 24 |
Finished | May 14 12:45:03 PM PDT 24 |
Peak memory | 204836 kb |
Host | smart-19c1a2cb-a134-4d61-875d-09ba7c314788 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279976318 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.4 279976318 |
Directory | /workspace/5.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.593736518 |
Short name | T216 |
Test name | |
Test status | |
Simulation time | 47467224 ps |
CPU time | 0.82 seconds |
Started | May 14 12:45:00 PM PDT 24 |
Finished | May 14 12:45:03 PM PDT 24 |
Peak memory | 204244 kb |
Host | smart-dcb03349-c382-4dfa-9a3e-9f2433eed632 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593736518 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.593736518 |
Directory | /workspace/5.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.2933289247 |
Short name | T73 |
Test name | |
Test status | |
Simulation time | 419952379 ps |
CPU time | 7.45 seconds |
Started | May 14 12:44:51 PM PDT 24 |
Finished | May 14 12:45:02 PM PDT 24 |
Peak memory | 204484 kb |
Host | smart-871df3c0-4925-4f85-b2c2-900542392a29 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933289247 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_ csr_outstanding.2933289247 |
Directory | /workspace/5.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.554222815 |
Short name | T69 |
Test name | |
Test status | |
Simulation time | 214150732 ps |
CPU time | 5.31 seconds |
Started | May 14 12:45:00 PM PDT 24 |
Finished | May 14 12:45:07 PM PDT 24 |
Peak memory | 212664 kb |
Host | smart-64af7038-aefb-4027-9fd7-c497c38ca976 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554222815 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.554222815 |
Directory | /workspace/5.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2067358758 |
Short name | T211 |
Test name | |
Test status | |
Simulation time | 1193213188 ps |
CPU time | 19.6 seconds |
Started | May 14 12:45:05 PM PDT 24 |
Finished | May 14 12:45:26 PM PDT 24 |
Peak memory | 220860 kb |
Host | smart-476ec923-207c-43f2-90fe-e1cfc4e725e5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067358758 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.2067358758 |
Directory | /workspace/5.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.9155673 |
Short name | T200 |
Test name | |
Test status | |
Simulation time | 172438010 ps |
CPU time | 3.74 seconds |
Started | May 14 12:44:53 PM PDT 24 |
Finished | May 14 12:44:59 PM PDT 24 |
Peak memory | 220924 kb |
Host | smart-c0a92e84-05df-4391-80b3-83b5b8bd9024 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9155673 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.9155673 |
Directory | /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.982748358 |
Short name | T100 |
Test name | |
Test status | |
Simulation time | 313167564 ps |
CPU time | 2.49 seconds |
Started | May 14 12:45:01 PM PDT 24 |
Finished | May 14 12:45:05 PM PDT 24 |
Peak memory | 212772 kb |
Host | smart-6cbfa4cc-a311-43e1-872f-343efea133a9 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982748358 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.982748358 |
Directory | /workspace/6.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.3227429423 |
Short name | T239 |
Test name | |
Test status | |
Simulation time | 267398125 ps |
CPU time | 1.21 seconds |
Started | May 14 12:44:52 PM PDT 24 |
Finished | May 14 12:44:56 PM PDT 24 |
Peak memory | 204496 kb |
Host | smart-4caf9410-3ec2-4f08-a6df-c11561e2ce5d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227429423 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.3 227429423 |
Directory | /workspace/6.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.3680381117 |
Short name | T219 |
Test name | |
Test status | |
Simulation time | 39557413 ps |
CPU time | 0.7 seconds |
Started | May 14 12:44:58 PM PDT 24 |
Finished | May 14 12:45:01 PM PDT 24 |
Peak memory | 204324 kb |
Host | smart-99fa436b-2cb7-4f01-bb5c-cf8b448300eb |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680381117 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.3 680381117 |
Directory | /workspace/6.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.4047041287 |
Short name | T52 |
Test name | |
Test status | |
Simulation time | 284066163 ps |
CPU time | 6.69 seconds |
Started | May 14 12:45:05 PM PDT 24 |
Finished | May 14 12:45:13 PM PDT 24 |
Peak memory | 204668 kb |
Host | smart-8f404851-3ca8-4e83-887d-3b4d42efa999 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047041287 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_ csr_outstanding.4047041287 |
Directory | /workspace/6.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.3723111924 |
Short name | T274 |
Test name | |
Test status | |
Simulation time | 410277238 ps |
CPU time | 4.92 seconds |
Started | May 14 12:45:00 PM PDT 24 |
Finished | May 14 12:45:07 PM PDT 24 |
Peak memory | 212808 kb |
Host | smart-597b9c83-d8b8-4651-8d46-8bab156e9cf1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723111924 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.3723111924 |
Directory | /workspace/6.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.760720779 |
Short name | T250 |
Test name | |
Test status | |
Simulation time | 130795059 ps |
CPU time | 1.95 seconds |
Started | May 14 12:45:14 PM PDT 24 |
Finished | May 14 12:45:19 PM PDT 24 |
Peak memory | 215984 kb |
Host | smart-8028703c-a273-4e9a-b79c-64bef3ed40a9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760720779 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.760720779 |
Directory | /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.42096654 |
Short name | T99 |
Test name | |
Test status | |
Simulation time | 223144020 ps |
CPU time | 2.39 seconds |
Started | May 14 12:44:57 PM PDT 24 |
Finished | May 14 12:45:01 PM PDT 24 |
Peak memory | 218844 kb |
Host | smart-7ac9c74c-50a8-4bc5-819a-37c39953c90f |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42096654 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.42096654 |
Directory | /workspace/7.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2237251050 |
Short name | T150 |
Test name | |
Test status | |
Simulation time | 365579847 ps |
CPU time | 1.2 seconds |
Started | May 14 12:44:59 PM PDT 24 |
Finished | May 14 12:45:02 PM PDT 24 |
Peak memory | 204472 kb |
Host | smart-0b2747e8-9400-405b-99f8-5b74d2cc08e0 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237251050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.2 237251050 |
Directory | /workspace/7.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.543978255 |
Short name | T61 |
Test name | |
Test status | |
Simulation time | 63451307 ps |
CPU time | 0.69 seconds |
Started | May 14 12:45:07 PM PDT 24 |
Finished | May 14 12:45:10 PM PDT 24 |
Peak memory | 204096 kb |
Host | smart-d97a4e5b-2cb0-4610-bb09-71259b9847fe |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543978255 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.543978255 |
Directory | /workspace/7.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.2610924880 |
Short name | T218 |
Test name | |
Test status | |
Simulation time | 514577029 ps |
CPU time | 4.27 seconds |
Started | May 14 12:45:07 PM PDT 24 |
Finished | May 14 12:45:13 PM PDT 24 |
Peak memory | 204592 kb |
Host | smart-b26b4c29-e719-497f-82a5-8fb58b13bb91 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610924880 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_ csr_outstanding.2610924880 |
Directory | /workspace/7.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.2914486854 |
Short name | T277 |
Test name | |
Test status | |
Simulation time | 295306128 ps |
CPU time | 2.25 seconds |
Started | May 14 12:45:07 PM PDT 24 |
Finished | May 14 12:45:11 PM PDT 24 |
Peak memory | 212852 kb |
Host | smart-ebdd5a93-5660-485c-afca-17bad82df27f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914486854 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.2914486854 |
Directory | /workspace/7.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.3433198143 |
Short name | T117 |
Test name | |
Test status | |
Simulation time | 450726325 ps |
CPU time | 8.55 seconds |
Started | May 14 12:44:54 PM PDT 24 |
Finished | May 14 12:45:05 PM PDT 24 |
Peak memory | 220844 kb |
Host | smart-65a9072e-dce0-489b-a0cb-757ff3efada8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433198143 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.3433198143 |
Directory | /workspace/7.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.2147916281 |
Short name | T199 |
Test name | |
Test status | |
Simulation time | 1980574246 ps |
CPU time | 3.46 seconds |
Started | May 14 12:45:06 PM PDT 24 |
Finished | May 14 12:45:11 PM PDT 24 |
Peak memory | 217864 kb |
Host | smart-3d69f59e-3f07-4d8f-a4ab-576e5d2f18b3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147916281 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.2147916281 |
Directory | /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.2286568301 |
Short name | T162 |
Test name | |
Test status | |
Simulation time | 596400957 ps |
CPU time | 2.58 seconds |
Started | May 14 12:45:16 PM PDT 24 |
Finished | May 14 12:45:21 PM PDT 24 |
Peak memory | 220896 kb |
Host | smart-a627876c-1b8b-418f-9389-b993c00374fc |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286568301 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.2286568301 |
Directory | /workspace/8.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.2271570073 |
Short name | T190 |
Test name | |
Test status | |
Simulation time | 934278223 ps |
CPU time | 3.61 seconds |
Started | May 14 12:45:06 PM PDT 24 |
Finished | May 14 12:45:11 PM PDT 24 |
Peak memory | 204312 kb |
Host | smart-dd36d62a-9b36-4904-a40d-6f4869daa5f8 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271570073 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.2 271570073 |
Directory | /workspace/8.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.594797763 |
Short name | T59 |
Test name | |
Test status | |
Simulation time | 68274667 ps |
CPU time | 0.81 seconds |
Started | May 14 12:45:14 PM PDT 24 |
Finished | May 14 12:45:17 PM PDT 24 |
Peak memory | 204568 kb |
Host | smart-faa70a02-5735-4a6e-a063-f9bcc947a1bb |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594797763 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.594797763 |
Directory | /workspace/8.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2611726399 |
Short name | T76 |
Test name | |
Test status | |
Simulation time | 293765429 ps |
CPU time | 3.54 seconds |
Started | May 14 12:44:58 PM PDT 24 |
Finished | May 14 12:45:03 PM PDT 24 |
Peak memory | 204532 kb |
Host | smart-0aab713d-530f-4e5e-abd6-3576f8f47262 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611726399 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_ csr_outstanding.2611726399 |
Directory | /workspace/8.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.3125359487 |
Short name | T267 |
Test name | |
Test status | |
Simulation time | 736063198 ps |
CPU time | 4.15 seconds |
Started | May 14 12:44:59 PM PDT 24 |
Finished | May 14 12:45:05 PM PDT 24 |
Peak memory | 212832 kb |
Host | smart-689e477b-69e6-4e99-a1c0-8d44e4942409 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125359487 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.3125359487 |
Directory | /workspace/8.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.516514064 |
Short name | T118 |
Test name | |
Test status | |
Simulation time | 1437773226 ps |
CPU time | 16.6 seconds |
Started | May 14 12:45:06 PM PDT 24 |
Finished | May 14 12:45:24 PM PDT 24 |
Peak memory | 221048 kb |
Host | smart-164e3879-17df-4c3c-8b5b-d3ac26166c66 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516514064 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.516514064 |
Directory | /workspace/8.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.1887023579 |
Short name | T27 |
Test name | |
Test status | |
Simulation time | 1051774673 ps |
CPU time | 4.31 seconds |
Started | May 14 12:44:59 PM PDT 24 |
Finished | May 14 12:45:05 PM PDT 24 |
Peak memory | 218488 kb |
Host | smart-b401aac6-b448-4971-ad1c-8cfd9bfdb711 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887023579 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.1887023579 |
Directory | /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.807498169 |
Short name | T92 |
Test name | |
Test status | |
Simulation time | 47888970 ps |
CPU time | 1.41 seconds |
Started | May 14 12:45:14 PM PDT 24 |
Finished | May 14 12:45:18 PM PDT 24 |
Peak memory | 218176 kb |
Host | smart-ecc3217b-4f6d-4302-b2c8-1394532c7707 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807498169 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.807498169 |
Directory | /workspace/9.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.2189901553 |
Short name | T40 |
Test name | |
Test status | |
Simulation time | 2524926226 ps |
CPU time | 6.09 seconds |
Started | May 14 12:45:05 PM PDT 24 |
Finished | May 14 12:45:12 PM PDT 24 |
Peak memory | 204520 kb |
Host | smart-6105e606-8e9f-490d-8939-e1b5c4dfa5e9 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189901553 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.2 189901553 |
Directory | /workspace/9.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.559725592 |
Short name | T213 |
Test name | |
Test status | |
Simulation time | 65378696 ps |
CPU time | 0.72 seconds |
Started | May 14 12:44:58 PM PDT 24 |
Finished | May 14 12:45:01 PM PDT 24 |
Peak memory | 204184 kb |
Host | smart-528732b0-797e-4d2a-a4e8-c9ad64f92d84 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559725592 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.559725592 |
Directory | /workspace/9.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.1311040625 |
Short name | T84 |
Test name | |
Test status | |
Simulation time | 286221060 ps |
CPU time | 6.53 seconds |
Started | May 14 12:45:11 PM PDT 24 |
Finished | May 14 12:45:21 PM PDT 24 |
Peak memory | 204496 kb |
Host | smart-4d366c97-2a0e-4124-bd29-f7d786833eba |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311040625 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_ csr_outstanding.1311040625 |
Directory | /workspace/9.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.760244102 |
Short name | T164 |
Test name | |
Test status | |
Simulation time | 470537385 ps |
CPU time | 3.45 seconds |
Started | May 14 12:45:08 PM PDT 24 |
Finished | May 14 12:45:14 PM PDT 24 |
Peak memory | 212844 kb |
Host | smart-befa977b-0b55-49a6-b77d-ab910565b940 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760244102 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.760244102 |
Directory | /workspace/9.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.4114188328 |
Short name | T104 |
Test name | |
Test status | |
Simulation time | 312989845 ps |
CPU time | 8.2 seconds |
Started | May 14 12:45:03 PM PDT 24 |
Finished | May 14 12:45:12 PM PDT 24 |
Peak memory | 212768 kb |
Host | smart-7cf05946-ba9f-4542-8430-03f1c313b6d9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114188328 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.4114188328 |
Directory | /workspace/9.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.rv_dm_alert_test.2509861229 |
Short name | T45 |
Test name | |
Test status | |
Simulation time | 68908756 ps |
CPU time | 0.7 seconds |
Started | May 14 12:49:49 PM PDT 24 |
Finished | May 14 12:49:50 PM PDT 24 |
Peak memory | 204376 kb |
Host | smart-3f1e82f3-ea31-41eb-8042-61ccca4dd075 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509861229 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.2509861229 |
Directory | /workspace/0.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.4147220576 |
Short name | T145 |
Test name | |
Test status | |
Simulation time | 73666648 ps |
CPU time | 0.74 seconds |
Started | May 14 12:49:38 PM PDT 24 |
Finished | May 14 12:49:40 PM PDT 24 |
Peak memory | 204328 kb |
Host | smart-87227dad-9eca-4d14-9487-23528cdb5264 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4147220576 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.4147220576 |
Directory | /workspace/0.rv_dm_jtag_dtm_idle_hint/latest |
Test location | /workspace/coverage/default/1.rv_dm_alert_test.154691528 |
Short name | T51 |
Test name | |
Test status | |
Simulation time | 29946924 ps |
CPU time | 0.71 seconds |
Started | May 14 12:49:45 PM PDT 24 |
Finished | May 14 12:49:48 PM PDT 24 |
Peak memory | 203964 kb |
Host | smart-a07d8127-c0b8-479a-8c53-671996f2f446 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154691528 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.154691528 |
Directory | /workspace/1.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.306944794 |
Short name | T8 |
Test name | |
Test status | |
Simulation time | 92660502 ps |
CPU time | 0.81 seconds |
Started | May 14 12:49:45 PM PDT 24 |
Finished | May 14 12:49:48 PM PDT 24 |
Peak memory | 204260 kb |
Host | smart-a299a488-020f-40fc-8588-92cf1678c301 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=306944794 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.306944794 |
Directory | /workspace/1.rv_dm_jtag_dtm_idle_hint/latest |
Test location | /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.1969580404 |
Short name | T16 |
Test name | |
Test status | |
Simulation time | 129746994 ps |
CPU time | 0.81 seconds |
Started | May 14 12:49:46 PM PDT 24 |
Finished | May 14 12:49:49 PM PDT 24 |
Peak memory | 204252 kb |
Host | smart-2040a03c-1b09-47ed-b57c-2fd3d131b030 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1969580404 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.1969580404 |
Directory | /workspace/1.rv_dm_progbuf_read_write_execute/latest |
Test location | /workspace/coverage/default/1.rv_dm_rom_read_access.1747743263 |
Short name | T12 |
Test name | |
Test status | |
Simulation time | 70545843 ps |
CPU time | 0.81 seconds |
Started | May 14 12:49:46 PM PDT 24 |
Finished | May 14 12:49:49 PM PDT 24 |
Peak memory | 212616 kb |
Host | smart-8d6659ee-be1e-488a-9deb-deab56adf1ee |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1747743263 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.1747743263 |
Directory | /workspace/1.rv_dm_rom_read_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_sec_cm.652225911 |
Short name | T23 |
Test name | |
Test status | |
Simulation time | 137971956 ps |
CPU time | 1.18 seconds |
Started | May 14 12:49:44 PM PDT 24 |
Finished | May 14 12:49:48 PM PDT 24 |
Peak memory | 229072 kb |
Host | smart-0bea6fcb-e042-4929-b4ab-e9266547d2b0 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652225911 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.652225911 |
Directory | /workspace/1.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/1.rv_dm_smoke.994703083 |
Short name | T148 |
Test name | |
Test status | |
Simulation time | 606209977 ps |
CPU time | 1.96 seconds |
Started | May 14 12:49:44 PM PDT 24 |
Finished | May 14 12:49:48 PM PDT 24 |
Peak memory | 204436 kb |
Host | smart-8ba7e77d-ef61-4dcc-91d2-ca989d0fc11c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=994703083 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.994703083 |
Directory | /workspace/1.rv_dm_smoke/latest |
Test location | /workspace/coverage/default/10.rv_dm_alert_test.4225788588 |
Short name | T125 |
Test name | |
Test status | |
Simulation time | 51746635 ps |
CPU time | 0.7 seconds |
Started | May 14 12:50:05 PM PDT 24 |
Finished | May 14 12:50:09 PM PDT 24 |
Peak memory | 204304 kb |
Host | smart-25e97612-3980-4ca1-8e62-ac3445976191 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225788588 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.4225788588 |
Directory | /workspace/10.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/11.rv_dm_alert_test.2181524534 |
Short name | T47 |
Test name | |
Test status | |
Simulation time | 42184343 ps |
CPU time | 0.7 seconds |
Started | May 14 12:50:02 PM PDT 24 |
Finished | May 14 12:50:06 PM PDT 24 |
Peak memory | 204372 kb |
Host | smart-77969b25-3268-4f72-bf0b-8bb484a76db0 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181524534 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.2181524534 |
Directory | /workspace/11.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/12.rv_dm_alert_test.3393514513 |
Short name | T121 |
Test name | |
Test status | |
Simulation time | 16871280 ps |
CPU time | 0.7 seconds |
Started | May 14 12:50:09 PM PDT 24 |
Finished | May 14 12:50:12 PM PDT 24 |
Peak memory | 204648 kb |
Host | smart-d8823792-d1f8-4406-95ea-84d892f00f24 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393514513 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.3393514513 |
Directory | /workspace/12.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/13.rv_dm_alert_test.958788815 |
Short name | T131 |
Test name | |
Test status | |
Simulation time | 17968113 ps |
CPU time | 0.71 seconds |
Started | May 14 12:50:08 PM PDT 24 |
Finished | May 14 12:50:12 PM PDT 24 |
Peak memory | 204368 kb |
Host | smart-5db177cd-fed1-46cc-b035-965f82c60c11 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958788815 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.958788815 |
Directory | /workspace/13.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/14.rv_dm_alert_test.2957027785 |
Short name | T3 |
Test name | |
Test status | |
Simulation time | 21835801 ps |
CPU time | 0.72 seconds |
Started | May 14 12:50:05 PM PDT 24 |
Finished | May 14 12:50:09 PM PDT 24 |
Peak memory | 204304 kb |
Host | smart-9689e4f7-bc26-4554-bcec-bd29489f06af |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957027785 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.2957027785 |
Directory | /workspace/14.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/15.rv_dm_alert_test.1565553100 |
Short name | T21 |
Test name | |
Test status | |
Simulation time | 126472659 ps |
CPU time | 0.75 seconds |
Started | May 14 12:50:06 PM PDT 24 |
Finished | May 14 12:50:10 PM PDT 24 |
Peak memory | 204340 kb |
Host | smart-079cc09a-4a50-45f8-be05-0c2fadfab13a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565553100 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.1565553100 |
Directory | /workspace/15.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/16.rv_dm_alert_test.2616104805 |
Short name | T64 |
Test name | |
Test status | |
Simulation time | 23790088 ps |
CPU time | 0.71 seconds |
Started | May 14 12:50:05 PM PDT 24 |
Finished | May 14 12:50:09 PM PDT 24 |
Peak memory | 204168 kb |
Host | smart-74067515-1052-4497-bac5-a9b455e9e826 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616104805 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.2616104805 |
Directory | /workspace/16.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/16.rv_dm_stress_all.2468972227 |
Short name | T11 |
Test name | |
Test status | |
Simulation time | 4347871459 ps |
CPU time | 8.08 seconds |
Started | May 14 12:50:10 PM PDT 24 |
Finished | May 14 12:50:21 PM PDT 24 |
Peak memory | 204548 kb |
Host | smart-9eaca9a9-4ec5-44bd-956a-8a7afd6623e3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468972227 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.2468972227 |
Directory | /workspace/16.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/17.rv_dm_alert_test.3606160824 |
Short name | T130 |
Test name | |
Test status | |
Simulation time | 30039160 ps |
CPU time | 0.73 seconds |
Started | May 14 12:50:05 PM PDT 24 |
Finished | May 14 12:50:08 PM PDT 24 |
Peak memory | 204360 kb |
Host | smart-2efd4303-01c3-4117-942b-e5cb36e02aa3 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606160824 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.3606160824 |
Directory | /workspace/17.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/18.rv_dm_alert_test.531608638 |
Short name | T134 |
Test name | |
Test status | |
Simulation time | 31696975 ps |
CPU time | 0.73 seconds |
Started | May 14 12:50:20 PM PDT 24 |
Finished | May 14 12:50:23 PM PDT 24 |
Peak memory | 204360 kb |
Host | smart-54c22b76-5228-481c-9764-40480e4596cb |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531608638 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.531608638 |
Directory | /workspace/18.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/19.rv_dm_alert_test.17098254 |
Short name | T18 |
Test name | |
Test status | |
Simulation time | 27919110 ps |
CPU time | 0.72 seconds |
Started | May 14 12:50:11 PM PDT 24 |
Finished | May 14 12:50:14 PM PDT 24 |
Peak memory | 204320 kb |
Host | smart-629aec63-d404-42b0-a1ff-cf80231bb497 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17098254 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.17098254 |
Directory | /workspace/19.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/19.rv_dm_stress_all.416068450 |
Short name | T24 |
Test name | |
Test status | |
Simulation time | 5881983409 ps |
CPU time | 10.49 seconds |
Started | May 14 12:50:12 PM PDT 24 |
Finished | May 14 12:50:25 PM PDT 24 |
Peak memory | 204556 kb |
Host | smart-4d5a5860-3efe-488e-836f-e2d6fe49cd47 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416068450 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.416068450 |
Directory | /workspace/19.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/2.rv_dm_alert_test.353181695 |
Short name | T144 |
Test name | |
Test status | |
Simulation time | 22830402 ps |
CPU time | 0.72 seconds |
Started | May 14 12:49:54 PM PDT 24 |
Finished | May 14 12:49:56 PM PDT 24 |
Peak memory | 204368 kb |
Host | smart-7cb7e231-e3d6-47d1-85da-ee92eb5caa2b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353181695 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.353181695 |
Directory | /workspace/2.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/2.rv_dm_sec_cm.1595058333 |
Short name | T50 |
Test name | |
Test status | |
Simulation time | 177321993 ps |
CPU time | 1.04 seconds |
Started | May 14 12:49:55 PM PDT 24 |
Finished | May 14 12:49:58 PM PDT 24 |
Peak memory | 228996 kb |
Host | smart-83e15e23-c8f0-4816-9714-bc9517347f8e |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595058333 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.1595058333 |
Directory | /workspace/2.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/20.rv_dm_alert_test.3395480473 |
Short name | T1 |
Test name | |
Test status | |
Simulation time | 31558631 ps |
CPU time | 0.7 seconds |
Started | May 14 12:50:11 PM PDT 24 |
Finished | May 14 12:50:14 PM PDT 24 |
Peak memory | 204264 kb |
Host | smart-c0e038c8-16c0-4617-abd2-ca2d9ffa1b7c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395480473 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.3395480473 |
Directory | /workspace/20.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/21.rv_dm_alert_test.1049681756 |
Short name | T22 |
Test name | |
Test status | |
Simulation time | 48992811 ps |
CPU time | 0.74 seconds |
Started | May 14 12:50:13 PM PDT 24 |
Finished | May 14 12:50:17 PM PDT 24 |
Peak memory | 204648 kb |
Host | smart-f5e64ad9-0279-456a-bea5-407558781bdc |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049681756 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.1049681756 |
Directory | /workspace/21.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/22.rv_dm_alert_test.1053512333 |
Short name | T20 |
Test name | |
Test status | |
Simulation time | 57310725 ps |
CPU time | 0.72 seconds |
Started | May 14 12:50:13 PM PDT 24 |
Finished | May 14 12:50:16 PM PDT 24 |
Peak memory | 204144 kb |
Host | smart-ef704ac5-a5f1-4154-b658-4532350748f6 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053512333 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.1053512333 |
Directory | /workspace/22.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/23.rv_dm_alert_test.3434197690 |
Short name | T129 |
Test name | |
Test status | |
Simulation time | 31827636 ps |
CPU time | 0.72 seconds |
Started | May 14 12:50:32 PM PDT 24 |
Finished | May 14 12:50:34 PM PDT 24 |
Peak memory | 204420 kb |
Host | smart-e078b966-5b29-4896-a8ed-7d9bcd571c71 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434197690 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.3434197690 |
Directory | /workspace/23.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/24.rv_dm_alert_test.1460268813 |
Short name | T46 |
Test name | |
Test status | |
Simulation time | 45659212 ps |
CPU time | 0.74 seconds |
Started | May 14 12:50:34 PM PDT 24 |
Finished | May 14 12:50:36 PM PDT 24 |
Peak memory | 204420 kb |
Host | smart-feaa3fa6-1107-4586-8ae2-cdfe75c5bc59 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460268813 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.1460268813 |
Directory | /workspace/24.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/25.rv_dm_alert_test.1643351238 |
Short name | T15 |
Test name | |
Test status | |
Simulation time | 20845744 ps |
CPU time | 0.73 seconds |
Started | May 14 12:50:13 PM PDT 24 |
Finished | May 14 12:50:17 PM PDT 24 |
Peak memory | 204244 kb |
Host | smart-d410f47b-effd-420a-8d70-c646f62e3d56 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643351238 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.1643351238 |
Directory | /workspace/25.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/26.rv_dm_alert_test.2606765287 |
Short name | T132 |
Test name | |
Test status | |
Simulation time | 15669264 ps |
CPU time | 0.72 seconds |
Started | May 14 12:50:14 PM PDT 24 |
Finished | May 14 12:50:18 PM PDT 24 |
Peak memory | 204344 kb |
Host | smart-b6195d3e-0523-40e4-85da-5fae490e6fee |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606765287 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.2606765287 |
Directory | /workspace/26.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/27.rv_dm_alert_test.3485270176 |
Short name | T138 |
Test name | |
Test status | |
Simulation time | 51150830 ps |
CPU time | 0.72 seconds |
Started | May 14 12:50:15 PM PDT 24 |
Finished | May 14 12:50:18 PM PDT 24 |
Peak memory | 204224 kb |
Host | smart-64352d05-b9ed-4413-a479-698b71cecf31 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485270176 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.3485270176 |
Directory | /workspace/27.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/28.rv_dm_alert_test.2201470916 |
Short name | T14 |
Test name | |
Test status | |
Simulation time | 64028654 ps |
CPU time | 0.72 seconds |
Started | May 14 12:50:14 PM PDT 24 |
Finished | May 14 12:50:18 PM PDT 24 |
Peak memory | 204316 kb |
Host | smart-cad465fa-6505-4bbf-b1ac-3c53ffa2f476 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201470916 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.2201470916 |
Directory | /workspace/28.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/29.rv_dm_alert_test.2292396768 |
Short name | T128 |
Test name | |
Test status | |
Simulation time | 67033354 ps |
CPU time | 0.74 seconds |
Started | May 14 12:50:14 PM PDT 24 |
Finished | May 14 12:50:20 PM PDT 24 |
Peak memory | 204316 kb |
Host | smart-2c1f7132-6659-4af7-8d06-ac5e7f01b840 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292396768 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.2292396768 |
Directory | /workspace/29.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/3.rv_dm_alert_test.968922103 |
Short name | T133 |
Test name | |
Test status | |
Simulation time | 25061850 ps |
CPU time | 0.78 seconds |
Started | May 14 12:49:56 PM PDT 24 |
Finished | May 14 12:49:59 PM PDT 24 |
Peak memory | 204300 kb |
Host | smart-d7345954-44d6-48d5-978b-7d75f9a9e18a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968922103 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.968922103 |
Directory | /workspace/3.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/3.rv_dm_sec_cm.834758296 |
Short name | T19 |
Test name | |
Test status | |
Simulation time | 83898768 ps |
CPU time | 1.19 seconds |
Started | May 14 12:49:59 PM PDT 24 |
Finished | May 14 12:50:03 PM PDT 24 |
Peak memory | 229064 kb |
Host | smart-a19c3c87-d62a-4acc-ae24-f09728b2d53a |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834758296 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.834758296 |
Directory | /workspace/3.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/30.rv_dm_alert_test.3959523286 |
Short name | T43 |
Test name | |
Test status | |
Simulation time | 49505642 ps |
CPU time | 0.72 seconds |
Started | May 14 12:50:13 PM PDT 24 |
Finished | May 14 12:50:16 PM PDT 24 |
Peak memory | 204356 kb |
Host | smart-afb9a208-ba40-459b-9e4e-d7c03561248e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959523286 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.3959523286 |
Directory | /workspace/30.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/31.rv_dm_alert_test.4050299019 |
Short name | T25 |
Test name | |
Test status | |
Simulation time | 20578250 ps |
CPU time | 0.72 seconds |
Started | May 14 12:50:18 PM PDT 24 |
Finished | May 14 12:50:21 PM PDT 24 |
Peak memory | 204164 kb |
Host | smart-860d02cb-00a4-448e-8302-921905db9a9a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050299019 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.4050299019 |
Directory | /workspace/31.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/32.rv_dm_alert_test.1599843258 |
Short name | T141 |
Test name | |
Test status | |
Simulation time | 95870257 ps |
CPU time | 0.71 seconds |
Started | May 14 12:50:16 PM PDT 24 |
Finished | May 14 12:50:20 PM PDT 24 |
Peak memory | 204364 kb |
Host | smart-88047cd1-0542-4c81-bdfa-2622592c7a99 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599843258 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.1599843258 |
Directory | /workspace/32.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/33.rv_dm_alert_test.1573438516 |
Short name | T136 |
Test name | |
Test status | |
Simulation time | 40473427 ps |
CPU time | 0.7 seconds |
Started | May 14 12:50:44 PM PDT 24 |
Finished | May 14 12:50:46 PM PDT 24 |
Peak memory | 204420 kb |
Host | smart-8eaa5c95-db91-4c68-ac97-b76cbca9d368 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573438516 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.1573438516 |
Directory | /workspace/33.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/34.rv_dm_alert_test.1745062702 |
Short name | T146 |
Test name | |
Test status | |
Simulation time | 55069476 ps |
CPU time | 0.78 seconds |
Started | May 14 12:50:14 PM PDT 24 |
Finished | May 14 12:50:18 PM PDT 24 |
Peak memory | 204344 kb |
Host | smart-e014427a-8beb-40a8-b371-e0527ef3e02f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745062702 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.1745062702 |
Directory | /workspace/34.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/35.rv_dm_alert_test.2630746826 |
Short name | T126 |
Test name | |
Test status | |
Simulation time | 162491317 ps |
CPU time | 0.7 seconds |
Started | May 14 12:50:13 PM PDT 24 |
Finished | May 14 12:50:17 PM PDT 24 |
Peak memory | 204304 kb |
Host | smart-14ef61d9-7e82-4381-b531-868fabbcc969 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630746826 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.2630746826 |
Directory | /workspace/35.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/36.rv_dm_alert_test.3282702501 |
Short name | T33 |
Test name | |
Test status | |
Simulation time | 33452959 ps |
CPU time | 0.73 seconds |
Started | May 14 12:50:19 PM PDT 24 |
Finished | May 14 12:50:22 PM PDT 24 |
Peak memory | 204164 kb |
Host | smart-42392e0e-4da3-4dd0-99e4-e73a1782874d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282702501 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.3282702501 |
Directory | /workspace/36.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/37.rv_dm_alert_test.2382653951 |
Short name | T32 |
Test name | |
Test status | |
Simulation time | 67194368 ps |
CPU time | 0.69 seconds |
Started | May 14 12:50:20 PM PDT 24 |
Finished | May 14 12:50:23 PM PDT 24 |
Peak memory | 204260 kb |
Host | smart-55686f06-263f-4110-a63d-9d62179fc36e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382653951 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.2382653951 |
Directory | /workspace/37.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/37.rv_dm_stress_all.127271446 |
Short name | T6 |
Test name | |
Test status | |
Simulation time | 5401390276 ps |
CPU time | 14.89 seconds |
Started | May 14 12:50:18 PM PDT 24 |
Finished | May 14 12:50:35 PM PDT 24 |
Peak memory | 204500 kb |
Host | smart-0a3e6195-7ed9-4552-a715-0f7ac5fc4e98 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127271446 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.127271446 |
Directory | /workspace/37.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/38.rv_dm_alert_test.258336976 |
Short name | T139 |
Test name | |
Test status | |
Simulation time | 15708779 ps |
CPU time | 0.71 seconds |
Started | May 14 12:50:22 PM PDT 24 |
Finished | May 14 12:50:24 PM PDT 24 |
Peak memory | 204260 kb |
Host | smart-24495954-4812-4ff7-9b5a-4c14f934131d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258336976 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.258336976 |
Directory | /workspace/38.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/39.rv_dm_alert_test.3202213752 |
Short name | T147 |
Test name | |
Test status | |
Simulation time | 44566329 ps |
CPU time | 0.69 seconds |
Started | May 14 12:50:28 PM PDT 24 |
Finished | May 14 12:50:29 PM PDT 24 |
Peak memory | 204320 kb |
Host | smart-4d2b5097-42c1-4806-8c8f-bc13b1502f7b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202213752 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.3202213752 |
Directory | /workspace/39.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/39.rv_dm_stress_all.387220649 |
Short name | T65 |
Test name | |
Test status | |
Simulation time | 9658650122 ps |
CPU time | 10.57 seconds |
Started | May 14 12:50:26 PM PDT 24 |
Finished | May 14 12:50:38 PM PDT 24 |
Peak memory | 204436 kb |
Host | smart-d6fe4a12-4b45-4d55-a55b-3783b003f6db |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387220649 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.387220649 |
Directory | /workspace/39.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/4.rv_dm_alert_test.968964432 |
Short name | T123 |
Test name | |
Test status | |
Simulation time | 30892184 ps |
CPU time | 0.68 seconds |
Started | May 14 12:49:54 PM PDT 24 |
Finished | May 14 12:49:56 PM PDT 24 |
Peak memory | 204284 kb |
Host | smart-73c94121-5556-4018-aaca-dbf48906ff10 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968964432 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.968964432 |
Directory | /workspace/4.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/4.rv_dm_sec_cm.397413367 |
Short name | T2 |
Test name | |
Test status | |
Simulation time | 83480176 ps |
CPU time | 1.15 seconds |
Started | May 14 12:49:58 PM PDT 24 |
Finished | May 14 12:50:03 PM PDT 24 |
Peak memory | 228904 kb |
Host | smart-e23a53b9-da6a-4610-a6e5-e61b8b07a0a8 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397413367 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.397413367 |
Directory | /workspace/4.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/40.rv_dm_alert_test.296782063 |
Short name | T108 |
Test name | |
Test status | |
Simulation time | 35642699 ps |
CPU time | 0.73 seconds |
Started | May 14 12:50:19 PM PDT 24 |
Finished | May 14 12:50:22 PM PDT 24 |
Peak memory | 204336 kb |
Host | smart-9954b596-c44d-4ceb-b7e2-22703b9b7679 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296782063 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.296782063 |
Directory | /workspace/40.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/41.rv_dm_alert_test.3424305177 |
Short name | T149 |
Test name | |
Test status | |
Simulation time | 55199222 ps |
CPU time | 0.68 seconds |
Started | May 14 12:50:19 PM PDT 24 |
Finished | May 14 12:50:22 PM PDT 24 |
Peak memory | 204360 kb |
Host | smart-eca67a7e-7197-409e-9c71-900e766d30d8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424305177 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.3424305177 |
Directory | /workspace/41.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/43.rv_dm_alert_test.2919866633 |
Short name | T122 |
Test name | |
Test status | |
Simulation time | 29704219 ps |
CPU time | 0.7 seconds |
Started | May 14 12:50:18 PM PDT 24 |
Finished | May 14 12:50:21 PM PDT 24 |
Peak memory | 204364 kb |
Host | smart-73f637e9-fc4e-43e4-aeb5-5ddfeaac1aa2 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919866633 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.2919866633 |
Directory | /workspace/43.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/44.rv_dm_alert_test.3462006881 |
Short name | T142 |
Test name | |
Test status | |
Simulation time | 39163811 ps |
CPU time | 0.71 seconds |
Started | May 14 12:50:21 PM PDT 24 |
Finished | May 14 12:50:24 PM PDT 24 |
Peak memory | 204368 kb |
Host | smart-0c79b3af-e87e-4bf9-820b-acd63aa65ca1 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462006881 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.3462006881 |
Directory | /workspace/44.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/46.rv_dm_alert_test.3241648946 |
Short name | T119 |
Test name | |
Test status | |
Simulation time | 59380092 ps |
CPU time | 0.7 seconds |
Started | May 14 12:50:35 PM PDT 24 |
Finished | May 14 12:50:37 PM PDT 24 |
Peak memory | 204336 kb |
Host | smart-60b8c0be-23f3-4e4e-b680-51775c3c7d7d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241648946 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.3241648946 |
Directory | /workspace/46.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/47.rv_dm_alert_test.1447138831 |
Short name | T135 |
Test name | |
Test status | |
Simulation time | 31686335 ps |
CPU time | 0.8 seconds |
Started | May 14 12:50:49 PM PDT 24 |
Finished | May 14 12:50:51 PM PDT 24 |
Peak memory | 204368 kb |
Host | smart-c9065852-d39a-4997-b7bd-3b503acb795b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447138831 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.1447138831 |
Directory | /workspace/47.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/48.rv_dm_alert_test.905197048 |
Short name | T143 |
Test name | |
Test status | |
Simulation time | 45799164 ps |
CPU time | 0.76 seconds |
Started | May 14 12:50:27 PM PDT 24 |
Finished | May 14 12:50:29 PM PDT 24 |
Peak memory | 204364 kb |
Host | smart-7bc84885-0247-40c1-a990-1599faa079e6 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905197048 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.905197048 |
Directory | /workspace/48.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/49.rv_dm_alert_test.2758437245 |
Short name | T120 |
Test name | |
Test status | |
Simulation time | 30773463 ps |
CPU time | 0.77 seconds |
Started | May 14 12:50:26 PM PDT 24 |
Finished | May 14 12:50:28 PM PDT 24 |
Peak memory | 204340 kb |
Host | smart-3850bdbe-46d6-4115-b3e1-01fb045f314b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758437245 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.2758437245 |
Directory | /workspace/49.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/5.rv_dm_alert_test.919792019 |
Short name | T48 |
Test name | |
Test status | |
Simulation time | 40661654 ps |
CPU time | 0.73 seconds |
Started | May 14 12:49:58 PM PDT 24 |
Finished | May 14 12:50:02 PM PDT 24 |
Peak memory | 204328 kb |
Host | smart-ecb8b3ea-99e1-4c85-880a-03fb52c8e549 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919792019 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.919792019 |
Directory | /workspace/5.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/6.rv_dm_alert_test.3765654383 |
Short name | T127 |
Test name | |
Test status | |
Simulation time | 23318822 ps |
CPU time | 0.71 seconds |
Started | May 14 12:49:54 PM PDT 24 |
Finished | May 14 12:49:55 PM PDT 24 |
Peak memory | 204252 kb |
Host | smart-ce7c59f9-568f-43bd-bcde-dce1e75f3235 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765654383 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.3765654383 |
Directory | /workspace/6.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/6.rv_dm_stress_all.1964779958 |
Short name | T62 |
Test name | |
Test status | |
Simulation time | 1182852841 ps |
CPU time | 2.59 seconds |
Started | May 14 12:49:57 PM PDT 24 |
Finished | May 14 12:50:03 PM PDT 24 |
Peak memory | 204592 kb |
Host | smart-4ece15e2-c22e-4c37-9bd9-d505c9d82669 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964779958 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.1964779958 |
Directory | /workspace/6.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/7.rv_dm_alert_test.2966346858 |
Short name | T63 |
Test name | |
Test status | |
Simulation time | 52856468 ps |
CPU time | 0.73 seconds |
Started | May 14 12:49:57 PM PDT 24 |
Finished | May 14 12:50:01 PM PDT 24 |
Peak memory | 204260 kb |
Host | smart-294a5d87-5755-443b-ad8e-ebf3070e7a5f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966346858 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.2966346858 |
Directory | /workspace/7.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/8.rv_dm_alert_test.902769644 |
Short name | T137 |
Test name | |
Test status | |
Simulation time | 60077992 ps |
CPU time | 0.69 seconds |
Started | May 14 12:50:04 PM PDT 24 |
Finished | May 14 12:50:07 PM PDT 24 |
Peak memory | 204244 kb |
Host | smart-3b78c5eb-5053-4ea8-af66-8e64c3ba4b42 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902769644 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.902769644 |
Directory | /workspace/8.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/9.rv_dm_alert_test.4164295411 |
Short name | T124 |
Test name | |
Test status | |
Simulation time | 113139540 ps |
CPU time | 0.7 seconds |
Started | May 14 12:50:05 PM PDT 24 |
Finished | May 14 12:50:08 PM PDT 24 |
Peak memory | 204332 kb |
Host | smart-1620a185-351d-427e-876d-bd864e361a1c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164295411 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.4164295411 |
Directory | /workspace/9.rv_dm_alert_test/latest |
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