Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	172249	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	486689	1		T9	35		T11	80		T6	4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	418588	1		T9	22		T11	80		T6	8
values[0x0]	118289	1		T9	14		T6	1		T7	43
values[0x1]	122061	1		T9	14		T7	35		T10	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	131500	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	527438	1		T9	39		T11	80		T6	6

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2288	1		T8	2		T32	24		T74	12
valid_sources[0x01]	2550	1		T12	1		T8	1		T32	58
valid_sources[0x02]	2613	1		T12	3		T32	24		T28	2
valid_sources[0x03]	3470	1		T8	1		T28	3		T79	2
valid_sources[0x04]	2333	1		T32	10		T28	2		T79	9
valid_sources[0x05]	2455	1		T32	47		T74	14		T80	14
valid_sources[0x06]	2509	1		T12	5		T32	95		T28	3
valid_sources[0x07]	3726	1		T8	1		T32	12		T28	1
valid_sources[0x08]	2586	1		T8	2		T27	1		T32	2
valid_sources[0x09]	2543	1		T12	1		T32	13		T28	1
valid_sources[0x0a]	2805	1		T12	7		T31	111		T32	8
valid_sources[0x0b]	2229	1		T27	1		T32	30		T74	2
valid_sources[0x0c]	2275	1		T7	90		T32	22		T28	1
valid_sources[0x0d]	2593	1		T17	5		T32	4		T74	11
valid_sources[0x0e]	2707	1		T32	1		T28	1		T74	11
valid_sources[0x0f]	2599	1		T32	7		T74	9		T80	3
valid_sources[0x10]	2794	1		T32	36		T28	1		T74	4
valid_sources[0x11]	2337	1		T8	1		T32	1		T28	1
valid_sources[0x12]	2770	1		T12	2		T17	4		T32	19
valid_sources[0x13]	2567	1		T32	27		T28	2		T79	3
valid_sources[0x14]	2691	1		T32	28		T28	1		T79	1
valid_sources[0x15]	2437	1		T8	1		T32	37		T28	1
valid_sources[0x16]	2724	1		T12	3		T8	4		T32	9
valid_sources[0x17]	2213	1		T32	1		T28	6		T74	11
valid_sources[0x18]	2335	1		T12	3		T32	30		T28	1
valid_sources[0x19]	3314	1		T8	1		T32	23		T28	4
valid_sources[0x1a]	1955	1		T32	21		T79	8		T74	7
valid_sources[0x1b]	2296	1		T32	25		T74	13		T80	1
valid_sources[0x1c]	2409	1		T8	2		T28	4		T74	7
valid_sources[0x1d]	2260	1		T32	39		T28	1		T74	1
valid_sources[0x1e]	2706	1		T12	1		T28	1		T79	80
valid_sources[0x1f]	2181	1		T12	1		T32	2		T79	1
valid_sources[0x20]	2572	1		T32	14		T28	1		T74	5
valid_sources[0x21]	2822	1		T32	23		T79	3		T74	15
valid_sources[0x22]	2677	1		T8	1		T32	38		T28	2
valid_sources[0x23]	2596	1		T12	1		T8	1		T32	40
valid_sources[0x24]	2967	1		T32	54		T28	2		T74	3
valid_sources[0x25]	2345	1		T27	1		T32	5		T28	1
valid_sources[0x26]	2259	1		T32	35		T28	1		T74	5
valid_sources[0x27]	2424	1		T32	41		T79	8		T74	13
valid_sources[0x28]	2551	1		T8	1		T32	55		T28	1
valid_sources[0x29]	2640	1		T31	135		T28	5		T74	5
valid_sources[0x2a]	2444	1		T32	22		T79	26		T74	13
valid_sources[0x2b]	3518	1		T32	21		T79	22		T80	3
valid_sources[0x2c]	2301	1		T32	6		T28	3		T74	8
valid_sources[0x2d]	2329	1		T18	1		T8	2		T32	13
valid_sources[0x2e]	2724	1		T27	1		T32	27		T28	1
valid_sources[0x2f]	3092	1		T6	9		T12	5		T32	76
valid_sources[0x30]	2698	1		T31	38		T32	14		T28	2
valid_sources[0x31]	2433	1		T12	1		T8	1		T32	99
valid_sources[0x32]	2270	1		T32	34		T28	3		T79	29
valid_sources[0x33]	2845	1		T32	8		T79	40		T74	3
valid_sources[0x34]	2421	1		T32	89		T28	2		T79	22
valid_sources[0x35]	2898	1		T32	36		T28	1		T74	13
valid_sources[0x36]	2754	1		T32	82		T28	3		T79	4
valid_sources[0x37]	2385	1		T9	50		T32	13		T28	1
valid_sources[0x38]	2647	1		T8	1		T32	19		T28	2
valid_sources[0x39]	2990	1		T27	1		T32	3		T79	15
valid_sources[0x3a]	2062	1		T8	1		T17	3		T32	15
valid_sources[0x3b]	2430	1		T32	17		T28	1		T74	2
valid_sources[0x3c]	2694	1		T75	1		T32	24		T28	2
valid_sources[0x3d]	2653	1		T12	5		T32	74		T28	1
valid_sources[0x3e]	2716	1		T32	27		T28	1		T79	62
valid_sources[0x3f]	2275	1		T12	2		T32	19		T28	1
valid_sources[0x40]	2806	1		T8	1		T32	15		T28	3
valid_sources[0x41]	2355	1		T32	43		T28	2		T79	28
valid_sources[0x42]	2680	1		T32	19		T28	2		T74	7
valid_sources[0x43]	2950	1		T8	1		T28	4		T79	14
valid_sources[0x44]	2479	1		T32	21		T74	8		T80	11
valid_sources[0x45]	2353	1		T32	13		T79	29		T74	9
valid_sources[0x46]	2478	1		T32	10		T74	10		T80	3
valid_sources[0x47]	2427	1		T8	2		T32	23		T28	4
valid_sources[0x48]	3054	1		T32	2		T74	6		T80	6
valid_sources[0x49]	2204	1		T8	1		T32	18		T28	3
valid_sources[0x4a]	2676	1		T12	5		T32	7		T28	1
valid_sources[0x4b]	2033	1		T32	25		T28	3		T74	3
valid_sources[0x4c]	2365	1		T12	4		T8	1		T17	22
valid_sources[0x4d]	2606	1		T28	6		T79	4		T74	10
valid_sources[0x4e]	2430	1		T12	2		T8	1		T32	1
valid_sources[0x4f]	2719	1		T8	1		T27	2		T32	32
valid_sources[0x50]	2505	1		T8	1		T32	42		T74	3
valid_sources[0x51]	2463	1		T32	32		T28	1		T79	14
valid_sources[0x52]	2642	1		T32	16		T28	2		T79	21
valid_sources[0x53]	2809	1		T32	38		T28	1		T79	7
valid_sources[0x54]	2546	1		T32	60		T74	12		T80	6
valid_sources[0x55]	2411	1		T32	16		T28	4		T74	1
valid_sources[0x56]	2418	1		T12	2		T79	3		T74	8
valid_sources[0x57]	2405	1		T32	46		T79	21		T74	10
valid_sources[0x58]	2270	1		T32	11		T79	28		T74	11
valid_sources[0x59]	2347	1		T10	3		T8	1		T32	23
valid_sources[0x5a]	2181	1		T32	30		T74	4		T80	9
valid_sources[0x5b]	2682	1		T8	1		T32	24		T28	2
valid_sources[0x5c]	2814	1		T32	23		T28	1		T79	10
valid_sources[0x5d]	2506	1		T12	4		T8	2		T75	1
valid_sources[0x5e]	2488	1		T12	5		T32	9		T28	2
valid_sources[0x5f]	2559	1		T32	17		T28	3		T74	15
valid_sources[0x60]	2132	1		T8	2		T32	1		T28	1
valid_sources[0x61]	2598	1		T8	2		T17	4		T28	3
valid_sources[0x62]	2289	1		T32	26		T74	11		T86	119
valid_sources[0x63]	2643	1		T12	1		T8	2		T32	13
valid_sources[0x64]	2325	1		T8	1		T32	9		T74	13
valid_sources[0x65]	2542	1		T8	1		T32	96		T28	1
valid_sources[0x66]	2571	1		T32	32		T74	13		T80	3
valid_sources[0x67]	2447	1		T8	2		T32	38		T28	1
valid_sources[0x68]	2412	1		T8	1		T32	30		T28	1
valid_sources[0x69]	2791	1		T32	23		T28	1		T80	2
valid_sources[0x6a]	2449	1		T12	1		T8	1		T32	58
valid_sources[0x6b]	2367	1		T32	27		T28	1		T74	16
valid_sources[0x6c]	2188	1		T32	2		T74	12		T80	3
valid_sources[0x6d]	2067	1		T32	46		T74	5		T80	2
valid_sources[0x6e]	2531	1		T8	1		T17	2		T32	29
valid_sources[0x6f]	3481	1		T32	32		T28	1		T74	1
valid_sources[0x70]	2329	1		T32	22		T28	1		T80	2
valid_sources[0x71]	2536	1		T8	1		T32	5		T28	1
valid_sources[0x72]	2313	1		T32	29		T79	33		T74	8
valid_sources[0x73]	2306	1		T8	1		T32	51		T28	1
valid_sources[0x74]	2402	1		T12	2		T32	7		T79	5
valid_sources[0x75]	2832	1		T12	5		T32	15		T28	2
valid_sources[0x76]	2301	1		T8	1		T32	11		T28	1
valid_sources[0x77]	2314	1		T32	13		T28	1		T74	6
valid_sources[0x78]	2517	1		T32	11		T28	1		T79	2
valid_sources[0x79]	2254	1		T32	58		T28	3		T74	8
valid_sources[0x7a]	2366	1		T27	1		T32	13		T79	1
valid_sources[0x7b]	2495	1		T8	1		T32	32		T74	4
valid_sources[0x7c]	3108	1		T8	1		T75	1		T32	8
valid_sources[0x7d]	2705	1		T32	14		T28	2		T79	13
valid_sources[0x7e]	2614	1		T32	35		T74	10		T80	1
valid_sources[0x7f]	2483	1		T32	16		T28	1		T79	28
valid_sources[0x80]	2895	1		T32	4		T28	1		T74	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

253210

1

T9

12

T11

80

T6

4

values[0x0]

all_enables

biggest_size

116839

1

T9

11

T7

13

T10

9

values[0x1]

all_enables

biggest_size

116640

1

T9

12

T7

6

T10

3

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4054	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	15470	1		T2	1		T3	5		T19	3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	7753	1		T31	28		T27	15		T32	24
values[0x0]	5742	1		T1	2		T2	8		T3	3
values[0x1]	6029	1		T1	4		T2	8		T3	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3066	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	16458	1		T1	1		T2	2		T3	5

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	65	1		T42	3		T130	1		T32	1
valid_sources[0x01]	59	1		T54	1		T28	1		T84	3
valid_sources[0x02]	51	1		T83	1		T89	2		T131	1
valid_sources[0x03]	62	1		T54	2		T83	1		T89	2
valid_sources[0x04]	85	1		T132	1		T27	2		T28	6
valid_sources[0x05]	58	1		T53	1		T28	2		T89	4
valid_sources[0x06]	48	1		T3	1		T28	1		T80	2
valid_sources[0x07]	103	1		T133	1		T27	1		T28	4
valid_sources[0x08]	45	1		T132	1		T28	1		T89	2
valid_sources[0x09]	86	1		T28	1		T74	1		T80	2
valid_sources[0x0a]	65	1		T28	4		T80	3		T83	1
valid_sources[0x0b]	75	1		T134	14		T28	2		T83	1
valid_sources[0x0c]	73	1		T31	6		T89	3		T84	3
valid_sources[0x0d]	74	1		T74	3		T80	7		T83	1
valid_sources[0x0e]	74	1		T20	13		T52	2		T28	1
valid_sources[0x0f]	82	1		T28	4		T83	1		T89	1
valid_sources[0x10]	65	1		T83	1		T89	3		T85	1
valid_sources[0x11]	95	1		T135	1		T27	1		T80	2
valid_sources[0x12]	78	1		T4	1		T56	2		T43	1
valid_sources[0x13]	68	1		T28	1		T80	1		T83	2
valid_sources[0x14]	71	1		T28	1		T83	1		T89	5
valid_sources[0x15]	65	1		T4	3		T27	1		T28	3
valid_sources[0x16]	49	1		T29	1		T83	3		T89	1
valid_sources[0x17]	90	1		T36	1		T27	1		T80	2
valid_sources[0x18]	72	1		T28	1		T29	1		T89	2
valid_sources[0x19]	67	1		T133	1		T32	2		T80	3
valid_sources[0x1a]	69	1		T41	4		T29	1		T80	1
valid_sources[0x1b]	116	1		T22	1		T116	1		T27	1
valid_sources[0x1c]	105	1		T40	1		T130	1		T28	2
valid_sources[0x1d]	94	1		T136	1		T31	1		T32	1
valid_sources[0x1e]	54	1		T1	1		T32	1		T28	2
valid_sources[0x1f]	87	1		T28	4		T80	2		T89	2
valid_sources[0x20]	70	1		T137	2		T28	3		T80	2
valid_sources[0x21]	68	1		T32	1		T28	4		T79	14
valid_sources[0x22]	70	1		T117	1		T80	5		T89	2
valid_sources[0x23]	85	1		T3	1		T133	1		T27	2
valid_sources[0x24]	51	1		T54	1		T132	1		T80	1
valid_sources[0x25]	84	1		T53	1		T28	4		T80	1
valid_sources[0x26]	72	1		T57	1		T138	1		T27	2
valid_sources[0x27]	69	1		T57	1		T28	3		T80	1
valid_sources[0x28]	152	1		T42	2		T80	1		T83	1
valid_sources[0x29]	73	1		T117	1		T28	3		T83	4
valid_sources[0x2a]	147	1		T53	1		T117	1		T32	1
valid_sources[0x2b]	61	1		T39	1		T31	1		T28	6
valid_sources[0x2c]	120	1		T136	1		T28	1		T83	2
valid_sources[0x2d]	50	1		T28	1		T80	2		T87	2
valid_sources[0x2e]	100	1		T32	2		T80	1		T83	1
valid_sources[0x2f]	84	1		T132	1		T27	1		T82	5
valid_sources[0x30]	70	1		T116	1		T28	2		T80	2
valid_sources[0x31]	59	1		T28	7		T80	1		T82	3
valid_sources[0x32]	35	1		T29	1		T83	1		T89	3
valid_sources[0x33]	60	1		T80	1		T82	3		T89	1
valid_sources[0x34]	48	1		T80	2		T83	2		T89	2
valid_sources[0x35]	77	1		T28	1		T80	1		T83	1
valid_sources[0x36]	85	1		T32	3		T28	1		T80	1
valid_sources[0x37]	47	1		T28	1		T80	1		T89	1
valid_sources[0x38]	75	1		T3	1		T28	3		T29	1
valid_sources[0x39]	102	1		T116	1		T89	3		T131	2
valid_sources[0x3a]	57	1		T27	1		T80	1		T82	3
valid_sources[0x3b]	56	1		T53	1		T27	3		T80	1
valid_sources[0x3c]	64	1		T53	2		T80	1		T83	2
valid_sources[0x3d]	86	1		T130	1		T28	9		T83	4
valid_sources[0x3e]	65	1		T35	1		T28	1		T29	1
valid_sources[0x3f]	83	1		T31	26		T80	2		T83	1
valid_sources[0x40]	63	1		T117	1		T32	1		T89	2
valid_sources[0x41]	59	1		T83	4		T89	4		T84	1
valid_sources[0x42]	78	1		T56	2		T139	4		T27	1
valid_sources[0x43]	67	1		T130	1		T28	6		T80	1
valid_sources[0x44]	97	1		T56	1		T116	1		T27	1
valid_sources[0x45]	122	1		T1	2		T54	1		T28	3
valid_sources[0x46]	62	1		T35	1		T28	1		T80	2
valid_sources[0x47]	63	1		T140	1		T28	1		T80	1
valid_sources[0x48]	90	1		T31	6		T74	2		T80	3
valid_sources[0x49]	68	1		T27	2		T32	2		T28	3
valid_sources[0x4a]	88	1		T53	1		T40	1		T80	1
valid_sources[0x4b]	90	1		T116	2		T27	2		T28	1
valid_sources[0x4c]	65	1		T135	3		T80	1		T85	2
valid_sources[0x4d]	65	1		T56	1		T27	1		T28	2
valid_sources[0x4e]	122	1		T130	1		T28	7		T80	2
valid_sources[0x4f]	80	1		T2	1		T80	5		T89	3
valid_sources[0x50]	66	1		T5	2		T27	1		T28	3
valid_sources[0x51]	98	1		T28	1		T80	3		T83	1
valid_sources[0x52]	94	1		T2	1		T32	1		T82	8
valid_sources[0x53]	70	1		T82	3		T89	1		T96	5
valid_sources[0x54]	48	1		T135	2		T80	2		T83	2
valid_sources[0x55]	53	1		T39	2		T82	1		T89	3
valid_sources[0x56]	70	1		T36	1		T31	3		T80	1
valid_sources[0x57]	77	1		T28	2		T80	4		T83	1
valid_sources[0x58]	60	1		T28	1		T29	2		T89	3
valid_sources[0x59]	101	1		T141	3		T28	3		T80	2
valid_sources[0x5a]	78	1		T130	1		T27	1		T80	1
valid_sources[0x5b]	103	1		T27	2		T28	1		T87	1
valid_sources[0x5c]	66	1		T28	4		T80	3		T82	1
valid_sources[0x5d]	75	1		T27	1		T32	2		T29	1
valid_sources[0x5e]	95	1		T2	2		T21	14		T116	1
valid_sources[0x5f]	94	1		T39	6		T117	2		T27	1
valid_sources[0x60]	65	1		T56	1		T142	1		T27	2
valid_sources[0x61]	95	1		T28	3		T83	3		T89	1
valid_sources[0x62]	71	1		T54	1		T31	3		T28	2
valid_sources[0x63]	75	1		T32	2		T81	6		T83	2
valid_sources[0x64]	97	1		T136	2		T27	1		T81	18
valid_sources[0x65]	75	1		T5	3		T35	1		T139	1
valid_sources[0x66]	89	1		T53	1		T31	3		T28	3
valid_sources[0x67]	92	1		T28	1		T82	25		T89	5
valid_sources[0x68]	36	1		T80	2		T82	1		T84	1
valid_sources[0x69]	62	1		T28	4		T80	2		T89	1
valid_sources[0x6a]	100	1		T16	1		T27	1		T28	1
valid_sources[0x6b]	75	1		T28	3		T74	3		T80	3
valid_sources[0x6c]	41	1		T27	1		T32	1		T80	2
valid_sources[0x6d]	79	1		T40	1		T43	1		T27	1
valid_sources[0x6e]	73	1		T28	2		T80	2		T89	2
valid_sources[0x6f]	66	1		T35	5		T140	2		T32	2
valid_sources[0x70]	75	1		T83	1		T89	4		T85	1
valid_sources[0x71]	87	1		T139	1		T28	1		T81	2
valid_sources[0x72]	95	1		T27	1		T32	2		T80	2
valid_sources[0x73]	94	1		T43	1		T27	1		T80	1
valid_sources[0x74]	45	1		T132	1		T27	1		T80	1
valid_sources[0x75]	181	1		T132	1		T31	3		T28	1
valid_sources[0x76]	101	1		T54	1		T27	2		T28	2
valid_sources[0x77]	59	1		T29	1		T80	2		T89	1
valid_sources[0x78]	57	1		T3	3		T143	1		T80	3
valid_sources[0x79]	53	1		T1	3		T32	2		T28	1
valid_sources[0x7a]	58	1		T80	2		T89	2		T85	1
valid_sources[0x7b]	64	1		T135	1		T133	1		T28	4
valid_sources[0x7c]	51	1		T28	1		T89	1		T96	4
valid_sources[0x7d]	98	1		T74	15		T80	1		T89	3
valid_sources[0x7e]	123	1		T32	2		T28	1		T85	1
valid_sources[0x7f]	56	1		T28	2		T80	1		T89	2
valid_sources[0x80]	79	1		T3	1		T28	2		T83	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

5372

1

T31

23

T27

15

T32

24

values[0x0]

all_enables

biggest_size

5107

1

T2

1

T3

2

T19

3

values[0x1]

all_enables

biggest_size

4991

1

T3

3

T20

1

T4

1