SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[rv_dm_mem_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[rv_dm_regs_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 677200 | 1 | T9 | 50 | T6 | 9 | T7 | 90 | |||
auto[1] | 12859 | 1 | T11 | 80 | T31 | 52 | T27 | 38 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 689845 | 1 | T9 | 50 | T11 | 80 | T6 | 9 | |||
values[1] | 20 | 1 | T82 | 1 | T84 | 1 | T85 | 2 | |||
values[2] | 5 | 1 | T84 | 1 | T85 | 1 | T121 | 1 | |||
values[3] | 109 | 1 | T81 | 2 | T82 | 9 | T84 | 10 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 689826 | 1 | T9 | 50 | T11 | 80 | T6 | 9 | |||
values[1] | 27 | 1 | T82 | 4 | T84 | 3 | T85 | 1 | |||
values[2] | 7 | 1 | T84 | 1 | T85 | 1 | T99 | 1 | |||
values[3] | 111 | 1 | T81 | 4 | T82 | 8 | T84 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 689739 | 1 | T9 | 50 | T11 | 80 | T6 | 9 | |||
auto[TlIntgErrCmd] | 87 | 1 | T81 | 3 | T82 | 4 | T84 | 5 | |||
auto[TlIntgErrData] | 106 | 1 | T81 | 4 | T82 | 7 | T84 | 6 | |||
auto[TlIntgErrBoth] | 127 | 1 | T81 | 3 | T82 | 9 | T84 | 9 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | |||
auto[0] | 30823 | 0 | T1 | 6 | T2 | 16 | T3 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 30593 | 1 | T1 | 6 | T2 | 16 | T3 | 8 | |||
values[1] | 19 | 1 | T82 | 1 | T122 | 1 | T99 | 1 | |||
values[2] | 10 | 1 | T82 | 1 | T85 | 3 | T123 | 2 | |||
values[3] | 115 | 1 | T81 | 2 | T82 | 7 | T84 | 11 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 30617 | 1 | T1 | 6 | T2 | 16 | T3 | 8 | |||
values[1] | 16 | 1 | T82 | 1 | T84 | 1 | T85 | 2 | |||
values[2] | 5 | 1 | T82 | 2 | T122 | 2 | T124 | 1 | |||
values[3] | 108 | 1 | T81 | 3 | T82 | 9 | T84 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 30503 | 1 | T1 | 6 | T2 | 16 | T3 | 8 | |||
auto[TlIntgErrCmd] | 114 | 1 | T81 | 3 | T82 | 5 | T84 | 7 | |||
auto[TlIntgErrData] | 90 | 1 | T81 | 4 | T82 | 8 | T84 | 4 | |||
auto[TlIntgErrBoth] | 116 | 1 | T81 | 3 | T82 | 7 | T84 | 9 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |