Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
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Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block] 100.00 1 100 1 64 64




Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
partial 202253 1 T9 15 T6 5 T7 65
full_word 487806 1 T9 35 T11 80 T6 4



Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 689739 1 T9 50 T11 80 T6 9
auto[TlIntgErrCmd] 87 1 T81 3 T82 4 T84 5
auto[TlIntgErrData] 106 1 T81 4 T82 7 T84 6
auto[TlIntgErrBoth] 127 1 T81 3 T82 9 T84 9



Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 419904 1 T9 22 T11 80 T6 8
auto[1] 270155 1 T9 28 T6 1 T7 78



Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 166425 1 T9 10 T6 4 T7 6
auto[TlIntgErrNone] partial auto[1] 35535 1 T9 5 T6 1 T7 59
auto[TlIntgErrNone] full_word auto[0] 253331 1 T9 12 T11 80 T6 4
auto[TlIntgErrNone] full_word auto[1] 234448 1 T9 23 T7 19 T10 12
auto[TlIntgErrCmd] partial auto[0] 38 1 T81 2 T82 4 T84 3
auto[TlIntgErrCmd] partial auto[1] 42 1 T81 1 T84 2 T85 1
auto[TlIntgErrCmd] full_word auto[0] 3 1 T125 1 T68 1 T123 1
auto[TlIntgErrCmd] full_word auto[1] 4 1 T122 1 T68 1 T126 2
auto[TlIntgErrData] partial auto[0] 45 1 T81 3 T82 2 T84 4
auto[TlIntgErrData] partial auto[1] 51 1 T82 4 T84 2 T85 5
auto[TlIntgErrData] full_word auto[0] 5 1 T81 1 T127 1 T128 1
auto[TlIntgErrData] full_word auto[1] 5 1 T82 1 T122 1 T99 1
auto[TlIntgErrBoth] partial auto[0] 52 1 T81 1 T82 4 T84 3
auto[TlIntgErrBoth] partial auto[1] 65 1 T81 2 T82 3 T84 6
auto[TlIntgErrBoth] full_word auto[0] 5 1 T122 1 T125 1 T127 1
auto[TlIntgErrBoth] full_word auto[1] 5 1 T82 2 T125 1 T123 1

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