SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.rv_dm_regs_csr_assert | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
85.64 | 100.00 | 55.32 | 85.38 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
TlulOOBAddrErr_A | 29499881 | 9729 | 0 | 0 |
late_debug_enable_rd_A | 29499881 | 1174 | 0 | 0 |
late_debug_enable_regwen_rd_A | 29499881 | 1152 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 29499881 | 9729 | 0 | 0 |
T27 | 303515 | 18 | 0 | 0 |
T28 | 690553 | 100 | 0 | 0 |
T29 | 300456 | 5 | 0 | 0 |
T31 | 8504 | 22 | 0 | 0 |
T74 | 475435 | 309 | 0 | 0 |
T79 | 14621 | 50 | 0 | 0 |
T80 | 3547 | 78 | 0 | 0 |
T81 | 19679 | 1 | 0 | 0 |
T82 | 34767 | 5 | 0 | 0 |
T83 | 45704 | 77 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 29499881 | 1174 | 0 | 0 |
T27 | 303515 | 24 | 0 | 0 |
T29 | 300456 | 10 | 0 | 0 |
T31 | 8504 | 52 | 0 | 0 |
T32 | 44933 | 31 | 0 | 0 |
T71 | 7100 | 20 | 0 | 0 |
T85 | 116976 | 108 | 0 | 0 |
T90 | 55929 | 26 | 0 | 0 |
T94 | 10047 | 6 | 0 | 0 |
T100 | 9470 | 4 | 0 | 0 |
T114 | 21284 | 27 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 29499881 | 1152 | 0 | 0 |
T27 | 303515 | 20 | 0 | 0 |
T29 | 300456 | 19 | 0 | 0 |
T31 | 8504 | 26 | 0 | 0 |
T32 | 44933 | 16 | 0 | 0 |
T71 | 7100 | 54 | 0 | 0 |
T85 | 116976 | 90 | 0 | 0 |
T90 | 55929 | 8 | 0 | 0 |
T94 | 10047 | 5 | 0 | 0 |
T100 | 9470 | 3 | 0 | 0 |
T114 | 21284 | 22 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |