Module Definition
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Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.30 100.00 88.89 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.30 100.00 88.89 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_clock_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.30 100.00 88.89 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.30 100.00 88.89 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_rst_n_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_scan.i_dft_tck_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT10,T17

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT10,T17
11CoveredT10,T17

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT10,T17
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 9562492 9561818 0 0
selKnown1 10356245 10355571 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 9562492 9561818 0 0
T1 310 308 0 0
T2 306 304 0 0
T3 306 304 0 0
T4 314 312 0 0
T5 336 334 0 0
T7 0 36 0 0
T8 0 15 0 0
T9 13 11 0 0
T10 0 25 0 0
T12 0 4 0 0
T15 2 0 0 0
T16 2 0 0 0
T19 306 304 0 0
T20 310 308 0 0
T21 408 406 0 0
T22 326 324 0 0
T23 344 342 0 0
T24 42 40 0 0
T25 0 40 0 0
T26 0 40 0 0
T34 2 0 0 0
T35 2 0 0 0
T38 0 20 0 0
T39 2 0 0 0
T54 2 0 0 0
T55 0 40 0 0
T56 2 0 0 0
T57 2 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 10356245 10355571 0 0
T1 3207 3205 0 0
T2 3070 3068 0 0
T3 1506 1504 0 0
T4 1858 1856 0 0
T5 1963 1961 0 0
T7 0 10 0 0
T8 0 10 0 0
T9 8 6 0 0
T10 0 6 0 0
T12 0 4 0 0
T15 2 0 0 0
T16 2 0 0 0
T19 3101 3099 0 0
T20 1613 1611 0 0
T21 2656 2654 0 0
T22 1719 1717 0 0
T23 2336 2334 0 0
T24 42 40 0 0
T25 0 40 0 0
T26 0 40 0 0
T34 2 0 0 0
T35 2 0 0 0
T38 0 20 0 0
T39 2 0 0 0
T54 2 0 0 0
T55 0 40 0 0
T56 2 0 0 0
T57 2 0 0 0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9888.89
Logical9888.89
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT10,T17

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT10,T17
11CoveredT10,T17

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 416912 416844 0 0
selKnown1 1210778 1210710 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 416912 416844 0 0
T1 155 154 0 0
T2 153 152 0 0
T3 153 152 0 0
T4 157 156 0 0
T5 168 167 0 0
T19 153 152 0 0
T20 155 154 0 0
T21 204 203 0 0
T22 163 162 0 0
T23 172 171 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1210778 1210710 0 0
T1 3052 3051 0 0
T2 2917 2916 0 0
T3 1353 1352 0 0
T4 1701 1700 0 0
T5 1795 1794 0 0
T19 2948 2947 0 0
T20 1458 1457 0 0
T21 2452 2451 0 0
T22 1556 1555 0 0
T23 2164 2163 0 0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9888.89
Logical9888.89
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT10,T17

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT10,T17
11CoveredT10,T17

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 199 131 0 0
selKnown1 183 115 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 199 131 0 0
T7 0 15 0 0
T8 0 5 0 0
T9 4 3 0 0
T10 0 10 0 0
T12 0 2 0 0
T15 1 0 0 0
T16 1 0 0 0
T24 21 20 0 0
T25 0 20 0 0
T26 0 20 0 0
T34 1 0 0 0
T35 1 0 0 0
T38 0 10 0 0
T39 1 0 0 0
T54 1 0 0 0
T55 0 20 0 0
T56 1 0 0 0
T57 1 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 183 115 0 0
T7 0 5 0 0
T8 0 5 0 0
T9 4 3 0 0
T10 0 3 0 0
T12 0 2 0 0
T15 1 0 0 0
T16 1 0 0 0
T24 21 20 0 0
T25 0 20 0 0
T26 0 20 0 0
T34 1 0 0 0
T35 1 0 0 0
T38 0 10 0 0
T39 1 0 0 0
T54 1 0 0 0
T55 0 20 0 0
T56 1 0 0 0
T57 1 0 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT10,T17

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT10,T17
11CoveredT10,T17

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT10,T17
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 9143976 9143707 0 0
selKnown1 9143976 9143707 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 9143976 9143707 0 0
T1 155 154 0 0
T2 153 152 0 0
T3 153 152 0 0
T4 157 156 0 0
T5 168 167 0 0
T19 153 152 0 0
T20 155 154 0 0
T21 204 203 0 0
T22 163 162 0 0
T23 172 171 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 9143976 9143707 0 0
T1 155 154 0 0
T2 153 152 0 0
T3 153 152 0 0
T4 157 156 0 0
T5 168 167 0 0
T19 153 152 0 0
T20 155 154 0 0
T21 204 203 0 0
T22 163 162 0 0
T23 172 171 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT10,T17

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT10,T17
11CoveredT10,T17

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT10,T17
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 1405 1136 0 0
selKnown1 1308 1039 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 1405 1136 0 0
T7 0 21 0 0
T8 0 10 0 0
T9 9 8 0 0
T10 0 15 0 0
T12 0 2 0 0
T15 1 0 0 0
T16 1 0 0 0
T24 21 20 0 0
T25 0 20 0 0
T26 0 20 0 0
T34 1 0 0 0
T35 1 0 0 0
T38 0 10 0 0
T39 1 0 0 0
T54 1 0 0 0
T55 0 20 0 0
T56 1 0 0 0
T57 1 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1308 1039 0 0
T7 0 5 0 0
T8 0 5 0 0
T9 4 3 0 0
T10 0 3 0 0
T12 0 2 0 0
T15 1 0 0 0
T16 1 0 0 0
T24 21 20 0 0
T25 0 20 0 0
T26 0 20 0 0
T34 1 0 0 0
T35 1 0 0 0
T38 0 10 0 0
T39 1 0 0 0
T54 1 0 0 0
T55 0 20 0 0
T56 1 0 0 0
T57 1 0 0 0

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