Unified Coverage Report :: Module :: prim_secded_inv_64_57_dec

Module : prim_secded_inv_64_57_dec

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23			89.23

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_64_57_dec.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.tl_adapter_host_sba.u_rsp_chk.u_chk	53.46			53.46
tb.dut.u_reg_regs.u_chk.u_chk	89.23			89.23
tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk.u_chk	89.23			89.23

---

Module Instance : tb.dut.tl_adapter_host_sba.u_rsp_chk.u_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
53.46			53.46

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
53.46			53.46

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44	100.00	83.33				100.00	u_rsp_chk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_regs.u_chk.u_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23			89.23

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23			89.23

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_chk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk.u_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23			89.23

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23			89.23

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	gen_cmd_intg_check.u_cmd_intg_chk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_secded_inv_64_57_dec

	Total	Covered	Percent
Totals	4	3	75.00
Total Bits	260	232	89.23
Total Bits 0->1	130	116	89.23
Total Bits 1->0	130	116	89.23

Ports	4	3	75.00
Port Bits	260	232	89.23
Port Bits 0->1	130	116	89.23
Port Bits 1->0	130	116	89.23

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[42:0]	Yes	Yes	*T1,*T2,*T19	Yes	T1,T2,T19	INPUT
data_i[56:43]	No	No		No		INPUT
data_i[63:57]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[56:0]	Yes	Yes	T1,T2,T19	Yes	T1,T2,T19	OUTPUT
syndrome_o[6:0]	Yes	Yes	T1,T2,T19	Yes	T1,T2,T19	OUTPUT
err_o[1:0]	Yes	Yes	T1,T2,T19	Yes	T1,T2,T19	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.tl_adapter_host_sba.u_rsp_chk.u_chk

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	260	139	53.46
Total Bits 0->1	130	71	54.62
Total Bits 1->0	130	68	52.31

Ports	4	2	50.00
Port Bits	260	139	53.46
Port Bits 0->1	130	71	54.62
Port Bits 1->0	130	68	52.31

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[3:0]	Yes	Yes	*T52,*T53,T9	Yes	T9,T10,T25	INPUT
data_i[56:4]	No	No		No		INPUT
data_i[63:57]	Yes	Yes	T9,T10,T25	Yes	T20,T9,T35	INPUT
data_o[5:0]	Yes	Yes	*T52,*T53,*T9	Yes	T9,T10,T25	OUTPUT
data_o[6]	No	No		Yes	T59	OUTPUT
data_o[8:7]	Yes	Yes	*T60,*T61	Yes	T60,T62,T61	OUTPUT
data_o[9]	No	No		No		OUTPUT
data_o[13:10]	Yes	Yes	*T63,*T64,*T65	Yes	T63,T64,T65	OUTPUT
data_o[14]	No	No		Yes	T9	OUTPUT
data_o[15]	No	No		No		OUTPUT
data_o[28:16]	Yes	Yes	*T64,*T66,*T60	Yes	T64,T67,T66	OUTPUT
data_o[29]	No	No		No		OUTPUT
data_o[31:30]	Yes	Yes	*T68,*T25,*T60	Yes	T69,T68,T70	OUTPUT
data_o[32]	No	No		No		OUTPUT
data_o[36:33]	Yes	Yes	*T25,*T71,*T70	Yes	T25,T71,T70	OUTPUT
data_o[37]	No	No		No		OUTPUT
data_o[45:38]	Yes	Yes	*T60,*T70,*T64	Yes	T1,T60,T70	OUTPUT
data_o[46]	No	No		Yes	T54,T72,T73	OUTPUT
data_o[47]	Yes	Yes	*T60,*T70	Yes	T60,T70	OUTPUT
data_o[48]	No	No		No		OUTPUT
data_o[56:49]	Yes	Yes	T68,T70,T10	Yes	T74,T68,T20	OUTPUT
syndrome_o[6:0]	Yes	Yes	T9,T10,T25	Yes	T1,T9,T54	OUTPUT
err_o[1:0]	Yes	Yes	T10,T25,T75	Yes	T1,T20,T33	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_reg_regs.u_chk.u_chk

	Total	Covered	Percent
Totals	4	3	75.00
Total Bits	260	232	89.23
Total Bits 0->1	130	116	89.23
Total Bits 1->0	130	116	89.23

Ports	4	3	75.00
Port Bits	260	232	89.23
Port Bits 0->1	130	116	89.23
Port Bits 1->0	130	116	89.23

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[42:0]	Yes	Yes	*T1,*T2,*T19	Yes	T1,T2,T19	INPUT
data_i[56:43]	No	No		No		INPUT
data_i[63:57]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[56:0]	Yes	Yes	T1,T2,T19	Yes	T1,T2,T19	OUTPUT
syndrome_o[6:0]	Yes	Yes	T1,T2,T19	Yes	T1,T2,T19	OUTPUT
err_o[1:0]	Yes	Yes	T1,T2,T19	Yes	T1,T2,T19	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk.u_chk

	Total	Covered	Percent
Totals	4	3	75.00
Total Bits	260	232	89.23
Total Bits 0->1	130	116	89.23
Total Bits 1->0	130	116	89.23

Ports	4	3	75.00
Port Bits	260	232	89.23
Port Bits 0->1	130	116	89.23
Port Bits 1->0	130	116	89.23

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[42:0]	Yes	Yes	*T9,*T6,*T7	Yes	T1,T33,T9	INPUT
data_i[56:43]	No	No		No		INPUT
data_i[63:57]	Yes	Yes	T9,T11,T6	Yes	T20,T33,T9	INPUT
data_o[56:0]	Yes	Yes	T9,T6,T7	Yes	T1,T33,T9	OUTPUT
syndrome_o[6:0]	Yes	Yes	T38,T31,T32	Yes	T1,T20,T22	OUTPUT
err_o[1:0]	Yes	Yes	T1,T4,T22	Yes	T9,T7,T10	OUTPUT

*Tests covering at least one bit in the range