SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
74.88 | 90.63 | 76.24 | 85.89 | 60.26 | 77.17 | 98.52 | 35.48 |
T255 | /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.3133967700 | May 21 12:34:10 PM PDT 24 | May 21 12:34:32 PM PDT 24 | 134480868 ps | ||
T256 | /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1902258480 | May 21 12:34:40 PM PDT 24 | May 21 12:35:04 PM PDT 24 | 795127971 ps | ||
T257 | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3747475440 | May 21 12:34:25 PM PDT 24 | May 21 12:34:44 PM PDT 24 | 579228527 ps | ||
T258 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.4242252551 | May 21 12:33:59 PM PDT 24 | May 21 12:34:24 PM PDT 24 | 99565279 ps | ||
T259 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2850448883 | May 21 12:34:06 PM PDT 24 | May 21 12:35:44 PM PDT 24 | 42034847267 ps | ||
T260 | /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.3519257378 | May 21 12:34:11 PM PDT 24 | May 21 12:34:35 PM PDT 24 | 119331996 ps | ||
T71 | /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2593644682 | May 21 12:34:25 PM PDT 24 | May 21 12:34:47 PM PDT 24 | 3327236092 ps | ||
T40 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.3393905086 | May 21 12:33:59 PM PDT 24 | May 21 12:34:26 PM PDT 24 | 3681383546 ps | ||
T261 | /workspace/coverage/cover_reg_top/22.rv_dm_tap_fsm_rand_reset.4171180138 | May 21 12:34:33 PM PDT 24 | May 21 12:35:16 PM PDT 24 | 30583156892 ps | ||
T262 | /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.854660089 | May 21 12:34:20 PM PDT 24 | May 21 12:34:40 PM PDT 24 | 125541820 ps | ||
T263 | /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.3270976386 | May 21 12:34:22 PM PDT 24 | May 21 12:34:56 PM PDT 24 | 2641846050 ps | ||
T264 | /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.3379509244 | May 21 12:34:26 PM PDT 24 | May 21 12:34:46 PM PDT 24 | 486580316 ps | ||
T265 | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.4245124430 | May 21 12:34:28 PM PDT 24 | May 21 12:34:46 PM PDT 24 | 31164028 ps | ||
T266 | /workspace/coverage/cover_reg_top/39.rv_dm_tap_fsm_rand_reset.1153031189 | May 21 12:34:46 PM PDT 24 | May 21 12:35:15 PM PDT 24 | 24026093526 ps | ||
T74 | /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.412213981 | May 21 12:34:13 PM PDT 24 | May 21 12:34:49 PM PDT 24 | 18162223592 ps | ||
T267 | /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.45439386 | May 21 12:34:19 PM PDT 24 | May 21 12:34:40 PM PDT 24 | 75307224 ps | ||
T268 | /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1080595225 | May 21 12:34:13 PM PDT 24 | May 21 12:34:34 PM PDT 24 | 28893764 ps | ||
T269 | /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1850162125 | May 21 12:34:24 PM PDT 24 | May 21 12:34:45 PM PDT 24 | 217044695 ps | ||
T270 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.408221602 | May 21 12:34:05 PM PDT 24 | May 21 12:34:50 PM PDT 24 | 19545624814 ps | ||
T73 | /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.2404714551 | May 21 12:34:20 PM PDT 24 | May 21 12:34:39 PM PDT 24 | 58208606 ps | ||
T271 | /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.221392116 | May 21 12:34:33 PM PDT 24 | May 21 12:34:57 PM PDT 24 | 3607480215 ps | ||
T272 | /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.2520000882 | May 21 12:34:10 PM PDT 24 | May 21 12:34:32 PM PDT 24 | 46638976 ps | ||
T273 | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.261820992 | May 21 12:34:24 PM PDT 24 | May 21 12:34:44 PM PDT 24 | 591379103 ps | ||
T274 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.1681783482 | May 21 12:34:10 PM PDT 24 | May 21 12:34:32 PM PDT 24 | 214784395 ps |
Test location | /workspace/coverage/default/19.rv_dm_stress_all.271239306 |
Short name | T4 |
Test name | |
Test status | |
Simulation time | 1890915752 ps |
CPU time | 7.58 seconds |
Started | May 21 12:34:58 PM PDT 24 |
Finished | May 21 12:35:26 PM PDT 24 |
Peak memory | 204724 kb |
Host | smart-ea1617c6-c16c-410c-aedf-9bc3ba3bba0e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271239306 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.271239306 |
Directory | /workspace/19.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/27.rv_dm_alert_test.3163651349 |
Short name | T18 |
Test name | |
Test status | |
Simulation time | 25162006 ps |
CPU time | 0.73 seconds |
Started | May 21 12:35:08 PM PDT 24 |
Finished | May 21 12:35:35 PM PDT 24 |
Peak memory | 204676 kb |
Host | smart-be142a8e-c947-45a5-9b99-e9e0c262d918 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163651349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.3163651349 |
Directory | /workspace/27.rv_dm_alert_test/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3041344676 |
Short name | T32 |
Test name | |
Test status | |
Simulation time | 308271941 ps |
CPU time | 4.68 seconds |
Started | May 21 12:34:22 PM PDT 24 |
Finished | May 21 12:34:44 PM PDT 24 |
Peak memory | 213380 kb |
Host | smart-3194a57d-23cd-4618-bb8f-eeff1f605555 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041344676 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.3041344676 |
Directory | /workspace/10.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/default/23.rv_dm_stress_all.245532171 |
Short name | T9 |
Test name | |
Test status | |
Simulation time | 2821401516 ps |
CPU time | 6.07 seconds |
Started | May 21 12:35:13 PM PDT 24 |
Finished | May 21 12:35:46 PM PDT 24 |
Peak memory | 205016 kb |
Host | smart-a1e10622-14cb-4efd-9c9f-4b25ce07c66b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245532171 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.245532171 |
Directory | /workspace/23.rv_dm_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/37.rv_dm_tap_fsm_rand_reset.3781307843 |
Short name | T23 |
Test name | |
Test status | |
Simulation time | 11040434076 ps |
CPU time | 17.89 seconds |
Started | May 21 12:34:38 PM PDT 24 |
Finished | May 21 12:35:11 PM PDT 24 |
Peak memory | 213448 kb |
Host | smart-f85fc2e6-2a33-4904-983f-bf7945f29222 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781307843 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 37.rv_dm_tap_fsm_rand_reset.3781307843 |
Directory | /workspace/37.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.3706987059 |
Short name | T29 |
Test name | |
Test status | |
Simulation time | 3155181911 ps |
CPU time | 8.19 seconds |
Started | May 21 12:34:02 PM PDT 24 |
Finished | May 21 12:34:34 PM PDT 24 |
Peak memory | 221476 kb |
Host | smart-964f3cb4-06d8-4e27-aece-e56dcf2630c8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706987059 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.3706987059 |
Directory | /workspace/2.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.4011541655 |
Short name | T36 |
Test name | |
Test status | |
Simulation time | 2813058783 ps |
CPU time | 5.98 seconds |
Started | May 21 12:34:46 PM PDT 24 |
Finished | May 21 12:35:09 PM PDT 24 |
Peak memory | 205000 kb |
Host | smart-2f846f05-8b9d-4a23-b7c5-b7deff7d63eb |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011541655 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs r_hw_reset.4011541655 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/default/1.rv_dm_sec_cm.1422945789 |
Short name | T21 |
Test name | |
Test status | |
Simulation time | 103214758 ps |
CPU time | 1.03 seconds |
Started | May 21 12:35:01 PM PDT 24 |
Finished | May 21 12:35:26 PM PDT 24 |
Peak memory | 229184 kb |
Host | smart-fc4b904e-e729-4d46-abc1-7a9f94bcf66e |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422945789 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.1422945789 |
Directory | /workspace/1.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/3.rv_dm_stress_all.464370709 |
Short name | T10 |
Test name | |
Test status | |
Simulation time | 2323296892 ps |
CPU time | 8.71 seconds |
Started | May 21 12:35:19 PM PDT 24 |
Finished | May 21 12:35:57 PM PDT 24 |
Peak memory | 204936 kb |
Host | smart-feb3144e-4d19-431e-bfdc-f1fa833bdadc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464370709 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.464370709 |
Directory | /workspace/3.rv_dm_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.1293448274 |
Short name | T61 |
Test name | |
Test status | |
Simulation time | 3113874133 ps |
CPU time | 19.1 seconds |
Started | May 21 12:34:27 PM PDT 24 |
Finished | May 21 12:35:03 PM PDT 24 |
Peak memory | 221640 kb |
Host | smart-9d2cca50-4e71-4729-89f4-d060041ab448 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293448274 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.1 293448274 |
Directory | /workspace/12.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.3824472838 |
Short name | T87 |
Test name | |
Test status | |
Simulation time | 67180531 ps |
CPU time | 1.52 seconds |
Started | May 21 12:34:12 PM PDT 24 |
Finished | May 21 12:34:33 PM PDT 24 |
Peak memory | 213344 kb |
Host | smart-eafda4f0-5b97-4c67-b638-a0949957a86c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824472838 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.3824472838 |
Directory | /workspace/4.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/default/14.rv_dm_alert_test.4126577095 |
Short name | T17 |
Test name | |
Test status | |
Simulation time | 32674371 ps |
CPU time | 0.67 seconds |
Started | May 21 12:35:11 PM PDT 24 |
Finished | May 21 12:35:37 PM PDT 24 |
Peak memory | 204576 kb |
Host | smart-7ab27d51-9f03-4ea0-85f6-ce8de645b35b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126577095 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.4126577095 |
Directory | /workspace/14.rv_dm_alert_test/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.3768507829 |
Short name | T38 |
Test name | |
Test status | |
Simulation time | 682509742 ps |
CPU time | 2.96 seconds |
Started | May 21 12:33:58 PM PDT 24 |
Finished | May 21 12:34:26 PM PDT 24 |
Peak memory | 205048 kb |
Host | smart-e2aa09c8-d338-4a8e-bebb-257a2cedcfb9 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768507829 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs r_hw_reset.3768507829 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2818398184 |
Short name | T66 |
Test name | |
Test status | |
Simulation time | 3174533262 ps |
CPU time | 17.6 seconds |
Started | May 21 12:34:24 PM PDT 24 |
Finished | May 21 12:34:59 PM PDT 24 |
Peak memory | 221440 kb |
Host | smart-f1667b08-26dc-4518-b740-fd4047587c7c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818398184 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.2 818398184 |
Directory | /workspace/13.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.1268407535 |
Short name | T97 |
Test name | |
Test status | |
Simulation time | 148761196 ps |
CPU time | 2.63 seconds |
Started | May 21 12:34:11 PM PDT 24 |
Finished | May 21 12:34:34 PM PDT 24 |
Peak memory | 213212 kb |
Host | smart-c3f900f4-3bae-4726-9cde-31dc7d51b0b6 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268407535 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.1268407535 |
Directory | /workspace/2.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/default/0.rv_dm_rom_read_access.2075825798 |
Short name | T11 |
Test name | |
Test status | |
Simulation time | 94631152 ps |
CPU time | 0.83 seconds |
Started | May 21 12:34:50 PM PDT 24 |
Finished | May 21 12:35:10 PM PDT 24 |
Peak memory | 213168 kb |
Host | smart-201b205a-dd7f-491c-a34d-c238ccace864 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2075825798 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.2075825798 |
Directory | /workspace/0.rv_dm_rom_read_access/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.378846133 |
Short name | T124 |
Test name | |
Test status | |
Simulation time | 399026307 ps |
CPU time | 4.86 seconds |
Started | May 21 12:34:30 PM PDT 24 |
Finished | May 21 12:34:52 PM PDT 24 |
Peak memory | 213444 kb |
Host | smart-a19af5f5-2e10-4e46-a22b-a5fe1f5f1b71 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378846133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.378846133 |
Directory | /workspace/15.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.1071095265 |
Short name | T65 |
Test name | |
Test status | |
Simulation time | 2111048760 ps |
CPU time | 10.17 seconds |
Started | May 21 12:34:32 PM PDT 24 |
Finished | May 21 12:34:59 PM PDT 24 |
Peak memory | 221456 kb |
Host | smart-6b6f0515-a482-4179-9511-dbb748352c92 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071095265 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.1 071095265 |
Directory | /workspace/15.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/10.rv_dm_stress_all.1523705214 |
Short name | T8 |
Test name | |
Test status | |
Simulation time | 8525996302 ps |
CPU time | 13.6 seconds |
Started | May 21 12:35:05 PM PDT 24 |
Finished | May 21 12:35:45 PM PDT 24 |
Peak memory | 204876 kb |
Host | smart-a6634370-5a38-4552-8dbd-43031b804f5d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523705214 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.1523705214 |
Directory | /workspace/10.rv_dm_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.2623216152 |
Short name | T26 |
Test name | |
Test status | |
Simulation time | 31251305793 ps |
CPU time | 12.04 seconds |
Started | May 21 12:34:19 PM PDT 24 |
Finished | May 21 12:34:49 PM PDT 24 |
Peak memory | 216796 kb |
Host | smart-2603ffca-5635-41e0-951e-f1054e12bfcf |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623216152 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.2623216152 |
Directory | /workspace/9.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.2190854227 |
Short name | T13 |
Test name | |
Test status | |
Simulation time | 49431169 ps |
CPU time | 0.8 seconds |
Started | May 21 12:34:52 PM PDT 24 |
Finished | May 21 12:35:13 PM PDT 24 |
Peak memory | 204900 kb |
Host | smart-4d38084b-5eea-4613-9d4e-a80bbc0e3917 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2190854227 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.2190854227 |
Directory | /workspace/0.rv_dm_progbuf_read_write_execute/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.3393905086 |
Short name | T40 |
Test name | |
Test status | |
Simulation time | 3681383546 ps |
CPU time | 2.1 seconds |
Started | May 21 12:33:59 PM PDT 24 |
Finished | May 21 12:34:26 PM PDT 24 |
Peak memory | 205068 kb |
Host | smart-4f09306c-3f85-4db2-9c87-96834bf552f5 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393905086 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs r_hw_reset.3393905086 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.4052597168 |
Short name | T41 |
Test name | |
Test status | |
Simulation time | 48398154423 ps |
CPU time | 154.47 seconds |
Started | May 21 12:34:01 PM PDT 24 |
Finished | May 21 12:36:59 PM PDT 24 |
Peak memory | 205008 kb |
Host | smart-9851461b-6552-48d4-858f-18e8bafb0815 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052597168 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_bit_bash.4052597168 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.412213981 |
Short name | T74 |
Test name | |
Test status | |
Simulation time | 18162223592 ps |
CPU time | 15.23 seconds |
Started | May 21 12:34:13 PM PDT 24 |
Finished | May 21 12:34:49 PM PDT 24 |
Peak memory | 215552 kb |
Host | smart-ac27cf89-670c-4079-ab94-b032737ca596 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412213981 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.412213981 |
Directory | /workspace/6.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/default/20.rv_dm_alert_test.1265058725 |
Short name | T54 |
Test name | |
Test status | |
Simulation time | 65165160 ps |
CPU time | 0.68 seconds |
Started | May 21 12:35:11 PM PDT 24 |
Finished | May 21 12:35:38 PM PDT 24 |
Peak memory | 204600 kb |
Host | smart-bae8d669-dfc0-4c45-b1cc-d3da92543690 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265058725 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.1265058725 |
Directory | /workspace/20.rv_dm_alert_test/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1824485192 |
Short name | T69 |
Test name | |
Test status | |
Simulation time | 918016352 ps |
CPU time | 9.63 seconds |
Started | May 21 12:34:27 PM PDT 24 |
Finished | May 21 12:34:53 PM PDT 24 |
Peak memory | 221448 kb |
Host | smart-2d20ec8b-c3e2-4f44-91a5-7d10dc1c7f7e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824485192 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.1 824485192 |
Directory | /workspace/14.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1036680294 |
Short name | T162 |
Test name | |
Test status | |
Simulation time | 54508472 ps |
CPU time | 0.74 seconds |
Started | May 21 12:34:01 PM PDT 24 |
Finished | May 21 12:34:25 PM PDT 24 |
Peak memory | 204736 kb |
Host | smart-5014204a-b143-4964-8293-2aba0fa61941 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036680294 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.1 036680294 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2405114006 |
Short name | T114 |
Test name | |
Test status | |
Simulation time | 154625367 ps |
CPU time | 6.7 seconds |
Started | May 21 12:33:59 PM PDT 24 |
Finished | May 21 12:34:30 PM PDT 24 |
Peak memory | 205152 kb |
Host | smart-a1e68da0-34f0-4c82-8bd3-38b2c75ef026 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405114006 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_ csr_outstanding.2405114006 |
Directory | /workspace/0.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.3212892761 |
Short name | T82 |
Test name | |
Test status | |
Simulation time | 118549678 ps |
CPU time | 3.7 seconds |
Started | May 21 12:34:26 PM PDT 24 |
Finished | May 21 12:34:47 PM PDT 24 |
Peak memory | 218280 kb |
Host | smart-6d8355d3-a5cd-44c1-a03c-1e623581354b |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212892761 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.3212892761 |
Directory | /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1902258480 |
Short name | T256 |
Test name | |
Test status | |
Simulation time | 795127971 ps |
CPU time | 7.17 seconds |
Started | May 21 12:34:40 PM PDT 24 |
Finished | May 21 12:35:04 PM PDT 24 |
Peak memory | 204980 kb |
Host | smart-f0bd9e10-1400-4d38-b821-2f213099178b |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902258480 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same _csr_outstanding.1902258480 |
Directory | /workspace/18.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.3284073025 |
Short name | T240 |
Test name | |
Test status | |
Simulation time | 2165082148 ps |
CPU time | 7.08 seconds |
Started | May 21 12:34:17 PM PDT 24 |
Finished | May 21 12:34:43 PM PDT 24 |
Peak memory | 219148 kb |
Host | smart-2fcf8375-f072-4a02-b931-e829e99d77b0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284073025 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.3284073025 |
Directory | /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.2220849085 |
Short name | T64 |
Test name | |
Test status | |
Simulation time | 358511994 ps |
CPU time | 6.63 seconds |
Started | May 21 12:34:20 PM PDT 24 |
Finished | May 21 12:34:44 PM PDT 24 |
Peak memory | 213268 kb |
Host | smart-72e581d8-f105-45bb-b355-e3a439edc47f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220849085 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.2220849085 |
Directory | /workspace/7.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/default/0.rv_dm_alert_test.1986595461 |
Short name | T132 |
Test name | |
Test status | |
Simulation time | 101208136 ps |
CPU time | 0.71 seconds |
Started | May 21 12:34:43 PM PDT 24 |
Finished | May 21 12:35:01 PM PDT 24 |
Peak memory | 204636 kb |
Host | smart-391da826-a3b7-45a3-ac1b-1b41521f89eb |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986595461 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.1986595461 |
Directory | /workspace/0.rv_dm_alert_test/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1900995315 |
Short name | T94 |
Test name | |
Test status | |
Simulation time | 23712012462 ps |
CPU time | 74.75 seconds |
Started | May 21 12:33:51 PM PDT 24 |
Finished | May 21 12:35:33 PM PDT 24 |
Peak memory | 213328 kb |
Host | smart-e1f8f6e8-7c46-41e5-8ac1-7517f7f79d04 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900995315 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 0.rv_dm_csr_aliasing.1900995315 |
Directory | /workspace/0.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.2306222459 |
Short name | T88 |
Test name | |
Test status | |
Simulation time | 727297085 ps |
CPU time | 26.77 seconds |
Started | May 21 12:33:57 PM PDT 24 |
Finished | May 21 12:34:49 PM PDT 24 |
Peak memory | 205008 kb |
Host | smart-b302711b-a70e-433b-90aa-342c1bac42b0 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306222459 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.2306222459 |
Directory | /workspace/0.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3586374303 |
Short name | T215 |
Test name | |
Test status | |
Simulation time | 97994176 ps |
CPU time | 1.72 seconds |
Started | May 21 12:34:04 PM PDT 24 |
Finished | May 21 12:34:29 PM PDT 24 |
Peak memory | 213552 kb |
Host | smart-4d583983-8859-4a70-8d68-3deca517a1e4 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586374303 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.3586374303 |
Directory | /workspace/0.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1985273991 |
Short name | T213 |
Test name | |
Test status | |
Simulation time | 3488153222 ps |
CPU time | 5.04 seconds |
Started | May 21 12:33:58 PM PDT 24 |
Finished | May 21 12:34:28 PM PDT 24 |
Peak memory | 219908 kb |
Host | smart-e8731cad-e5d7-4223-8019-ecd17d155cd6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985273991 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.1985273991 |
Directory | /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2232642487 |
Short name | T91 |
Test name | |
Test status | |
Simulation time | 209118654 ps |
CPU time | 1.58 seconds |
Started | May 21 12:34:01 PM PDT 24 |
Finished | May 21 12:34:26 PM PDT 24 |
Peak memory | 213288 kb |
Host | smart-696eab60-866f-49d9-9a9c-8886545e6a9e |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232642487 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.2232642487 |
Directory | /workspace/0.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.55333929 |
Short name | T51 |
Test name | |
Test status | |
Simulation time | 3523113101 ps |
CPU time | 8.01 seconds |
Started | May 21 12:33:50 PM PDT 24 |
Finished | May 21 12:34:25 PM PDT 24 |
Peak memory | 205056 kb |
Host | smart-51cf06fa-9454-43a6-871e-1b6bc25383bf |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55333929 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_ aliasing.55333929 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.90667189 |
Short name | T174 |
Test name | |
Test status | |
Simulation time | 48685524256 ps |
CPU time | 92.66 seconds |
Started | May 21 12:33:49 PM PDT 24 |
Finished | May 21 12:35:50 PM PDT 24 |
Peak memory | 205016 kb |
Host | smart-4c25181f-9ddb-49de-b1f4-3a28eeb022e2 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90667189 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UV M_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null - cm_name 0.rv_dm_jtag_dmi_csr_bit_bash.90667189 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2307921192 |
Short name | T173 |
Test name | |
Test status | |
Simulation time | 459495767 ps |
CPU time | 2.17 seconds |
Started | May 21 12:33:51 PM PDT 24 |
Finished | May 21 12:34:21 PM PDT 24 |
Peak memory | 204872 kb |
Host | smart-cf48b342-bccd-4717-9781-c12412f15f5c |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307921192 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.2 307921192 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3587357884 |
Short name | T178 |
Test name | |
Test status | |
Simulation time | 72644984 ps |
CPU time | 0.91 seconds |
Started | May 21 12:33:48 PM PDT 24 |
Finished | May 21 12:34:17 PM PDT 24 |
Peak memory | 204704 kb |
Host | smart-b74e4934-8e6e-4030-ba82-14a92e81aa07 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587357884 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_aliasing.3587357884 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.370454488 |
Short name | T171 |
Test name | |
Test status | |
Simulation time | 809168003 ps |
CPU time | 2.33 seconds |
Started | May 21 12:33:51 PM PDT 24 |
Finished | May 21 12:34:20 PM PDT 24 |
Peak memory | 204920 kb |
Host | smart-27cd59ac-556b-4d29-bfcc-279453fd5a4d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370454488 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr _bit_bash.370454488 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2617236205 |
Short name | T201 |
Test name | |
Test status | |
Simulation time | 29775233 ps |
CPU time | 0.72 seconds |
Started | May 21 12:33:50 PM PDT 24 |
Finished | May 21 12:34:18 PM PDT 24 |
Peak memory | 204872 kb |
Host | smart-319f7f76-bf1d-4368-8ef7-78d14ad72aa0 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617236205 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_hw_reset.2617236205 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.2713851289 |
Short name | T175 |
Test name | |
Test status | |
Simulation time | 47476463 ps |
CPU time | 0.72 seconds |
Started | May 21 12:34:03 PM PDT 24 |
Finished | May 21 12:34:27 PM PDT 24 |
Peak memory | 204720 kb |
Host | smart-6613ad96-4477-4f24-8389-ce8c0919f2c6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713851289 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par tial_access.2713851289 |
Directory | /workspace/0.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.345092774 |
Short name | T211 |
Test name | |
Test status | |
Simulation time | 48604778 ps |
CPU time | 0.67 seconds |
Started | May 21 12:34:02 PM PDT 24 |
Finished | May 21 12:34:26 PM PDT 24 |
Peak memory | 204768 kb |
Host | smart-3a6c07c2-9f65-416f-8cbb-37115650ca16 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345092774 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.345092774 |
Directory | /workspace/0.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.751029801 |
Short name | T185 |
Test name | |
Test status | |
Simulation time | 10595932900 ps |
CPU time | 20.68 seconds |
Started | May 21 12:33:59 PM PDT 24 |
Finished | May 21 12:34:44 PM PDT 24 |
Peak memory | 219636 kb |
Host | smart-a0240cd0-936b-4430-b240-e39d2ae85d39 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751029801 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.751029801 |
Directory | /workspace/0.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.3712896874 |
Short name | T31 |
Test name | |
Test status | |
Simulation time | 310219135 ps |
CPU time | 4.26 seconds |
Started | May 21 12:33:51 PM PDT 24 |
Finished | May 21 12:34:22 PM PDT 24 |
Peak memory | 213312 kb |
Host | smart-22b0a2b3-982d-4ed9-a2ab-eb4caf16645c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712896874 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.3712896874 |
Directory | /workspace/0.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.1286589106 |
Short name | T131 |
Test name | |
Test status | |
Simulation time | 2374187041 ps |
CPU time | 9.59 seconds |
Started | May 21 12:33:57 PM PDT 24 |
Finished | May 21 12:34:32 PM PDT 24 |
Peak memory | 213256 kb |
Host | smart-661daa6a-5a52-401d-a479-edf871bad644 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286589106 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.1286589106 |
Directory | /workspace/0.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.2184288832 |
Short name | T102 |
Test name | |
Test status | |
Simulation time | 12206899090 ps |
CPU time | 75.85 seconds |
Started | May 21 12:33:57 PM PDT 24 |
Finished | May 21 12:35:39 PM PDT 24 |
Peak memory | 205132 kb |
Host | smart-b18978e0-d68c-415c-bf14-14264708baa9 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184288832 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 1.rv_dm_csr_aliasing.2184288832 |
Directory | /workspace/1.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.3565081018 |
Short name | T251 |
Test name | |
Test status | |
Simulation time | 6505203918 ps |
CPU time | 33.17 seconds |
Started | May 21 12:34:01 PM PDT 24 |
Finished | May 21 12:34:58 PM PDT 24 |
Peak memory | 205080 kb |
Host | smart-54b0d6b4-cbaa-4978-b56c-c4ede39e32e0 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565081018 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.3565081018 |
Directory | /workspace/1.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2554055320 |
Short name | T195 |
Test name | |
Test status | |
Simulation time | 121052792 ps |
CPU time | 1.64 seconds |
Started | May 21 12:34:00 PM PDT 24 |
Finished | May 21 12:34:25 PM PDT 24 |
Peak memory | 213228 kb |
Host | smart-234f283f-e4f3-473d-8337-f10805c56ffc |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554055320 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.2554055320 |
Directory | /workspace/1.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.1127720420 |
Short name | T62 |
Test name | |
Test status | |
Simulation time | 157569190 ps |
CPU time | 3.91 seconds |
Started | May 21 12:34:03 PM PDT 24 |
Finished | May 21 12:34:30 PM PDT 24 |
Peak memory | 221500 kb |
Host | smart-8076183f-3008-4fb4-b0a0-292965e1aec5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127720420 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.1127720420 |
Directory | /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2542371083 |
Short name | T93 |
Test name | |
Test status | |
Simulation time | 218309166 ps |
CPU time | 2.18 seconds |
Started | May 21 12:34:04 PM PDT 24 |
Finished | May 21 12:34:29 PM PDT 24 |
Peak memory | 219028 kb |
Host | smart-a4c1d10e-41cf-4972-a682-0a887a7e98c4 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542371083 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.2542371083 |
Directory | /workspace/1.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1742873337 |
Short name | T163 |
Test name | |
Test status | |
Simulation time | 8588595968 ps |
CPU time | 18.14 seconds |
Started | May 21 12:34:01 PM PDT 24 |
Finished | May 21 12:34:42 PM PDT 24 |
Peak memory | 205124 kb |
Host | smart-9c21d78b-1380-4102-82a5-45b1b7975f27 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742873337 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs r_aliasing.1742873337 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1754758891 |
Short name | T42 |
Test name | |
Test status | |
Simulation time | 1994020812 ps |
CPU time | 2.82 seconds |
Started | May 21 12:33:58 PM PDT 24 |
Finished | May 21 12:34:26 PM PDT 24 |
Peak memory | 205028 kb |
Host | smart-1c18f345-2f98-433a-ae28-dd92ae992f20 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754758891 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.1 754758891 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.327367883 |
Short name | T159 |
Test name | |
Test status | |
Simulation time | 143308496 ps |
CPU time | 1.18 seconds |
Started | May 21 12:34:03 PM PDT 24 |
Finished | May 21 12:34:27 PM PDT 24 |
Peak memory | 204732 kb |
Host | smart-aaeb1307-4bf2-4afc-a667-bab11ee45ee1 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327367883 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr _aliasing.327367883 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.32361977 |
Short name | T172 |
Test name | |
Test status | |
Simulation time | 2052113654 ps |
CPU time | 2.45 seconds |
Started | May 21 12:34:06 PM PDT 24 |
Finished | May 21 12:34:30 PM PDT 24 |
Peak memory | 204988 kb |
Host | smart-63693f58-0670-4a92-b158-ab3686fa6fc6 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32361977 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_ bit_bash.32361977 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.4242252551 |
Short name | T258 |
Test name | |
Test status | |
Simulation time | 99565279 ps |
CPU time | 0.72 seconds |
Started | May 21 12:33:59 PM PDT 24 |
Finished | May 21 12:34:24 PM PDT 24 |
Peak memory | 204824 kb |
Host | smart-d2b60b20-05c9-45e6-b6f1-8337610f3ac2 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242252551 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_hw_reset.4242252551 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.1892342615 |
Short name | T203 |
Test name | |
Test status | |
Simulation time | 28633910 ps |
CPU time | 0.72 seconds |
Started | May 21 12:33:57 PM PDT 24 |
Finished | May 21 12:34:22 PM PDT 24 |
Peak memory | 204808 kb |
Host | smart-e068e9b3-3169-4c52-9998-0e00012ae4e2 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892342615 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.1 892342615 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3303660080 |
Short name | T180 |
Test name | |
Test status | |
Simulation time | 32120835 ps |
CPU time | 0.68 seconds |
Started | May 21 12:33:59 PM PDT 24 |
Finished | May 21 12:34:24 PM PDT 24 |
Peak memory | 204700 kb |
Host | smart-01e7b553-dd50-4148-a447-bff609563c3d |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303660080 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par tial_access.3303660080 |
Directory | /workspace/1.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.3206013704 |
Short name | T155 |
Test name | |
Test status | |
Simulation time | 54258627 ps |
CPU time | 0.68 seconds |
Started | May 21 12:34:03 PM PDT 24 |
Finished | May 21 12:34:27 PM PDT 24 |
Peak memory | 204732 kb |
Host | smart-5e3a2bce-820a-414f-a996-037a274273e7 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206013704 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.3206013704 |
Directory | /workspace/1.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3109658802 |
Short name | T89 |
Test name | |
Test status | |
Simulation time | 566287795 ps |
CPU time | 6.55 seconds |
Started | May 21 12:33:56 PM PDT 24 |
Finished | May 21 12:34:28 PM PDT 24 |
Peak memory | 205136 kb |
Host | smart-efad7ac3-8150-43c0-afde-c7a1dc035cd4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109658802 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_ csr_outstanding.3109658802 |
Directory | /workspace/1.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.4278674287 |
Short name | T252 |
Test name | |
Test status | |
Simulation time | 21568487139 ps |
CPU time | 10.04 seconds |
Started | May 21 12:34:01 PM PDT 24 |
Finished | May 21 12:34:34 PM PDT 24 |
Peak memory | 218792 kb |
Host | smart-a98ce32d-e590-46a8-80a3-fd015b243092 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278674287 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.4278674287 |
Directory | /workspace/1.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.237008426 |
Short name | T254 |
Test name | |
Test status | |
Simulation time | 262175393 ps |
CPU time | 3.11 seconds |
Started | May 21 12:34:01 PM PDT 24 |
Finished | May 21 12:34:28 PM PDT 24 |
Peak memory | 213348 kb |
Host | smart-c37bb26e-9f4f-43dd-9491-a3afefc2ef1b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237008426 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.237008426 |
Directory | /workspace/1.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.174007706 |
Short name | T119 |
Test name | |
Test status | |
Simulation time | 1178811487 ps |
CPU time | 18.88 seconds |
Started | May 21 12:33:59 PM PDT 24 |
Finished | May 21 12:34:42 PM PDT 24 |
Peak memory | 213252 kb |
Host | smart-43f4cd10-4b74-43b5-b8bb-3d12c4d230de |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174007706 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.174007706 |
Directory | /workspace/1.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.1238420586 |
Short name | T186 |
Test name | |
Test status | |
Simulation time | 3325845475 ps |
CPU time | 4.88 seconds |
Started | May 21 12:34:25 PM PDT 24 |
Finished | May 21 12:34:47 PM PDT 24 |
Peak memory | 213392 kb |
Host | smart-81d184e0-1d0e-4e9b-b5b4-cbc88552cc13 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238420586 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.1238420586 |
Directory | /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.2404714551 |
Short name | T73 |
Test name | |
Test status | |
Simulation time | 58208606 ps |
CPU time | 1.4 seconds |
Started | May 21 12:34:20 PM PDT 24 |
Finished | May 21 12:34:39 PM PDT 24 |
Peak memory | 213316 kb |
Host | smart-bab88211-87d3-4d85-b843-7362718c6e11 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404714551 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.2404714551 |
Directory | /workspace/10.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3747475440 |
Short name | T257 |
Test name | |
Test status | |
Simulation time | 579228527 ps |
CPU time | 2.03 seconds |
Started | May 21 12:34:25 PM PDT 24 |
Finished | May 21 12:34:44 PM PDT 24 |
Peak memory | 205132 kb |
Host | smart-5126f416-3e75-4e42-8ad1-30106aa801f8 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747475440 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw. 3747475440 |
Directory | /workspace/10.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.160841833 |
Short name | T164 |
Test name | |
Test status | |
Simulation time | 82178310 ps |
CPU time | 0.89 seconds |
Started | May 21 12:34:20 PM PDT 24 |
Finished | May 21 12:34:39 PM PDT 24 |
Peak memory | 204780 kb |
Host | smart-7e6bb884-c130-457d-94d4-d6b76bedc2e2 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160841833 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.160841833 |
Directory | /workspace/10.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.1015672229 |
Short name | T100 |
Test name | |
Test status | |
Simulation time | 161236560 ps |
CPU time | 3.53 seconds |
Started | May 21 12:34:20 PM PDT 24 |
Finished | May 21 12:34:41 PM PDT 24 |
Peak memory | 205068 kb |
Host | smart-9fbb9d78-cfce-4698-b87e-b89fa7d113cb |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015672229 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same _csr_outstanding.1015672229 |
Directory | /workspace/10.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1955985618 |
Short name | T128 |
Test name | |
Test status | |
Simulation time | 209748014 ps |
CPU time | 7.59 seconds |
Started | May 21 12:34:19 PM PDT 24 |
Finished | May 21 12:34:45 PM PDT 24 |
Peak memory | 213228 kb |
Host | smart-58c4cdd4-88a7-498a-b2d2-eb7c6401804d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955985618 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.1 955985618 |
Directory | /workspace/10.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1885828317 |
Short name | T234 |
Test name | |
Test status | |
Simulation time | 334806776 ps |
CPU time | 2.3 seconds |
Started | May 21 12:34:24 PM PDT 24 |
Finished | May 21 12:34:44 PM PDT 24 |
Peak memory | 217100 kb |
Host | smart-4714c5ff-bfa3-407d-b3b8-2da963ddc300 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885828317 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.1885828317 |
Directory | /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.3263323348 |
Short name | T96 |
Test name | |
Test status | |
Simulation time | 98152740 ps |
CPU time | 2.41 seconds |
Started | May 21 12:34:27 PM PDT 24 |
Finished | May 21 12:34:46 PM PDT 24 |
Peak memory | 213296 kb |
Host | smart-6bb00487-23f9-4e72-8d2e-4e7e6c8e8f5a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263323348 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.3263323348 |
Directory | /workspace/11.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3722005435 |
Short name | T181 |
Test name | |
Test status | |
Simulation time | 658280905 ps |
CPU time | 1.49 seconds |
Started | May 21 12:34:17 PM PDT 24 |
Finished | May 21 12:34:37 PM PDT 24 |
Peak memory | 204996 kb |
Host | smart-1e799f6b-3a22-45b7-824e-8bb9e5716c0e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722005435 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw. 3722005435 |
Directory | /workspace/11.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3490443788 |
Short name | T177 |
Test name | |
Test status | |
Simulation time | 65308844 ps |
CPU time | 0.75 seconds |
Started | May 21 12:34:23 PM PDT 24 |
Finished | May 21 12:34:41 PM PDT 24 |
Peak memory | 204796 kb |
Host | smart-50d3069f-eb5d-4ec0-bb08-0be5bf5bcb44 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490443788 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw. 3490443788 |
Directory | /workspace/11.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.3520581992 |
Short name | T115 |
Test name | |
Test status | |
Simulation time | 1128578182 ps |
CPU time | 7.78 seconds |
Started | May 21 12:34:28 PM PDT 24 |
Finished | May 21 12:34:52 PM PDT 24 |
Peak memory | 205064 kb |
Host | smart-2ce6d6e3-04ee-484c-8bae-de47dcb1ad06 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520581992 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same _csr_outstanding.3520581992 |
Directory | /workspace/11.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.3434765034 |
Short name | T83 |
Test name | |
Test status | |
Simulation time | 76687847 ps |
CPU time | 4.72 seconds |
Started | May 21 12:34:27 PM PDT 24 |
Finished | May 21 12:34:48 PM PDT 24 |
Peak memory | 213344 kb |
Host | smart-b083bb4b-08b0-4b58-b79a-0ea03428bbb1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434765034 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.3434765034 |
Directory | /workspace/11.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.1730639618 |
Short name | T125 |
Test name | |
Test status | |
Simulation time | 3573734387 ps |
CPU time | 19.94 seconds |
Started | May 21 12:34:24 PM PDT 24 |
Finished | May 21 12:35:01 PM PDT 24 |
Peak memory | 221424 kb |
Host | smart-c9f3a7d3-da73-400f-9019-7bdae07d1803 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730639618 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.1 730639618 |
Directory | /workspace/11.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.4011553778 |
Short name | T108 |
Test name | |
Test status | |
Simulation time | 152702467 ps |
CPU time | 1.58 seconds |
Started | May 21 12:34:24 PM PDT 24 |
Finished | May 21 12:34:43 PM PDT 24 |
Peak memory | 213328 kb |
Host | smart-8eebf5df-226a-46c3-9c4d-a62669627807 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011553778 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.4011553778 |
Directory | /workspace/12.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.796386808 |
Short name | T165 |
Test name | |
Test status | |
Simulation time | 1218727131 ps |
CPU time | 1.64 seconds |
Started | May 21 12:34:28 PM PDT 24 |
Finished | May 21 12:34:46 PM PDT 24 |
Peak memory | 204984 kb |
Host | smart-fe82bd96-9bb5-40e5-9c6f-e012e9df04d3 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796386808 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.796386808 |
Directory | /workspace/12.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1736814934 |
Short name | T176 |
Test name | |
Test status | |
Simulation time | 61223044 ps |
CPU time | 0.71 seconds |
Started | May 21 12:34:26 PM PDT 24 |
Finished | May 21 12:34:44 PM PDT 24 |
Peak memory | 204728 kb |
Host | smart-096d0754-6123-4b13-abee-c412b4042534 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736814934 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw. 1736814934 |
Directory | /workspace/12.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.762738197 |
Short name | T33 |
Test name | |
Test status | |
Simulation time | 1855520926 ps |
CPU time | 6.18 seconds |
Started | May 21 12:34:25 PM PDT 24 |
Finished | May 21 12:34:49 PM PDT 24 |
Peak memory | 205048 kb |
Host | smart-9c3fad36-b937-46d3-92a2-cf43dd1a69cf |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762738197 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same_ csr_outstanding.762738197 |
Directory | /workspace/12.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_tap_fsm_rand_reset.2394138340 |
Short name | T212 |
Test name | |
Test status | |
Simulation time | 17516692300 ps |
CPU time | 15.93 seconds |
Started | May 21 12:34:28 PM PDT 24 |
Finished | May 21 12:35:01 PM PDT 24 |
Peak memory | 214068 kb |
Host | smart-d904d7ac-033c-45d4-8df9-74cabc5734ee |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394138340 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 12.rv_dm_tap_fsm_rand_reset.2394138340 |
Directory | /workspace/12.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.3379509244 |
Short name | T264 |
Test name | |
Test status | |
Simulation time | 486580316 ps |
CPU time | 3.02 seconds |
Started | May 21 12:34:26 PM PDT 24 |
Finished | May 21 12:34:46 PM PDT 24 |
Peak memory | 221592 kb |
Host | smart-5084ce72-f5c3-4030-ad59-3d692edcac40 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379509244 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.3379509244 |
Directory | /workspace/12.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.1048143891 |
Short name | T28 |
Test name | |
Test status | |
Simulation time | 139910493 ps |
CPU time | 2.2 seconds |
Started | May 21 12:34:28 PM PDT 24 |
Finished | May 21 12:34:47 PM PDT 24 |
Peak memory | 216932 kb |
Host | smart-0c812720-edf5-404e-9f71-c96072d185ef |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048143891 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.1048143891 |
Directory | /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.930743789 |
Short name | T246 |
Test name | |
Test status | |
Simulation time | 146115403 ps |
CPU time | 2.26 seconds |
Started | May 21 12:34:28 PM PDT 24 |
Finished | May 21 12:34:47 PM PDT 24 |
Peak memory | 213484 kb |
Host | smart-573183f3-f62d-4639-bd42-377e2c253244 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930743789 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.930743789 |
Directory | /workspace/13.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.261820992 |
Short name | T273 |
Test name | |
Test status | |
Simulation time | 591379103 ps |
CPU time | 2.63 seconds |
Started | May 21 12:34:24 PM PDT 24 |
Finished | May 21 12:34:44 PM PDT 24 |
Peak memory | 204896 kb |
Host | smart-32c4f9b2-47e5-49f9-a1ec-a27d2a93f4b7 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261820992 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.261820992 |
Directory | /workspace/13.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.584078554 |
Short name | T157 |
Test name | |
Test status | |
Simulation time | 57876810 ps |
CPU time | 0.69 seconds |
Started | May 21 12:34:23 PM PDT 24 |
Finished | May 21 12:34:41 PM PDT 24 |
Peak memory | 204696 kb |
Host | smart-dcfdd223-9828-4903-baaa-1ce3c047c6ac |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584078554 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.584078554 |
Directory | /workspace/13.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2716764444 |
Short name | T239 |
Test name | |
Test status | |
Simulation time | 143740254 ps |
CPU time | 6.41 seconds |
Started | May 21 12:34:23 PM PDT 24 |
Finished | May 21 12:34:47 PM PDT 24 |
Peak memory | 205124 kb |
Host | smart-01695f73-9217-465e-979f-bcfa922d9831 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716764444 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same _csr_outstanding.2716764444 |
Directory | /workspace/13.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_tap_fsm_rand_reset.3001482290 |
Short name | T63 |
Test name | |
Test status | |
Simulation time | 8113635495 ps |
CPU time | 27.97 seconds |
Started | May 21 12:34:26 PM PDT 24 |
Finished | May 21 12:35:11 PM PDT 24 |
Peak memory | 219248 kb |
Host | smart-6163e172-4f4f-4cba-a3ff-e47f412d0858 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001482290 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 13.rv_dm_tap_fsm_rand_reset.3001482290 |
Directory | /workspace/13.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.859006572 |
Short name | T226 |
Test name | |
Test status | |
Simulation time | 3959303741 ps |
CPU time | 10.3 seconds |
Started | May 21 12:34:24 PM PDT 24 |
Finished | May 21 12:34:52 PM PDT 24 |
Peak memory | 221484 kb |
Host | smart-1fcafd1f-d45e-4519-bc91-bdaef237287f |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859006572 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.859006572 |
Directory | /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.2905124459 |
Short name | T120 |
Test name | |
Test status | |
Simulation time | 326243879 ps |
CPU time | 2.43 seconds |
Started | May 21 12:34:26 PM PDT 24 |
Finished | May 21 12:34:45 PM PDT 24 |
Peak memory | 213296 kb |
Host | smart-80dbf3f3-7c68-4339-9eda-8e43897db0d8 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905124459 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.2905124459 |
Directory | /workspace/14.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.3213104997 |
Short name | T235 |
Test name | |
Test status | |
Simulation time | 2574545328 ps |
CPU time | 3.12 seconds |
Started | May 21 12:34:25 PM PDT 24 |
Finished | May 21 12:34:45 PM PDT 24 |
Peak memory | 205048 kb |
Host | smart-a29314cc-62e4-4a0c-9440-f298eefa21f5 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213104997 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw. 3213104997 |
Directory | /workspace/14.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.4245124430 |
Short name | T265 |
Test name | |
Test status | |
Simulation time | 31164028 ps |
CPU time | 0.7 seconds |
Started | May 21 12:34:28 PM PDT 24 |
Finished | May 21 12:34:46 PM PDT 24 |
Peak memory | 204792 kb |
Host | smart-c4849efb-9146-4ec9-8915-ab168817da1a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245124430 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw. 4245124430 |
Directory | /workspace/14.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1850162125 |
Short name | T269 |
Test name | |
Test status | |
Simulation time | 217044695 ps |
CPU time | 4.19 seconds |
Started | May 21 12:34:24 PM PDT 24 |
Finished | May 21 12:34:45 PM PDT 24 |
Peak memory | 205008 kb |
Host | smart-e75c50ce-6940-4541-8b73-8f74e77dc1ce |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850162125 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same _csr_outstanding.1850162125 |
Directory | /workspace/14.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_tap_fsm_rand_reset.3518826968 |
Short name | T247 |
Test name | |
Test status | |
Simulation time | 19063697027 ps |
CPU time | 35.37 seconds |
Started | May 21 12:34:27 PM PDT 24 |
Finished | May 21 12:35:19 PM PDT 24 |
Peak memory | 230936 kb |
Host | smart-0f511ff7-dc7f-4d75-b2a8-adf98371af59 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518826968 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 14.rv_dm_tap_fsm_rand_reset.3518826968 |
Directory | /workspace/14.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.3622799980 |
Short name | T143 |
Test name | |
Test status | |
Simulation time | 159625518 ps |
CPU time | 2.66 seconds |
Started | May 21 12:34:25 PM PDT 24 |
Finished | May 21 12:34:45 PM PDT 24 |
Peak memory | 213316 kb |
Host | smart-dfd64a54-7025-4864-9cf8-6d844e091f68 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622799980 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.3622799980 |
Directory | /workspace/14.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.2024471787 |
Short name | T76 |
Test name | |
Test status | |
Simulation time | 4173605647 ps |
CPU time | 5.3 seconds |
Started | May 21 12:34:30 PM PDT 24 |
Finished | May 21 12:34:52 PM PDT 24 |
Peak memory | 221580 kb |
Host | smart-eda87dba-5686-46f4-8c4d-3edbc98e8398 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024471787 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.2024471787 |
Directory | /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2128495920 |
Short name | T106 |
Test name | |
Test status | |
Simulation time | 224806335 ps |
CPU time | 1.61 seconds |
Started | May 21 12:34:39 PM PDT 24 |
Finished | May 21 12:34:56 PM PDT 24 |
Peak memory | 213216 kb |
Host | smart-12dd15c1-c6ab-4783-8b60-b1aa2f0f7ecf |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128495920 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.2128495920 |
Directory | /workspace/15.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.2443679124 |
Short name | T248 |
Test name | |
Test status | |
Simulation time | 685169819 ps |
CPU time | 1.68 seconds |
Started | May 21 12:34:29 PM PDT 24 |
Finished | May 21 12:34:48 PM PDT 24 |
Peak memory | 205020 kb |
Host | smart-215d49bb-dece-419a-b52a-30b00efa8947 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443679124 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw. 2443679124 |
Directory | /workspace/15.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.835619768 |
Short name | T200 |
Test name | |
Test status | |
Simulation time | 55005189 ps |
CPU time | 0.73 seconds |
Started | May 21 12:34:26 PM PDT 24 |
Finished | May 21 12:34:44 PM PDT 24 |
Peak memory | 204716 kb |
Host | smart-2f124edf-ddba-4c8f-b1a8-a91ef9cdd458 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835619768 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.835619768 |
Directory | /workspace/15.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.496233456 |
Short name | T243 |
Test name | |
Test status | |
Simulation time | 1661931534 ps |
CPU time | 7.89 seconds |
Started | May 21 12:34:30 PM PDT 24 |
Finished | May 21 12:34:54 PM PDT 24 |
Peak memory | 205120 kb |
Host | smart-76ab5c83-e1e8-40ef-a69d-35459d9ce9cd |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496233456 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same_ csr_outstanding.496233456 |
Directory | /workspace/15.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_tap_fsm_rand_reset.2423227435 |
Short name | T241 |
Test name | |
Test status | |
Simulation time | 17037410110 ps |
CPU time | 34.17 seconds |
Started | May 21 12:34:32 PM PDT 24 |
Finished | May 21 12:35:23 PM PDT 24 |
Peak memory | 221444 kb |
Host | smart-0b55fe7e-a1e3-428c-9e9c-752615c14239 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423227435 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 15.rv_dm_tap_fsm_rand_reset.2423227435 |
Directory | /workspace/15.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.221392116 |
Short name | T271 |
Test name | |
Test status | |
Simulation time | 3607480215 ps |
CPU time | 7.73 seconds |
Started | May 21 12:34:33 PM PDT 24 |
Finished | May 21 12:34:57 PM PDT 24 |
Peak memory | 221484 kb |
Host | smart-1709a091-f290-4538-b314-da3ba5562650 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221392116 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.221392116 |
Directory | /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.2376834705 |
Short name | T34 |
Test name | |
Test status | |
Simulation time | 143229868 ps |
CPU time | 1.52 seconds |
Started | May 21 12:34:30 PM PDT 24 |
Finished | May 21 12:34:48 PM PDT 24 |
Peak memory | 218436 kb |
Host | smart-e81455ec-1c6b-494f-810f-8642d885b717 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376834705 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.2376834705 |
Directory | /workspace/16.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2560625429 |
Short name | T43 |
Test name | |
Test status | |
Simulation time | 1148640323 ps |
CPU time | 3.45 seconds |
Started | May 21 12:34:30 PM PDT 24 |
Finished | May 21 12:34:55 PM PDT 24 |
Peak memory | 204980 kb |
Host | smart-464e9af3-af50-435b-966d-9a73f09f1845 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560625429 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw. 2560625429 |
Directory | /workspace/16.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2805548074 |
Short name | T206 |
Test name | |
Test status | |
Simulation time | 90672388 ps |
CPU time | 0.67 seconds |
Started | May 21 12:34:37 PM PDT 24 |
Finished | May 21 12:34:53 PM PDT 24 |
Peak memory | 204724 kb |
Host | smart-aa244a65-2162-4281-9116-f04afde2d1ca |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805548074 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw. 2805548074 |
Directory | /workspace/16.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.2114602254 |
Short name | T112 |
Test name | |
Test status | |
Simulation time | 137425015 ps |
CPU time | 6.18 seconds |
Started | May 21 12:34:40 PM PDT 24 |
Finished | May 21 12:35:02 PM PDT 24 |
Peak memory | 204984 kb |
Host | smart-9b9b6979-48bb-4a10-8363-83bff669fbd6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114602254 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same _csr_outstanding.2114602254 |
Directory | /workspace/16.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.1307437718 |
Short name | T192 |
Test name | |
Test status | |
Simulation time | 381434776 ps |
CPU time | 4.69 seconds |
Started | May 21 12:34:33 PM PDT 24 |
Finished | May 21 12:34:54 PM PDT 24 |
Peak memory | 213260 kb |
Host | smart-e2f0a06c-a3d6-4af2-9acb-646d076bbf07 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307437718 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.1307437718 |
Directory | /workspace/16.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.629596735 |
Short name | T130 |
Test name | |
Test status | |
Simulation time | 1343935137 ps |
CPU time | 20.91 seconds |
Started | May 21 12:34:33 PM PDT 24 |
Finished | May 21 12:35:10 PM PDT 24 |
Peak memory | 221388 kb |
Host | smart-0b84570d-4014-4bf4-9741-11dc82596426 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629596735 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.629596735 |
Directory | /workspace/16.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.725374755 |
Short name | T81 |
Test name | |
Test status | |
Simulation time | 495315937 ps |
CPU time | 2.6 seconds |
Started | May 21 12:34:32 PM PDT 24 |
Finished | May 21 12:34:51 PM PDT 24 |
Peak memory | 218988 kb |
Host | smart-08aa865f-a227-4135-ab35-82968eb12bab |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725374755 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.725374755 |
Directory | /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.1901109015 |
Short name | T237 |
Test name | |
Test status | |
Simulation time | 68722822 ps |
CPU time | 1.64 seconds |
Started | May 21 12:34:32 PM PDT 24 |
Finished | May 21 12:34:51 PM PDT 24 |
Peak memory | 213296 kb |
Host | smart-9e1266e0-aade-4329-9845-5ddb1142e46c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901109015 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.1901109015 |
Directory | /workspace/17.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2229001371 |
Short name | T231 |
Test name | |
Test status | |
Simulation time | 226987773 ps |
CPU time | 1.56 seconds |
Started | May 21 12:34:40 PM PDT 24 |
Finished | May 21 12:34:58 PM PDT 24 |
Peak memory | 204840 kb |
Host | smart-e7479e9f-f351-4754-b413-85a9b0f2c3b0 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229001371 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw. 2229001371 |
Directory | /workspace/17.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.3956665086 |
Short name | T249 |
Test name | |
Test status | |
Simulation time | 37050611 ps |
CPU time | 0.72 seconds |
Started | May 21 12:34:36 PM PDT 24 |
Finished | May 21 12:34:53 PM PDT 24 |
Peak memory | 204552 kb |
Host | smart-2a87a8cb-1bbb-4773-8d14-ce48e508594a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956665086 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw. 3956665086 |
Directory | /workspace/17.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.1579993231 |
Short name | T250 |
Test name | |
Test status | |
Simulation time | 276767056 ps |
CPU time | 3.48 seconds |
Started | May 21 12:34:35 PM PDT 24 |
Finished | May 21 12:34:55 PM PDT 24 |
Peak memory | 205060 kb |
Host | smart-59c3bf39-9c68-4d09-ac6c-386adb0bcce7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579993231 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same _csr_outstanding.1579993231 |
Directory | /workspace/17.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_tap_fsm_rand_reset.9307757 |
Short name | T24 |
Test name | |
Test status | |
Simulation time | 15922210601 ps |
CPU time | 50.74 seconds |
Started | May 21 12:34:32 PM PDT 24 |
Finished | May 21 12:35:40 PM PDT 24 |
Peak memory | 221460 kb |
Host | smart-e6101bdc-2d04-4f28-9d20-441bfad6f055 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9307757 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 17.rv_dm_tap_fsm_rand_reset.9307757 |
Directory | /workspace/17.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.832370624 |
Short name | T209 |
Test name | |
Test status | |
Simulation time | 362558892 ps |
CPU time | 6.32 seconds |
Started | May 21 12:34:35 PM PDT 24 |
Finished | May 21 12:34:58 PM PDT 24 |
Peak memory | 213268 kb |
Host | smart-6afe0c90-f10d-4546-b5e6-b1b684ae14a7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832370624 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.832370624 |
Directory | /workspace/17.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2288802988 |
Short name | T219 |
Test name | |
Test status | |
Simulation time | 988882142 ps |
CPU time | 16.55 seconds |
Started | May 21 12:34:33 PM PDT 24 |
Finished | May 21 12:35:06 PM PDT 24 |
Peak memory | 221420 kb |
Host | smart-d8ad2960-541a-4915-9d66-24f6527fa75e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288802988 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.2 288802988 |
Directory | /workspace/17.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.1500372659 |
Short name | T85 |
Test name | |
Test status | |
Simulation time | 1725251255 ps |
CPU time | 4.31 seconds |
Started | May 21 12:34:33 PM PDT 24 |
Finished | May 21 12:34:54 PM PDT 24 |
Peak memory | 219080 kb |
Host | smart-033bbac9-0ab3-4de4-9faa-50b768053b7c |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500372659 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.1500372659 |
Directory | /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.1330244502 |
Short name | T104 |
Test name | |
Test status | |
Simulation time | 223155591 ps |
CPU time | 2.25 seconds |
Started | May 21 12:34:33 PM PDT 24 |
Finished | May 21 12:34:52 PM PDT 24 |
Peak memory | 213208 kb |
Host | smart-0c6b6fd2-9d67-4739-9fcd-1135255d3c17 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330244502 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.1330244502 |
Directory | /workspace/18.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1211360717 |
Short name | T190 |
Test name | |
Test status | |
Simulation time | 1245540159 ps |
CPU time | 2.04 seconds |
Started | May 21 12:34:32 PM PDT 24 |
Finished | May 21 12:34:50 PM PDT 24 |
Peak memory | 204936 kb |
Host | smart-9ad4f765-1abd-4602-be53-506f7ccf388f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211360717 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw. 1211360717 |
Directory | /workspace/18.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.1315341385 |
Short name | T167 |
Test name | |
Test status | |
Simulation time | 95714005 ps |
CPU time | 0.74 seconds |
Started | May 21 12:34:34 PM PDT 24 |
Finished | May 21 12:34:51 PM PDT 24 |
Peak memory | 204728 kb |
Host | smart-270952a3-20b0-4fd2-9208-535d02992cba |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315341385 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw. 1315341385 |
Directory | /workspace/18.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.1881407530 |
Short name | T196 |
Test name | |
Test status | |
Simulation time | 136126205 ps |
CPU time | 4 seconds |
Started | May 21 12:34:33 PM PDT 24 |
Finished | May 21 12:34:53 PM PDT 24 |
Peak memory | 213636 kb |
Host | smart-ffea01b4-3a30-43ff-a22c-3685615cd9e0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881407530 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.1881407530 |
Directory | /workspace/18.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.2726062369 |
Short name | T122 |
Test name | |
Test status | |
Simulation time | 2236309799 ps |
CPU time | 8.18 seconds |
Started | May 21 12:34:33 PM PDT 24 |
Finished | May 21 12:34:58 PM PDT 24 |
Peak memory | 221480 kb |
Host | smart-c353be15-38e8-4447-8c0a-08a5a812c103 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726062369 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.2 726062369 |
Directory | /workspace/18.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3367888402 |
Short name | T84 |
Test name | |
Test status | |
Simulation time | 4380418632 ps |
CPU time | 5.16 seconds |
Started | May 21 12:34:36 PM PDT 24 |
Finished | May 21 12:34:57 PM PDT 24 |
Peak memory | 214944 kb |
Host | smart-7ec0ab29-8ea0-4edf-804b-0a6f4b6bd39b |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367888402 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.3367888402 |
Directory | /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.1529923778 |
Short name | T109 |
Test name | |
Test status | |
Simulation time | 103418038 ps |
CPU time | 1.48 seconds |
Started | May 21 12:34:30 PM PDT 24 |
Finished | May 21 12:34:49 PM PDT 24 |
Peak memory | 221440 kb |
Host | smart-e3e25ee7-e4ec-4fbd-819f-c56e3680795e |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529923778 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.1529923778 |
Directory | /workspace/19.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2991465538 |
Short name | T44 |
Test name | |
Test status | |
Simulation time | 258442919 ps |
CPU time | 1.29 seconds |
Started | May 21 12:34:35 PM PDT 24 |
Finished | May 21 12:34:53 PM PDT 24 |
Peak memory | 204880 kb |
Host | smart-1fcdf96f-c586-4833-a3bc-1938357a4479 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991465538 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw. 2991465538 |
Directory | /workspace/19.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2967517475 |
Short name | T156 |
Test name | |
Test status | |
Simulation time | 62772548 ps |
CPU time | 0.85 seconds |
Started | May 21 12:34:39 PM PDT 24 |
Finished | May 21 12:34:55 PM PDT 24 |
Peak memory | 204664 kb |
Host | smart-da9470e4-b630-483f-ac95-348db27dc112 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967517475 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw. 2967517475 |
Directory | /workspace/19.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.2619917818 |
Short name | T111 |
Test name | |
Test status | |
Simulation time | 1074486689 ps |
CPU time | 6.66 seconds |
Started | May 21 12:34:32 PM PDT 24 |
Finished | May 21 12:34:55 PM PDT 24 |
Peak memory | 205024 kb |
Host | smart-dbe0cfc3-65a1-4f2d-83d5-81e3bb572961 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619917818 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same _csr_outstanding.2619917818 |
Directory | /workspace/19.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.869485024 |
Short name | T242 |
Test name | |
Test status | |
Simulation time | 461581637 ps |
CPU time | 5.32 seconds |
Started | May 21 12:34:30 PM PDT 24 |
Finished | May 21 12:34:52 PM PDT 24 |
Peak memory | 213340 kb |
Host | smart-6806674e-58af-434b-b3f5-54d100baaa60 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869485024 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.869485024 |
Directory | /workspace/19.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.436405244 |
Short name | T126 |
Test name | |
Test status | |
Simulation time | 333256433 ps |
CPU time | 8.84 seconds |
Started | May 21 12:34:35 PM PDT 24 |
Finished | May 21 12:35:00 PM PDT 24 |
Peak memory | 213292 kb |
Host | smart-614bced3-9ddb-40aa-9280-d763eec5d9c1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436405244 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.436405244 |
Directory | /workspace/19.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2244696827 |
Short name | T197 |
Test name | |
Test status | |
Simulation time | 1077877572 ps |
CPU time | 64.35 seconds |
Started | May 21 12:33:57 PM PDT 24 |
Finished | May 21 12:35:27 PM PDT 24 |
Peak memory | 213248 kb |
Host | smart-fcb9cff7-b32e-4a98-915a-5f2e210d96ce |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244696827 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 2.rv_dm_csr_aliasing.2244696827 |
Directory | /workspace/2.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2850448883 |
Short name | T259 |
Test name | |
Test status | |
Simulation time | 42034847267 ps |
CPU time | 75.96 seconds |
Started | May 21 12:34:06 PM PDT 24 |
Finished | May 21 12:35:44 PM PDT 24 |
Peak memory | 205176 kb |
Host | smart-15ac6407-f16b-41fd-8cf7-ad8db46984ad |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850448883 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.2850448883 |
Directory | /workspace/2.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3494552806 |
Short name | T188 |
Test name | |
Test status | |
Simulation time | 1744653287 ps |
CPU time | 3.77 seconds |
Started | May 21 12:34:04 PM PDT 24 |
Finished | May 21 12:34:31 PM PDT 24 |
Peak memory | 217528 kb |
Host | smart-41d49b22-b8bf-4e80-bd51-2b9f60f38366 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494552806 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.3494552806 |
Directory | /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.2282142733 |
Short name | T90 |
Test name | |
Test status | |
Simulation time | 150324303 ps |
CPU time | 1.53 seconds |
Started | May 21 12:34:03 PM PDT 24 |
Finished | May 21 12:34:28 PM PDT 24 |
Peak memory | 218444 kb |
Host | smart-eeb3f183-b76f-4df0-b54e-48c02a09755f |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282142733 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.2282142733 |
Directory | /workspace/2.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.3625736806 |
Short name | T158 |
Test name | |
Test status | |
Simulation time | 25385051506 ps |
CPU time | 68.09 seconds |
Started | May 21 12:34:00 PM PDT 24 |
Finished | May 21 12:35:32 PM PDT 24 |
Peak memory | 205112 kb |
Host | smart-f445fe47-de19-4f7b-b111-08d3c3007e41 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625736806 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs r_aliasing.3625736806 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.2184770212 |
Short name | T210 |
Test name | |
Test status | |
Simulation time | 20742886496 ps |
CPU time | 30.43 seconds |
Started | May 21 12:34:01 PM PDT 24 |
Finished | May 21 12:34:55 PM PDT 24 |
Peak memory | 205024 kb |
Host | smart-c7d71be6-553f-4be6-957d-63977c58b451 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184770212 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_bit_bash.2184770212 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.3068552223 |
Short name | T37 |
Test name | |
Test status | |
Simulation time | 730267689 ps |
CPU time | 3.75 seconds |
Started | May 21 12:34:05 PM PDT 24 |
Finished | May 21 12:34:31 PM PDT 24 |
Peak memory | 205344 kb |
Host | smart-d12efc7c-009f-4743-9fb6-d08723ca5a95 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068552223 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs r_hw_reset.3068552223 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.3096912252 |
Short name | T160 |
Test name | |
Test status | |
Simulation time | 191537995 ps |
CPU time | 1.07 seconds |
Started | May 21 12:34:01 PM PDT 24 |
Finished | May 21 12:34:26 PM PDT 24 |
Peak memory | 204952 kb |
Host | smart-9d1495ee-e1e9-4615-bc74-432231f60461 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096912252 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.3 096912252 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.142168208 |
Short name | T205 |
Test name | |
Test status | |
Simulation time | 38382313 ps |
CPU time | 0.81 seconds |
Started | May 21 12:34:01 PM PDT 24 |
Finished | May 21 12:34:25 PM PDT 24 |
Peak memory | 204748 kb |
Host | smart-1373dcb8-426d-4025-9271-3b11f38d661f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142168208 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr _aliasing.142168208 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.878645773 |
Short name | T218 |
Test name | |
Test status | |
Simulation time | 1850911323 ps |
CPU time | 7.14 seconds |
Started | May 21 12:33:58 PM PDT 24 |
Finished | May 21 12:34:30 PM PDT 24 |
Peak memory | 204996 kb |
Host | smart-ba14d30f-d909-4843-8727-a9ef453cc634 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878645773 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr _bit_bash.878645773 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3523212937 |
Short name | T244 |
Test name | |
Test status | |
Simulation time | 77486122 ps |
CPU time | 0.77 seconds |
Started | May 21 12:34:00 PM PDT 24 |
Finished | May 21 12:34:25 PM PDT 24 |
Peak memory | 204776 kb |
Host | smart-c0b1ff1b-97dd-41cb-84ae-71c921ce8749 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523212937 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_hw_reset.3523212937 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.1827683271 |
Short name | T166 |
Test name | |
Test status | |
Simulation time | 27667330 ps |
CPU time | 0.74 seconds |
Started | May 21 12:34:00 PM PDT 24 |
Finished | May 21 12:34:24 PM PDT 24 |
Peak memory | 204708 kb |
Host | smart-e9c626cf-c257-4002-a343-e69085b99cdb |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827683271 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.1 827683271 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.3116326111 |
Short name | T169 |
Test name | |
Test status | |
Simulation time | 30107899 ps |
CPU time | 0.71 seconds |
Started | May 21 12:34:04 PM PDT 24 |
Finished | May 21 12:34:28 PM PDT 24 |
Peak memory | 204708 kb |
Host | smart-c02f12cb-36dd-4656-9923-c712ad3ec6ea |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116326111 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par tial_access.3116326111 |
Directory | /workspace/2.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.3133967700 |
Short name | T255 |
Test name | |
Test status | |
Simulation time | 134480868 ps |
CPU time | 0.68 seconds |
Started | May 21 12:34:10 PM PDT 24 |
Finished | May 21 12:34:32 PM PDT 24 |
Peak memory | 204776 kb |
Host | smart-51d2cd74-6053-4a30-afc0-930f3bf25f33 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133967700 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.3133967700 |
Directory | /workspace/2.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3800621678 |
Short name | T110 |
Test name | |
Test status | |
Simulation time | 486933035 ps |
CPU time | 7.61 seconds |
Started | May 21 12:34:11 PM PDT 24 |
Finished | May 21 12:34:39 PM PDT 24 |
Peak memory | 205060 kb |
Host | smart-6921fcc6-4f1c-4d07-8ef8-1ff4a8c1117e |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800621678 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_ csr_outstanding.3800621678 |
Directory | /workspace/2.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.3519257378 |
Short name | T260 |
Test name | |
Test status | |
Simulation time | 119331996 ps |
CPU time | 3.68 seconds |
Started | May 21 12:34:11 PM PDT 24 |
Finished | May 21 12:34:35 PM PDT 24 |
Peak memory | 213280 kb |
Host | smart-332a1a52-3828-4476-bd91-b22e6df46d56 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519257378 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.3519257378 |
Directory | /workspace/2.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/20.rv_dm_tap_fsm_rand_reset.759664365 |
Short name | T25 |
Test name | |
Test status | |
Simulation time | 19443643915 ps |
CPU time | 35.23 seconds |
Started | May 21 12:34:30 PM PDT 24 |
Finished | May 21 12:35:22 PM PDT 24 |
Peak memory | 221540 kb |
Host | smart-2f0ca1ef-d785-459b-9dc8-5653e1821102 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759664365 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 20.rv_dm_tap_fsm_rand_reset.759664365 |
Directory | /workspace/20.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/21.rv_dm_tap_fsm_rand_reset.2084860231 |
Short name | T194 |
Test name | |
Test status | |
Simulation time | 31455645382 ps |
CPU time | 28.02 seconds |
Started | May 21 12:34:31 PM PDT 24 |
Finished | May 21 12:35:15 PM PDT 24 |
Peak memory | 221612 kb |
Host | smart-6b0b17e5-d424-47d0-89ca-d20a304ae708 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084860231 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 21.rv_dm_tap_fsm_rand_reset.2084860231 |
Directory | /workspace/21.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/22.rv_dm_tap_fsm_rand_reset.4171180138 |
Short name | T261 |
Test name | |
Test status | |
Simulation time | 30583156892 ps |
CPU time | 26.99 seconds |
Started | May 21 12:34:33 PM PDT 24 |
Finished | May 21 12:35:16 PM PDT 24 |
Peak memory | 221512 kb |
Host | smart-f2a84318-87c4-4d2e-9691-fbcae28d129a |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171180138 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 22.rv_dm_tap_fsm_rand_reset.4171180138 |
Directory | /workspace/22.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1894972924 |
Short name | T105 |
Test name | |
Test status | |
Simulation time | 8657010855 ps |
CPU time | 80.01 seconds |
Started | May 21 12:34:11 PM PDT 24 |
Finished | May 21 12:35:52 PM PDT 24 |
Peak memory | 217684 kb |
Host | smart-dfeff97f-bdf6-4848-8f44-7b432eacf6c2 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894972924 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 3.rv_dm_csr_aliasing.1894972924 |
Directory | /workspace/3.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1058417934 |
Short name | T103 |
Test name | |
Test status | |
Simulation time | 1462881573 ps |
CPU time | 53.17 seconds |
Started | May 21 12:34:14 PM PDT 24 |
Finished | May 21 12:35:27 PM PDT 24 |
Peak memory | 205048 kb |
Host | smart-098fd7e4-b7a6-40d1-9001-ff6b11c90001 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058417934 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.1058417934 |
Directory | /workspace/3.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.4054934691 |
Short name | T116 |
Test name | |
Test status | |
Simulation time | 145973123 ps |
CPU time | 1.68 seconds |
Started | May 21 12:34:10 PM PDT 24 |
Finished | May 21 12:34:33 PM PDT 24 |
Peak memory | 213204 kb |
Host | smart-15e89005-00ca-41a5-8cfe-bd14f7d98c5f |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054934691 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.4054934691 |
Directory | /workspace/3.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.186134581 |
Short name | T238 |
Test name | |
Test status | |
Simulation time | 3813262118 ps |
CPU time | 5.19 seconds |
Started | May 21 12:34:12 PM PDT 24 |
Finished | May 21 12:34:37 PM PDT 24 |
Peak memory | 220124 kb |
Host | smart-20015a2f-d160-4f93-8d85-6f9bb834c498 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186134581 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.186134581 |
Directory | /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2801850250 |
Short name | T99 |
Test name | |
Test status | |
Simulation time | 57480008 ps |
CPU time | 1.45 seconds |
Started | May 21 12:34:10 PM PDT 24 |
Finished | May 21 12:34:32 PM PDT 24 |
Peak memory | 218464 kb |
Host | smart-59da627c-4a26-43a6-8922-b380e5d88c32 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801850250 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.2801850250 |
Directory | /workspace/3.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.870681053 |
Short name | T253 |
Test name | |
Test status | |
Simulation time | 3585279307 ps |
CPU time | 10.77 seconds |
Started | May 21 12:34:10 PM PDT 24 |
Finished | May 21 12:34:41 PM PDT 24 |
Peak memory | 205068 kb |
Host | smart-de4f415e-1e2c-46c8-9f8b-cd43eecfcaf3 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870681053 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr _aliasing.870681053 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.408221602 |
Short name | T270 |
Test name | |
Test status | |
Simulation time | 19545624814 ps |
CPU time | 22.67 seconds |
Started | May 21 12:34:05 PM PDT 24 |
Finished | May 21 12:34:50 PM PDT 24 |
Peak memory | 205000 kb |
Host | smart-ac9dd947-08fa-469e-b573-a00be4a51254 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408221602 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U VM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_bit_bash.408221602 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2539794521 |
Short name | T39 |
Test name | |
Test status | |
Simulation time | 1717013962 ps |
CPU time | 4.07 seconds |
Started | May 21 12:34:10 PM PDT 24 |
Finished | May 21 12:34:35 PM PDT 24 |
Peak memory | 205060 kb |
Host | smart-fa67c1f3-2576-4021-87b9-4404c89c7d24 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539794521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs r_hw_reset.2539794521 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.2173881206 |
Short name | T202 |
Test name | |
Test status | |
Simulation time | 1990416699 ps |
CPU time | 3.02 seconds |
Started | May 21 12:34:11 PM PDT 24 |
Finished | May 21 12:34:35 PM PDT 24 |
Peak memory | 204992 kb |
Host | smart-407edaaa-6a62-4ab0-aa80-5b3d116d6897 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173881206 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.2 173881206 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3696332648 |
Short name | T228 |
Test name | |
Test status | |
Simulation time | 155548347 ps |
CPU time | 0.92 seconds |
Started | May 21 12:34:08 PM PDT 24 |
Finished | May 21 12:34:30 PM PDT 24 |
Peak memory | 204816 kb |
Host | smart-c9895a57-d392-4c7b-8735-9034e0f479b2 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696332648 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_aliasing.3696332648 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2390702975 |
Short name | T221 |
Test name | |
Test status | |
Simulation time | 3110335969 ps |
CPU time | 9.58 seconds |
Started | May 21 12:34:10 PM PDT 24 |
Finished | May 21 12:34:41 PM PDT 24 |
Peak memory | 205036 kb |
Host | smart-90ffb1e3-3db8-4b20-8d91-f2f4d40bb111 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390702975 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_bit_bash.2390702975 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3093085420 |
Short name | T220 |
Test name | |
Test status | |
Simulation time | 116532515 ps |
CPU time | 0.7 seconds |
Started | May 21 12:34:08 PM PDT 24 |
Finished | May 21 12:34:30 PM PDT 24 |
Peak memory | 204812 kb |
Host | smart-da347665-a46e-4f7d-b71b-2f43e69ef51e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093085420 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_hw_reset.3093085420 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2336557041 |
Short name | T77 |
Test name | |
Test status | |
Simulation time | 62442649 ps |
CPU time | 0.7 seconds |
Started | May 21 12:34:08 PM PDT 24 |
Finished | May 21 12:34:30 PM PDT 24 |
Peak memory | 204748 kb |
Host | smart-e0974285-ba8e-4992-9292-2efbc92525c6 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336557041 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.2 336557041 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.2991879032 |
Short name | T204 |
Test name | |
Test status | |
Simulation time | 23439748 ps |
CPU time | 0.65 seconds |
Started | May 21 12:34:10 PM PDT 24 |
Finished | May 21 12:34:31 PM PDT 24 |
Peak memory | 204768 kb |
Host | smart-8847a99f-3564-485e-a7ae-7589cb9c7409 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991879032 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par tial_access.2991879032 |
Directory | /workspace/3.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1080595225 |
Short name | T268 |
Test name | |
Test status | |
Simulation time | 28893764 ps |
CPU time | 0.68 seconds |
Started | May 21 12:34:13 PM PDT 24 |
Finished | May 21 12:34:34 PM PDT 24 |
Peak memory | 204812 kb |
Host | smart-9393ff5f-eacf-48cb-9acb-4a865152fa96 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080595225 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.1080595225 |
Directory | /workspace/3.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.4073983907 |
Short name | T233 |
Test name | |
Test status | |
Simulation time | 217338350 ps |
CPU time | 4 seconds |
Started | May 21 12:34:10 PM PDT 24 |
Finished | May 21 12:34:35 PM PDT 24 |
Peak memory | 205152 kb |
Host | smart-382d833b-10d6-4dc0-98f9-f79c32269df3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073983907 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_ csr_outstanding.4073983907 |
Directory | /workspace/3.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.3425010330 |
Short name | T117 |
Test name | |
Test status | |
Simulation time | 2227642465 ps |
CPU time | 5.12 seconds |
Started | May 21 12:34:10 PM PDT 24 |
Finished | May 21 12:34:36 PM PDT 24 |
Peak memory | 213428 kb |
Host | smart-beb4daa3-c583-40da-9b6e-b16fe4f654ee |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425010330 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.3425010330 |
Directory | /workspace/3.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.713799771 |
Short name | T127 |
Test name | |
Test status | |
Simulation time | 1813808519 ps |
CPU time | 19.28 seconds |
Started | May 21 12:34:14 PM PDT 24 |
Finished | May 21 12:34:53 PM PDT 24 |
Peak memory | 213252 kb |
Host | smart-3874ed3a-03d5-4f3b-9906-0c21da9dd06a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713799771 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.713799771 |
Directory | /workspace/3.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/39.rv_dm_tap_fsm_rand_reset.1153031189 |
Short name | T266 |
Test name | |
Test status | |
Simulation time | 24026093526 ps |
CPU time | 12.07 seconds |
Started | May 21 12:34:46 PM PDT 24 |
Finished | May 21 12:35:15 PM PDT 24 |
Peak memory | 215284 kb |
Host | smart-9982ff72-5857-4bdb-9e12-5c933db4e34d |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153031189 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 39.rv_dm_tap_fsm_rand_reset.1153031189 |
Directory | /workspace/39.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1109104933 |
Short name | T101 |
Test name | |
Test status | |
Simulation time | 8274506802 ps |
CPU time | 76.83 seconds |
Started | May 21 12:34:17 PM PDT 24 |
Finished | May 21 12:35:52 PM PDT 24 |
Peak memory | 213280 kb |
Host | smart-10ca8835-9cff-459b-847a-d2523beb9467 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109104933 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 4.rv_dm_csr_aliasing.1109104933 |
Directory | /workspace/4.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.1599057583 |
Short name | T232 |
Test name | |
Test status | |
Simulation time | 2956711639 ps |
CPU time | 27.48 seconds |
Started | May 21 12:34:13 PM PDT 24 |
Finished | May 21 12:35:01 PM PDT 24 |
Peak memory | 213588 kb |
Host | smart-9757055a-fd55-4a92-a13d-0e3090b7815d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599057583 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.1599057583 |
Directory | /workspace/4.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.953945339 |
Short name | T118 |
Test name | |
Test status | |
Simulation time | 161541097 ps |
CPU time | 2.28 seconds |
Started | May 21 12:34:11 PM PDT 24 |
Finished | May 21 12:34:34 PM PDT 24 |
Peak memory | 217228 kb |
Host | smart-d9de89da-8475-44a8-a9a7-e78691f02ad7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953945339 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.953945339 |
Directory | /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.1267802426 |
Short name | T107 |
Test name | |
Test status | |
Simulation time | 559572573 ps |
CPU time | 2.18 seconds |
Started | May 21 12:34:14 PM PDT 24 |
Finished | May 21 12:34:36 PM PDT 24 |
Peak memory | 218228 kb |
Host | smart-67e4e0de-9379-43ba-8ed4-739f5cad6a22 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267802426 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.1267802426 |
Directory | /workspace/4.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.3412195204 |
Short name | T230 |
Test name | |
Test status | |
Simulation time | 45101392269 ps |
CPU time | 75.4 seconds |
Started | May 21 12:34:14 PM PDT 24 |
Finished | May 21 12:35:49 PM PDT 24 |
Peak memory | 204984 kb |
Host | smart-159a8085-d1da-48c8-9580-f5157f8339dd |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412195204 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs r_aliasing.3412195204 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.1247318805 |
Short name | T193 |
Test name | |
Test status | |
Simulation time | 7131785364 ps |
CPU time | 33.73 seconds |
Started | May 21 12:34:13 PM PDT 24 |
Finished | May 21 12:35:07 PM PDT 24 |
Peak memory | 205036 kb |
Host | smart-8cb5b7ae-2e6b-4120-a780-4e4aaa9f4738 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247318805 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_bit_bash.1247318805 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3264852150 |
Short name | T208 |
Test name | |
Test status | |
Simulation time | 636695415 ps |
CPU time | 1.81 seconds |
Started | May 21 12:34:11 PM PDT 24 |
Finished | May 21 12:34:33 PM PDT 24 |
Peak memory | 205048 kb |
Host | smart-920c0ab7-3d4b-4b51-9ef1-7a9572f37dfc |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264852150 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.3 264852150 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.1681783482 |
Short name | T274 |
Test name | |
Test status | |
Simulation time | 214784395 ps |
CPU time | 1.13 seconds |
Started | May 21 12:34:10 PM PDT 24 |
Finished | May 21 12:34:32 PM PDT 24 |
Peak memory | 204720 kb |
Host | smart-c376025d-c936-46e0-94c4-11f126be980e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681783482 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs r_aliasing.1681783482 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2638904094 |
Short name | T216 |
Test name | |
Test status | |
Simulation time | 558785197 ps |
CPU time | 1.28 seconds |
Started | May 21 12:34:51 PM PDT 24 |
Finished | May 21 12:35:11 PM PDT 24 |
Peak memory | 204880 kb |
Host | smart-04e38362-553f-405f-b04e-9a62b4f7cc2a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638904094 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs r_bit_bash.2638904094 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.1806144882 |
Short name | T22 |
Test name | |
Test status | |
Simulation time | 52300869 ps |
CPU time | 0.73 seconds |
Started | May 21 12:34:11 PM PDT 24 |
Finished | May 21 12:34:32 PM PDT 24 |
Peak memory | 204880 kb |
Host | smart-bf7bd9e8-bc17-4cd5-a1be-9c4169fd8303 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806144882 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs r_hw_reset.1806144882 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2862442516 |
Short name | T222 |
Test name | |
Test status | |
Simulation time | 69599137 ps |
CPU time | 0.76 seconds |
Started | May 21 12:34:12 PM PDT 24 |
Finished | May 21 12:34:33 PM PDT 24 |
Peak memory | 204808 kb |
Host | smart-66547ea6-5f82-4a78-9573-214b16aa2fbe |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862442516 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.2 862442516 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.2700017508 |
Short name | T224 |
Test name | |
Test status | |
Simulation time | 23463357 ps |
CPU time | 0.66 seconds |
Started | May 21 12:34:10 PM PDT 24 |
Finished | May 21 12:34:31 PM PDT 24 |
Peak memory | 204816 kb |
Host | smart-f5b3875d-0275-4995-b487-c623e278ca48 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700017508 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par tial_access.2700017508 |
Directory | /workspace/4.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.2520000882 |
Short name | T272 |
Test name | |
Test status | |
Simulation time | 46638976 ps |
CPU time | 0.67 seconds |
Started | May 21 12:34:10 PM PDT 24 |
Finished | May 21 12:34:32 PM PDT 24 |
Peak memory | 204804 kb |
Host | smart-9c4d8465-94ea-4fe0-9ce0-f887696e9042 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520000882 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.2520000882 |
Directory | /workspace/4.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1531908736 |
Short name | T245 |
Test name | |
Test status | |
Simulation time | 1556580523 ps |
CPU time | 7.38 seconds |
Started | May 21 12:34:13 PM PDT 24 |
Finished | May 21 12:34:40 PM PDT 24 |
Peak memory | 205068 kb |
Host | smart-fc5b6f06-71fe-49f1-bc4e-9cfdb1ae7011 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531908736 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_ csr_outstanding.1531908736 |
Directory | /workspace/4.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.608969279 |
Short name | T191 |
Test name | |
Test status | |
Simulation time | 8165113435 ps |
CPU time | 29.73 seconds |
Started | May 21 12:34:11 PM PDT 24 |
Finished | May 21 12:35:01 PM PDT 24 |
Peak memory | 220148 kb |
Host | smart-02017b2e-10c2-4cc4-8dcc-19f5d9aba3c8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608969279 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.608969279 |
Directory | /workspace/4.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.3056053820 |
Short name | T182 |
Test name | |
Test status | |
Simulation time | 895754503 ps |
CPU time | 5.75 seconds |
Started | May 21 12:34:16 PM PDT 24 |
Finished | May 21 12:34:41 PM PDT 24 |
Peak memory | 213200 kb |
Host | smart-9d2300fc-dd56-44e9-962d-8a040eea859b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056053820 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.3056053820 |
Directory | /workspace/4.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.2540640800 |
Short name | T236 |
Test name | |
Test status | |
Simulation time | 874526210 ps |
CPU time | 9.72 seconds |
Started | May 21 12:34:09 PM PDT 24 |
Finished | May 21 12:34:40 PM PDT 24 |
Peak memory | 213204 kb |
Host | smart-3cecb6ef-345e-4731-bcd0-c754e970c15c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540640800 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.2540640800 |
Directory | /workspace/4.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.2217648399 |
Short name | T30 |
Test name | |
Test status | |
Simulation time | 5583935491 ps |
CPU time | 5.61 seconds |
Started | May 21 12:34:11 PM PDT 24 |
Finished | May 21 12:34:37 PM PDT 24 |
Peak memory | 219460 kb |
Host | smart-f3a7a947-291f-4461-a7c1-92bcf83151ae |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217648399 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.2217648399 |
Directory | /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.4239741057 |
Short name | T189 |
Test name | |
Test status | |
Simulation time | 68061379 ps |
CPU time | 1.5 seconds |
Started | May 21 12:34:10 PM PDT 24 |
Finished | May 21 12:34:32 PM PDT 24 |
Peak memory | 213216 kb |
Host | smart-19a93063-d08c-452e-8d83-6ac0c49c02dc |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239741057 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.4239741057 |
Directory | /workspace/5.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3971555305 |
Short name | T187 |
Test name | |
Test status | |
Simulation time | 497828637 ps |
CPU time | 1.81 seconds |
Started | May 21 12:34:14 PM PDT 24 |
Finished | May 21 12:34:35 PM PDT 24 |
Peak memory | 204912 kb |
Host | smart-89baed65-904d-45bc-8084-4f3afa946a7f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971555305 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.3 971555305 |
Directory | /workspace/5.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.2237907858 |
Short name | T78 |
Test name | |
Test status | |
Simulation time | 60046959 ps |
CPU time | 0.65 seconds |
Started | May 21 12:34:59 PM PDT 24 |
Finished | May 21 12:35:21 PM PDT 24 |
Peak memory | 204636 kb |
Host | smart-784f23e8-1e57-413f-b6ae-917159515990 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237907858 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.2 237907858 |
Directory | /workspace/5.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.2719834845 |
Short name | T113 |
Test name | |
Test status | |
Simulation time | 167015592 ps |
CPU time | 6.26 seconds |
Started | May 21 12:34:10 PM PDT 24 |
Finished | May 21 12:34:37 PM PDT 24 |
Peak memory | 205028 kb |
Host | smart-9c56c653-325a-42a2-ae41-5b48969be897 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719834845 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_ csr_outstanding.2719834845 |
Directory | /workspace/5.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.497172126 |
Short name | T217 |
Test name | |
Test status | |
Simulation time | 25546247649 ps |
CPU time | 13.62 seconds |
Started | May 21 12:34:12 PM PDT 24 |
Finished | May 21 12:34:46 PM PDT 24 |
Peak memory | 215936 kb |
Host | smart-fd1fea3d-7491-406a-a94b-fde92f8ef9c0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497172126 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.497172126 |
Directory | /workspace/5.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2938337754 |
Short name | T179 |
Test name | |
Test status | |
Simulation time | 1372491640 ps |
CPU time | 15.41 seconds |
Started | May 21 12:34:13 PM PDT 24 |
Finished | May 21 12:34:48 PM PDT 24 |
Peak memory | 221300 kb |
Host | smart-0bac990b-2b04-4b4e-b45e-5382be01f469 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938337754 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.2938337754 |
Directory | /workspace/5.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.4044389535 |
Short name | T229 |
Test name | |
Test status | |
Simulation time | 182621286 ps |
CPU time | 1.45 seconds |
Started | May 21 12:34:16 PM PDT 24 |
Finished | May 21 12:34:37 PM PDT 24 |
Peak memory | 213112 kb |
Host | smart-d68fdffa-b617-4e73-8644-cce6a11a2c17 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044389535 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.4044389535 |
Directory | /workspace/6.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.3849718603 |
Short name | T70 |
Test name | |
Test status | |
Simulation time | 318821293 ps |
CPU time | 1.51 seconds |
Started | May 21 12:34:10 PM PDT 24 |
Finished | May 21 12:34:32 PM PDT 24 |
Peak memory | 204884 kb |
Host | smart-dafb2489-d30d-47d9-af01-9fe9a45a8c03 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849718603 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.3 849718603 |
Directory | /workspace/6.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2495850540 |
Short name | T161 |
Test name | |
Test status | |
Simulation time | 57812509 ps |
CPU time | 0.75 seconds |
Started | May 21 12:34:13 PM PDT 24 |
Finished | May 21 12:34:34 PM PDT 24 |
Peak memory | 204776 kb |
Host | smart-b2b91dbc-4e6f-45e7-a041-966d5eb4837b |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495850540 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.2 495850540 |
Directory | /workspace/6.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.3062103912 |
Short name | T92 |
Test name | |
Test status | |
Simulation time | 336520010 ps |
CPU time | 4.34 seconds |
Started | May 21 12:34:19 PM PDT 24 |
Finished | May 21 12:34:42 PM PDT 24 |
Peak memory | 205028 kb |
Host | smart-c91c2de2-58d8-4bfd-b09f-2edec46c2abc |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062103912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_ csr_outstanding.3062103912 |
Directory | /workspace/6.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.494258032 |
Short name | T223 |
Test name | |
Test status | |
Simulation time | 123276676 ps |
CPU time | 2.95 seconds |
Started | May 21 12:34:09 PM PDT 24 |
Finished | May 21 12:34:33 PM PDT 24 |
Peak memory | 213284 kb |
Host | smart-64b8e38f-712e-46ed-8a9e-3772b338a0ef |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494258032 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.494258032 |
Directory | /workspace/6.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1152145905 |
Short name | T129 |
Test name | |
Test status | |
Simulation time | 574298578 ps |
CPU time | 9.88 seconds |
Started | May 21 12:34:17 PM PDT 24 |
Finished | May 21 12:34:45 PM PDT 24 |
Peak memory | 221280 kb |
Host | smart-a2befccf-1a84-4869-a01e-51c6862798a1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152145905 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.1152145905 |
Directory | /workspace/6.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2593644682 |
Short name | T71 |
Test name | |
Test status | |
Simulation time | 3327236092 ps |
CPU time | 5.31 seconds |
Started | May 21 12:34:25 PM PDT 24 |
Finished | May 21 12:34:47 PM PDT 24 |
Peak memory | 218920 kb |
Host | smart-320eb20e-726b-4d9b-838a-fbc89b8f02a2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593644682 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.2593644682 |
Directory | /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.3539593772 |
Short name | T86 |
Test name | |
Test status | |
Simulation time | 190905770 ps |
CPU time | 1.52 seconds |
Started | May 21 12:34:20 PM PDT 24 |
Finished | May 21 12:34:40 PM PDT 24 |
Peak memory | 213324 kb |
Host | smart-3e20a5e9-66af-449a-ac2b-f91cacb4ba38 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539593772 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.3539593772 |
Directory | /workspace/7.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.620301110 |
Short name | T199 |
Test name | |
Test status | |
Simulation time | 285903278 ps |
CPU time | 1.4 seconds |
Started | May 21 12:34:20 PM PDT 24 |
Finished | May 21 12:34:40 PM PDT 24 |
Peak memory | 204988 kb |
Host | smart-dacceaeb-2bab-4984-a225-f21e9023db8a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620301110 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.620301110 |
Directory | /workspace/7.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1305052809 |
Short name | T183 |
Test name | |
Test status | |
Simulation time | 31789915 ps |
CPU time | 0.72 seconds |
Started | May 21 12:34:18 PM PDT 24 |
Finished | May 21 12:34:37 PM PDT 24 |
Peak memory | 204740 kb |
Host | smart-9b12dcb1-a127-4ae0-bb09-86ed2a8ec603 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305052809 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.1 305052809 |
Directory | /workspace/7.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3647253937 |
Short name | T227 |
Test name | |
Test status | |
Simulation time | 324179571 ps |
CPU time | 6.23 seconds |
Started | May 21 12:34:20 PM PDT 24 |
Finished | May 21 12:34:44 PM PDT 24 |
Peak memory | 205104 kb |
Host | smart-a95c2fb3-dd2a-44d3-8152-215d7f5233aa |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647253937 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_ csr_outstanding.3647253937 |
Directory | /workspace/7.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.3270976386 |
Short name | T263 |
Test name | |
Test status | |
Simulation time | 2641846050 ps |
CPU time | 16.32 seconds |
Started | May 21 12:34:22 PM PDT 24 |
Finished | May 21 12:34:56 PM PDT 24 |
Peak memory | 213344 kb |
Host | smart-96eff0f8-0050-46a4-95a6-6ca0381f75e7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270976386 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.3270976386 |
Directory | /workspace/7.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1421584448 |
Short name | T75 |
Test name | |
Test status | |
Simulation time | 1119423020 ps |
CPU time | 3.98 seconds |
Started | May 21 12:34:18 PM PDT 24 |
Finished | May 21 12:34:41 PM PDT 24 |
Peak memory | 217320 kb |
Host | smart-334ad35f-50ad-42c0-8348-c23fdd5aac1b |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421584448 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.1421584448 |
Directory | /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1788571293 |
Short name | T67 |
Test name | |
Test status | |
Simulation time | 85555941 ps |
CPU time | 1.49 seconds |
Started | May 21 12:34:22 PM PDT 24 |
Finished | May 21 12:34:40 PM PDT 24 |
Peak memory | 213560 kb |
Host | smart-1df14bfd-1f01-4e39-8c4f-6d1ccad44f65 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788571293 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.1788571293 |
Directory | /workspace/8.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.2585309845 |
Short name | T170 |
Test name | |
Test status | |
Simulation time | 402233152 ps |
CPU time | 1.61 seconds |
Started | May 21 12:34:20 PM PDT 24 |
Finished | May 21 12:34:40 PM PDT 24 |
Peak memory | 204940 kb |
Host | smart-b6b8e2f1-c35b-49fb-96c0-c9c913b6b1b3 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585309845 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.2 585309845 |
Directory | /workspace/8.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.1820672859 |
Short name | T168 |
Test name | |
Test status | |
Simulation time | 33959534 ps |
CPU time | 0.69 seconds |
Started | May 21 12:34:20 PM PDT 24 |
Finished | May 21 12:34:39 PM PDT 24 |
Peak memory | 204804 kb |
Host | smart-11154416-bd0c-4e8b-a8c5-b1c09bcb710a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820672859 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.1 820672859 |
Directory | /workspace/8.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.3312279529 |
Short name | T98 |
Test name | |
Test status | |
Simulation time | 1481147769 ps |
CPU time | 4.62 seconds |
Started | May 21 12:34:19 PM PDT 24 |
Finished | May 21 12:34:42 PM PDT 24 |
Peak memory | 205016 kb |
Host | smart-aead29a3-07d6-4686-9ab7-6bdc15378fc3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312279529 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_ csr_outstanding.3312279529 |
Directory | /workspace/8.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.854660089 |
Short name | T262 |
Test name | |
Test status | |
Simulation time | 125541820 ps |
CPU time | 2.52 seconds |
Started | May 21 12:34:20 PM PDT 24 |
Finished | May 21 12:34:40 PM PDT 24 |
Peak memory | 213336 kb |
Host | smart-caaeadb6-7778-4194-a655-9e938ab9c78b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854660089 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.854660089 |
Directory | /workspace/8.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3651537148 |
Short name | T225 |
Test name | |
Test status | |
Simulation time | 302241040 ps |
CPU time | 8.44 seconds |
Started | May 21 12:34:25 PM PDT 24 |
Finished | May 21 12:34:51 PM PDT 24 |
Peak memory | 221684 kb |
Host | smart-349e2653-9a2f-41c2-9abe-2ee1f697c2bc |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651537148 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.3651537148 |
Directory | /workspace/8.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3045555868 |
Short name | T198 |
Test name | |
Test status | |
Simulation time | 1960425346 ps |
CPU time | 4.92 seconds |
Started | May 21 12:34:22 PM PDT 24 |
Finished | May 21 12:34:45 PM PDT 24 |
Peak memory | 216356 kb |
Host | smart-3947a27b-087b-4a02-bdb0-a389513d15a1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045555868 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.3045555868 |
Directory | /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.4198322658 |
Short name | T184 |
Test name | |
Test status | |
Simulation time | 105397589 ps |
CPU time | 1.53 seconds |
Started | May 21 12:34:20 PM PDT 24 |
Finished | May 21 12:34:39 PM PDT 24 |
Peak memory | 213292 kb |
Host | smart-bb911150-ba55-42f9-9b9e-a3bb6f57b27d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198322658 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.4198322658 |
Directory | /workspace/9.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.45536851 |
Short name | T207 |
Test name | |
Test status | |
Simulation time | 392914783 ps |
CPU time | 1.48 seconds |
Started | May 21 12:34:18 PM PDT 24 |
Finished | May 21 12:34:38 PM PDT 24 |
Peak memory | 204892 kb |
Host | smart-c03b3840-891a-456a-b4ef-d86e77a9c1b5 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45536851 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.45536851 |
Directory | /workspace/9.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.660767721 |
Short name | T214 |
Test name | |
Test status | |
Simulation time | 164495860 ps |
CPU time | 0.71 seconds |
Started | May 21 12:34:19 PM PDT 24 |
Finished | May 21 12:34:38 PM PDT 24 |
Peak memory | 204780 kb |
Host | smart-c7be9a6d-9663-46d6-a804-aac1a0f3d500 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660767721 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.660767721 |
Directory | /workspace/9.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.902703201 |
Short name | T95 |
Test name | |
Test status | |
Simulation time | 229186177 ps |
CPU time | 3.66 seconds |
Started | May 21 12:34:20 PM PDT 24 |
Finished | May 21 12:34:42 PM PDT 24 |
Peak memory | 205080 kb |
Host | smart-c96de502-1221-4db4-9c92-27f6ce8a2a34 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902703201 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_c sr_outstanding.902703201 |
Directory | /workspace/9.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.45439386 |
Short name | T267 |
Test name | |
Test status | |
Simulation time | 75307224 ps |
CPU time | 2.78 seconds |
Started | May 21 12:34:19 PM PDT 24 |
Finished | May 21 12:34:40 PM PDT 24 |
Peak memory | 213388 kb |
Host | smart-4710451f-2771-40e5-9e4c-0aa17d0fae2f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45439386 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.45439386 |
Directory | /workspace/9.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.3788946121 |
Short name | T68 |
Test name | |
Test status | |
Simulation time | 1908738053 ps |
CPU time | 10.43 seconds |
Started | May 21 12:34:18 PM PDT 24 |
Finished | May 21 12:34:47 PM PDT 24 |
Peak memory | 221484 kb |
Host | smart-7af18c81-32a1-4ef5-82a8-04ce6ecbb80f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788946121 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.3788946121 |
Directory | /workspace/9.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.rv_dm_sec_cm.312443470 |
Short name | T20 |
Test name | |
Test status | |
Simulation time | 602645918 ps |
CPU time | 1.31 seconds |
Started | May 21 12:34:44 PM PDT 24 |
Finished | May 21 12:35:02 PM PDT 24 |
Peak memory | 229384 kb |
Host | smart-a1c1f917-68ad-47f1-98f3-d7c06c28808a |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312443470 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.312443470 |
Directory | /workspace/0.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/1.rv_dm_alert_test.256171014 |
Short name | T16 |
Test name | |
Test status | |
Simulation time | 19636503 ps |
CPU time | 0.7 seconds |
Started | May 21 12:34:58 PM PDT 24 |
Finished | May 21 12:35:19 PM PDT 24 |
Peak memory | 204672 kb |
Host | smart-6c10e03f-3791-4765-b9bd-76be2868a352 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256171014 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.256171014 |
Directory | /workspace/1.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.765849121 |
Short name | T7 |
Test name | |
Test status | |
Simulation time | 55735620 ps |
CPU time | 0.67 seconds |
Started | May 21 12:34:40 PM PDT 24 |
Finished | May 21 12:34:57 PM PDT 24 |
Peak memory | 204468 kb |
Host | smart-1b47fc13-2acf-4957-845d-f24a4f7f9639 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=765849121 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.765849121 |
Directory | /workspace/1.rv_dm_jtag_dtm_idle_hint/latest |
Test location | /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.4243814456 |
Short name | T2 |
Test name | |
Test status | |
Simulation time | 41145641 ps |
CPU time | 0.82 seconds |
Started | May 21 12:34:40 PM PDT 24 |
Finished | May 21 12:34:58 PM PDT 24 |
Peak memory | 204688 kb |
Host | smart-0a07c6ef-90fd-40f7-b812-79519beb924a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4243814456 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.4243814456 |
Directory | /workspace/1.rv_dm_progbuf_read_write_execute/latest |
Test location | /workspace/coverage/default/10.rv_dm_alert_test.1870403852 |
Short name | T59 |
Test name | |
Test status | |
Simulation time | 34273768 ps |
CPU time | 0.68 seconds |
Started | May 21 12:34:58 PM PDT 24 |
Finished | May 21 12:35:20 PM PDT 24 |
Peak memory | 204616 kb |
Host | smart-a62b7b57-08a5-48ef-b8a9-22d983f79c0d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870403852 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.1870403852 |
Directory | /workspace/10.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/11.rv_dm_alert_test.1262464157 |
Short name | T134 |
Test name | |
Test status | |
Simulation time | 42954143 ps |
CPU time | 0.69 seconds |
Started | May 21 12:35:00 PM PDT 24 |
Finished | May 21 12:35:23 PM PDT 24 |
Peak memory | 204632 kb |
Host | smart-811801fe-d7a0-4466-b89c-127d486d8fde |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262464157 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.1262464157 |
Directory | /workspace/11.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/12.rv_dm_alert_test.2074157694 |
Short name | T45 |
Test name | |
Test status | |
Simulation time | 57145965 ps |
CPU time | 0.71 seconds |
Started | May 21 12:34:55 PM PDT 24 |
Finished | May 21 12:35:16 PM PDT 24 |
Peak memory | 204584 kb |
Host | smart-53f650c7-e976-46c2-8a63-d3be5330c708 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074157694 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.2074157694 |
Directory | /workspace/12.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/13.rv_dm_alert_test.1768545438 |
Short name | T146 |
Test name | |
Test status | |
Simulation time | 37413250 ps |
CPU time | 0.73 seconds |
Started | May 21 12:34:52 PM PDT 24 |
Finished | May 21 12:35:13 PM PDT 24 |
Peak memory | 204840 kb |
Host | smart-9e820c40-7849-422f-847f-d6ae061fb8d3 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768545438 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.1768545438 |
Directory | /workspace/13.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/15.rv_dm_alert_test.287050972 |
Short name | T72 |
Test name | |
Test status | |
Simulation time | 46076383 ps |
CPU time | 0.71 seconds |
Started | May 21 12:35:03 PM PDT 24 |
Finished | May 21 12:35:29 PM PDT 24 |
Peak memory | 204688 kb |
Host | smart-30e0a0d4-0ee8-4179-a305-22c3a2342827 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287050972 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.287050972 |
Directory | /workspace/15.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/16.rv_dm_alert_test.1993299933 |
Short name | T151 |
Test name | |
Test status | |
Simulation time | 33675837 ps |
CPU time | 0.74 seconds |
Started | May 21 12:34:52 PM PDT 24 |
Finished | May 21 12:35:12 PM PDT 24 |
Peak memory | 204672 kb |
Host | smart-6a71501b-eb7f-4fff-884e-a593b1eeac31 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993299933 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.1993299933 |
Directory | /workspace/16.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/17.rv_dm_alert_test.4035671170 |
Short name | T57 |
Test name | |
Test status | |
Simulation time | 79542072 ps |
CPU time | 0.69 seconds |
Started | May 21 12:35:02 PM PDT 24 |
Finished | May 21 12:35:27 PM PDT 24 |
Peak memory | 204584 kb |
Host | smart-0bdbb12e-aa14-4750-9f41-0a30acfd8e85 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035671170 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.4035671170 |
Directory | /workspace/17.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/18.rv_dm_alert_test.3278311478 |
Short name | T50 |
Test name | |
Test status | |
Simulation time | 17577520 ps |
CPU time | 0.71 seconds |
Started | May 21 12:35:00 PM PDT 24 |
Finished | May 21 12:35:23 PM PDT 24 |
Peak memory | 204620 kb |
Host | smart-3829fc4d-414f-4c79-9639-8d31dc10e767 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278311478 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.3278311478 |
Directory | /workspace/18.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/19.rv_dm_alert_test.3448808776 |
Short name | T154 |
Test name | |
Test status | |
Simulation time | 41701469 ps |
CPU time | 0.72 seconds |
Started | May 21 12:35:13 PM PDT 24 |
Finished | May 21 12:35:40 PM PDT 24 |
Peak memory | 204640 kb |
Host | smart-4c4bf23d-60a1-4095-a343-0d2a0ed2b146 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448808776 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.3448808776 |
Directory | /workspace/19.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/2.rv_dm_alert_test.1242272352 |
Short name | T79 |
Test name | |
Test status | |
Simulation time | 28827774 ps |
CPU time | 0.73 seconds |
Started | May 21 12:34:54 PM PDT 24 |
Finished | May 21 12:35:15 PM PDT 24 |
Peak memory | 204636 kb |
Host | smart-b08bad46-5927-4365-a1d6-018b1ba64278 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242272352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.1242272352 |
Directory | /workspace/2.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/2.rv_dm_sec_cm.2805063105 |
Short name | T55 |
Test name | |
Test status | |
Simulation time | 129745884 ps |
CPU time | 1.09 seconds |
Started | May 21 12:35:02 PM PDT 24 |
Finished | May 21 12:35:27 PM PDT 24 |
Peak memory | 229356 kb |
Host | smart-92b1221e-44c4-4011-9b3b-cbd46c9f5559 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805063105 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.2805063105 |
Directory | /workspace/2.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/21.rv_dm_alert_test.849743926 |
Short name | T46 |
Test name | |
Test status | |
Simulation time | 31203934 ps |
CPU time | 0.7 seconds |
Started | May 21 12:34:57 PM PDT 24 |
Finished | May 21 12:35:18 PM PDT 24 |
Peak memory | 204688 kb |
Host | smart-a20023f3-27b3-47c6-8d94-97bbbbde0351 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849743926 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.849743926 |
Directory | /workspace/21.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/22.rv_dm_alert_test.2882894945 |
Short name | T12 |
Test name | |
Test status | |
Simulation time | 24122268 ps |
CPU time | 0.72 seconds |
Started | May 21 12:35:12 PM PDT 24 |
Finished | May 21 12:35:39 PM PDT 24 |
Peak memory | 204700 kb |
Host | smart-01937500-7b11-41cc-9d70-707cfe9827b1 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882894945 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.2882894945 |
Directory | /workspace/22.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/23.rv_dm_alert_test.312040401 |
Short name | T52 |
Test name | |
Test status | |
Simulation time | 28372173 ps |
CPU time | 0.74 seconds |
Started | May 21 12:35:02 PM PDT 24 |
Finished | May 21 12:35:26 PM PDT 24 |
Peak memory | 204676 kb |
Host | smart-c9b1f5f4-8613-4cc7-9527-71de8106b9ff |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312040401 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.312040401 |
Directory | /workspace/23.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/24.rv_dm_alert_test.1912561819 |
Short name | T150 |
Test name | |
Test status | |
Simulation time | 23931183 ps |
CPU time | 0.75 seconds |
Started | May 21 12:35:13 PM PDT 24 |
Finished | May 21 12:35:40 PM PDT 24 |
Peak memory | 204684 kb |
Host | smart-90e6e8c0-dc7a-4f10-a166-246d0f2d8d50 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912561819 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.1912561819 |
Directory | /workspace/24.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/25.rv_dm_alert_test.1730139130 |
Short name | T49 |
Test name | |
Test status | |
Simulation time | 18481133 ps |
CPU time | 0.74 seconds |
Started | May 21 12:35:15 PM PDT 24 |
Finished | May 21 12:35:42 PM PDT 24 |
Peak memory | 204584 kb |
Host | smart-7c667425-4348-45b6-8543-592957f4152a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730139130 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.1730139130 |
Directory | /workspace/25.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/25.rv_dm_stress_all.529216086 |
Short name | T6 |
Test name | |
Test status | |
Simulation time | 2772218154 ps |
CPU time | 6.51 seconds |
Started | May 21 12:35:17 PM PDT 24 |
Finished | May 21 12:35:52 PM PDT 24 |
Peak memory | 204840 kb |
Host | smart-036135d5-30d4-4d0c-b120-b81225ed37bf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529216086 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.529216086 |
Directory | /workspace/25.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/26.rv_dm_alert_test.222910412 |
Short name | T60 |
Test name | |
Test status | |
Simulation time | 68691229 ps |
CPU time | 0.71 seconds |
Started | May 21 12:34:58 PM PDT 24 |
Finished | May 21 12:35:20 PM PDT 24 |
Peak memory | 204592 kb |
Host | smart-bad08330-3794-4562-9b07-f409605ebc54 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222910412 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.222910412 |
Directory | /workspace/26.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/28.rv_dm_alert_test.4101864966 |
Short name | T138 |
Test name | |
Test status | |
Simulation time | 46764830 ps |
CPU time | 0.67 seconds |
Started | May 21 12:35:06 PM PDT 24 |
Finished | May 21 12:35:33 PM PDT 24 |
Peak memory | 204604 kb |
Host | smart-e8aaddbd-9076-4002-8c5f-420e59301322 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101864966 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.4101864966 |
Directory | /workspace/28.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/29.rv_dm_alert_test.788276644 |
Short name | T15 |
Test name | |
Test status | |
Simulation time | 31577768 ps |
CPU time | 0.75 seconds |
Started | May 21 12:35:13 PM PDT 24 |
Finished | May 21 12:35:41 PM PDT 24 |
Peak memory | 204764 kb |
Host | smart-2cc80393-a744-42ff-a377-927429a95d57 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788276644 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.788276644 |
Directory | /workspace/29.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/3.rv_dm_alert_test.926705490 |
Short name | T3 |
Test name | |
Test status | |
Simulation time | 17655898 ps |
CPU time | 0.68 seconds |
Started | May 21 12:35:00 PM PDT 24 |
Finished | May 21 12:35:23 PM PDT 24 |
Peak memory | 204584 kb |
Host | smart-049523bb-8bcf-44e1-b373-4510f784e0b6 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926705490 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.926705490 |
Directory | /workspace/3.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/3.rv_dm_sec_cm.1903080330 |
Short name | T19 |
Test name | |
Test status | |
Simulation time | 122230308 ps |
CPU time | 1.21 seconds |
Started | May 21 12:34:54 PM PDT 24 |
Finished | May 21 12:35:15 PM PDT 24 |
Peak memory | 229372 kb |
Host | smart-658df237-7730-4896-ade1-7c947556f09f |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903080330 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.1903080330 |
Directory | /workspace/3.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/30.rv_dm_alert_test.2670176400 |
Short name | T149 |
Test name | |
Test status | |
Simulation time | 121075926 ps |
CPU time | 0.69 seconds |
Started | May 21 12:35:21 PM PDT 24 |
Finished | May 21 12:35:53 PM PDT 24 |
Peak memory | 204584 kb |
Host | smart-646e6256-b8b5-4b99-90ba-f4991e54eede |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670176400 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.2670176400 |
Directory | /workspace/30.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/31.rv_dm_alert_test.1323856376 |
Short name | T152 |
Test name | |
Test status | |
Simulation time | 66262652 ps |
CPU time | 0.71 seconds |
Started | May 21 12:35:31 PM PDT 24 |
Finished | May 21 12:36:02 PM PDT 24 |
Peak memory | 204596 kb |
Host | smart-a9380da8-65c5-40d7-b650-bfc575915c8d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323856376 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.1323856376 |
Directory | /workspace/31.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/32.rv_dm_alert_test.731123580 |
Short name | T137 |
Test name | |
Test status | |
Simulation time | 38028098 ps |
CPU time | 0.74 seconds |
Started | May 21 12:35:11 PM PDT 24 |
Finished | May 21 12:35:38 PM PDT 24 |
Peak memory | 204644 kb |
Host | smart-ee0d9c48-67e7-4e67-b309-7c3ccde3eb2e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731123580 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.731123580 |
Directory | /workspace/32.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/33.rv_dm_alert_test.164833008 |
Short name | T153 |
Test name | |
Test status | |
Simulation time | 16915063 ps |
CPU time | 0.7 seconds |
Started | May 21 12:35:13 PM PDT 24 |
Finished | May 21 12:35:40 PM PDT 24 |
Peak memory | 204532 kb |
Host | smart-2d45dcda-c34c-44b4-953f-ffac6abc61d5 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164833008 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.164833008 |
Directory | /workspace/33.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/34.rv_dm_alert_test.3623640096 |
Short name | T123 |
Test name | |
Test status | |
Simulation time | 16803452 ps |
CPU time | 0.74 seconds |
Started | May 21 12:35:15 PM PDT 24 |
Finished | May 21 12:35:44 PM PDT 24 |
Peak memory | 204672 kb |
Host | smart-d9ebb9ee-19ed-44aa-81ee-2e89e149cb19 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623640096 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.3623640096 |
Directory | /workspace/34.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/35.rv_dm_alert_test.3875997259 |
Short name | T147 |
Test name | |
Test status | |
Simulation time | 67618291 ps |
CPU time | 0.7 seconds |
Started | May 21 12:35:06 PM PDT 24 |
Finished | May 21 12:35:33 PM PDT 24 |
Peak memory | 204656 kb |
Host | smart-aa654d29-05c2-41b2-999d-77428c356ec6 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875997259 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.3875997259 |
Directory | /workspace/35.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/36.rv_dm_alert_test.795623387 |
Short name | T35 |
Test name | |
Test status | |
Simulation time | 93099078 ps |
CPU time | 0.68 seconds |
Started | May 21 12:35:15 PM PDT 24 |
Finished | May 21 12:35:44 PM PDT 24 |
Peak memory | 204576 kb |
Host | smart-3ad54d82-5f7d-4883-9db9-658113148bd3 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795623387 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.795623387 |
Directory | /workspace/36.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/37.rv_dm_alert_test.3860911546 |
Short name | T133 |
Test name | |
Test status | |
Simulation time | 29991258 ps |
CPU time | 0.72 seconds |
Started | May 21 12:35:19 PM PDT 24 |
Finished | May 21 12:35:49 PM PDT 24 |
Peak memory | 204672 kb |
Host | smart-87c57d39-320d-456a-a27d-ee943db3ad63 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860911546 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.3860911546 |
Directory | /workspace/37.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/38.rv_dm_alert_test.230398475 |
Short name | T136 |
Test name | |
Test status | |
Simulation time | 90113916 ps |
CPU time | 0.74 seconds |
Started | May 21 12:35:15 PM PDT 24 |
Finished | May 21 12:35:45 PM PDT 24 |
Peak memory | 204696 kb |
Host | smart-ef135f86-0efe-4b2a-b52b-e1f7c640a458 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230398475 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.230398475 |
Directory | /workspace/38.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/39.rv_dm_alert_test.4260552601 |
Short name | T148 |
Test name | |
Test status | |
Simulation time | 70786199 ps |
CPU time | 0.73 seconds |
Started | May 21 12:35:15 PM PDT 24 |
Finished | May 21 12:35:42 PM PDT 24 |
Peak memory | 204672 kb |
Host | smart-9deeefa3-81e4-4ca0-b28c-84ebc1c6ea64 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260552601 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.4260552601 |
Directory | /workspace/39.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/4.rv_dm_alert_test.80713255 |
Short name | T58 |
Test name | |
Test status | |
Simulation time | 49188928 ps |
CPU time | 0.69 seconds |
Started | May 21 12:34:53 PM PDT 24 |
Finished | May 21 12:35:13 PM PDT 24 |
Peak memory | 204632 kb |
Host | smart-9bb92c9b-daf5-4f11-b215-fd228baeae7d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80713255 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.80713255 |
Directory | /workspace/4.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/4.rv_dm_sec_cm.3786494657 |
Short name | T56 |
Test name | |
Test status | |
Simulation time | 128852368 ps |
CPU time | 1.3 seconds |
Started | May 21 12:35:01 PM PDT 24 |
Finished | May 21 12:35:25 PM PDT 24 |
Peak memory | 229084 kb |
Host | smart-74e30cc5-e4ab-4a2c-a8e1-0d243d6dce1f |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786494657 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.3786494657 |
Directory | /workspace/4.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/40.rv_dm_alert_test.4082976419 |
Short name | T145 |
Test name | |
Test status | |
Simulation time | 51239961 ps |
CPU time | 0.73 seconds |
Started | May 21 12:35:09 PM PDT 24 |
Finished | May 21 12:35:35 PM PDT 24 |
Peak memory | 204616 kb |
Host | smart-928aca7f-fe86-4bca-83f7-16460267b747 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082976419 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.4082976419 |
Directory | /workspace/40.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/41.rv_dm_alert_test.2386538026 |
Short name | T48 |
Test name | |
Test status | |
Simulation time | 103784750 ps |
CPU time | 0.74 seconds |
Started | May 21 12:35:08 PM PDT 24 |
Finished | May 21 12:35:35 PM PDT 24 |
Peak memory | 204692 kb |
Host | smart-d8b5bf76-ab4b-455a-8f38-921b706e93bc |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386538026 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.2386538026 |
Directory | /workspace/41.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/42.rv_dm_alert_test.1112179800 |
Short name | T140 |
Test name | |
Test status | |
Simulation time | 57361706 ps |
CPU time | 0.75 seconds |
Started | May 21 12:35:15 PM PDT 24 |
Finished | May 21 12:35:42 PM PDT 24 |
Peak memory | 204672 kb |
Host | smart-b8d148c3-cf7f-437e-8b47-109cf11a32d3 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112179800 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.1112179800 |
Directory | /workspace/42.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/43.rv_dm_alert_test.567806271 |
Short name | T14 |
Test name | |
Test status | |
Simulation time | 67796818 ps |
CPU time | 0.71 seconds |
Started | May 21 12:35:16 PM PDT 24 |
Finished | May 21 12:35:45 PM PDT 24 |
Peak memory | 204620 kb |
Host | smart-ecd52a7a-fad7-46d5-ba01-78bbb79ca579 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567806271 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.567806271 |
Directory | /workspace/43.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/43.rv_dm_stress_all.3501252236 |
Short name | T5 |
Test name | |
Test status | |
Simulation time | 2726688742 ps |
CPU time | 4.88 seconds |
Started | May 21 12:35:17 PM PDT 24 |
Finished | May 21 12:35:50 PM PDT 24 |
Peak memory | 204936 kb |
Host | smart-f50133ce-8538-4f8b-99a9-5e7a0bb34ded |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501252236 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.3501252236 |
Directory | /workspace/43.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/44.rv_dm_alert_test.934883694 |
Short name | T142 |
Test name | |
Test status | |
Simulation time | 35790376 ps |
CPU time | 0.76 seconds |
Started | May 21 12:35:16 PM PDT 24 |
Finished | May 21 12:35:45 PM PDT 24 |
Peak memory | 204664 kb |
Host | smart-c2b3ce67-f11c-4755-a067-045d1aede386 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934883694 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.934883694 |
Directory | /workspace/44.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/45.rv_dm_alert_test.3405715278 |
Short name | T139 |
Test name | |
Test status | |
Simulation time | 26472725 ps |
CPU time | 0.71 seconds |
Started | May 21 12:35:17 PM PDT 24 |
Finished | May 21 12:35:46 PM PDT 24 |
Peak memory | 204648 kb |
Host | smart-a2d26818-a852-4280-bf71-f192c15d022c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405715278 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.3405715278 |
Directory | /workspace/45.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/46.rv_dm_alert_test.2054871345 |
Short name | T135 |
Test name | |
Test status | |
Simulation time | 27216912 ps |
CPU time | 0.71 seconds |
Started | May 21 12:35:22 PM PDT 24 |
Finished | May 21 12:35:54 PM PDT 24 |
Peak memory | 204556 kb |
Host | smart-a6a5a185-a121-4ffb-a44d-0707c1fbc971 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054871345 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.2054871345 |
Directory | /workspace/46.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/47.rv_dm_alert_test.2823242645 |
Short name | T1 |
Test name | |
Test status | |
Simulation time | 59117191 ps |
CPU time | 0.69 seconds |
Started | May 21 12:35:15 PM PDT 24 |
Finished | May 21 12:35:44 PM PDT 24 |
Peak memory | 204624 kb |
Host | smart-3cf8e6f3-327f-45a3-bae0-37f0b6d81b8d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823242645 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.2823242645 |
Directory | /workspace/47.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/48.rv_dm_alert_test.266273644 |
Short name | T53 |
Test name | |
Test status | |
Simulation time | 103001393 ps |
CPU time | 0.72 seconds |
Started | May 21 12:35:14 PM PDT 24 |
Finished | May 21 12:35:42 PM PDT 24 |
Peak memory | 204644 kb |
Host | smart-3f0c5805-b6bf-45fd-9ba1-9c3bbd548ad4 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266273644 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.266273644 |
Directory | /workspace/48.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/49.rv_dm_alert_test.1088887971 |
Short name | T141 |
Test name | |
Test status | |
Simulation time | 120763728 ps |
CPU time | 0.7 seconds |
Started | May 21 12:35:15 PM PDT 24 |
Finished | May 21 12:35:45 PM PDT 24 |
Peak memory | 204528 kb |
Host | smart-54a5c13b-3665-4800-9d50-39183596dd62 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088887971 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.1088887971 |
Directory | /workspace/49.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/5.rv_dm_alert_test.964070731 |
Short name | T47 |
Test name | |
Test status | |
Simulation time | 18819772 ps |
CPU time | 0.77 seconds |
Started | May 21 12:34:50 PM PDT 24 |
Finished | May 21 12:35:10 PM PDT 24 |
Peak memory | 204676 kb |
Host | smart-8defcd91-0d51-47df-86f2-40ae3e91bcf5 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964070731 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.964070731 |
Directory | /workspace/5.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/6.rv_dm_alert_test.3632364515 |
Short name | T80 |
Test name | |
Test status | |
Simulation time | 54225137 ps |
CPU time | 0.66 seconds |
Started | May 21 12:34:59 PM PDT 24 |
Finished | May 21 12:35:22 PM PDT 24 |
Peak memory | 204652 kb |
Host | smart-79b2df56-655f-4574-941a-e1a13788ac66 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632364515 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.3632364515 |
Directory | /workspace/6.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/7.rv_dm_alert_test.1990065501 |
Short name | T27 |
Test name | |
Test status | |
Simulation time | 22957214 ps |
CPU time | 0.76 seconds |
Started | May 21 12:34:52 PM PDT 24 |
Finished | May 21 12:35:12 PM PDT 24 |
Peak memory | 204616 kb |
Host | smart-68db72de-4c5f-43ab-bb85-edc4afd0c87e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990065501 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.1990065501 |
Directory | /workspace/7.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/8.rv_dm_alert_test.588931771 |
Short name | T144 |
Test name | |
Test status | |
Simulation time | 57049312 ps |
CPU time | 0.72 seconds |
Started | May 21 12:34:50 PM PDT 24 |
Finished | May 21 12:35:10 PM PDT 24 |
Peak memory | 204692 kb |
Host | smart-9e259fe7-f63e-4215-8903-4c3a7769f987 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588931771 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.588931771 |
Directory | /workspace/8.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/9.rv_dm_alert_test.3850852118 |
Short name | T121 |
Test name | |
Test status | |
Simulation time | 22949344 ps |
CPU time | 0.71 seconds |
Started | May 21 12:34:50 PM PDT 24 |
Finished | May 21 12:35:10 PM PDT 24 |
Peak memory | 204604 kb |
Host | smart-2fcf5c12-ff0b-437f-b136-55ecd88d0cfd |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850852118 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.3850852118 |
Directory | /workspace/9.rv_dm_alert_test/latest |
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