Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
75.05	90.63	76.24	86.17	60.26	77.17	98.42	36.48

Total test records in report: 275

tests.html | tests1.html | tests2.html | tests3.html | tests4.html

T255	/workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.336070039	May 26 02:51:28 PM PDT 24	May 26 02:51:58 PM PDT 24	596070820 ps
T256	/workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.3019633379	May 26 02:51:46 PM PDT 24	May 26 02:51:52 PM PDT 24	238205499 ps
T257	/workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1285989308	May 26 02:51:36 PM PDT 24	May 26 02:51:39 PM PDT 24	101042562 ps
T258	/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3824366945	May 26 02:51:20 PM PDT 24	May 26 02:51:23 PM PDT 24	57507557 ps
T87	/workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1549383032	May 26 02:51:38 PM PDT 24	May 26 02:51:47 PM PDT 24	1812454817 ps
T259	/workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.1128542187	May 26 02:51:48 PM PDT 24	May 26 02:51:52 PM PDT 24	76812421 ps
T260	/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.2297142555	May 26 02:51:25 PM PDT 24	May 26 02:51:27 PM PDT 24	230581318 ps
T261	/workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1414785353	May 26 02:51:27 PM PDT 24	May 26 02:51:58 PM PDT 24	754292255 ps
T88	/workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.3531639172	May 26 02:51:28 PM PDT 24	May 26 02:51:37 PM PDT 24	495445090 ps
T262	/workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.4977545	May 26 02:51:15 PM PDT 24	May 26 02:51:18 PM PDT 24	29623528 ps
T89	/workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2369971263	May 26 02:51:35 PM PDT 24	May 26 02:51:40 PM PDT 24	94411770 ps
T263	/workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2477456021	May 26 02:51:38 PM PDT 24	May 26 02:51:42 PM PDT 24	90646392 ps
T264	/workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3297628500	May 26 02:51:47 PM PDT 24	May 26 02:51:51 PM PDT 24	30466538 ps
T265	/workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.1925066912	May 26 02:51:34 PM PDT 24	May 26 02:51:38 PM PDT 24	45002697 ps
T266	/workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.1061911551	May 26 02:51:37 PM PDT 24	May 26 02:51:44 PM PDT 24	1483638914 ps
T267	/workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.3036849421	May 26 02:51:44 PM PDT 24	May 26 02:51:51 PM PDT 24	1167430075 ps
T114	/workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.1771017635	May 26 02:51:35 PM PDT 24	May 26 02:51:57 PM PDT 24	1951139381 ps
T268	/workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.3483355439	May 26 02:51:24 PM PDT 24	May 26 02:52:05 PM PDT 24	40518705987 ps
T269	/workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3387008821	May 26 02:51:44 PM PDT 24	May 26 02:51:50 PM PDT 24	797729636 ps
T270	/workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3294306090	May 26 02:51:47 PM PDT 24	May 26 02:51:52 PM PDT 24	205332405 ps
T271	/workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1588893373	May 26 02:51:46 PM PDT 24	May 26 02:51:51 PM PDT 24	733615340 ps
T272	/workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.264782509	May 26 02:51:28 PM PDT 24	May 26 02:51:33 PM PDT 24	94864363 ps
T273	/workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.3565468220	May 26 02:51:26 PM PDT 24	May 26 02:51:28 PM PDT 24	46553460 ps
T274	/workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3767477887	May 26 02:51:26 PM PDT 24	May 26 02:51:32 PM PDT 24	227038348 ps
T275	/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3750422551	May 26 02:51:22 PM PDT 24	May 26 02:51:24 PM PDT 24	93086607 ps

Test location	/workspace/coverage/default/38.rv_dm_stress_all.918911009
Short name	T8
Test name
Test status
Simulation time	2798807141 ps
CPU time	8.85 seconds
Started	May 26 02:47:34 PM PDT 24
Finished	May 26 02:47:44 PM PDT 24
Peak memory	204928 kb
Host	smart-d58d719d-060c-4c5b-9930-9735bd9e5e93
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918911009 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.918911009
Directory	/workspace/38.rv_dm_stress_all/latest

Test location	/workspace/coverage/default/49.rv_dm_alert_test.3809479048
Short name	T3
Test name
Test status
Simulation time	20034627 ps
CPU time	0.74 seconds
Started	May 26 02:47:40 PM PDT 24
Finished	May 26 02:47:43 PM PDT 24
Peak memory	204688 kb
Host	smart-49e08258-c6cd-4616-a665-8efd8d0b349a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809479048 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.3809479048
Directory	/workspace/49.rv_dm_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/10.rv_dm_tap_fsm_rand_reset.660148446
Short name	T24
Test name
Test status
Simulation time	17313581518 ps
CPU time	51.73 seconds
Started	May 26 02:51:36 PM PDT 24
Finished	May 26 02:52:29 PM PDT 24
Peak memory	221584 kb
Host	smart-3312b3d3-bb97-4f15-904d-7fe912e561e4
User	root
Command	/workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660148446 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 10.rv_dm_tap_fsm_rand_reset.660148446
Directory	/workspace/10.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspace/coverage/default/46.rv_dm_stress_all.73368036
Short name	T6
Test name
Test status
Simulation time	9768830110 ps
CPU time	11.41 seconds
Started	May 26 02:47:33 PM PDT 24
Finished	May 26 02:47:46 PM PDT 24
Peak memory	204984 kb
Host	smart-836b1ca5-fb4a-40c1-8195-ec466d92336f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73368036 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.73368036
Directory	/workspace/46.rv_dm_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2199662658
Short name	T33
Test name
Test status
Simulation time	1748738098 ps
CPU time	5.99 seconds
Started	May 26 02:51:27 PM PDT 24
Finished	May 26 02:51:35 PM PDT 24
Peak memory	205048 kb
Host	smart-1d352346-8e0c-4d44-9560-d116bb5ea4a5
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199662658 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs r_hw_reset.2199662658
Directory	/workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.251159959
Short name	T30
Test name
Test status
Simulation time	1715762791 ps
CPU time	8.24 seconds
Started	May 26 02:51:24 PM PDT 24
Finished	May 26 02:51:33 PM PDT 24
Peak memory	205124 kb
Host	smart-93a1de78-4f39-4cdd-8980-e18e28703fb3
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251159959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_c sr_outstanding.251159959
Directory	/workspace/4.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.2477214125
Short name	T60
Test name
Test status
Simulation time	1602520261 ps
CPU time	20.22 seconds
Started	May 26 02:51:37 PM PDT 24
Finished	May 26 02:52:00 PM PDT 24
Peak memory	221420 kb
Host	smart-140e5c4b-751e-4886-90ff-c9a9b66ed352
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477214125 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.2477214125
Directory	/workspace/8.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.2312516891
Short name	T55
Test name
Test status
Simulation time	1086572927 ps
CPU time	18.3 seconds
Started	May 26 02:51:32 PM PDT 24
Finished	May 26 02:51:52 PM PDT 24
Peak memory	213328 kb
Host	smart-aea3ea72-5aef-4eb8-a5e7-b373320fd78d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312516891 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.2312516891
Directory	/workspace/4.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/default/30.rv_dm_stress_all.3701841038
Short name	T5
Test name
Test status
Simulation time	7492428738 ps
CPU time	14.9 seconds
Started	May 26 02:47:27 PM PDT 24
Finished	May 26 02:47:45 PM PDT 24
Peak memory	204932 kb
Host	smart-10d1927f-ad42-4287-ba1d-fb1294b5e2fb
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701841038 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.3701841038
Directory	/workspace/30.rv_dm_stress_all/latest

Test location	/workspace/coverage/default/4.rv_dm_sec_cm.1494150855
Short name	T20
Test name
Test status
Simulation time	701912124 ps
CPU time	1.07 seconds
Started	May 26 02:46:48 PM PDT 24
Finished	May 26 02:46:50 PM PDT 24
Peak memory	229100 kb
Host	smart-4e3d94eb-2e5d-421a-ade6-5b746c242c76
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494150855 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.1494150855
Directory	/workspace/4.rv_dm_sec_cm/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3931785661
Short name	T85
Test name
Test status
Simulation time	8035433803 ps
CPU time	75.13 seconds
Started	May 26 02:51:18 PM PDT 24
Finished	May 26 02:52:36 PM PDT 24
Peak memory	205112 kb
Host	smart-ce83a945-f591-442c-af9c-4d4e531623a1
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931785661 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 0.rv_dm_csr_aliasing.3931785661
Directory	/workspace/0.rv_dm_csr_aliasing/latest

Test location	/workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.1035392298
Short name	T7
Test name
Test status
Simulation time	76757994 ps
CPU time	0.74 seconds
Started	May 26 02:46:27 PM PDT 24
Finished	May 26 02:46:28 PM PDT 24
Peak memory	204724 kb
Host	smart-34bbbd5a-e13c-4d68-abc8-e54040fbdd74
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1035392298 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.1035392298
Directory	/workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location	/workspace/coverage/default/1.rv_dm_rom_read_access.164281251
Short name	T15
Test name
Test status
Simulation time	31717237 ps
CPU time	0.85 seconds
Started	May 26 02:46:36 PM PDT 24
Finished	May 26 02:46:37 PM PDT 24
Peak memory	212968 kb
Host	smart-6ed1d2de-3048-440b-9711-96cd4a1957cb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=164281251 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.164281251
Directory	/workspace/1.rv_dm_rom_read_access/latest

Test location	/workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.1848258259
Short name	T57
Test name
Test status
Simulation time	5179418054 ps
CPU time	21.12 seconds
Started	May 26 02:51:46 PM PDT 24
Finished	May 26 02:52:10 PM PDT 24
Peak memory	221612 kb
Host	smart-f29ad29b-6328-4e77-a166-b84123cdf191
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848258259 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.1 848258259
Directory	/workspace/19.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.3961906798
Short name	T37
Test name
Test status
Simulation time	40395337862 ps
CPU time	98.86 seconds
Started	May 26 02:51:27 PM PDT 24
Finished	May 26 02:53:08 PM PDT 24
Peak memory	205144 kb
Host	smart-af53b8e0-6fbf-44b1-bef1-65ce1fd66577
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961906798 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_bit_bash.3961906798
Directory	/workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3928120057
Short name	T105
Test name
Test status
Simulation time	1375308274 ps
CPU time	15.93 seconds
Started	May 26 02:51:45 PM PDT 24
Finished	May 26 02:52:04 PM PDT 24
Peak memory	213396 kb
Host	smart-59842759-4cfb-46fd-b469-f27324b4627d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928120057 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.3 928120057
Directory	/workspace/15.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.100640798
Short name	T63
Test name
Test status
Simulation time	340629393 ps
CPU time	8.94 seconds
Started	May 26 02:51:26 PM PDT 24
Finished	May 26 02:51:37 PM PDT 24
Peak memory	221584 kb
Host	smart-025fc71d-8a7b-4a97-87a5-cb34cd657412
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100640798 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.100640798
Directory	/workspace/2.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.3005805621
Short name	T41
Test name
Test status
Simulation time	1566115659 ps
CPU time	2.52 seconds
Started	May 26 02:51:16 PM PDT 24
Finished	May 26 02:51:20 PM PDT 24
Peak memory	205116 kb
Host	smart-fd9f96bf-7a0b-49bc-a2b2-107c34f396b4
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005805621 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs r_hw_reset.3005805621
Directory	/workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location	/workspace/coverage/default/35.rv_dm_alert_test.2401409189
Short name	T32
Test name
Test status
Simulation time	84181147 ps
CPU time	0.7 seconds
Started	May 26 02:47:24 PM PDT 24
Finished	May 26 02:47:27 PM PDT 24
Peak memory	204720 kb
Host	smart-35433d37-b322-4ae0-bac6-aa15775dec3f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401409189 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.2401409189
Directory	/workspace/35.rv_dm_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/11.rv_dm_tap_fsm_rand_reset.2415854842
Short name	T25
Test name
Test status
Simulation time	6369326490 ps
CPU time	12.94 seconds
Started	May 26 02:51:45 PM PDT 24
Finished	May 26 02:52:01 PM PDT 24
Peak memory	220448 kb
Host	smart-c96fe280-dc87-4982-b2f4-211faf6c0657
User	root
Command	/workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415854842 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 11.rv_dm_tap_fsm_rand_reset.2415854842
Directory	/workspace/11.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2839865934
Short name	T54
Test name
Test status
Simulation time	107839354 ps
CPU time	0.76 seconds
Started	May 26 02:51:20 PM PDT 24
Finished	May 26 02:51:23 PM PDT 24
Peak memory	204876 kb
Host	smart-cb3b2c2c-ceed-4955-af57-53da82fe8e32
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839865934 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_hw_reset.2839865934
Directory	/workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3189533624
Short name	T112
Test name
Test status
Simulation time	895916533 ps
CPU time	9.68 seconds
Started	May 26 02:51:44 PM PDT 24
Finished	May 26 02:51:57 PM PDT 24
Peak memory	221504 kb
Host	smart-dc499d2c-78a3-4a3a-9be8-2c2de86994de
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189533624 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.3 189533624
Directory	/workspace/13.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.4133701068
Short name	T183
Test name
Test status
Simulation time	1920414389 ps
CPU time	11.45 seconds
Started	May 26 02:51:38 PM PDT 24
Finished	May 26 02:51:51 PM PDT 24
Peak memory	220744 kb
Host	smart-d449fae9-6f6d-4b02-a01c-443e394891fd
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133701068 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.4133701068
Directory	/workspace/5.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.2882702791
Short name	T61
Test name
Test status
Simulation time	15132706159 ps
CPU time	39.68 seconds
Started	May 26 02:51:18 PM PDT 24
Finished	May 26 02:52:00 PM PDT 24
Peak memory	213380 kb
Host	smart-25b8eb37-3ca6-4a7a-af51-3f95a98ea8e5
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882702791 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.2882702791
Directory	/workspace/0.rv_dm_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1707500776
Short name	T104
Test name
Test status
Simulation time	1939909949 ps
CPU time	30.69 seconds
Started	May 26 02:51:27 PM PDT 24
Finished	May 26 02:52:00 PM PDT 24
Peak memory	205160 kb
Host	smart-98130dfb-c591-4971-9d6f-103f47f0e316
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707500776 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 3.rv_dm_csr_aliasing.1707500776
Directory	/workspace/3.rv_dm_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.1289204829
Short name	T236
Test name
Test status
Simulation time	140666892 ps
CPU time	2.35 seconds
Started	May 26 02:51:39 PM PDT 24
Finished	May 26 02:51:43 PM PDT 24
Peak memory	217524 kb
Host	smart-bc447ef3-6273-4fec-b777-11c319a476b6
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289204829 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.1289204829
Directory	/workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.310247848
Short name	T110
Test name
Test status
Simulation time	1335058235 ps
CPU time	19.53 seconds
Started	May 26 02:51:39 PM PDT 24
Finished	May 26 02:52:00 PM PDT 24
Peak memory	221340 kb
Host	smart-5dfcb474-9374-4543-b666-101f936d0322
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310247848 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.310247848
Directory	/workspace/10.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.620223058
Short name	T113
Test name
Test status
Simulation time	1248639714 ps
CPU time	9.61 seconds
Started	May 26 02:51:45 PM PDT 24
Finished	May 26 02:51:59 PM PDT 24
Peak memory	213296 kb
Host	smart-3545d437-6cea-489b-8c93-2ed66c40ad28
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620223058 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.620223058
Directory	/workspace/12.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.1119272858
Short name	T28
Test name
Test status
Simulation time	174284049 ps
CPU time	2.34 seconds
Started	May 26 02:51:47 PM PDT 24
Finished	May 26 02:51:52 PM PDT 24
Peak memory	215648 kb
Host	smart-d4876b25-4703-48a0-a276-50d4658f4b33
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119272858 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.1119272858
Directory	/workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.1700148253
Short name	T247
Test name
Test status
Simulation time	1990291487 ps
CPU time	10.83 seconds
Started	May 26 02:51:55 PM PDT 24
Finished	May 26 02:52:09 PM PDT 24
Peak memory	221504 kb
Host	smart-4510e98e-be23-4e5d-bed5-b01a89decfa1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700148253 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.1 700148253
Directory	/workspace/18.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/27.rv_dm_tap_fsm_rand_reset.127520368
Short name	T197
Test name
Test status
Simulation time	13475694746 ps
CPU time	15.33 seconds
Started	May 26 02:51:56 PM PDT 24
Finished	May 26 02:52:14 PM PDT 24
Peak memory	219168 kb
Host	smart-a646794b-c2b4-4553-ae16-45be68ec8221
User	root
Command	/workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127520368 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 27.rv_dm_tap_fsm_rand_reset.127520368
Directory	/workspace/27.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.2972629433
Short name	T59
Test name
Test status
Simulation time	106744201 ps
CPU time	2.45 seconds
Started	May 26 02:51:32 PM PDT 24
Finished	May 26 02:51:36 PM PDT 24
Peak memory	218760 kb
Host	smart-40d999f2-7737-4cae-859f-9bdbbc7bd1a9
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972629433 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.2972629433
Directory	/workspace/4.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.255599814
Short name	T195
Test name
Test status
Simulation time	964609933 ps
CPU time	1.73 seconds
Started	May 26 02:51:18 PM PDT 24
Finished	May 26 02:51:22 PM PDT 24
Peak memory	213344 kb
Host	smart-4324976f-546f-4285-a758-f5c21546aa60
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255599814 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.255599814
Directory	/workspace/0.rv_dm_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3595303729
Short name	T241
Test name
Test status
Simulation time	146681843 ps
CPU time	3.78 seconds
Started	May 26 02:51:18 PM PDT 24
Finished	May 26 02:51:24 PM PDT 24
Peak memory	217724 kb
Host	smart-6399ad8f-5d66-4a43-9744-8acf2258d806
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595303729 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.3595303729
Directory	/workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2809597387
Short name	T80
Test name
Test status
Simulation time	54791689 ps
CPU time	1.38 seconds
Started	May 26 02:51:19 PM PDT 24
Finished	May 26 02:51:23 PM PDT 24
Peak memory	218176 kb
Host	smart-393a2c90-067c-4f33-b487-28f98e57b349
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809597387 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.2809597387
Directory	/workspace/0.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.456463672
Short name	T159
Test name
Test status
Simulation time	8261552421 ps
CPU time	31.11 seconds
Started	May 26 02:51:17 PM PDT 24
Finished	May 26 02:51:50 PM PDT 24
Peak memory	205076 kb
Host	smart-30d9008d-d5bb-489b-b7ce-dc08d5579f2d
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456463672 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr _aliasing.456463672
Directory	/workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1090469308
Short name	T220
Test name
Test status
Simulation time	84296376254 ps
CPU time	267.55 seconds
Started	May 26 02:51:17 PM PDT 24
Finished	May 26 02:55:47 PM PDT 24
Peak memory	205040 kb
Host	smart-24e231f8-320c-4d21-aa90-90d3d2bf1261
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090469308 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_bit_bash.1090469308
Directory	/workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2639153680
Short name	T155
Test name
Test status
Simulation time	294609467 ps
CPU time	1.18 seconds
Started	May 26 02:51:20 PM PDT 24
Finished	May 26 02:51:23 PM PDT 24
Peak memory	205008 kb
Host	smart-a90239cf-94e0-475a-9741-c47b0d2aa185
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639153680 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.2 639153680
Directory	/workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2389952261
Short name	T177
Test name
Test status
Simulation time	217487565 ps
CPU time	0.84 seconds
Started	May 26 02:51:17 PM PDT 24
Finished	May 26 02:51:20 PM PDT 24
Peak memory	204840 kb
Host	smart-147d9e71-3a92-4101-8d2a-ceb9baff29ef
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389952261 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_aliasing.2389952261
Directory	/workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.4008341638
Short name	T169
Test name
Test status
Simulation time	914039991 ps
CPU time	2.5 seconds
Started	May 26 02:51:17 PM PDT 24
Finished	May 26 02:51:22 PM PDT 24
Peak memory	205056 kb
Host	smart-85a7a71e-f502-4934-b855-f31920e33440
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008341638 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_bit_bash.4008341638
Directory	/workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3290461113
Short name	T192
Test name
Test status
Simulation time	335276751 ps
CPU time	0.86 seconds
Started	May 26 02:51:17 PM PDT 24
Finished	May 26 02:51:20 PM PDT 24
Peak memory	204856 kb
Host	smart-be131226-fc92-4d1e-b752-bd53c2fbf72e
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290461113 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_hw_reset.3290461113
Directory	/workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3750422551
Short name	T275
Test name
Test status
Simulation time	93086607 ps
CPU time	0.93 seconds
Started	May 26 02:51:22 PM PDT 24
Finished	May 26 02:51:24 PM PDT 24
Peak memory	204776 kb
Host	smart-72bde408-54a5-4394-aa6b-05ef19dc6d7e
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750422551 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.3 750422551
Directory	/workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.4977545
Short name	T262
Test name
Test status
Simulation time	29623528 ps
CPU time	0.65 seconds
Started	May 26 02:51:15 PM PDT 24
Finished	May 26 02:51:18 PM PDT 24
Peak memory	204832 kb
Host	smart-44b5d801-e51f-4c25-86aa-476ce7474f7d
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4977545 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_partia l_access.4977545
Directory	/workspace/0.rv_dm_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.2277979764
Short name	T174
Test name
Test status
Simulation time	24071000 ps
CPU time	0.73 seconds
Started	May 26 02:51:19 PM PDT 24
Finished	May 26 02:51:22 PM PDT 24
Peak memory	204860 kb
Host	smart-abab5adc-56d5-46cd-8dc2-5b941cc42cc9
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277979764 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.2277979764
Directory	/workspace/0.rv_dm_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.677504617
Short name	T99
Test name
Test status
Simulation time	82644824 ps
CPU time	3.59 seconds
Started	May 26 02:51:18 PM PDT 24
Finished	May 26 02:51:24 PM PDT 24
Peak memory	205188 kb
Host	smart-4cf5238d-4c64-413f-8e69-0993bd4d7cd6
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677504617 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_c sr_outstanding.677504617
Directory	/workspace/0.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.2802132981
Short name	T213
Test name
Test status
Simulation time	169797824 ps
CPU time	4.23 seconds
Started	May 26 02:51:20 PM PDT 24
Finished	May 26 02:51:26 PM PDT 24
Peak memory	213440 kb
Host	smart-6e9308b0-49c0-44d5-aed7-40d480ed4eae
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802132981 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.2802132981
Directory	/workspace/0.rv_dm_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.4104315246
Short name	T115
Test name
Test status
Simulation time	2091251554 ps
CPU time	9.95 seconds
Started	May 26 02:51:20 PM PDT 24
Finished	May 26 02:51:32 PM PDT 24
Peak memory	221396 kb
Host	smart-6e81c431-43ea-485b-af9c-6837d94fe81a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104315246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.4104315246
Directory	/workspace/0.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.4268459183
Short name	T200
Test name
Test status
Simulation time	4434179386 ps
CPU time	66.01 seconds
Started	May 26 02:51:21 PM PDT 24
Finished	May 26 02:52:28 PM PDT 24
Peak memory	205208 kb
Host	smart-422f8de1-5b29-450a-944e-36f2740e9349
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268459183 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 1.rv_dm_csr_aliasing.4268459183
Directory	/workspace/1.rv_dm_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.4069006746
Short name	T206
Test name
Test status
Simulation time	3811483964 ps
CPU time	37.95 seconds
Started	May 26 02:51:18 PM PDT 24
Finished	May 26 02:51:59 PM PDT 24
Peak memory	205344 kb
Host	smart-88727c82-5989-4027-b29f-9762c965ddca
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069006746 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.4069006746
Directory	/workspace/1.rv_dm_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.1963419191
Short name	T194
Test name
Test status
Simulation time	937558302 ps
CPU time	1.65 seconds
Started	May 26 02:51:18 PM PDT 24
Finished	May 26 02:51:23 PM PDT 24
Peak memory	213324 kb
Host	smart-d346037e-806d-448d-84ea-c121a305ab51
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963419191 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.1963419191
Directory	/workspace/1.rv_dm_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.1450765951
Short name	T103
Test name
Test status
Simulation time	964036414 ps
CPU time	2.41 seconds
Started	May 26 02:51:22 PM PDT 24
Finished	May 26 02:51:25 PM PDT 24
Peak memory	216128 kb
Host	smart-bac0446c-4573-47e0-bdc2-6d028d6c4d62
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450765951 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.1450765951
Directory	/workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.833129693
Short name	T248
Test name
Test status
Simulation time	93694287 ps
CPU time	1.53 seconds
Started	May 26 02:51:18 PM PDT 24
Finished	May 26 02:51:22 PM PDT 24
Peak memory	221456 kb
Host	smart-1ebf5cc4-0fda-4e22-83dc-ca2013e7f164
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833129693 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.833129693
Directory	/workspace/1.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.574969588
Short name	T157
Test name
Test status
Simulation time	3215430330 ps
CPU time	6.8 seconds
Started	May 26 02:51:20 PM PDT 24
Finished	May 26 02:51:29 PM PDT 24
Peak memory	205060 kb
Host	smart-e64b28c0-f476-4036-a1e0-1977c7cffac1
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574969588 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr _aliasing.574969588
Directory	/workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2768687436
Short name	T165
Test name
Test status
Simulation time	9437459575 ps
CPU time	18.41 seconds
Started	May 26 02:51:20 PM PDT 24
Finished	May 26 02:51:41 PM PDT 24
Peak memory	205024 kb
Host	smart-e16d56d2-f889-46df-bc62-52eeef68cdcf
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768687436 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_bit_bash.2768687436
Directory	/workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2679647661
Short name	T35
Test name
Test status
Simulation time	2074546943 ps
CPU time	4.62 seconds
Started	May 26 02:51:17 PM PDT 24
Finished	May 26 02:51:25 PM PDT 24
Peak memory	205096 kb
Host	smart-127c4c47-62f9-4ff1-a86e-f70b3073391e
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679647661 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs r_hw_reset.2679647661
Directory	/workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1561235557
Short name	T224
Test name
Test status
Simulation time	1012994387 ps
CPU time	1.71 seconds
Started	May 26 02:51:18 PM PDT 24
Finished	May 26 02:51:22 PM PDT 24
Peak memory	205008 kb
Host	smart-8c1fa307-1be1-4a28-bf6f-6f047d766753
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561235557 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.1 561235557
Directory	/workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3824366945
Short name	T258
Test name
Test status
Simulation time	57507557 ps
CPU time	0.92 seconds
Started	May 26 02:51:20 PM PDT 24
Finished	May 26 02:51:23 PM PDT 24
Peak memory	204824 kb
Host	smart-6df4d5b8-02bd-48eb-acda-a5323babb1ad
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824366945 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_aliasing.3824366945
Directory	/workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2639354521
Short name	T254
Test name
Test status
Simulation time	435023003 ps
CPU time	2.26 seconds
Started	May 26 02:51:17 PM PDT 24
Finished	May 26 02:51:22 PM PDT 24
Peak memory	205012 kb
Host	smart-5ab3c898-abd8-4d7b-8e94-7019e6c273a9
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639354521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_bit_bash.2639354521
Directory	/workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.3885208621
Short name	T215
Test name
Test status
Simulation time	54060535 ps
CPU time	0.74 seconds
Started	May 26 02:51:17 PM PDT 24
Finished	May 26 02:51:20 PM PDT 24
Peak memory	204908 kb
Host	smart-c9f220da-164a-4c07-9428-501f75c81f30
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885208621 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_hw_reset.3885208621
Directory	/workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.543406538
Short name	T168
Test name
Test status
Simulation time	63260395 ps
CPU time	0.88 seconds
Started	May 26 02:51:16 PM PDT 24
Finished	May 26 02:51:19 PM PDT 24
Peak memory	204860 kb
Host	smart-388fd88d-bd5c-4f8a-8035-ac7dbbe8fa7e
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543406538 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.543406538
Directory	/workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2673986226
Short name	T171
Test name
Test status
Simulation time	16627961 ps
CPU time	0.7 seconds
Started	May 26 02:51:19 PM PDT 24
Finished	May 26 02:51:22 PM PDT 24
Peak memory	204832 kb
Host	smart-dd85988b-2e70-4c43-b191-3e40dbf53ff1
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673986226 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par tial_access.2673986226
Directory	/workspace/1.rv_dm_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.3647136271
Short name	T58
Test name
Test status
Simulation time	32193199 ps
CPU time	0.68 seconds
Started	May 26 02:51:17 PM PDT 24
Finished	May 26 02:51:20 PM PDT 24
Peak memory	204840 kb
Host	smart-41cafae7-4afb-40f7-9296-aa157a54072d
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647136271 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.3647136271
Directory	/workspace/1.rv_dm_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.1893531007
Short name	T97
Test name
Test status
Simulation time	760970846 ps
CPU time	7.83 seconds
Started	May 26 02:51:18 PM PDT 24
Finished	May 26 02:51:28 PM PDT 24
Peak memory	205136 kb
Host	smart-219f0ea1-f167-4797-b76f-922997520989
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893531007 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_ csr_outstanding.1893531007
Directory	/workspace/1.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1757644348
Short name	T176
Test name
Test status
Simulation time	70069778 ps
CPU time	4.94 seconds
Started	May 26 02:51:17 PM PDT 24
Finished	May 26 02:51:25 PM PDT 24
Peak memory	213468 kb
Host	smart-c8490541-33f1-4135-b6cb-9125c09331c7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757644348 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.1757644348
Directory	/workspace/1.rv_dm_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.2290492635
Short name	T244
Test name
Test status
Simulation time	651842138 ps
CPU time	8.58 seconds
Started	May 26 02:51:21 PM PDT 24
Finished	May 26 02:51:31 PM PDT 24
Peak memory	213260 kb
Host	smart-24d5e4d8-6717-469d-9b1f-fc3e21878937
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290492635 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.2290492635
Directory	/workspace/1.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.1191828298
Short name	T92
Test name
Test status
Simulation time	78186144 ps
CPU time	2.21 seconds
Started	May 26 02:51:37 PM PDT 24
Finished	May 26 02:51:41 PM PDT 24
Peak memory	213332 kb
Host	smart-dacaf64f-62d5-455a-bad9-c3f081729a97
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191828298 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.1191828298
Directory	/workspace/10.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.1336216000
Short name	T26
Test name
Test status
Simulation time	351593466 ps
CPU time	1.03 seconds
Started	May 26 02:51:36 PM PDT 24
Finished	May 26 02:51:39 PM PDT 24
Peak memory	205092 kb
Host	smart-ee135ee1-af46-4eb3-9ea1-c41fea40975c
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336216000 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw. 1336216000
Directory	/workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.4253868669
Short name	T239
Test name
Test status
Simulation time	66441326 ps
CPU time	0.72 seconds
Started	May 26 02:51:38 PM PDT 24
Finished	May 26 02:51:41 PM PDT 24
Peak memory	204836 kb
Host	smart-24ca9d90-4ed8-4d8c-9bce-3ce1476868ea
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253868669 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw. 4253868669
Directory	/workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.4233691638
Short name	T81
Test name
Test status
Simulation time	2298790477 ps
CPU time	4.47 seconds
Started	May 26 02:51:45 PM PDT 24
Finished	May 26 02:51:53 PM PDT 24
Peak memory	205248 kb
Host	smart-896ce5db-70d2-4dac-9b34-73a501eaada1
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233691638 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same _csr_outstanding.4233691638
Directory	/workspace/10.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.798163757
Short name	T175
Test name
Test status
Simulation time	497532622 ps
CPU time	3.86 seconds
Started	May 26 02:51:46 PM PDT 24
Finished	May 26 02:51:53 PM PDT 24
Peak memory	219160 kb
Host	smart-73725de4-57ed-46a3-b544-7f9da39c96df
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798163757 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.798163757
Directory	/workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.468133999
Short name	T76
Test name
Test status
Simulation time	28971086 ps
CPU time	1.42 seconds
Started	May 26 02:51:45 PM PDT 24
Finished	May 26 02:51:50 PM PDT 24
Peak memory	218904 kb
Host	smart-6744a098-72a5-42ef-9ece-f7b89fbc5727
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468133999 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.468133999
Directory	/workspace/11.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.690451870
Short name	T179
Test name
Test status
Simulation time	495839635 ps
CPU time	1.89 seconds
Started	May 26 02:51:45 PM PDT 24
Finished	May 26 02:51:50 PM PDT 24
Peak memory	205088 kb
Host	smart-17090a69-e821-43f6-a01c-879954aaa775
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690451870 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.690451870
Directory	/workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.340175106
Short name	T233
Test name
Test status
Simulation time	46676108 ps
CPU time	0.78 seconds
Started	May 26 02:51:44 PM PDT 24
Finished	May 26 02:51:48 PM PDT 24
Peak memory	204824 kb
Host	smart-d25afd1b-f3a8-467c-9c63-8d870e38acb6
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340175106 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.340175106
Directory	/workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.3284883809
Short name	T218
Test name
Test status
Simulation time	550494371 ps
CPU time	6.52 seconds
Started	May 26 02:51:45 PM PDT 24
Finished	May 26 02:51:55 PM PDT 24
Peak memory	205120 kb
Host	smart-2e46c638-c762-4a52-8637-fb49d25d4368
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284883809 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same _csr_outstanding.3284883809
Directory	/workspace/11.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.1397707182
Short name	T178
Test name
Test status
Simulation time	203567096 ps
CPU time	2.44 seconds
Started	May 26 02:51:47 PM PDT 24
Finished	May 26 02:51:53 PM PDT 24
Peak memory	213468 kb
Host	smart-d290d704-bb97-41df-9d7b-941e64258c87
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397707182 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.1397707182
Directory	/workspace/11.rv_dm_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.2362874773
Short name	T106
Test name
Test status
Simulation time	287921596 ps
CPU time	8.44 seconds
Started	May 26 02:51:46 PM PDT 24
Finished	May 26 02:51:58 PM PDT 24
Peak memory	221484 kb
Host	smart-e924a975-2407-4b67-976b-e4f404f2586e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362874773 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.2 362874773
Directory	/workspace/11.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.2784935478
Short name	T201
Test name
Test status
Simulation time	699828585 ps
CPU time	2.14 seconds
Started	May 26 02:51:43 PM PDT 24
Finished	May 26 02:51:47 PM PDT 24
Peak memory	214656 kb
Host	smart-d917aa80-cbaa-4553-a2c3-839c25e0522a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784935478 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.2784935478
Directory	/workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.4293932158
Short name	T75
Test name
Test status
Simulation time	66326422 ps
CPU time	1.63 seconds
Started	May 26 02:51:46 PM PDT 24
Finished	May 26 02:51:51 PM PDT 24
Peak memory	213316 kb
Host	smart-72729fa3-e24b-4fa1-b297-347d2c64a934
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293932158 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.4293932158
Directory	/workspace/12.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1588893373
Short name	T271
Test name
Test status
Simulation time	733615340 ps
CPU time	1.74 seconds
Started	May 26 02:51:46 PM PDT 24
Finished	May 26 02:51:51 PM PDT 24
Peak memory	205032 kb
Host	smart-cd43a0f2-93f5-48e2-8558-67385f4903f3
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588893373 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw. 1588893373
Directory	/workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.953410884
Short name	T211
Test name
Test status
Simulation time	100201227 ps
CPU time	0.84 seconds
Started	May 26 02:51:46 PM PDT 24
Finished	May 26 02:51:50 PM PDT 24
Peak memory	204876 kb
Host	smart-d6c1d247-e60a-4657-947f-b61d772ccc7b
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953410884 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.953410884
Directory	/workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3387008821
Short name	T269
Test name
Test status
Simulation time	797729636 ps
CPU time	4.22 seconds
Started	May 26 02:51:44 PM PDT 24
Finished	May 26 02:51:50 PM PDT 24
Peak memory	205140 kb
Host	smart-9f89d1ed-79ba-4b12-ae91-bbab2b52dc1a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387008821 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same _csr_outstanding.3387008821
Directory	/workspace/12.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.3307882183
Short name	T225
Test name
Test status
Simulation time	726521159 ps
CPU time	4.5 seconds
Started	May 26 02:51:42 PM PDT 24
Finished	May 26 02:51:47 PM PDT 24
Peak memory	213516 kb
Host	smart-663d3f6c-4e08-4f74-8de9-fad760ec3881
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307882183 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.3307882183
Directory	/workspace/12.rv_dm_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.2066898464
Short name	T191
Test name
Test status
Simulation time	6704896955 ps
CPU time	10.49 seconds
Started	May 26 02:51:47 PM PDT 24
Finished	May 26 02:52:01 PM PDT 24
Peak memory	219436 kb
Host	smart-0cf6446b-404e-4e4d-8b09-00badbd85e3a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066898464 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.2066898464
Directory	/workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.3248828660
Short name	T31
Test name
Test status
Simulation time	228608386 ps
CPU time	2.53 seconds
Started	May 26 02:51:47 PM PDT 24
Finished	May 26 02:51:53 PM PDT 24
Peak memory	218936 kb
Host	smart-6b5d6c1b-758e-47ac-b19e-bd2dd48c4a59
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248828660 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.3248828660
Directory	/workspace/13.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.3036849421
Short name	T267
Test name
Test status
Simulation time	1167430075 ps
CPU time	4.2 seconds
Started	May 26 02:51:44 PM PDT 24
Finished	May 26 02:51:51 PM PDT 24
Peak memory	205004 kb
Host	smart-2390827b-e5cb-480b-8883-1d10d81a2aab
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036849421 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw. 3036849421
Directory	/workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.4143684254
Short name	T167
Test name
Test status
Simulation time	34870979 ps
CPU time	0.69 seconds
Started	May 26 02:51:43 PM PDT 24
Finished	May 26 02:51:46 PM PDT 24
Peak memory	204808 kb
Host	smart-46771c6b-3af8-4262-a37f-93cc0a9fea90
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143684254 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw. 4143684254
Directory	/workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.580522631
Short name	T98
Test name
Test status
Simulation time	796549577 ps
CPU time	7.65 seconds
Started	May 26 02:51:45 PM PDT 24
Finished	May 26 02:51:56 PM PDT 24
Peak memory	205204 kb
Host	smart-2dbc1e41-dc97-4168-ba08-c1789f77c256
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580522631 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same_ csr_outstanding.580522631
Directory	/workspace/13.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.rv_dm_tap_fsm_rand_reset.2472277887
Short name	T203
Test name
Test status
Simulation time	27975860376 ps
CPU time	27.31 seconds
Started	May 26 02:51:46 PM PDT 24
Finished	May 26 02:52:16 PM PDT 24
Peak memory	229840 kb
Host	smart-e309b77b-2ed1-4c43-867e-6544e174e709
User	root
Command	/workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472277887 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 13.rv_dm_tap_fsm_rand_reset.2472277887
Directory	/workspace/13.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.3052185357
Short name	T136
Test name
Test status
Simulation time	111225352 ps
CPU time	2.2 seconds
Started	May 26 02:51:47 PM PDT 24
Finished	May 26 02:51:52 PM PDT 24
Peak memory	213432 kb
Host	smart-d5a67f32-8606-4e88-862a-61ca2127a0bd
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052185357 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.3052185357
Directory	/workspace/13.rv_dm_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.1337356689
Short name	T67
Test name
Test status
Simulation time	4250683398 ps
CPU time	5.2 seconds
Started	May 26 02:51:44 PM PDT 24
Finished	May 26 02:51:52 PM PDT 24
Peak memory	213444 kb
Host	smart-b3e2eb90-3fe5-4a5d-8312-f8e8b1724d3f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337356689 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.1337356689
Directory	/workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.3277902558
Short name	T246
Test name
Test status
Simulation time	35337172 ps
CPU time	1.44 seconds
Started	May 26 02:51:43 PM PDT 24
Finished	May 26 02:51:45 PM PDT 24
Peak memory	218756 kb
Host	smart-898f66e7-2207-4b8b-bf2f-c8448a7f2472
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277902558 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.3277902558
Directory	/workspace/14.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1052968445
Short name	T234
Test name
Test status
Simulation time	419648730 ps
CPU time	2.28 seconds
Started	May 26 02:51:46 PM PDT 24
Finished	May 26 02:51:52 PM PDT 24
Peak memory	205048 kb
Host	smart-df886e0e-d15f-45bc-8972-a8ee8333010d
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052968445 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw. 1052968445
Directory	/workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.925412541
Short name	T158
Test name
Test status
Simulation time	94579707 ps
CPU time	0.93 seconds
Started	May 26 02:51:46 PM PDT 24
Finished	May 26 02:51:51 PM PDT 24
Peak memory	204824 kb
Host	smart-63674316-df50-4578-97d7-2bc238353278
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925412541 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.925412541
Directory	/workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2591454362
Short name	T96
Test name
Test status
Simulation time	684571232 ps
CPU time	8 seconds
Started	May 26 02:51:46 PM PDT 24
Finished	May 26 02:51:57 PM PDT 24
Peak memory	205148 kb
Host	smart-bcdb9dec-8b10-44ca-b655-033b3106755c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591454362 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same _csr_outstanding.2591454362
Directory	/workspace/14.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3967164546
Short name	T62
Test name
Test status
Simulation time	3141601216 ps
CPU time	20.13 seconds
Started	May 26 02:51:48 PM PDT 24
Finished	May 26 02:52:11 PM PDT 24
Peak memory	221524 kb
Host	smart-6aedcdd6-2696-4da0-bfe1-3cfea7d3fe56
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967164546 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.3 967164546
Directory	/workspace/14.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.3975455758
Short name	T70
Test name
Test status
Simulation time	1113229575 ps
CPU time	4.28 seconds
Started	May 26 02:51:44 PM PDT 24
Finished	May 26 02:51:51 PM PDT 24
Peak memory	218068 kb
Host	smart-90253c0e-ba36-4b15-b227-e36920a0ec1b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975455758 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.3975455758
Directory	/workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2256072246
Short name	T91
Test name
Test status
Simulation time	1321898265 ps
CPU time	2.94 seconds
Started	May 26 02:51:44 PM PDT 24
Finished	May 26 02:51:50 PM PDT 24
Peak memory	213344 kb
Host	smart-1b065de0-89c3-401a-ad5b-18e83a8af9ab
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256072246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.2256072246
Directory	/workspace/15.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3087505187
Short name	T243
Test name
Test status
Simulation time	328361155 ps
CPU time	1.14 seconds
Started	May 26 02:51:42 PM PDT 24
Finished	May 26 02:51:43 PM PDT 24
Peak memory	205032 kb
Host	smart-8bfa6f27-a34a-4700-9c39-552f0863fc00
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087505187 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw. 3087505187
Directory	/workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3153835839
Short name	T182
Test name
Test status
Simulation time	50252867 ps
CPU time	0.75 seconds
Started	May 26 02:51:43 PM PDT 24
Finished	May 26 02:51:45 PM PDT 24
Peak memory	204828 kb
Host	smart-3f0f9d53-29dd-48d9-93f0-81248cb16bf0
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153835839 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw. 3153835839
Directory	/workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.3106496231
Short name	T29
Test name
Test status
Simulation time	997780844 ps
CPU time	4.38 seconds
Started	May 26 02:51:46 PM PDT 24
Finished	May 26 02:51:54 PM PDT 24
Peak memory	205148 kb
Host	smart-3d7b3120-0e75-4b63-95e7-cb48489605b3
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106496231 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same _csr_outstanding.3106496231
Directory	/workspace/15.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.479199106
Short name	T74
Test name
Test status
Simulation time	108663952 ps
CPU time	6.42 seconds
Started	May 26 02:51:44 PM PDT 24
Finished	May 26 02:51:53 PM PDT 24
Peak memory	213312 kb
Host	smart-fab0e033-11d3-4e82-9e89-c146dd9f7abe
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479199106 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.479199106
Directory	/workspace/15.rv_dm_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.3972805385
Short name	T170
Test name
Test status
Simulation time	338442086 ps
CPU time	2.35 seconds
Started	May 26 02:51:45 PM PDT 24
Finished	May 26 02:51:50 PM PDT 24
Peak memory	216616 kb
Host	smart-5ea83e75-90b8-4b55-9b9b-853eae096fa8
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972805385 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.3972805385
Directory	/workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.2074094286
Short name	T78
Test name
Test status
Simulation time	266100427 ps
CPU time	1.6 seconds
Started	May 26 02:51:46 PM PDT 24
Finished	May 26 02:51:51 PM PDT 24
Peak memory	218488 kb
Host	smart-17ca5ede-28c9-403d-89d4-878cb31f69d4
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074094286 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.2074094286
Directory	/workspace/16.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.1383394010
Short name	T217
Test name
Test status
Simulation time	1963033420 ps
CPU time	3.83 seconds
Started	May 26 02:51:45 PM PDT 24
Finished	May 26 02:51:52 PM PDT 24
Peak memory	205004 kb
Host	smart-98a27eb6-2277-43c2-a300-6b77ee33c678
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383394010 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw. 1383394010
Directory	/workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3297628500
Short name	T264
Test name
Test status
Simulation time	30466538 ps
CPU time	0.71 seconds
Started	May 26 02:51:47 PM PDT 24
Finished	May 26 02:51:51 PM PDT 24
Peak memory	204844 kb
Host	smart-23526cf6-d480-488f-8765-cabf5c042b7d
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297628500 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw. 3297628500
Directory	/workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.714186348
Short name	T84
Test name
Test status
Simulation time	289358077 ps
CPU time	6.55 seconds
Started	May 26 02:51:47 PM PDT 24
Finished	May 26 02:51:57 PM PDT 24
Peak memory	205172 kb
Host	smart-aeaa54d6-5982-4df1-bf9a-8b97cbf380e6
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714186348 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same_ csr_outstanding.714186348
Directory	/workspace/16.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.2769113501
Short name	T72
Test name
Test status
Simulation time	137135391 ps
CPU time	3.4 seconds
Started	May 26 02:51:44 PM PDT 24
Finished	May 26 02:51:50 PM PDT 24
Peak memory	213384 kb
Host	smart-08d44753-44c6-48b4-921d-adf612224732
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769113501 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.2769113501
Directory	/workspace/16.rv_dm_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.1289993814
Short name	T109
Test name
Test status
Simulation time	3721153540 ps
CPU time	18.58 seconds
Started	May 26 02:51:43 PM PDT 24
Finished	May 26 02:52:04 PM PDT 24
Peak memory	221544 kb
Host	smart-bf6ee647-d3ef-4e8e-8a2e-818dfdc32842
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289993814 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.1 289993814
Directory	/workspace/16.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.1381785919
Short name	T173
Test name
Test status
Simulation time	65126258 ps
CPU time	3.86 seconds
Started	May 26 02:51:45 PM PDT 24
Finished	May 26 02:51:52 PM PDT 24
Peak memory	221316 kb
Host	smart-6b3b809f-627f-450d-b472-eeca9d310640
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381785919 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.1381785919
Directory	/workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.2699130639
Short name	T226
Test name
Test status
Simulation time	117261316 ps
CPU time	1.57 seconds
Started	May 26 02:51:47 PM PDT 24
Finished	May 26 02:51:52 PM PDT 24
Peak memory	213368 kb
Host	smart-204428e5-e411-4033-8692-e46734e7e890
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699130639 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.2699130639
Directory	/workspace/17.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.4284507896
Short name	T38
Test name
Test status
Simulation time	407910860 ps
CPU time	1.57 seconds
Started	May 26 02:51:45 PM PDT 24
Finished	May 26 02:51:50 PM PDT 24
Peak memory	205004 kb
Host	smart-c64ff01c-5c48-442a-9dbe-85f972a8347b
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284507896 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw. 4284507896
Directory	/workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.240838282
Short name	T184
Test name
Test status
Simulation time	46541394 ps
CPU time	0.75 seconds
Started	May 26 02:51:49 PM PDT 24
Finished	May 26 02:51:52 PM PDT 24
Peak memory	204028 kb
Host	smart-746f4da7-13b3-4f3c-ae4c-00397b76f03b
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240838282 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.240838282
Directory	/workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.107218204
Short name	T230
Test name
Test status
Simulation time	275056820 ps
CPU time	6.3 seconds
Started	May 26 02:51:46 PM PDT 24
Finished	May 26 02:51:56 PM PDT 24
Peak memory	205156 kb
Host	smart-2774619a-725e-437d-8b17-abc2ca49721b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107218204 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same_ csr_outstanding.107218204
Directory	/workspace/17.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.1483334034
Short name	T73
Test name
Test status
Simulation time	57678065 ps
CPU time	3.19 seconds
Started	May 26 02:51:55 PM PDT 24
Finished	May 26 02:52:00 PM PDT 24
Peak memory	213400 kb
Host	smart-0932426a-f20e-4250-ad3a-f5f11355ab0a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483334034 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.1483334034
Directory	/workspace/17.rv_dm_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.1970052019
Short name	T204
Test name
Test status
Simulation time	355335728 ps
CPU time	8.75 seconds
Started	May 26 02:51:46 PM PDT 24
Finished	May 26 02:51:58 PM PDT 24
Peak memory	221496 kb
Host	smart-75761245-e538-409c-a234-6e4195a0cff7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970052019 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.1 970052019
Directory	/workspace/17.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.3030366747
Short name	T249
Test name
Test status
Simulation time	2651690162 ps
CPU time	2.68 seconds
Started	May 26 02:51:55 PM PDT 24
Finished	May 26 02:52:05 PM PDT 24
Peak memory	217620 kb
Host	smart-52c29c0e-4f5c-4c57-b050-cb3e9a6af1e2
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030366747 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.3030366747
Directory	/workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.1893343344
Short name	T250
Test name
Test status
Simulation time	302594440 ps
CPU time	2.22 seconds
Started	May 26 02:51:55 PM PDT 24
Finished	May 26 02:51:59 PM PDT 24
Peak memory	221500 kb
Host	smart-0fae0821-f856-420f-896d-5c83d69523f7
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893343344 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.1893343344
Directory	/workspace/18.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1369490399
Short name	T188
Test name
Test status
Simulation time	706596473 ps
CPU time	3.03 seconds
Started	May 26 02:51:46 PM PDT 24
Finished	May 26 02:51:53 PM PDT 24
Peak memory	205036 kb
Host	smart-e90b4ac1-4925-41de-aeff-ee57ca0027b3
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369490399 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw. 1369490399
Directory	/workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.843311374
Short name	T232
Test name
Test status
Simulation time	42717388 ps
CPU time	0.81 seconds
Started	May 26 02:51:47 PM PDT 24
Finished	May 26 02:51:51 PM PDT 24
Peak memory	204836 kb
Host	smart-6e93f5af-f1cc-4c64-a7c7-1b4bb8635c47
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843311374 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.843311374
Directory	/workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.2596019951
Short name	T228
Test name
Test status
Simulation time	2040488034 ps
CPU time	8.12 seconds
Started	May 26 02:51:56 PM PDT 24
Finished	May 26 02:52:07 PM PDT 24
Peak memory	205164 kb
Host	smart-e280e11f-b2ec-4fd4-8cf4-8e24216bc88a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596019951 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same _csr_outstanding.2596019951
Directory	/workspace/18.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.3019633379
Short name	T256
Test name
Test status
Simulation time	238205499 ps
CPU time	2.01 seconds
Started	May 26 02:51:46 PM PDT 24
Finished	May 26 02:51:52 PM PDT 24
Peak memory	213388 kb
Host	smart-46c5f4c2-fdf8-4329-8064-bc65e910c82a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019633379 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.3019633379
Directory	/workspace/18.rv_dm_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1818371275
Short name	T27
Test name
Test status
Simulation time	2877725843 ps
CPU time	3.1 seconds
Started	May 26 02:51:55 PM PDT 24
Finished	May 26 02:52:01 PM PDT 24
Peak memory	214860 kb
Host	smart-f2616227-daa7-4816-be59-6d437f500d7f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818371275 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.1818371275
Directory	/workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3294306090
Short name	T270
Test name
Test status
Simulation time	205332405 ps
CPU time	1.69 seconds
Started	May 26 02:51:47 PM PDT 24
Finished	May 26 02:51:52 PM PDT 24
Peak memory	218392 kb
Host	smart-9080c43a-9714-4d3d-9969-7c4cbaec6627
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294306090 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.3294306090
Directory	/workspace/19.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2058741362
Short name	T153
Test name
Test status
Simulation time	291151269 ps
CPU time	1.54 seconds
Started	May 26 02:51:45 PM PDT 24
Finished	May 26 02:51:50 PM PDT 24
Peak memory	205176 kb
Host	smart-eb35ecbc-5da1-4f24-a199-d9006fc655ba
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058741362 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw. 2058741362
Directory	/workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.1128542187
Short name	T259
Test name
Test status
Simulation time	76812421 ps
CPU time	0.8 seconds
Started	May 26 02:51:48 PM PDT 24
Finished	May 26 02:51:52 PM PDT 24
Peak memory	204760 kb
Host	smart-d6089ce2-bb96-4483-ac56-8b7454b8048a
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128542187 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw. 1128542187
Directory	/workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.60573402
Short name	T79
Test name
Test status
Simulation time	545269744 ps
CPU time	4.25 seconds
Started	May 26 02:51:54 PM PDT 24
Finished	May 26 02:52:01 PM PDT 24
Peak memory	205136 kb
Host	smart-c2a06758-3e35-4871-ba49-23d76574317f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60573402 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same_c sr_outstanding.60573402
Directory	/workspace/19.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3671524955
Short name	T193
Test name
Test status
Simulation time	35951533 ps
CPU time	2.35 seconds
Started	May 26 02:51:48 PM PDT 24
Finished	May 26 02:51:53 PM PDT 24
Peak memory	213320 kb
Host	smart-f187c2bf-fbe8-4ea7-92e9-341748668c4f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671524955 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.3671524955
Directory	/workspace/19.rv_dm_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.3389600902
Short name	T86
Test name
Test status
Simulation time	8425265229 ps
CPU time	79.11 seconds
Started	May 26 02:51:21 PM PDT 24
Finished	May 26 02:52:42 PM PDT 24
Peak memory	218076 kb
Host	smart-2f4545d1-3237-41ff-8732-e6e3c11c7e05
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389600902 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 2.rv_dm_csr_aliasing.3389600902
Directory	/workspace/2.rv_dm_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.3483355439
Short name	T268
Test name
Test status
Simulation time	40518705987 ps
CPU time	39.2 seconds
Started	May 26 02:51:24 PM PDT 24
Finished	May 26 02:52:05 PM PDT 24
Peak memory	205188 kb
Host	smart-cb1aadd3-6089-495d-b6fd-19d439f9dde2
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483355439 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.3483355439
Directory	/workspace/2.rv_dm_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3286759079
Short name	T94
Test name
Test status
Simulation time	447903113 ps
CPU time	1.69 seconds
Started	May 26 02:51:28 PM PDT 24
Finished	May 26 02:51:31 PM PDT 24
Peak memory	213324 kb
Host	smart-0c2ef08e-fc97-44f4-b228-5a0fd0db2350
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286759079 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.3286759079
Directory	/workspace/2.rv_dm_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.4145953911
Short name	T71
Test name
Test status
Simulation time	4614308714 ps
CPU time	12.21 seconds
Started	May 26 02:51:32 PM PDT 24
Finished	May 26 02:51:46 PM PDT 24
Peak memory	221512 kb
Host	smart-b721a14e-2502-46e4-b83d-34b2c4e37e91
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145953911 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.4145953911
Directory	/workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.3314741067
Short name	T90
Test name
Test status
Simulation time	57844641 ps
CPU time	1.57 seconds
Started	May 26 02:51:25 PM PDT 24
Finished	May 26 02:51:29 PM PDT 24
Peak memory	217668 kb
Host	smart-ade09033-c082-4752-a2ab-f99c3bc6f118
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314741067 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.3314741067
Directory	/workspace/2.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2465412837
Short name	T190
Test name
Test status
Simulation time	6036149199 ps
CPU time	10.94 seconds
Started	May 26 02:51:25 PM PDT 24
Finished	May 26 02:51:38 PM PDT 24
Peak memory	205072 kb
Host	smart-be88a152-a24f-4138-864c-fcfd69661ca3
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465412837 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs r_aliasing.2465412837
Directory	/workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2206345168
Short name	T34
Test name
Test status
Simulation time	959265321 ps
CPU time	2.53 seconds
Started	May 26 02:51:32 PM PDT 24
Finished	May 26 02:51:36 PM PDT 24
Peak memory	205116 kb
Host	smart-746e0163-bb32-41fe-bef3-4b9bd5e84d91
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206345168 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs r_hw_reset.2206345168
Directory	/workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.2145222825
Short name	T199
Test name
Test status
Simulation time	462552961 ps
CPU time	2.39 seconds
Started	May 26 02:51:27 PM PDT 24
Finished	May 26 02:51:31 PM PDT 24
Peak memory	205060 kb
Host	smart-f0bbe9d4-047a-4790-bc8c-e6311fe9a55b
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145222825 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.2 145222825
Directory	/workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3394469978
Short name	T152
Test name
Test status
Simulation time	101764556 ps
CPU time	0.72 seconds
Started	May 26 02:51:25 PM PDT 24
Finished	May 26 02:51:28 PM PDT 24
Peak memory	203884 kb
Host	smart-bc7001b4-d771-4af4-aa5d-08cba97b36ab
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394469978 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_aliasing.3394469978
Directory	/workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.2887008336
Short name	T240
Test name
Test status
Simulation time	1764785647 ps
CPU time	3.05 seconds
Started	May 26 02:51:18 PM PDT 24
Finished	May 26 02:51:24 PM PDT 24
Peak memory	205000 kb
Host	smart-d7f04b06-8220-410c-8f52-db6b2d5144c2
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887008336 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_bit_bash.2887008336
Directory	/workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.3722482602
Short name	T242
Test name
Test status
Simulation time	50936185 ps
CPU time	0.75 seconds
Started	May 26 02:51:22 PM PDT 24
Finished	May 26 02:51:24 PM PDT 24
Peak memory	204788 kb
Host	smart-e2ef2257-7beb-4261-9fa2-dd8562cc7409
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722482602 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.3 722482602
Directory	/workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2671362619
Short name	T237
Test name
Test status
Simulation time	21434711 ps
CPU time	0.73 seconds
Started	May 26 02:51:28 PM PDT 24
Finished	May 26 02:51:31 PM PDT 24
Peak memory	204836 kb
Host	smart-d2f82428-e37e-4e64-96b5-65825e7bd9c4
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671362619 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par tial_access.2671362619
Directory	/workspace/2.rv_dm_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.3565468220
Short name	T273
Test name
Test status
Simulation time	46553460 ps
CPU time	0.67 seconds
Started	May 26 02:51:26 PM PDT 24
Finished	May 26 02:51:28 PM PDT 24
Peak memory	204856 kb
Host	smart-5e996f1c-c109-44d5-ad4c-351bb968e5c2
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565468220 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.3565468220
Directory	/workspace/2.rv_dm_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3767477887
Short name	T274
Test name
Test status
Simulation time	227038348 ps
CPU time	4.15 seconds
Started	May 26 02:51:26 PM PDT 24
Finished	May 26 02:51:32 PM PDT 24
Peak memory	205144 kb
Host	smart-26a591af-7cef-4a92-84dc-5405d3dfa7fc
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767477887 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_ csr_outstanding.3767477887
Directory	/workspace/2.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.3880115149
Short name	T68
Test name
Test status
Simulation time	20018801501 ps
CPU time	31.55 seconds
Started	May 26 02:51:28 PM PDT 24
Finished	May 26 02:52:02 PM PDT 24
Peak memory	229900 kb
Host	smart-4e36d200-cb81-4e7f-b054-9bd086b999cb
User	root
Command	/workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880115149 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.3880115149
Directory	/workspace/2.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.3480714930
Short name	T252
Test name
Test status
Simulation time	648507176 ps
CPU time	4.43 seconds
Started	May 26 02:51:25 PM PDT 24
Finished	May 26 02:51:31 PM PDT 24
Peak memory	213392 kb
Host	smart-7ff6bc77-dfcf-4b8c-8ced-667c35d64e70
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480714930 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.3480714930
Directory	/workspace/2.rv_dm_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/22.rv_dm_tap_fsm_rand_reset.2246737427
Short name	T210
Test name
Test status
Simulation time	13845203153 ps
CPU time	28.38 seconds
Started	May 26 02:51:54 PM PDT 24
Finished	May 26 02:52:24 PM PDT 24
Peak memory	221632 kb
Host	smart-c759a93f-b48a-40ba-a65b-890157232fb4
User	root
Command	/workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246737427 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 22.rv_dm_tap_fsm_rand_reset.2246737427
Directory	/workspace/22.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/25.rv_dm_tap_fsm_rand_reset.2769404443
Short name	T101
Test name
Test status
Simulation time	31166028999 ps
CPU time	38.87 seconds
Started	May 26 02:51:55 PM PDT 24
Finished	May 26 02:52:36 PM PDT 24
Peak memory	230064 kb
Host	smart-dc5f8245-ad60-4eb6-b19d-d95a6267adea
User	root
Command	/workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769404443 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 25.rv_dm_tap_fsm_rand_reset.2769404443
Directory	/workspace/25.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/28.rv_dm_tap_fsm_rand_reset.2596378600
Short name	T202
Test name
Test status
Simulation time	10706720486 ps
CPU time	23.85 seconds
Started	May 26 02:51:59 PM PDT 24
Finished	May 26 02:52:25 PM PDT 24
Peak memory	214836 kb
Host	smart-01debbcc-7e26-43a0-b52e-f165b3a6b499
User	root
Command	/workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596378600 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 28.rv_dm_tap_fsm_rand_reset.2596378600
Directory	/workspace/28.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/29.rv_dm_tap_fsm_rand_reset.3382139093
Short name	T102
Test name
Test status
Simulation time	7386475295 ps
CPU time	23.67 seconds
Started	May 26 02:51:52 PM PDT 24
Finished	May 26 02:52:17 PM PDT 24
Peak memory	214640 kb
Host	smart-404ac401-1495-42fa-8ede-3f5a1e995462
User	root
Command	/workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382139093 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 29.rv_dm_tap_fsm_rand_reset.3382139093
Directory	/workspace/29.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1414785353
Short name	T261
Test name
Test status
Simulation time	754292255 ps
CPU time	29.1 seconds
Started	May 26 02:51:27 PM PDT 24
Finished	May 26 02:51:58 PM PDT 24
Peak memory	205044 kb
Host	smart-fac4ca8e-e9a6-4e25-8071-f0d33b5ab354
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414785353 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.1414785353
Directory	/workspace/3.rv_dm_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.205700306
Short name	T56
Test name
Test status
Simulation time	34428254 ps
CPU time	1.6 seconds
Started	May 26 02:51:27 PM PDT 24
Finished	May 26 02:51:31 PM PDT 24
Peak memory	213312 kb
Host	smart-a6dbb5f2-e2e6-4264-b187-ea0b34ec66b1
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205700306 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.205700306
Directory	/workspace/3.rv_dm_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.512097562
Short name	T186
Test name
Test status
Simulation time	3287133881 ps
CPU time	8.84 seconds
Started	May 26 02:51:29 PM PDT 24
Finished	May 26 02:51:39 PM PDT 24
Peak memory	221604 kb
Host	smart-93fa4964-280a-4961-9740-40cd2118e432
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512097562 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.512097562
Directory	/workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.990782094
Short name	T77
Test name
Test status
Simulation time	107055560 ps
CPU time	2.32 seconds
Started	May 26 02:51:26 PM PDT 24
Finished	May 26 02:51:30 PM PDT 24
Peak memory	218760 kb
Host	smart-1f8b3d99-d30d-4e3d-b434-72ba8cddc074
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990782094 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.990782094
Directory	/workspace/3.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1583905128
Short name	T150
Test name
Test status
Simulation time	7055021186 ps
CPU time	29.31 seconds
Started	May 26 02:51:24 PM PDT 24
Finished	May 26 02:51:54 PM PDT 24
Peak memory	205100 kb
Host	smart-c745676c-c535-4f4f-a5fc-d9685a06ebba
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583905128 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs r_aliasing.1583905128
Directory	/workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.3399516211
Short name	T36
Test name
Test status
Simulation time	13098858427 ps
CPU time	54.8 seconds
Started	May 26 02:51:25 PM PDT 24
Finished	May 26 02:52:22 PM PDT 24
Peak memory	205028 kb
Host	smart-fdd206cd-3afc-4b5e-a805-2b89a8f09a4e
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399516211 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_bit_bash.3399516211
Directory	/workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.1377645914
Short name	T40
Test name
Test status
Simulation time	699174165 ps
CPU time	1.52 seconds
Started	May 26 02:51:38 PM PDT 24
Finished	May 26 02:51:41 PM PDT 24
Peak memory	205048 kb
Host	smart-22f08215-dfab-4a9f-b5c3-95c55cadec3c
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377645914 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs r_hw_reset.1377645914
Directory	/workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.704868534
Short name	T216
Test name
Test status
Simulation time	492379184 ps
CPU time	2.84 seconds
Started	May 26 02:51:33 PM PDT 24
Finished	May 26 02:51:37 PM PDT 24
Peak memory	205052 kb
Host	smart-ac9ce332-2f74-48b7-b921-1a6c60b3d21c
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704868534 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.704868534
Directory	/workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3061912839
Short name	T65
Test name
Test status
Simulation time	248941416 ps
CPU time	0.8 seconds
Started	May 26 02:51:25 PM PDT 24
Finished	May 26 02:51:28 PM PDT 24
Peak memory	204820 kb
Host	smart-0a0e5147-29f5-426f-83b4-169c8756c796
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061912839 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_aliasing.3061912839
Directory	/workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.1768202038
Short name	T253
Test name
Test status
Simulation time	1160103184 ps
CPU time	3.09 seconds
Started	May 26 02:51:24 PM PDT 24
Finished	May 26 02:51:28 PM PDT 24
Peak memory	205012 kb
Host	smart-9addf9f5-cd88-4c4d-8dea-42b9cfa5de72
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768202038 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_bit_bash.1768202038
Directory	/workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1156484605
Short name	T64
Test name
Test status
Simulation time	99897142 ps
CPU time	0.95 seconds
Started	May 26 02:51:27 PM PDT 24
Finished	May 26 02:51:30 PM PDT 24
Peak memory	204896 kb
Host	smart-1902544b-408d-4a8f-8468-8943454739d7
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156484605 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_hw_reset.1156484605
Directory	/workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2909122968
Short name	T160
Test name
Test status
Simulation time	53581780 ps
CPU time	0.75 seconds
Started	May 26 02:51:26 PM PDT 24
Finished	May 26 02:51:28 PM PDT 24
Peak memory	204852 kb
Host	smart-a3389aa1-d2c2-4b7d-87a0-ebafb6b6c5f2
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909122968 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.2 909122968
Directory	/workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.181489684
Short name	T161
Test name
Test status
Simulation time	33722517 ps
CPU time	0.69 seconds
Started	May 26 02:51:26 PM PDT 24
Finished	May 26 02:51:28 PM PDT 24
Peak memory	204836 kb
Host	smart-7b9d85fd-754f-458e-bbc1-033df1ca35d4
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181489684 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_part ial_access.181489684
Directory	/workspace/3.rv_dm_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.4043633330
Short name	T156
Test name
Test status
Simulation time	26809066 ps
CPU time	0.71 seconds
Started	May 26 02:51:23 PM PDT 24
Finished	May 26 02:51:25 PM PDT 24
Peak memory	204844 kb
Host	smart-7546ac5c-7e1e-4e1a-816d-43e3989b4e7a
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043633330 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.4043633330
Directory	/workspace/3.rv_dm_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.3531639172
Short name	T88
Test name
Test status
Simulation time	495445090 ps
CPU time	7.66 seconds
Started	May 26 02:51:28 PM PDT 24
Finished	May 26 02:51:37 PM PDT 24
Peak memory	205192 kb
Host	smart-b2ba9b99-8f45-427e-a3aa-57a83a5f52c6
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531639172 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_ csr_outstanding.3531639172
Directory	/workspace/3.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.789550542
Short name	T223
Test name
Test status
Simulation time	50240742 ps
CPU time	1.69 seconds
Started	May 26 02:51:25 PM PDT 24
Finished	May 26 02:51:29 PM PDT 24
Peak memory	213388 kb
Host	smart-e7b2ef43-de71-4201-b7ec-9a47a45b97a5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789550542 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.789550542
Directory	/workspace/3.rv_dm_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2013403711
Short name	T116
Test name
Test status
Simulation time	637292239 ps
CPU time	10.03 seconds
Started	May 26 02:51:29 PM PDT 24
Finished	May 26 02:51:40 PM PDT 24
Peak memory	221500 kb
Host	smart-0a0b7cee-9d9a-4290-975a-f7c3221cc871
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013403711 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.2013403711
Directory	/workspace/3.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/34.rv_dm_tap_fsm_rand_reset.1838274344
Short name	T205
Test name
Test status
Simulation time	20087782585 ps
CPU time	15.38 seconds
Started	May 26 02:51:54 PM PDT 24
Finished	May 26 02:52:12 PM PDT 24
Peak memory	221636 kb
Host	smart-f0344e7a-d572-4c40-ae53-419379793274
User	root
Command	/workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838274344 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 34.rv_dm_tap_fsm_rand_reset.1838274344
Directory	/workspace/34.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.336070039
Short name	T255
Test name
Test status
Simulation time	596070820 ps
CPU time	28.08 seconds
Started	May 26 02:51:28 PM PDT 24
Finished	May 26 02:51:58 PM PDT 24
Peak memory	205116 kb
Host	smart-1c16f525-270d-418b-9443-06c1d8ee0d64
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336070039 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 4.rv_dm_csr_aliasing.336070039
Directory	/workspace/4.rv_dm_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.2661079430
Short name	T95
Test name
Test status
Simulation time	5396673562 ps
CPU time	54.69 seconds
Started	May 26 02:51:30 PM PDT 24
Finished	May 26 02:52:26 PM PDT 24
Peak memory	205136 kb
Host	smart-55936111-2b00-4874-8cfc-293fff2f722b
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661079430 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.2661079430
Directory	/workspace/4.rv_dm_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2416734708
Short name	T93
Test name
Test status
Simulation time	72941373 ps
CPU time	2.33 seconds
Started	May 26 02:51:27 PM PDT 24
Finished	May 26 02:51:31 PM PDT 24
Peak memory	213332 kb
Host	smart-778f1cec-4086-4857-a34a-82f491739354
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416734708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.2416734708
Directory	/workspace/4.rv_dm_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2127674714
Short name	T235
Test name
Test status
Simulation time	1578349894 ps
CPU time	6.35 seconds
Started	May 26 02:51:29 PM PDT 24
Finished	May 26 02:51:37 PM PDT 24
Peak memory	218836 kb
Host	smart-39c64222-0f8e-4dba-8c38-b0cf7fb7dd5a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127674714 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.2127674714
Directory	/workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2202323624
Short name	T238
Test name
Test status
Simulation time	7557765198 ps
CPU time	17.8 seconds
Started	May 26 02:51:37 PM PDT 24
Finished	May 26 02:51:57 PM PDT 24
Peak memory	205100 kb
Host	smart-5f7fc45e-d380-42a1-9ede-0f7947eb11b4
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202323624 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs r_aliasing.2202323624
Directory	/workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.2471590811
Short name	T219
Test name
Test status
Simulation time	26893772588 ps
CPU time	78.63 seconds
Started	May 26 02:51:31 PM PDT 24
Finished	May 26 02:52:51 PM PDT 24
Peak memory	205092 kb
Host	smart-82253a67-c15d-4fd0-b649-142a3e061e05
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471590811 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_bit_bash.2471590811
Directory	/workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.671071064
Short name	T189
Test name
Test status
Simulation time	895431574 ps
CPU time	2.75 seconds
Started	May 26 02:51:25 PM PDT 24
Finished	May 26 02:51:30 PM PDT 24
Peak memory	205032 kb
Host	smart-85c544e2-60ec-4624-a28c-354ff2e7fd5a
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671071064 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.671071064
Directory	/workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.2297142555
Short name	T260
Test name
Test status
Simulation time	230581318 ps
CPU time	0.85 seconds
Started	May 26 02:51:25 PM PDT 24
Finished	May 26 02:51:27 PM PDT 24
Peak memory	204848 kb
Host	smart-f61ff435-87c6-4dfa-b8ff-6d909114ad8a
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297142555 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs r_aliasing.2297142555
Directory	/workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.1619645024
Short name	T151
Test name
Test status
Simulation time	1664966824 ps
CPU time	3.62 seconds
Started	May 26 02:51:28 PM PDT 24
Finished	May 26 02:51:34 PM PDT 24
Peak memory	205004 kb
Host	smart-6e932912-1dd5-4120-91e7-e8dab6cf5914
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619645024 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs r_bit_bash.1619645024
Directory	/workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.3712519482
Short name	T163
Test name
Test status
Simulation time	95958523 ps
CPU time	0.72 seconds
Started	May 26 02:51:29 PM PDT 24
Finished	May 26 02:51:31 PM PDT 24
Peak memory	204876 kb
Host	smart-8dc19683-057d-46c2-967c-b0ed4eaeadad
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712519482 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs r_hw_reset.3712519482
Directory	/workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2839417010
Short name	T187
Test name
Test status
Simulation time	70129513 ps
CPU time	0.88 seconds
Started	May 26 02:51:28 PM PDT 24
Finished	May 26 02:51:31 PM PDT 24
Peak memory	204824 kb
Host	smart-df83ec09-a123-41ba-9ed2-e28099f08f23
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839417010 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.2 839417010
Directory	/workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1944015082
Short name	T162
Test name
Test status
Simulation time	14206075 ps
CPU time	0.68 seconds
Started	May 26 02:51:27 PM PDT 24
Finished	May 26 02:51:30 PM PDT 24
Peak memory	204840 kb
Host	smart-5a96b983-61e4-4d86-b6db-e08b467e9531
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944015082 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par tial_access.1944015082
Directory	/workspace/4.rv_dm_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.1519164805
Short name	T164
Test name
Test status
Simulation time	20852506 ps
CPU time	0.68 seconds
Started	May 26 02:51:32 PM PDT 24
Finished	May 26 02:51:34 PM PDT 24
Peak memory	204836 kb
Host	smart-12b58d27-f54c-4fda-b23c-f7f135235831
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519164805 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.1519164805
Directory	/workspace/4.rv_dm_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.264782509
Short name	T272
Test name
Test status
Simulation time	94864363 ps
CPU time	3.11 seconds
Started	May 26 02:51:28 PM PDT 24
Finished	May 26 02:51:33 PM PDT 24
Peak memory	213388 kb
Host	smart-6ac958d0-92ec-4f6a-8d37-f2eb0123f57f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264782509 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.264782509
Directory	/workspace/4.rv_dm_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.1061911551
Short name	T266
Test name
Test status
Simulation time	1483638914 ps
CPU time	5.04 seconds
Started	May 26 02:51:37 PM PDT 24
Finished	May 26 02:51:44 PM PDT 24
Peak memory	219460 kb
Host	smart-49c16db5-ce59-4d6b-902f-82ff9c512306
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061911551 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.1061911551
Directory	/workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.1925066912
Short name	T265
Test name
Test status
Simulation time	45002697 ps
CPU time	2.3 seconds
Started	May 26 02:51:34 PM PDT 24
Finished	May 26 02:51:38 PM PDT 24
Peak memory	219168 kb
Host	smart-3cbce32f-cd46-44cc-8914-d91f3b6063aa
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925066912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.1925066912
Directory	/workspace/5.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.1541446357
Short name	T154
Test name
Test status
Simulation time	2307052250 ps
CPU time	3.55 seconds
Started	May 26 02:51:34 PM PDT 24
Finished	May 26 02:51:39 PM PDT 24
Peak memory	205068 kb
Host	smart-f7e6b84f-50c9-42f5-b321-9d5dd339f159
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541446357 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.1 541446357
Directory	/workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.1018990421
Short name	T231
Test name
Test status
Simulation time	166280081 ps
CPU time	0.97 seconds
Started	May 26 02:51:29 PM PDT 24
Finished	May 26 02:51:31 PM PDT 24
Peak memory	204852 kb
Host	smart-681d62c8-9797-4162-99c8-e64bed1a2199
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018990421 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.1 018990421
Directory	/workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1549383032
Short name	T87
Test name
Test status
Simulation time	1812454817 ps
CPU time	6.86 seconds
Started	May 26 02:51:38 PM PDT 24
Finished	May 26 02:51:47 PM PDT 24
Peak memory	205112 kb
Host	smart-f0baf706-aa8d-4cb6-80da-9c6291e179c6
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549383032 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_ csr_outstanding.1549383032
Directory	/workspace/5.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.2826459207
Short name	T181
Test name
Test status
Simulation time	75670021 ps
CPU time	2.49 seconds
Started	May 26 02:51:36 PM PDT 24
Finished	May 26 02:51:40 PM PDT 24
Peak memory	213412 kb
Host	smart-3aa4d62f-3ca7-4a94-8464-dc9e3ed0cf85
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826459207 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.2826459207
Directory	/workspace/5.rv_dm_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.2059889013
Short name	T212
Test name
Test status
Simulation time	46804383 ps
CPU time	1.44 seconds
Started	May 26 02:51:39 PM PDT 24
Finished	May 26 02:51:42 PM PDT 24
Peak memory	213344 kb
Host	smart-76ff5775-8131-4408-9a0c-6a6405bc16ec
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059889013 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.2059889013
Directory	/workspace/6.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2385773190
Short name	T39
Test name
Test status
Simulation time	1596870571 ps
CPU time	2.5 seconds
Started	May 26 02:51:35 PM PDT 24
Finished	May 26 02:51:39 PM PDT 24
Peak memory	204972 kb
Host	smart-c6fbe950-4879-4b2f-a225-5bcf7f4c4129
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385773190 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.2 385773190
Directory	/workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.3278093920
Short name	T172
Test name
Test status
Simulation time	97599198 ps
CPU time	0.73 seconds
Started	May 26 02:51:39 PM PDT 24
Finished	May 26 02:51:41 PM PDT 24
Peak memory	204828 kb
Host	smart-5ecdd325-a51e-46fe-a71b-dbb435b7b57b
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278093920 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.3 278093920
Directory	/workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.266994489
Short name	T198
Test name
Test status
Simulation time	1048680565 ps
CPU time	4.14 seconds
Started	May 26 02:51:34 PM PDT 24
Finished	May 26 02:51:40 PM PDT 24
Peak memory	205144 kb
Host	smart-9075af57-2716-4471-88af-74c9bb7d798c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266994489 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_c sr_outstanding.266994489
Directory	/workspace/6.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.1830752274
Short name	T208
Test name
Test status
Simulation time	18052332482 ps
CPU time	32.18 seconds
Started	May 26 02:51:37 PM PDT 24
Finished	May 26 02:52:11 PM PDT 24
Peak memory	217024 kb
Host	smart-aa3fa3c5-50a3-4e01-9927-654adb9a4d04
User	root
Command	/workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830752274 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.1830752274
Directory	/workspace/6.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.4086730836
Short name	T69
Test name
Test status
Simulation time	213701610 ps
CPU time	5.52 seconds
Started	May 26 02:51:36 PM PDT 24
Finished	May 26 02:51:43 PM PDT 24
Peak memory	213428 kb
Host	smart-9361cbd0-46d5-44f4-9d55-3ff8f64eaec2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086730836 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.4086730836
Directory	/workspace/6.rv_dm_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1346907940
Short name	T107
Test name
Test status
Simulation time	1521869135 ps
CPU time	16.37 seconds
Started	May 26 02:51:36 PM PDT 24
Finished	May 26 02:51:55 PM PDT 24
Peak memory	221496 kb
Host	smart-899d5b0e-3657-437d-b6f3-34dc07b254e9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346907940 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.1346907940
Directory	/workspace/6.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2477456021
Short name	T263
Test name
Test status
Simulation time	90646392 ps
CPU time	2.42 seconds
Started	May 26 02:51:38 PM PDT 24
Finished	May 26 02:51:42 PM PDT 24
Peak memory	221472 kb
Host	smart-25344ac1-8acc-49e6-b512-e8e28f819b37
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477456021 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.2477456021
Directory	/workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.1505857399
Short name	T82
Test name
Test status
Simulation time	330896608 ps
CPU time	2.36 seconds
Started	May 26 02:51:35 PM PDT 24
Finished	May 26 02:51:39 PM PDT 24
Peak memory	218768 kb
Host	smart-c6d5c5f4-1fed-4ae5-af88-f49f45fc968d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505857399 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.1505857399
Directory	/workspace/7.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3949290994
Short name	T222
Test name
Test status
Simulation time	1394956501 ps
CPU time	3.75 seconds
Started	May 26 02:51:36 PM PDT 24
Finished	May 26 02:51:42 PM PDT 24
Peak memory	205096 kb
Host	smart-3544a06f-9768-4240-bf28-4a9acf4bc8c6
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949290994 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.3 949290994
Directory	/workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.656383761
Short name	T196
Test name
Test status
Simulation time	100336068 ps
CPU time	0.75 seconds
Started	May 26 02:51:37 PM PDT 24
Finished	May 26 02:51:39 PM PDT 24
Peak memory	204860 kb
Host	smart-8f4fa0c0-5b51-43eb-8515-f7f9470bcddb
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656383761 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.656383761
Directory	/workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.2792649336
Short name	T83
Test name
Test status
Simulation time	302743442 ps
CPU time	6.64 seconds
Started	May 26 02:51:39 PM PDT 24
Finished	May 26 02:51:47 PM PDT 24
Peak memory	205128 kb
Host	smart-7521faa7-0094-4ff3-a2f9-eb2001cf7d3a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792649336 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_ csr_outstanding.2792649336
Directory	/workspace/7.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.4200117551
Short name	T209
Test name
Test status
Simulation time	1361533871 ps
CPU time	3.29 seconds
Started	May 26 02:51:36 PM PDT 24
Finished	May 26 02:51:41 PM PDT 24
Peak memory	213380 kb
Host	smart-c31e3d80-b7eb-4f08-9566-4eadfcf2bda4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200117551 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.4200117551
Directory	/workspace/7.rv_dm_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.366344363
Short name	T111
Test name
Test status
Simulation time	663369831 ps
CPU time	8.83 seconds
Started	May 26 02:51:36 PM PDT 24
Finished	May 26 02:51:47 PM PDT 24
Peak memory	221500 kb
Host	smart-a2ec044d-e461-48f0-b374-23b7da0edc21
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366344363 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.366344363
Directory	/workspace/7.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.2878696068
Short name	T207
Test name
Test status
Simulation time	65507943 ps
CPU time	2.51 seconds
Started	May 26 02:51:35 PM PDT 24
Finished	May 26 02:51:39 PM PDT 24
Peak memory	218900 kb
Host	smart-f0e1a1d6-0068-4f84-aef9-bc31267327cf
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878696068 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.2878696068
Directory	/workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.3051988916
Short name	T251
Test name
Test status
Simulation time	299258919 ps
CPU time	1.58 seconds
Started	May 26 02:51:35 PM PDT 24
Finished	May 26 02:51:39 PM PDT 24
Peak memory	213348 kb
Host	smart-10622949-64dd-48e9-a071-2bdd092d30d2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051988916 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.3051988916
Directory	/workspace/8.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1441542636
Short name	T166
Test name
Test status
Simulation time	925287578 ps
CPU time	1.68 seconds
Started	May 26 02:51:37 PM PDT 24
Finished	May 26 02:51:40 PM PDT 24
Peak memory	205060 kb
Host	smart-04dfb086-a0e6-416e-819c-3bcf31fc3d5a
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441542636 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.1 441542636
Directory	/workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.74546436
Short name	T221
Test name
Test status
Simulation time	70075977 ps
CPU time	0.76 seconds
Started	May 26 02:51:38 PM PDT 24
Finished	May 26 02:51:40 PM PDT 24
Peak memory	204820 kb
Host	smart-3a52e443-54ca-4450-8434-503dea6983da
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74546436 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.74546436
Directory	/workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2369971263
Short name	T89
Test name
Test status
Simulation time	94411770 ps
CPU time	3.68 seconds
Started	May 26 02:51:35 PM PDT 24
Finished	May 26 02:51:40 PM PDT 24
Peak memory	205152 kb
Host	smart-bbd0a2f3-4d53-443d-aa64-6baa991811da
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369971263 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_ csr_outstanding.2369971263
Directory	/workspace/8.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.3857518971
Short name	T214
Test name
Test status
Simulation time	100412963 ps
CPU time	2.01 seconds
Started	May 26 02:51:35 PM PDT 24
Finished	May 26 02:51:39 PM PDT 24
Peak memory	213412 kb
Host	smart-04dc6cbc-25cf-4fee-9cb2-b9842aec89f7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857518971 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.3857518971
Directory	/workspace/8.rv_dm_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.1918588459
Short name	T180
Test name
Test status
Simulation time	2372284495 ps
CPU time	5.64 seconds
Started	May 26 02:51:36 PM PDT 24
Finished	May 26 02:51:44 PM PDT 24
Peak memory	221540 kb
Host	smart-a88beb66-8296-4023-a76f-9256faf7fe7a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918588459 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.1918588459
Directory	/workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1203543253
Short name	T229
Test name
Test status
Simulation time	83449383 ps
CPU time	2.28 seconds
Started	May 26 02:51:37 PM PDT 24
Finished	May 26 02:51:41 PM PDT 24
Peak memory	218284 kb
Host	smart-fd659b78-deaf-4fc9-b1f6-f05b97320744
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203543253 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.1203543253
Directory	/workspace/9.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.2366393497
Short name	T227
Test name
Test status
Simulation time	798465929 ps
CPU time	1.79 seconds
Started	May 26 02:51:34 PM PDT 24
Finished	May 26 02:51:37 PM PDT 24
Peak memory	205080 kb
Host	smart-7ed92c76-3056-4c85-a779-748286a5dd0b
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366393497 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.2 366393497
Directory	/workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1285989308
Short name	T257
Test name
Test status
Simulation time	101042562 ps
CPU time	0.74 seconds
Started	May 26 02:51:36 PM PDT 24
Finished	May 26 02:51:39 PM PDT 24
Peak memory	204844 kb
Host	smart-e475a7c1-b0de-4609-a168-46cc77ae8fe9
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285989308 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.1 285989308
Directory	/workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.4286534460
Short name	T245
Test name
Test status
Simulation time	517307086 ps
CPU time	4.41 seconds
Started	May 26 02:51:36 PM PDT 24
Finished	May 26 02:51:42 PM PDT 24
Peak memory	205200 kb
Host	smart-c93ad9f6-2b7b-441a-8534-b469f62213f8
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286534460 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_ csr_outstanding.4286534460
Directory	/workspace/9.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.313301948
Short name	T23
Test name
Test status
Simulation time	16253075554 ps
CPU time	20.18 seconds
Started	May 26 02:51:39 PM PDT 24
Finished	May 26 02:52:01 PM PDT 24
Peak memory	214892 kb
Host	smart-e5098342-94e3-4b15-bcc1-cb8f1193e427
User	root
Command	/workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313301948 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.313301948
Directory	/workspace/9.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.2928919804
Short name	T185
Test name
Test status
Simulation time	783167813 ps
CPU time	5.78 seconds
Started	May 26 02:51:37 PM PDT 24
Finished	May 26 02:51:45 PM PDT 24
Peak memory	213388 kb
Host	smart-f642c99b-c7ed-40ce-8b1c-487ff917eb1b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928919804 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.2928919804
Directory	/workspace/9.rv_dm_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.1771017635
Short name	T114
Test name
Test status
Simulation time	1951139381 ps
CPU time	20.74 seconds
Started	May 26 02:51:35 PM PDT 24
Finished	May 26 02:51:57 PM PDT 24
Peak memory	221476 kb
Host	smart-39012461-3c57-4835-bf64-35016aeb401b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771017635 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.1771017635
Directory	/workspace/9.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/default/0.rv_dm_alert_test.1110391599
Short name	T121
Test name
Test status
Simulation time	31544374 ps
CPU time	0.74 seconds
Started	May 26 02:46:32 PM PDT 24
Finished	May 26 02:46:34 PM PDT 24
Peak memory	204628 kb
Host	smart-96f7bfa2-c6ba-4f79-83c6-b5c9d4216ac6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110391599 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.1110391599
Directory	/workspace/0.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.3114090689
Short name	T13
Test name
Test status
Simulation time	68437620 ps
CPU time	0.82 seconds
Started	May 26 02:46:26 PM PDT 24
Finished	May 26 02:46:28 PM PDT 24
Peak memory	204560 kb
Host	smart-8ee8e8c9-2802-4c49-b684-326f66653f6c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3114090689 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.3114090689
Directory	/workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location	/workspace/coverage/default/0.rv_dm_rom_read_access.1506975981
Short name	T14
Test name
Test status
Simulation time	35327426 ps
CPU time	0.76 seconds
Started	May 26 02:46:27 PM PDT 24
Finished	May 26 02:46:30 PM PDT 24
Peak memory	212936 kb
Host	smart-fedc6e99-4c31-4c8b-b06b-9bf5287a6d9b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1506975981 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.1506975981
Directory	/workspace/0.rv_dm_rom_read_access/latest

Test location	/workspace/coverage/default/0.rv_dm_sec_cm.1662658524
Short name	T22
Test name
Test status
Simulation time	291967982 ps
CPU time	1.87 seconds
Started	May 26 02:46:33 PM PDT 24
Finished	May 26 02:46:36 PM PDT 24
Peak memory	229088 kb
Host	smart-d0978e96-1018-4dad-a137-ee51939b92ae
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662658524 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.1662658524
Directory	/workspace/0.rv_dm_sec_cm/latest

Test location	/workspace/coverage/default/1.rv_dm_alert_test.3883632042
Short name	T140
Test name
Test status
Simulation time	23471159 ps
CPU time	0.72 seconds
Started	May 26 02:46:38 PM PDT 24
Finished	May 26 02:46:39 PM PDT 24
Peak memory	204696 kb
Host	smart-0610a578-af33-4c8a-8060-1869d40f93e3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883632042 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.3883632042
Directory	/workspace/1.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.2201921445
Short name	T145
Test name
Test status
Simulation time	50327388 ps
CPU time	0.8 seconds
Started	May 26 02:46:33 PM PDT 24
Finished	May 26 02:46:35 PM PDT 24
Peak memory	204608 kb
Host	smart-5b0697c6-a418-458f-b2e7-2b447df91c65
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2201921445 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.2201921445
Directory	/workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location	/workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.4256364607
Short name	T16
Test name
Test status
Simulation time	53893414 ps
CPU time	0.77 seconds
Started	May 26 02:46:34 PM PDT 24
Finished	May 26 02:46:37 PM PDT 24
Peak memory	204748 kb
Host	smart-fc834f57-a2c7-4628-9743-9c0fb2cd4fa3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4256364607 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.4256364607
Directory	/workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location	/workspace/coverage/default/1.rv_dm_sec_cm.2957487529
Short name	T21
Test name
Test status
Simulation time	79281815 ps
CPU time	1.09 seconds
Started	May 26 02:46:33 PM PDT 24
Finished	May 26 02:46:35 PM PDT 24
Peak memory	229212 kb
Host	smart-1cd9c1ac-ceca-4d0d-8ce2-9f9bd5c7739f
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957487529 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.2957487529
Directory	/workspace/1.rv_dm_sec_cm/latest

Test location	/workspace/coverage/default/10.rv_dm_alert_test.95220618
Short name	T128
Test name
Test status
Simulation time	19571780 ps
CPU time	0.76 seconds
Started	May 26 02:47:04 PM PDT 24
Finished	May 26 02:47:05 PM PDT 24
Peak memory	204708 kb
Host	smart-b920b89c-d4b4-42b7-acd5-eea12a0e7011
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95220618 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.95220618
Directory	/workspace/10.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/10.rv_dm_stress_all.1729238093
Short name	T66
Test name
Test status
Simulation time	6637428833 ps
CPU time	4.34 seconds
Started	May 26 02:47:04 PM PDT 24
Finished	May 26 02:47:09 PM PDT 24
Peak memory	204940 kb
Host	smart-ca86af3b-2832-4e79-887b-d6f45643e159
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729238093 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.1729238093
Directory	/workspace/10.rv_dm_stress_all/latest

Test location	/workspace/coverage/default/11.rv_dm_alert_test.3698570976
Short name	T131
Test name
Test status
Simulation time	23378527 ps
CPU time	0.76 seconds
Started	May 26 02:47:08 PM PDT 24
Finished	May 26 02:47:10 PM PDT 24
Peak memory	204688 kb
Host	smart-c37e74c2-3878-4095-8ce1-d36d4edd006f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698570976 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.3698570976
Directory	/workspace/11.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/12.rv_dm_alert_test.3420566958
Short name	T134
Test name
Test status
Simulation time	16236707 ps
CPU time	0.76 seconds
Started	May 26 02:47:05 PM PDT 24
Finished	May 26 02:47:07 PM PDT 24
Peak memory	204720 kb
Host	smart-57e6b305-ad46-42cb-b08f-4acfbe2e5dce
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420566958 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.3420566958
Directory	/workspace/12.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/13.rv_dm_alert_test.1684846743
Short name	T123
Test name
Test status
Simulation time	53829201 ps
CPU time	0.75 seconds
Started	May 26 02:47:05 PM PDT 24
Finished	May 26 02:47:07 PM PDT 24
Peak memory	204700 kb
Host	smart-5a1f726d-06c7-470b-b91e-4c8392accfe3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684846743 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.1684846743
Directory	/workspace/13.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/14.rv_dm_alert_test.1049288138
Short name	T118
Test name
Test status
Simulation time	140672394 ps
CPU time	0.73 seconds
Started	May 26 02:47:06 PM PDT 24
Finished	May 26 02:47:08 PM PDT 24
Peak memory	204696 kb
Host	smart-ca8081fa-dd8b-466c-94db-20875d38f460
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049288138 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.1049288138
Directory	/workspace/14.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/15.rv_dm_alert_test.3819960677
Short name	T146
Test name
Test status
Simulation time	63252272 ps
CPU time	0.71 seconds
Started	May 26 02:47:20 PM PDT 24
Finished	May 26 02:47:22 PM PDT 24
Peak memory	204708 kb
Host	smart-0c47c7c3-cfe9-4fd1-8531-0fa15b867dd3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819960677 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.3819960677
Directory	/workspace/15.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/16.rv_dm_alert_test.4095816779
Short name	T19
Test name
Test status
Simulation time	58355669 ps
CPU time	0.72 seconds
Started	May 26 02:47:15 PM PDT 24
Finished	May 26 02:47:17 PM PDT 24
Peak memory	204688 kb
Host	smart-8b34500d-83b4-4c95-ba10-aec7381747b8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095816779 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.4095816779
Directory	/workspace/16.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/17.rv_dm_alert_test.271227827
Short name	T47
Test name
Test status
Simulation time	27513774 ps
CPU time	0.73 seconds
Started	May 26 02:47:15 PM PDT 24
Finished	May 26 02:47:17 PM PDT 24
Peak memory	204716 kb
Host	smart-1d0fe8ed-4d7d-452c-83b9-826b934e7799
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271227827 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.271227827
Directory	/workspace/17.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/18.rv_dm_alert_test.2097284394
Short name	T42
Test name
Test status
Simulation time	38871195 ps
CPU time	0.73 seconds
Started	May 26 02:47:17 PM PDT 24
Finished	May 26 02:47:19 PM PDT 24
Peak memory	204712 kb
Host	smart-c468a493-5ed1-433b-a2ed-84d0ca2f3e0e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097284394 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.2097284394
Directory	/workspace/18.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/19.rv_dm_alert_test.2692727631
Short name	T122
Test name
Test status
Simulation time	27399373 ps
CPU time	0.71 seconds
Started	May 26 02:47:18 PM PDT 24
Finished	May 26 02:47:21 PM PDT 24
Peak memory	204640 kb
Host	smart-0f31a1fc-41bd-4bcd-8b92-6a30eaea688b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692727631 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.2692727631
Directory	/workspace/19.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/2.rv_dm_alert_test.4204716339
Short name	T127
Test name
Test status
Simulation time	84882688 ps
CPU time	0.75 seconds
Started	May 26 02:46:41 PM PDT 24
Finished	May 26 02:46:43 PM PDT 24
Peak memory	204692 kb
Host	smart-dea9342e-ecf9-4d83-b3fd-b6b3bb1c444c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204716339 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.4204716339
Directory	/workspace/2.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/2.rv_dm_sec_cm.440491270
Short name	T48
Test name
Test status
Simulation time	221345963 ps
CPU time	1.24 seconds
Started	May 26 02:46:42 PM PDT 24
Finished	May 26 02:46:44 PM PDT 24
Peak memory	228832 kb
Host	smart-43758bdf-53ce-4321-86a2-69ad1a1a9fca
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440491270 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.440491270
Directory	/workspace/2.rv_dm_sec_cm/latest

Test location	/workspace/coverage/default/20.rv_dm_alert_test.3605059209
Short name	T43
Test name
Test status
Simulation time	19979645 ps
CPU time	0.75 seconds
Started	May 26 02:47:17 PM PDT 24
Finished	May 26 02:47:19 PM PDT 24
Peak memory	204720 kb
Host	smart-c7584494-ccf0-491e-8515-3a63228086fc
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605059209 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.3605059209
Directory	/workspace/20.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/21.rv_dm_alert_test.2757446238
Short name	T108
Test name
Test status
Simulation time	30330181 ps
CPU time	0.74 seconds
Started	May 26 02:47:16 PM PDT 24
Finished	May 26 02:47:18 PM PDT 24
Peak memory	204712 kb
Host	smart-72d9091b-4b51-4b5a-a891-a784788b6f5a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757446238 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.2757446238
Directory	/workspace/21.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/21.rv_dm_stress_all.843213522
Short name	T9
Test name
Test status
Simulation time	5206301754 ps
CPU time	17.91 seconds
Started	May 26 02:47:19 PM PDT 24
Finished	May 26 02:47:38 PM PDT 24
Peak memory	204936 kb
Host	smart-7c01ceae-4955-464f-9703-46974e16393a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843213522 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.843213522
Directory	/workspace/21.rv_dm_stress_all/latest

Test location	/workspace/coverage/default/22.rv_dm_alert_test.2009251377
Short name	T139
Test name
Test status
Simulation time	53162244 ps
CPU time	0.71 seconds
Started	May 26 02:47:17 PM PDT 24
Finished	May 26 02:47:19 PM PDT 24
Peak memory	204700 kb
Host	smart-ba2eb5a5-12c4-4ad5-ad77-f0a6939f3181
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009251377 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.2009251377
Directory	/workspace/22.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/23.rv_dm_alert_test.1284372010
Short name	T133
Test name
Test status
Simulation time	49940876 ps
CPU time	0.72 seconds
Started	May 26 02:47:25 PM PDT 24
Finished	May 26 02:47:28 PM PDT 24
Peak memory	204728 kb
Host	smart-7204ccff-2798-4a43-8dad-4e6a0b517e20
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284372010 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.1284372010
Directory	/workspace/23.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/24.rv_dm_alert_test.2879750401
Short name	T141
Test name
Test status
Simulation time	28435576 ps
CPU time	0.75 seconds
Started	May 26 02:47:24 PM PDT 24
Finished	May 26 02:47:26 PM PDT 24
Peak memory	204716 kb
Host	smart-3ad84a54-07cc-4931-901a-778ec2748f6b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879750401 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.2879750401
Directory	/workspace/24.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/25.rv_dm_alert_test.2378283471
Short name	T1
Test name
Test status
Simulation time	21626424 ps
CPU time	0.8 seconds
Started	May 26 02:47:24 PM PDT 24
Finished	May 26 02:47:27 PM PDT 24
Peak memory	204692 kb
Host	smart-512cb012-46ff-47d0-907a-ced8a68736ca
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378283471 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.2378283471
Directory	/workspace/25.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/26.rv_dm_alert_test.3086407330
Short name	T51
Test name
Test status
Simulation time	21942435 ps
CPU time	0.7 seconds
Started	May 26 02:47:23 PM PDT 24
Finished	May 26 02:47:25 PM PDT 24
Peak memory	204652 kb
Host	smart-ec91d469-4273-481c-9b81-660cf815ee31
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086407330 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.3086407330
Directory	/workspace/26.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/27.rv_dm_alert_test.4225084504
Short name	T117
Test name
Test status
Simulation time	160240625 ps
CPU time	0.73 seconds
Started	May 26 02:47:25 PM PDT 24
Finished	May 26 02:47:28 PM PDT 24
Peak memory	204720 kb
Host	smart-183e4057-596c-4a54-95b2-d97d4cc28f99
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225084504 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.4225084504
Directory	/workspace/27.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/28.rv_dm_alert_test.2061514167
Short name	T126
Test name
Test status
Simulation time	60975263 ps
CPU time	0.72 seconds
Started	May 26 02:47:23 PM PDT 24
Finished	May 26 02:47:25 PM PDT 24
Peak memory	204716 kb
Host	smart-89f5899f-fe80-46e1-9257-4d014898a3ea
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061514167 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.2061514167
Directory	/workspace/28.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/29.rv_dm_alert_test.3056863713
Short name	T142
Test name
Test status
Simulation time	98426765 ps
CPU time	0.71 seconds
Started	May 26 02:47:23 PM PDT 24
Finished	May 26 02:47:25 PM PDT 24
Peak memory	204696 kb
Host	smart-b80170a1-1577-47a5-bf70-715e5ae0885b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056863713 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.3056863713
Directory	/workspace/29.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/3.rv_dm_alert_test.2581685827
Short name	T44
Test name
Test status
Simulation time	55521748 ps
CPU time	0.71 seconds
Started	May 26 02:46:43 PM PDT 24
Finished	May 26 02:46:45 PM PDT 24
Peak memory	204676 kb
Host	smart-868491f0-796a-4537-b050-dbbe5e2043a2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581685827 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.2581685827
Directory	/workspace/3.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/3.rv_dm_sec_cm.438725291
Short name	T49
Test name
Test status
Simulation time	590941711 ps
CPU time	1.36 seconds
Started	May 26 02:46:42 PM PDT 24
Finished	May 26 02:46:45 PM PDT 24
Peak memory	229080 kb
Host	smart-29b52ef8-7f8b-4e9f-891c-148735c3d8cc
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438725291 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.438725291
Directory	/workspace/3.rv_dm_sec_cm/latest

Test location	/workspace/coverage/default/3.rv_dm_stress_all.1675069575
Short name	T17
Test name
Test status
Simulation time	3734427890 ps
CPU time	3.42 seconds
Started	May 26 02:46:41 PM PDT 24
Finished	May 26 02:46:46 PM PDT 24
Peak memory	213240 kb
Host	smart-f87155b4-90d8-4120-a190-49f0ef84af9d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675069575 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.1675069575
Directory	/workspace/3.rv_dm_stress_all/latest

Test location	/workspace/coverage/default/30.rv_dm_alert_test.579881906
Short name	T130
Test name
Test status
Simulation time	39659606 ps
CPU time	0.7 seconds
Started	May 26 02:47:26 PM PDT 24
Finished	May 26 02:47:30 PM PDT 24
Peak memory	204684 kb
Host	smart-50f00d1c-9044-4e3a-9403-2300faaf1f50
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579881906 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.579881906
Directory	/workspace/30.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/31.rv_dm_alert_test.2348263556
Short name	T137
Test name
Test status
Simulation time	27280336 ps
CPU time	0.7 seconds
Started	May 26 02:47:26 PM PDT 24
Finished	May 26 02:47:30 PM PDT 24
Peak memory	204700 kb
Host	smart-311139b5-9c22-4443-95d2-f2dd4325c560
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348263556 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.2348263556
Directory	/workspace/31.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/32.rv_dm_alert_test.2112724715
Short name	T149
Test name
Test status
Simulation time	29015110 ps
CPU time	0.73 seconds
Started	May 26 02:47:23 PM PDT 24
Finished	May 26 02:47:24 PM PDT 24
Peak memory	204712 kb
Host	smart-48fbf0c6-19f9-4aec-8b11-2902873a8c8a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112724715 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.2112724715
Directory	/workspace/32.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/32.rv_dm_stress_all.1072234152
Short name	T11
Test name
Test status
Simulation time	1589383842 ps
CPU time	2.27 seconds
Started	May 26 02:47:27 PM PDT 24
Finished	May 26 02:47:32 PM PDT 24
Peak memory	204904 kb
Host	smart-1b8f26a3-def3-4a04-acf0-cc0f5b4b0293
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072234152 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.1072234152
Directory	/workspace/32.rv_dm_stress_all/latest

Test location	/workspace/coverage/default/33.rv_dm_alert_test.2489518073
Short name	T143
Test name
Test status
Simulation time	21009309 ps
CPU time	0.72 seconds
Started	May 26 02:47:26 PM PDT 24
Finished	May 26 02:47:30 PM PDT 24
Peak memory	204688 kb
Host	smart-d850bd32-e109-47fe-a3bc-14afefab34f1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489518073 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.2489518073
Directory	/workspace/33.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/34.rv_dm_alert_test.1495766012
Short name	T2
Test name
Test status
Simulation time	21435129 ps
CPU time	0.73 seconds
Started	May 26 02:47:26 PM PDT 24
Finished	May 26 02:47:31 PM PDT 24
Peak memory	204696 kb
Host	smart-51e47e6d-a618-42bd-9754-13d1c430c703
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495766012 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.1495766012
Directory	/workspace/34.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/35.rv_dm_stress_all.1929399839
Short name	T12
Test name
Test status
Simulation time	19610767597 ps
CPU time	5.38 seconds
Started	May 26 02:47:25 PM PDT 24
Finished	May 26 02:47:34 PM PDT 24
Peak memory	204996 kb
Host	smart-35edf63e-d912-4830-ad4e-a99e78c72bfe
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929399839 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.1929399839
Directory	/workspace/35.rv_dm_stress_all/latest

Test location	/workspace/coverage/default/36.rv_dm_alert_test.1686845426
Short name	T125
Test name
Test status
Simulation time	25060853 ps
CPU time	0.73 seconds
Started	May 26 02:47:24 PM PDT 24
Finished	May 26 02:47:26 PM PDT 24
Peak memory	204700 kb
Host	smart-7dc6f93a-6655-4c58-a28f-ba3cd842482a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686845426 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.1686845426
Directory	/workspace/36.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/37.rv_dm_alert_test.1904992342
Short name	T45
Test name
Test status
Simulation time	20863904 ps
CPU time	0.73 seconds
Started	May 26 02:47:32 PM PDT 24
Finished	May 26 02:47:34 PM PDT 24
Peak memory	204632 kb
Host	smart-d8a79592-6fd5-4f5b-9143-42f3076ff627
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904992342 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.1904992342
Directory	/workspace/37.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/38.rv_dm_alert_test.1868663129
Short name	T50
Test name
Test status
Simulation time	25313003 ps
CPU time	0.75 seconds
Started	May 26 02:47:33 PM PDT 24
Finished	May 26 02:47:36 PM PDT 24
Peak memory	204692 kb
Host	smart-4119e554-55ef-4963-a598-30e564f2a16f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868663129 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.1868663129
Directory	/workspace/38.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/39.rv_dm_alert_test.319580266
Short name	T124
Test name
Test status
Simulation time	94578284 ps
CPU time	0.73 seconds
Started	May 26 02:47:33 PM PDT 24
Finished	May 26 02:47:35 PM PDT 24
Peak memory	204696 kb
Host	smart-20ae5fc7-d7df-42dd-a25b-99891a38b4fd
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319580266 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.319580266
Directory	/workspace/39.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/4.rv_dm_alert_test.1596498797
Short name	T120
Test name
Test status
Simulation time	136048187 ps
CPU time	0.71 seconds
Started	May 26 02:46:50 PM PDT 24
Finished	May 26 02:46:52 PM PDT 24
Peak memory	204716 kb
Host	smart-e5bc85bc-1c9f-4c61-ba8c-618fc917e509
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596498797 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.1596498797
Directory	/workspace/4.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/40.rv_dm_alert_test.1898995414
Short name	T52
Test name
Test status
Simulation time	33826085 ps
CPU time	0.71 seconds
Started	May 26 02:47:33 PM PDT 24
Finished	May 26 02:47:36 PM PDT 24
Peak memory	204632 kb
Host	smart-5d9b1add-4306-4947-9988-0a377efec4ce
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898995414 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.1898995414
Directory	/workspace/40.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/41.rv_dm_alert_test.3238657188
Short name	T4
Test name
Test status
Simulation time	25719455 ps
CPU time	0.72 seconds
Started	May 26 02:47:31 PM PDT 24
Finished	May 26 02:47:34 PM PDT 24
Peak memory	204720 kb
Host	smart-2117332d-fb33-41f3-af26-6537520e21fd
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238657188 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.3238657188
Directory	/workspace/41.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/41.rv_dm_stress_all.1889410357
Short name	T10
Test name
Test status
Simulation time	1558654255 ps
CPU time	6.55 seconds
Started	May 26 02:47:32 PM PDT 24
Finished	May 26 02:47:40 PM PDT 24
Peak memory	204820 kb
Host	smart-31a46714-250e-4fab-b30f-aa0101d424d8
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889410357 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.1889410357
Directory	/workspace/41.rv_dm_stress_all/latest

Test location	/workspace/coverage/default/42.rv_dm_alert_test.1959879834
Short name	T147
Test name
Test status
Simulation time	58601291 ps
CPU time	0.75 seconds
Started	May 26 02:47:32 PM PDT 24
Finished	May 26 02:47:35 PM PDT 24
Peak memory	204624 kb
Host	smart-bd9cb78f-889f-4fab-be91-da1535056487
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959879834 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.1959879834
Directory	/workspace/42.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/43.rv_dm_alert_test.272363176
Short name	T144
Test name
Test status
Simulation time	47205846 ps
CPU time	0.74 seconds
Started	May 26 02:47:32 PM PDT 24
Finished	May 26 02:47:34 PM PDT 24
Peak memory	204628 kb
Host	smart-d2f0d7ab-8281-4ecc-a216-c28617bce21a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272363176 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.272363176
Directory	/workspace/43.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/44.rv_dm_alert_test.4028766036
Short name	T132
Test name
Test status
Simulation time	22866966 ps
CPU time	0.74 seconds
Started	May 26 02:47:34 PM PDT 24
Finished	May 26 02:47:36 PM PDT 24
Peak memory	204704 kb
Host	smart-ee8fac03-f01a-48e3-acb5-535765480ae7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028766036 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.4028766036
Directory	/workspace/44.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/45.rv_dm_alert_test.300877528
Short name	T148
Test name
Test status
Simulation time	21619607 ps
CPU time	0.72 seconds
Started	May 26 02:47:33 PM PDT 24
Finished	May 26 02:47:35 PM PDT 24
Peak memory	204816 kb
Host	smart-2652da89-6a4c-4280-a995-5846c5267fe8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300877528 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.300877528
Directory	/workspace/45.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/46.rv_dm_alert_test.916586878
Short name	T135
Test name
Test status
Simulation time	27744626 ps
CPU time	0.75 seconds
Started	May 26 02:47:33 PM PDT 24
Finished	May 26 02:47:36 PM PDT 24
Peak memory	204688 kb
Host	smart-b6b257d8-7c0a-4dee-9d69-86fb5cb927b1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916586878 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.916586878
Directory	/workspace/46.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/47.rv_dm_alert_test.1051836860
Short name	T53
Test name
Test status
Simulation time	35162387 ps
CPU time	0.73 seconds
Started	May 26 02:47:39 PM PDT 24
Finished	May 26 02:47:41 PM PDT 24
Peak memory	204636 kb
Host	smart-be38866f-5791-49e5-8d66-c8a94bbe4d2b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051836860 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.1051836860
Directory	/workspace/47.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/48.rv_dm_alert_test.2900491546
Short name	T46
Test name
Test status
Simulation time	58780763 ps
CPU time	0.7 seconds
Started	May 26 02:47:41 PM PDT 24
Finished	May 26 02:47:44 PM PDT 24
Peak memory	204716 kb
Host	smart-f31eb439-cddb-4af8-b282-c58bd1229fa7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900491546 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.2900491546
Directory	/workspace/48.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/5.rv_dm_alert_test.1851430275
Short name	T18
Test name
Test status
Simulation time	42596801 ps
CPU time	0.75 seconds
Started	May 26 02:46:51 PM PDT 24
Finished	May 26 02:46:52 PM PDT 24
Peak memory	204824 kb
Host	smart-75452dfb-2dc2-4885-a89b-16d41fa8c65f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851430275 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.1851430275
Directory	/workspace/5.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/6.rv_dm_alert_test.4025135015
Short name	T100
Test name
Test status
Simulation time	57564027 ps
CPU time	0.69 seconds
Started	May 26 02:46:56 PM PDT 24
Finished	May 26 02:46:57 PM PDT 24
Peak memory	204688 kb
Host	smart-e6f15e6a-2f75-4496-95e5-06ffe5f143b9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025135015 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.4025135015
Directory	/workspace/6.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/7.rv_dm_alert_test.3000356675
Short name	T119
Test name
Test status
Simulation time	17268033 ps
CPU time	0.74 seconds
Started	May 26 02:46:56 PM PDT 24
Finished	May 26 02:46:58 PM PDT 24
Peak memory	204716 kb
Host	smart-2a17f3bf-8440-4697-81fb-70ea84b2a0e0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000356675 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.3000356675
Directory	/workspace/7.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/8.rv_dm_alert_test.709686985
Short name	T138
Test name
Test status
Simulation time	126646712 ps
CPU time	0.71 seconds
Started	May 26 02:46:58 PM PDT 24
Finished	May 26 02:47:00 PM PDT 24
Peak memory	204696 kb
Host	smart-cce10c61-b106-4cb8-a2e8-7cce2ba5f0c0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709686985 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.709686985
Directory	/workspace/8.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/9.rv_dm_alert_test.1616945058
Short name	T129
Test name
Test status
Simulation time	93269832 ps
CPU time	0.73 seconds
Started	May 26 02:46:59 PM PDT 24
Finished	May 26 02:47:00 PM PDT 24
Peak memory	204688 kb
Host	smart-b34ff228-4497-4ac0-bf0f-1763ceae903e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616945058 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.1616945058
Directory	/workspace/9.rv_dm_alert_test/latest