Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
75.05 90.63 76.24 86.17 60.26 77.17 98.42 36.48


Total tests in report: 275
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
54.63 54.63 82.28 82.28 52.06 52.06 44.16 44.16 44.87 44.87 64.00 64.00 91.87 91.87 3.18 3.18 /workspace/coverage/default/38.rv_dm_stress_all.918911009
61.21 6.57 86.46 4.18 62.50 10.44 70.26 26.10 44.87 0.00 66.33 2.33 93.24 1.37 4.77 1.59 /workspace/coverage/default/49.rv_dm_alert_test.3809479048
67.23 6.02 86.91 0.45 66.76 4.26 73.50 3.24 50.00 5.13 67.67 1.33 94.30 1.06 31.45 26.68 /workspace/coverage/cover_reg_top/10.rv_dm_tap_fsm_rand_reset.660148446
70.67 3.44 90.13 3.22 71.15 4.40 74.14 0.64 58.97 8.97 74.00 6.33 94.40 0.11 31.89 0.44 /workspace/coverage/default/46.rv_dm_stress_all.73368036
71.82 1.15 90.13 0.00 71.70 0.55 79.26 5.12 58.97 0.00 74.17 0.17 96.09 1.69 32.42 0.53 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2199662658
72.54 0.72 90.23 0.10 73.90 2.20 79.82 0.56 58.97 0.00 75.17 1.00 96.94 0.84 32.77 0.35 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.251159959
73.19 0.64 90.28 0.05 74.59 0.69 81.29 1.48 58.97 0.00 75.33 0.17 96.94 0.00 34.89 2.12 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.2477214125
73.45 0.26 90.28 0.00 74.73 0.14 82.45 1.16 58.97 0.00 75.33 0.00 96.94 0.00 35.42 0.53 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.2312516891
73.67 0.22 90.28 0.00 74.73 0.00 82.57 0.12 60.26 1.28 75.50 0.17 96.94 0.00 35.42 0.00 /workspace/coverage/default/30.rv_dm_stress_all.3701841038
73.86 0.18 90.33 0.05 75.27 0.55 82.81 0.24 60.26 0.00 75.67 0.17 97.04 0.11 35.60 0.18 /workspace/coverage/default/4.rv_dm_sec_cm.1494150855
74.02 0.17 90.33 0.00 75.27 0.00 82.81 0.00 60.26 0.00 75.67 0.00 98.20 1.16 35.60 0.00 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3931785661
74.18 0.16 90.43 0.10 75.55 0.27 82.89 0.08 60.26 0.00 76.33 0.67 98.20 0.00 35.60 0.00 /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.1035392298
74.33 0.14 90.53 0.10 75.96 0.41 82.89 0.00 60.26 0.00 76.83 0.50 98.20 0.00 35.60 0.00 /workspace/coverage/default/1.rv_dm_rom_read_access.164281251
74.45 0.13 90.53 0.00 75.96 0.00 83.61 0.72 60.26 0.00 76.83 0.00 98.20 0.00 35.78 0.18 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.1848258259
74.57 0.11 90.53 0.00 75.96 0.00 84.41 0.80 60.26 0.00 76.83 0.00 98.20 0.00 35.78 0.00 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.3961906798
74.64 0.07 90.53 0.00 75.96 0.00 84.49 0.08 60.26 0.00 76.83 0.00 98.20 0.00 36.22 0.44 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3928120057
74.70 0.06 90.53 0.00 75.96 0.00 84.89 0.40 60.26 0.00 76.83 0.00 98.20 0.00 36.22 0.00 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.100640798
74.75 0.05 90.53 0.00 76.10 0.14 85.13 0.24 60.26 0.00 76.83 0.00 98.20 0.00 36.22 0.00 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.3005805621
74.81 0.05 90.58 0.05 76.10 0.00 85.17 0.04 60.26 0.00 77.00 0.17 98.31 0.11 36.22 0.00 /workspace/coverage/default/35.rv_dm_alert_test.2401409189
74.85 0.04 90.58 0.00 76.24 0.14 85.17 0.00 60.26 0.00 77.00 0.00 98.31 0.00 36.40 0.18 /workspace/coverage/cover_reg_top/11.rv_dm_tap_fsm_rand_reset.2415854842
74.89 0.04 90.63 0.05 76.24 0.00 85.25 0.08 60.26 0.00 77.17 0.17 98.31 0.00 36.40 0.00 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2839865934
74.93 0.03 90.63 0.00 76.24 0.00 85.49 0.24 60.26 0.00 77.17 0.00 98.31 0.00 36.40 0.00 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3189533624
74.95 0.02 90.63 0.00 76.24 0.00 85.65 0.16 60.26 0.00 77.17 0.00 98.31 0.00 36.40 0.00 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.4133701068
74.97 0.02 90.63 0.00 76.24 0.00 85.69 0.04 60.26 0.00 77.17 0.00 98.42 0.11 36.40 0.00 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.2882702791
74.99 0.02 90.63 0.00 76.24 0.00 85.81 0.12 60.26 0.00 77.17 0.00 98.42 0.00 36.40 0.00 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1707500776
75.01 0.02 90.63 0.00 76.24 0.00 85.93 0.12 60.26 0.00 77.17 0.00 98.42 0.00 36.40 0.00 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.1289204829
75.02 0.01 90.63 0.00 76.24 0.00 85.93 0.00 60.26 0.00 77.17 0.00 98.42 0.00 36.48 0.09 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.310247848
75.03 0.01 90.63 0.00 76.24 0.00 86.01 0.08 60.26 0.00 77.17 0.00 98.42 0.00 36.48 0.00 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.620223058
75.04 0.01 90.63 0.00 76.24 0.00 86.05 0.04 60.26 0.00 77.17 0.00 98.42 0.00 36.48 0.00 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.1119272858
75.04 0.01 90.63 0.00 76.24 0.00 86.09 0.04 60.26 0.00 77.17 0.00 98.42 0.00 36.48 0.00 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.1700148253
75.05 0.01 90.63 0.00 76.24 0.00 86.13 0.04 60.26 0.00 77.17 0.00 98.42 0.00 36.48 0.00 /workspace/coverage/cover_reg_top/27.rv_dm_tap_fsm_rand_reset.127520368
75.05 0.01 90.63 0.00 76.24 0.00 86.17 0.04 60.26 0.00 77.17 0.00 98.42 0.00 36.48 0.00 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.2972629433

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.255599814
/workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3595303729
/workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2809597387
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.456463672
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1090469308
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2639153680
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2389952261
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.4008341638
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3290461113
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3750422551
/workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.4977545
/workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.2277979764
/workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.677504617
/workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.2802132981
/workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.4104315246
/workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.4268459183
/workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.4069006746
/workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.1963419191
/workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.1450765951
/workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.833129693
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.574969588
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2768687436
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2679647661
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1561235557
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3824366945
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2639354521
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.3885208621
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.543406538
/workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2673986226
/workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.3647136271
/workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.1893531007
/workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1757644348
/workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.2290492635
/workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.1191828298
/workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.1336216000
/workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.4253868669
/workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.4233691638
/workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.798163757
/workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.468133999
/workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.690451870
/workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.340175106
/workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.3284883809
/workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.1397707182
/workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.2362874773
/workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.2784935478
/workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.4293932158
/workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1588893373
/workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.953410884
/workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3387008821
/workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.3307882183
/workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.2066898464
/workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.3248828660
/workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.3036849421
/workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.4143684254
/workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.580522631
/workspace/coverage/cover_reg_top/13.rv_dm_tap_fsm_rand_reset.2472277887
/workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.3052185357
/workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.1337356689
/workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.3277902558
/workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1052968445
/workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.925412541
/workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2591454362
/workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3967164546
/workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.3975455758
/workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2256072246
/workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3087505187
/workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3153835839
/workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.3106496231
/workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.479199106
/workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.3972805385
/workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.2074094286
/workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.1383394010
/workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3297628500
/workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.714186348
/workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.2769113501
/workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.1289993814
/workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.1381785919
/workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.2699130639
/workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.4284507896
/workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.240838282
/workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.107218204
/workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.1483334034
/workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.1970052019
/workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.3030366747
/workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.1893343344
/workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1369490399
/workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.843311374
/workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.2596019951
/workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.3019633379
/workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1818371275
/workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3294306090
/workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2058741362
/workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.1128542187
/workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.60573402
/workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3671524955
/workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.3389600902
/workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.3483355439
/workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3286759079
/workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.4145953911
/workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.3314741067
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2465412837
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2206345168
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.2145222825
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3394469978
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.2887008336
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.3722482602
/workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2671362619
/workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.3565468220
/workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3767477887
/workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.3880115149
/workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.3480714930
/workspace/coverage/cover_reg_top/22.rv_dm_tap_fsm_rand_reset.2246737427
/workspace/coverage/cover_reg_top/25.rv_dm_tap_fsm_rand_reset.2769404443
/workspace/coverage/cover_reg_top/28.rv_dm_tap_fsm_rand_reset.2596378600
/workspace/coverage/cover_reg_top/29.rv_dm_tap_fsm_rand_reset.3382139093
/workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1414785353
/workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.205700306
/workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.512097562
/workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.990782094
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1583905128
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.3399516211
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.1377645914
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.704868534
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3061912839
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.1768202038
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1156484605
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2909122968
/workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.181489684
/workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.4043633330
/workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.3531639172
/workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.789550542
/workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2013403711
/workspace/coverage/cover_reg_top/34.rv_dm_tap_fsm_rand_reset.1838274344
/workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.336070039
/workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.2661079430
/workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2416734708
/workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2127674714
/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2202323624
/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.2471590811
/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.671071064
/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.2297142555
/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.1619645024
/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.3712519482
/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2839417010
/workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1944015082
/workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.1519164805
/workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.264782509
/workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.1061911551
/workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.1925066912
/workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.1541446357
/workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.1018990421
/workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1549383032
/workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.2826459207
/workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.2059889013
/workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2385773190
/workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.3278093920
/workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.266994489
/workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.1830752274
/workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.4086730836
/workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1346907940
/workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2477456021
/workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.1505857399
/workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3949290994
/workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.656383761
/workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.2792649336
/workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.4200117551
/workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.366344363
/workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.2878696068
/workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.3051988916
/workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1441542636
/workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.74546436
/workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2369971263
/workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.3857518971
/workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.1918588459
/workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1203543253
/workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.2366393497
/workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1285989308
/workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.4286534460
/workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.313301948
/workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.2928919804
/workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.1771017635
/workspace/coverage/default/0.rv_dm_alert_test.1110391599
/workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.3114090689
/workspace/coverage/default/0.rv_dm_rom_read_access.1506975981
/workspace/coverage/default/0.rv_dm_sec_cm.1662658524
/workspace/coverage/default/1.rv_dm_alert_test.3883632042
/workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.2201921445
/workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.4256364607
/workspace/coverage/default/1.rv_dm_sec_cm.2957487529
/workspace/coverage/default/10.rv_dm_alert_test.95220618
/workspace/coverage/default/10.rv_dm_stress_all.1729238093
/workspace/coverage/default/11.rv_dm_alert_test.3698570976
/workspace/coverage/default/12.rv_dm_alert_test.3420566958
/workspace/coverage/default/13.rv_dm_alert_test.1684846743
/workspace/coverage/default/14.rv_dm_alert_test.1049288138
/workspace/coverage/default/15.rv_dm_alert_test.3819960677
/workspace/coverage/default/16.rv_dm_alert_test.4095816779
/workspace/coverage/default/17.rv_dm_alert_test.271227827
/workspace/coverage/default/18.rv_dm_alert_test.2097284394
/workspace/coverage/default/19.rv_dm_alert_test.2692727631
/workspace/coverage/default/2.rv_dm_alert_test.4204716339
/workspace/coverage/default/2.rv_dm_sec_cm.440491270
/workspace/coverage/default/20.rv_dm_alert_test.3605059209
/workspace/coverage/default/21.rv_dm_alert_test.2757446238
/workspace/coverage/default/21.rv_dm_stress_all.843213522
/workspace/coverage/default/22.rv_dm_alert_test.2009251377
/workspace/coverage/default/23.rv_dm_alert_test.1284372010
/workspace/coverage/default/24.rv_dm_alert_test.2879750401
/workspace/coverage/default/25.rv_dm_alert_test.2378283471
/workspace/coverage/default/26.rv_dm_alert_test.3086407330
/workspace/coverage/default/27.rv_dm_alert_test.4225084504
/workspace/coverage/default/28.rv_dm_alert_test.2061514167
/workspace/coverage/default/29.rv_dm_alert_test.3056863713
/workspace/coverage/default/3.rv_dm_alert_test.2581685827
/workspace/coverage/default/3.rv_dm_sec_cm.438725291
/workspace/coverage/default/3.rv_dm_stress_all.1675069575
/workspace/coverage/default/30.rv_dm_alert_test.579881906
/workspace/coverage/default/31.rv_dm_alert_test.2348263556
/workspace/coverage/default/32.rv_dm_alert_test.2112724715
/workspace/coverage/default/32.rv_dm_stress_all.1072234152
/workspace/coverage/default/33.rv_dm_alert_test.2489518073
/workspace/coverage/default/34.rv_dm_alert_test.1495766012
/workspace/coverage/default/35.rv_dm_stress_all.1929399839
/workspace/coverage/default/36.rv_dm_alert_test.1686845426
/workspace/coverage/default/37.rv_dm_alert_test.1904992342
/workspace/coverage/default/38.rv_dm_alert_test.1868663129
/workspace/coverage/default/39.rv_dm_alert_test.319580266
/workspace/coverage/default/4.rv_dm_alert_test.1596498797
/workspace/coverage/default/40.rv_dm_alert_test.1898995414
/workspace/coverage/default/41.rv_dm_alert_test.3238657188
/workspace/coverage/default/41.rv_dm_stress_all.1889410357
/workspace/coverage/default/42.rv_dm_alert_test.1959879834
/workspace/coverage/default/43.rv_dm_alert_test.272363176
/workspace/coverage/default/44.rv_dm_alert_test.4028766036
/workspace/coverage/default/45.rv_dm_alert_test.300877528
/workspace/coverage/default/46.rv_dm_alert_test.916586878
/workspace/coverage/default/47.rv_dm_alert_test.1051836860
/workspace/coverage/default/48.rv_dm_alert_test.2900491546
/workspace/coverage/default/5.rv_dm_alert_test.1851430275
/workspace/coverage/default/6.rv_dm_alert_test.4025135015
/workspace/coverage/default/7.rv_dm_alert_test.3000356675
/workspace/coverage/default/8.rv_dm_alert_test.709686985
/workspace/coverage/default/9.rv_dm_alert_test.1616945058



Total test records in report: 275
tests.html | tests1.html | tests2.html | tests3.html | tests4.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/25.rv_dm_alert_test.2378283471 May 26 02:47:24 PM PDT 24 May 26 02:47:27 PM PDT 24 21626424 ps
T2 /workspace/coverage/default/34.rv_dm_alert_test.1495766012 May 26 02:47:26 PM PDT 24 May 26 02:47:31 PM PDT 24 21435129 ps
T3 /workspace/coverage/default/49.rv_dm_alert_test.3809479048 May 26 02:47:40 PM PDT 24 May 26 02:47:43 PM PDT 24 20034627 ps
T4 /workspace/coverage/default/41.rv_dm_alert_test.3238657188 May 26 02:47:31 PM PDT 24 May 26 02:47:34 PM PDT 24 25719455 ps
T5 /workspace/coverage/default/30.rv_dm_stress_all.3701841038 May 26 02:47:27 PM PDT 24 May 26 02:47:45 PM PDT 24 7492428738 ps
T6 /workspace/coverage/default/46.rv_dm_stress_all.73368036 May 26 02:47:33 PM PDT 24 May 26 02:47:46 PM PDT 24 9768830110 ps
T18 /workspace/coverage/default/5.rv_dm_alert_test.1851430275 May 26 02:46:51 PM PDT 24 May 26 02:46:52 PM PDT 24 42596801 ps
T7 /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.1035392298 May 26 02:46:27 PM PDT 24 May 26 02:46:28 PM PDT 24 76757994 ps
T8 /workspace/coverage/default/38.rv_dm_stress_all.918911009 May 26 02:47:34 PM PDT 24 May 26 02:47:44 PM PDT 24 2798807141 ps
T19 /workspace/coverage/default/16.rv_dm_alert_test.4095816779 May 26 02:47:15 PM PDT 24 May 26 02:47:17 PM PDT 24 58355669 ps
T32 /workspace/coverage/default/35.rv_dm_alert_test.2401409189 May 26 02:47:24 PM PDT 24 May 26 02:47:27 PM PDT 24 84181147 ps
T20 /workspace/coverage/default/4.rv_dm_sec_cm.1494150855 May 26 02:46:48 PM PDT 24 May 26 02:46:50 PM PDT 24 701912124 ps
T50 /workspace/coverage/default/38.rv_dm_alert_test.1868663129 May 26 02:47:33 PM PDT 24 May 26 02:47:36 PM PDT 24 25313003 ps
T51 /workspace/coverage/default/26.rv_dm_alert_test.3086407330 May 26 02:47:23 PM PDT 24 May 26 02:47:25 PM PDT 24 21942435 ps
T45 /workspace/coverage/default/37.rv_dm_alert_test.1904992342 May 26 02:47:32 PM PDT 24 May 26 02:47:34 PM PDT 24 20863904 ps
T10 /workspace/coverage/default/41.rv_dm_stress_all.1889410357 May 26 02:47:32 PM PDT 24 May 26 02:47:40 PM PDT 24 1558654255 ps
T13 /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.3114090689 May 26 02:46:26 PM PDT 24 May 26 02:46:28 PM PDT 24 68437620 ps
T52 /workspace/coverage/default/40.rv_dm_alert_test.1898995414 May 26 02:47:33 PM PDT 24 May 26 02:47:36 PM PDT 24 33826085 ps
T53 /workspace/coverage/default/47.rv_dm_alert_test.1051836860 May 26 02:47:39 PM PDT 24 May 26 02:47:41 PM PDT 24 35162387 ps
T46 /workspace/coverage/default/48.rv_dm_alert_test.2900491546 May 26 02:47:41 PM PDT 24 May 26 02:47:44 PM PDT 24 58780763 ps
T11 /workspace/coverage/default/32.rv_dm_stress_all.1072234152 May 26 02:47:27 PM PDT 24 May 26 02:47:32 PM PDT 24 1589383842 ps
T100 /workspace/coverage/default/6.rv_dm_alert_test.4025135015 May 26 02:46:56 PM PDT 24 May 26 02:46:57 PM PDT 24 57564027 ps
T120 /workspace/coverage/default/4.rv_dm_alert_test.1596498797 May 26 02:46:50 PM PDT 24 May 26 02:46:52 PM PDT 24 136048187 ps
T122 /workspace/coverage/default/19.rv_dm_alert_test.2692727631 May 26 02:47:18 PM PDT 24 May 26 02:47:21 PM PDT 24 27399373 ps
T16 /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.4256364607 May 26 02:46:34 PM PDT 24 May 26 02:46:37 PM PDT 24 53893414 ps
T42 /workspace/coverage/default/18.rv_dm_alert_test.2097284394 May 26 02:47:17 PM PDT 24 May 26 02:47:19 PM PDT 24 38871195 ps
T21 /workspace/coverage/default/1.rv_dm_sec_cm.2957487529 May 26 02:46:33 PM PDT 24 May 26 02:46:35 PM PDT 24 79281815 ps
T47 /workspace/coverage/default/17.rv_dm_alert_test.271227827 May 26 02:47:15 PM PDT 24 May 26 02:47:17 PM PDT 24 27513774 ps
T43 /workspace/coverage/default/20.rv_dm_alert_test.3605059209 May 26 02:47:17 PM PDT 24 May 26 02:47:19 PM PDT 24 19979645 ps
T140 /workspace/coverage/default/1.rv_dm_alert_test.3883632042 May 26 02:46:38 PM PDT 24 May 26 02:46:39 PM PDT 24 23471159 ps
T134 /workspace/coverage/default/12.rv_dm_alert_test.3420566958 May 26 02:47:05 PM PDT 24 May 26 02:47:07 PM PDT 24 16236707 ps
T142 /workspace/coverage/default/29.rv_dm_alert_test.3056863713 May 26 02:47:23 PM PDT 24 May 26 02:47:25 PM PDT 24 98426765 ps
T44 /workspace/coverage/default/3.rv_dm_alert_test.2581685827 May 26 02:46:43 PM PDT 24 May 26 02:46:45 PM PDT 24 55521748 ps
T119 /workspace/coverage/default/7.rv_dm_alert_test.3000356675 May 26 02:46:56 PM PDT 24 May 26 02:46:58 PM PDT 24 17268033 ps
T108 /workspace/coverage/default/21.rv_dm_alert_test.2757446238 May 26 02:47:16 PM PDT 24 May 26 02:47:18 PM PDT 24 30330181 ps
T138 /workspace/coverage/default/8.rv_dm_alert_test.709686985 May 26 02:46:58 PM PDT 24 May 26 02:47:00 PM PDT 24 126646712 ps
T14 /workspace/coverage/default/0.rv_dm_rom_read_access.1506975981 May 26 02:46:27 PM PDT 24 May 26 02:46:30 PM PDT 24 35327426 ps
T124 /workspace/coverage/default/39.rv_dm_alert_test.319580266 May 26 02:47:33 PM PDT 24 May 26 02:47:35 PM PDT 24 94578284 ps
T141 /workspace/coverage/default/24.rv_dm_alert_test.2879750401 May 26 02:47:24 PM PDT 24 May 26 02:47:26 PM PDT 24 28435576 ps
T139 /workspace/coverage/default/22.rv_dm_alert_test.2009251377 May 26 02:47:17 PM PDT 24 May 26 02:47:19 PM PDT 24 53162244 ps
T12 /workspace/coverage/default/35.rv_dm_stress_all.1929399839 May 26 02:47:25 PM PDT 24 May 26 02:47:34 PM PDT 24 19610767597 ps
T125 /workspace/coverage/default/36.rv_dm_alert_test.1686845426 May 26 02:47:24 PM PDT 24 May 26 02:47:26 PM PDT 24 25060853 ps
T143 /workspace/coverage/default/33.rv_dm_alert_test.2489518073 May 26 02:47:26 PM PDT 24 May 26 02:47:30 PM PDT 24 21009309 ps
T118 /workspace/coverage/default/14.rv_dm_alert_test.1049288138 May 26 02:47:06 PM PDT 24 May 26 02:47:08 PM PDT 24 140672394 ps
T133 /workspace/coverage/default/23.rv_dm_alert_test.1284372010 May 26 02:47:25 PM PDT 24 May 26 02:47:28 PM PDT 24 49940876 ps
T22 /workspace/coverage/default/0.rv_dm_sec_cm.1662658524 May 26 02:46:33 PM PDT 24 May 26 02:46:36 PM PDT 24 291967982 ps
T130 /workspace/coverage/default/30.rv_dm_alert_test.579881906 May 26 02:47:26 PM PDT 24 May 26 02:47:30 PM PDT 24 39659606 ps
T144 /workspace/coverage/default/43.rv_dm_alert_test.272363176 May 26 02:47:32 PM PDT 24 May 26 02:47:34 PM PDT 24 47205846 ps
T126 /workspace/coverage/default/28.rv_dm_alert_test.2061514167 May 26 02:47:23 PM PDT 24 May 26 02:47:25 PM PDT 24 60975263 ps
T135 /workspace/coverage/default/46.rv_dm_alert_test.916586878 May 26 02:47:33 PM PDT 24 May 26 02:47:36 PM PDT 24 27744626 ps
T145 /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.2201921445 May 26 02:46:33 PM PDT 24 May 26 02:46:35 PM PDT 24 50327388 ps
T117 /workspace/coverage/default/27.rv_dm_alert_test.4225084504 May 26 02:47:25 PM PDT 24 May 26 02:47:28 PM PDT 24 160240625 ps
T15 /workspace/coverage/default/1.rv_dm_rom_read_access.164281251 May 26 02:46:36 PM PDT 24 May 26 02:46:37 PM PDT 24 31717237 ps
T121 /workspace/coverage/default/0.rv_dm_alert_test.1110391599 May 26 02:46:32 PM PDT 24 May 26 02:46:34 PM PDT 24 31544374 ps
T129 /workspace/coverage/default/9.rv_dm_alert_test.1616945058 May 26 02:46:59 PM PDT 24 May 26 02:47:00 PM PDT 24 93269832 ps
T128 /workspace/coverage/default/10.rv_dm_alert_test.95220618 May 26 02:47:04 PM PDT 24 May 26 02:47:05 PM PDT 24 19571780 ps
T9 /workspace/coverage/default/21.rv_dm_stress_all.843213522 May 26 02:47:19 PM PDT 24 May 26 02:47:38 PM PDT 24 5206301754 ps
T131 /workspace/coverage/default/11.rv_dm_alert_test.3698570976 May 26 02:47:08 PM PDT 24 May 26 02:47:10 PM PDT 24 23378527 ps
T146 /workspace/coverage/default/15.rv_dm_alert_test.3819960677 May 26 02:47:20 PM PDT 24 May 26 02:47:22 PM PDT 24 63252272 ps
T48 /workspace/coverage/default/2.rv_dm_sec_cm.440491270 May 26 02:46:42 PM PDT 24 May 26 02:46:44 PM PDT 24 221345963 ps
T137 /workspace/coverage/default/31.rv_dm_alert_test.2348263556 May 26 02:47:26 PM PDT 24 May 26 02:47:30 PM PDT 24 27280336 ps
T147 /workspace/coverage/default/42.rv_dm_alert_test.1959879834 May 26 02:47:32 PM PDT 24 May 26 02:47:35 PM PDT 24 58601291 ps
T127 /workspace/coverage/default/2.rv_dm_alert_test.4204716339 May 26 02:46:41 PM PDT 24 May 26 02:46:43 PM PDT 24 84882688 ps
T148 /workspace/coverage/default/45.rv_dm_alert_test.300877528 May 26 02:47:33 PM PDT 24 May 26 02:47:35 PM PDT 24 21619607 ps
T149 /workspace/coverage/default/32.rv_dm_alert_test.2112724715 May 26 02:47:23 PM PDT 24 May 26 02:47:24 PM PDT 24 29015110 ps
T66 /workspace/coverage/default/10.rv_dm_stress_all.1729238093 May 26 02:47:04 PM PDT 24 May 26 02:47:09 PM PDT 24 6637428833 ps
T132 /workspace/coverage/default/44.rv_dm_alert_test.4028766036 May 26 02:47:34 PM PDT 24 May 26 02:47:36 PM PDT 24 22866966 ps
T123 /workspace/coverage/default/13.rv_dm_alert_test.1684846743 May 26 02:47:05 PM PDT 24 May 26 02:47:07 PM PDT 24 53829201 ps
T17 /workspace/coverage/default/3.rv_dm_stress_all.1675069575 May 26 02:46:41 PM PDT 24 May 26 02:46:46 PM PDT 24 3734427890 ps
T49 /workspace/coverage/default/3.rv_dm_sec_cm.438725291 May 26 02:46:42 PM PDT 24 May 26 02:46:45 PM PDT 24 590941711 ps
T31 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.3248828660 May 26 02:51:47 PM PDT 24 May 26 02:51:53 PM PDT 24 228608386 ps
T23 /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.313301948 May 26 02:51:39 PM PDT 24 May 26 02:52:01 PM PDT 24 16253075554 ps
T27 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1818371275 May 26 02:51:55 PM PDT 24 May 26 02:52:01 PM PDT 24 2877725843 ps
T75 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.4293932158 May 26 02:51:46 PM PDT 24 May 26 02:51:51 PM PDT 24 66326422 ps
T64 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1156484605 May 26 02:51:27 PM PDT 24 May 26 02:51:30 PM PDT 24 99897142 ps
T65 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3061912839 May 26 02:51:25 PM PDT 24 May 26 02:51:28 PM PDT 24 248941416 ps
T150 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1583905128 May 26 02:51:24 PM PDT 24 May 26 02:51:54 PM PDT 24 7055021186 ps
T29 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.3106496231 May 26 02:51:46 PM PDT 24 May 26 02:51:54 PM PDT 24 997780844 ps
T28 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.1119272858 May 26 02:51:47 PM PDT 24 May 26 02:51:52 PM PDT 24 174284049 ps
T38 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.4284507896 May 26 02:51:45 PM PDT 24 May 26 02:51:50 PM PDT 24 407910860 ps
T39 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2385773190 May 26 02:51:35 PM PDT 24 May 26 02:51:39 PM PDT 24 1596870571 ps
T54 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2839865934 May 26 02:51:20 PM PDT 24 May 26 02:51:23 PM PDT 24 107839354 ps
T36 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.3399516211 May 26 02:51:25 PM PDT 24 May 26 02:52:22 PM PDT 24 13098858427 ps
T30 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.251159959 May 26 02:51:24 PM PDT 24 May 26 02:51:33 PM PDT 24 1715762791 ps
T151 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.1619645024 May 26 02:51:28 PM PDT 24 May 26 02:51:34 PM PDT 24 1664966824 ps
T33 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2199662658 May 26 02:51:27 PM PDT 24 May 26 02:51:35 PM PDT 24 1748738098 ps
T24 /workspace/coverage/cover_reg_top/10.rv_dm_tap_fsm_rand_reset.660148446 May 26 02:51:36 PM PDT 24 May 26 02:52:29 PM PDT 24 17313581518 ps
T152 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3394469978 May 26 02:51:25 PM PDT 24 May 26 02:51:28 PM PDT 24 101764556 ps
T76 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.468133999 May 26 02:51:45 PM PDT 24 May 26 02:51:50 PM PDT 24 28971086 ps
T25 /workspace/coverage/cover_reg_top/11.rv_dm_tap_fsm_rand_reset.2415854842 May 26 02:51:45 PM PDT 24 May 26 02:52:01 PM PDT 24 6369326490 ps
T153 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2058741362 May 26 02:51:45 PM PDT 24 May 26 02:51:50 PM PDT 24 291151269 ps
T154 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.1541446357 May 26 02:51:34 PM PDT 24 May 26 02:51:39 PM PDT 24 2307052250 ps
T67 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.1337356689 May 26 02:51:44 PM PDT 24 May 26 02:51:52 PM PDT 24 4250683398 ps
T37 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.3961906798 May 26 02:51:27 PM PDT 24 May 26 02:53:08 PM PDT 24 40395337862 ps
T68 /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.3880115149 May 26 02:51:28 PM PDT 24 May 26 02:52:02 PM PDT 24 20018801501 ps
T155 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2639153680 May 26 02:51:20 PM PDT 24 May 26 02:51:23 PM PDT 24 294609467 ps
T77 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.990782094 May 26 02:51:26 PM PDT 24 May 26 02:51:30 PM PDT 24 107055560 ps
T69 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.4086730836 May 26 02:51:36 PM PDT 24 May 26 02:51:43 PM PDT 24 213701610 ps
T78 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.2074094286 May 26 02:51:46 PM PDT 24 May 26 02:51:51 PM PDT 24 266100427 ps
T70 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.3975455758 May 26 02:51:44 PM PDT 24 May 26 02:51:51 PM PDT 24 1113229575 ps
T26 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.1336216000 May 26 02:51:36 PM PDT 24 May 26 02:51:39 PM PDT 24 351593466 ps
T156 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.4043633330 May 26 02:51:23 PM PDT 24 May 26 02:51:25 PM PDT 24 26809066 ps
T157 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.574969588 May 26 02:51:20 PM PDT 24 May 26 02:51:29 PM PDT 24 3215430330 ps
T158 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.925412541 May 26 02:51:46 PM PDT 24 May 26 02:51:51 PM PDT 24 94579707 ps
T79 /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.60573402 May 26 02:51:54 PM PDT 24 May 26 02:52:01 PM PDT 24 545269744 ps
T159 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.456463672 May 26 02:51:17 PM PDT 24 May 26 02:51:50 PM PDT 24 8261552421 ps
T160 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2909122968 May 26 02:51:26 PM PDT 24 May 26 02:51:28 PM PDT 24 53581780 ps
T71 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.4145953911 May 26 02:51:32 PM PDT 24 May 26 02:51:46 PM PDT 24 4614308714 ps
T161 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.181489684 May 26 02:51:26 PM PDT 24 May 26 02:51:28 PM PDT 24 33722517 ps
T162 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1944015082 May 26 02:51:27 PM PDT 24 May 26 02:51:30 PM PDT 24 14206075 ps
T163 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.3712519482 May 26 02:51:29 PM PDT 24 May 26 02:51:31 PM PDT 24 95958523 ps
T34 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2206345168 May 26 02:51:32 PM PDT 24 May 26 02:51:36 PM PDT 24 959265321 ps
T164 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.1519164805 May 26 02:51:32 PM PDT 24 May 26 02:51:34 PM PDT 24 20852506 ps
T72 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.2769113501 May 26 02:51:44 PM PDT 24 May 26 02:51:50 PM PDT 24 137135391 ps
T73 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.1483334034 May 26 02:51:55 PM PDT 24 May 26 02:52:00 PM PDT 24 57678065 ps
T165 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2768687436 May 26 02:51:20 PM PDT 24 May 26 02:51:41 PM PDT 24 9437459575 ps
T166 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1441542636 May 26 02:51:37 PM PDT 24 May 26 02:51:40 PM PDT 24 925287578 ps
T167 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.4143684254 May 26 02:51:43 PM PDT 24 May 26 02:51:46 PM PDT 24 34870979 ps
T168 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.543406538 May 26 02:51:16 PM PDT 24 May 26 02:51:19 PM PDT 24 63260395 ps
T74 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.479199106 May 26 02:51:44 PM PDT 24 May 26 02:51:53 PM PDT 24 108663952 ps
T102 /workspace/coverage/cover_reg_top/29.rv_dm_tap_fsm_rand_reset.3382139093 May 26 02:51:52 PM PDT 24 May 26 02:52:17 PM PDT 24 7386475295 ps
T169 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.4008341638 May 26 02:51:17 PM PDT 24 May 26 02:51:22 PM PDT 24 914039991 ps
T80 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2809597387 May 26 02:51:19 PM PDT 24 May 26 02:51:23 PM PDT 24 54791689 ps
T103 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.1450765951 May 26 02:51:22 PM PDT 24 May 26 02:51:25 PM PDT 24 964036414 ps
T170 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.3972805385 May 26 02:51:45 PM PDT 24 May 26 02:51:50 PM PDT 24 338442086 ps
T105 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3928120057 May 26 02:51:45 PM PDT 24 May 26 02:52:04 PM PDT 24 1375308274 ps
T171 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2673986226 May 26 02:51:19 PM PDT 24 May 26 02:51:22 PM PDT 24 16627961 ps
T172 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.3278093920 May 26 02:51:39 PM PDT 24 May 26 02:51:41 PM PDT 24 97599198 ps
T81 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.4233691638 May 26 02:51:45 PM PDT 24 May 26 02:51:53 PM PDT 24 2298790477 ps
T173 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.1381785919 May 26 02:51:45 PM PDT 24 May 26 02:51:52 PM PDT 24 65126258 ps
T96 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2591454362 May 26 02:51:46 PM PDT 24 May 26 02:51:57 PM PDT 24 684571232 ps
T136 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.3052185357 May 26 02:51:47 PM PDT 24 May 26 02:51:52 PM PDT 24 111225352 ps
T174 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.2277979764 May 26 02:51:19 PM PDT 24 May 26 02:51:22 PM PDT 24 24071000 ps
T175 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.798163757 May 26 02:51:46 PM PDT 24 May 26 02:51:53 PM PDT 24 497532622 ps
T82 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.1505857399 May 26 02:51:35 PM PDT 24 May 26 02:51:39 PM PDT 24 330896608 ps
T104 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1707500776 May 26 02:51:27 PM PDT 24 May 26 02:52:00 PM PDT 24 1939909949 ps
T176 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1757644348 May 26 02:51:17 PM PDT 24 May 26 02:51:25 PM PDT 24 70069778 ps
T177 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2389952261 May 26 02:51:17 PM PDT 24 May 26 02:51:20 PM PDT 24 217487565 ps
T106 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.2362874773 May 26 02:51:46 PM PDT 24 May 26 02:51:58 PM PDT 24 287921596 ps
T107 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1346907940 May 26 02:51:36 PM PDT 24 May 26 02:51:55 PM PDT 24 1521869135 ps
T178 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.1397707182 May 26 02:51:47 PM PDT 24 May 26 02:51:53 PM PDT 24 203567096 ps
T83 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.2792649336 May 26 02:51:39 PM PDT 24 May 26 02:51:47 PM PDT 24 302743442 ps
T59 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.2972629433 May 26 02:51:32 PM PDT 24 May 26 02:51:36 PM PDT 24 106744201 ps
T97 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.1893531007 May 26 02:51:18 PM PDT 24 May 26 02:51:28 PM PDT 24 760970846 ps
T109 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.1289993814 May 26 02:51:43 PM PDT 24 May 26 02:52:04 PM PDT 24 3721153540 ps
T60 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.2477214125 May 26 02:51:37 PM PDT 24 May 26 02:52:00 PM PDT 24 1602520261 ps
T179 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.690451870 May 26 02:51:45 PM PDT 24 May 26 02:51:50 PM PDT 24 495839635 ps
T61 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.2882702791 May 26 02:51:18 PM PDT 24 May 26 02:52:00 PM PDT 24 15132706159 ps
T180 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.1918588459 May 26 02:51:36 PM PDT 24 May 26 02:51:44 PM PDT 24 2372284495 ps
T181 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.2826459207 May 26 02:51:36 PM PDT 24 May 26 02:51:40 PM PDT 24 75670021 ps
T182 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3153835839 May 26 02:51:43 PM PDT 24 May 26 02:51:45 PM PDT 24 50252867 ps
T111 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.366344363 May 26 02:51:36 PM PDT 24 May 26 02:51:47 PM PDT 24 663369831 ps
T84 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.714186348 May 26 02:51:47 PM PDT 24 May 26 02:51:57 PM PDT 24 289358077 ps
T183 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.4133701068 May 26 02:51:38 PM PDT 24 May 26 02:51:51 PM PDT 24 1920414389 ps
T184 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.240838282 May 26 02:51:49 PM PDT 24 May 26 02:51:52 PM PDT 24 46541394 ps
T35 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2679647661 May 26 02:51:17 PM PDT 24 May 26 02:51:25 PM PDT 24 2074546943 ps
T185 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.2928919804 May 26 02:51:37 PM PDT 24 May 26 02:51:45 PM PDT 24 783167813 ps
T98 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.580522631 May 26 02:51:45 PM PDT 24 May 26 02:51:56 PM PDT 24 796549577 ps
T186 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.512097562 May 26 02:51:29 PM PDT 24 May 26 02:51:39 PM PDT 24 3287133881 ps
T85 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3931785661 May 26 02:51:18 PM PDT 24 May 26 02:52:36 PM PDT 24 8035433803 ps
T99 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.677504617 May 26 02:51:18 PM PDT 24 May 26 02:51:24 PM PDT 24 82644824 ps
T90 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.3314741067 May 26 02:51:25 PM PDT 24 May 26 02:51:29 PM PDT 24 57844641 ps
T187 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2839417010 May 26 02:51:28 PM PDT 24 May 26 02:51:31 PM PDT 24 70129513 ps
T188 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1369490399 May 26 02:51:46 PM PDT 24 May 26 02:51:53 PM PDT 24 706596473 ps
T110 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.310247848 May 26 02:51:39 PM PDT 24 May 26 02:52:00 PM PDT 24 1335058235 ps
T189 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.671071064 May 26 02:51:25 PM PDT 24 May 26 02:51:30 PM PDT 24 895431574 ps
T190 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2465412837 May 26 02:51:25 PM PDT 24 May 26 02:51:38 PM PDT 24 6036149199 ps
T191 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.2066898464 May 26 02:51:47 PM PDT 24 May 26 02:52:01 PM PDT 24 6704896955 ps
T112 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3189533624 May 26 02:51:44 PM PDT 24 May 26 02:51:57 PM PDT 24 895916533 ps
T192 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3290461113 May 26 02:51:17 PM PDT 24 May 26 02:51:20 PM PDT 24 335276751 ps
T55 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.2312516891 May 26 02:51:32 PM PDT 24 May 26 02:51:52 PM PDT 24 1086572927 ps
T193 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3671524955 May 26 02:51:48 PM PDT 24 May 26 02:51:53 PM PDT 24 35951533 ps
T194 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.1963419191 May 26 02:51:18 PM PDT 24 May 26 02:51:23 PM PDT 24 937558302 ps
T40 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.1377645914 May 26 02:51:38 PM PDT 24 May 26 02:51:41 PM PDT 24 699174165 ps
T195 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.255599814 May 26 02:51:18 PM PDT 24 May 26 02:51:22 PM PDT 24 964609933 ps
T196 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.656383761 May 26 02:51:37 PM PDT 24 May 26 02:51:39 PM PDT 24 100336068 ps
T197 /workspace/coverage/cover_reg_top/27.rv_dm_tap_fsm_rand_reset.127520368 May 26 02:51:56 PM PDT 24 May 26 02:52:14 PM PDT 24 13475694746 ps
T115 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.4104315246 May 26 02:51:20 PM PDT 24 May 26 02:51:32 PM PDT 24 2091251554 ps
T198 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.266994489 May 26 02:51:34 PM PDT 24 May 26 02:51:40 PM PDT 24 1048680565 ps
T199 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.2145222825 May 26 02:51:27 PM PDT 24 May 26 02:51:31 PM PDT 24 462552961 ps
T200 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.4268459183 May 26 02:51:21 PM PDT 24 May 26 02:52:28 PM PDT 24 4434179386 ps
T116 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2013403711 May 26 02:51:29 PM PDT 24 May 26 02:51:40 PM PDT 24 637292239 ps
T201 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.2784935478 May 26 02:51:43 PM PDT 24 May 26 02:51:47 PM PDT 24 699828585 ps
T202 /workspace/coverage/cover_reg_top/28.rv_dm_tap_fsm_rand_reset.2596378600 May 26 02:51:59 PM PDT 24 May 26 02:52:25 PM PDT 24 10706720486 ps
T203 /workspace/coverage/cover_reg_top/13.rv_dm_tap_fsm_rand_reset.2472277887 May 26 02:51:46 PM PDT 24 May 26 02:52:16 PM PDT 24 27975860376 ps
T204 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.1970052019 May 26 02:51:46 PM PDT 24 May 26 02:51:58 PM PDT 24 355335728 ps
T91 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2256072246 May 26 02:51:44 PM PDT 24 May 26 02:51:50 PM PDT 24 1321898265 ps
T101 /workspace/coverage/cover_reg_top/25.rv_dm_tap_fsm_rand_reset.2769404443 May 26 02:51:55 PM PDT 24 May 26 02:52:36 PM PDT 24 31166028999 ps
T92 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.1191828298 May 26 02:51:37 PM PDT 24 May 26 02:51:41 PM PDT 24 78186144 ps
T205 /workspace/coverage/cover_reg_top/34.rv_dm_tap_fsm_rand_reset.1838274344 May 26 02:51:54 PM PDT 24 May 26 02:52:12 PM PDT 24 20087782585 ps
T206 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.4069006746 May 26 02:51:18 PM PDT 24 May 26 02:51:59 PM PDT 24 3811483964 ps
T207 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.2878696068 May 26 02:51:35 PM PDT 24 May 26 02:51:39 PM PDT 24 65507943 ps
T208 /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.1830752274 May 26 02:51:37 PM PDT 24 May 26 02:52:11 PM PDT 24 18052332482 ps
T209 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.4200117551 May 26 02:51:36 PM PDT 24 May 26 02:51:41 PM PDT 24 1361533871 ps
T210 /workspace/coverage/cover_reg_top/22.rv_dm_tap_fsm_rand_reset.2246737427 May 26 02:51:54 PM PDT 24 May 26 02:52:24 PM PDT 24 13845203153 ps
T211 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.953410884 May 26 02:51:46 PM PDT 24 May 26 02:51:50 PM PDT 24 100201227 ps
T212 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.2059889013 May 26 02:51:39 PM PDT 24 May 26 02:51:42 PM PDT 24 46804383 ps
T213 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.2802132981 May 26 02:51:20 PM PDT 24 May 26 02:51:26 PM PDT 24 169797824 ps
T214 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.3857518971 May 26 02:51:35 PM PDT 24 May 26 02:51:39 PM PDT 24 100412963 ps
T215 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.3885208621 May 26 02:51:17 PM PDT 24 May 26 02:51:20 PM PDT 24 54060535 ps
T56 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.205700306 May 26 02:51:27 PM PDT 24 May 26 02:51:31 PM PDT 24 34428254 ps
T216 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.704868534 May 26 02:51:33 PM PDT 24 May 26 02:51:37 PM PDT 24 492379184 ps
T217 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.1383394010 May 26 02:51:45 PM PDT 24 May 26 02:51:52 PM PDT 24 1963033420 ps
T218 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.3284883809 May 26 02:51:45 PM PDT 24 May 26 02:51:55 PM PDT 24 550494371 ps
T219 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.2471590811 May 26 02:51:31 PM PDT 24 May 26 02:52:51 PM PDT 24 26893772588 ps
T220 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1090469308 May 26 02:51:17 PM PDT 24 May 26 02:55:47 PM PDT 24 84296376254 ps
T221 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.74546436 May 26 02:51:38 PM PDT 24 May 26 02:51:40 PM PDT 24 70075977 ps
T62 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3967164546 May 26 02:51:48 PM PDT 24 May 26 02:52:11 PM PDT 24 3141601216 ps
T222 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3949290994 May 26 02:51:36 PM PDT 24 May 26 02:51:42 PM PDT 24 1394956501 ps
T223 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.789550542 May 26 02:51:25 PM PDT 24 May 26 02:51:29 PM PDT 24 50240742 ps
T224 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1561235557 May 26 02:51:18 PM PDT 24 May 26 02:51:22 PM PDT 24 1012994387 ps
T225 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.3307882183 May 26 02:51:42 PM PDT 24 May 26 02:51:47 PM PDT 24 726521159 ps
T226 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.2699130639 May 26 02:51:47 PM PDT 24 May 26 02:51:52 PM PDT 24 117261316 ps
T227 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.2366393497 May 26 02:51:34 PM PDT 24 May 26 02:51:37 PM PDT 24 798465929 ps
T228 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.2596019951 May 26 02:51:56 PM PDT 24 May 26 02:52:07 PM PDT 24 2040488034 ps
T229 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1203543253 May 26 02:51:37 PM PDT 24 May 26 02:51:41 PM PDT 24 83449383 ps
T230 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.107218204 May 26 02:51:46 PM PDT 24 May 26 02:51:56 PM PDT 24 275056820 ps
T93 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2416734708 May 26 02:51:27 PM PDT 24 May 26 02:51:31 PM PDT 24 72941373 ps
T231 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.1018990421 May 26 02:51:29 PM PDT 24 May 26 02:51:31 PM PDT 24 166280081 ps
T232 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.843311374 May 26 02:51:47 PM PDT 24 May 26 02:51:51 PM PDT 24 42717388 ps
T233 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.340175106 May 26 02:51:44 PM PDT 24 May 26 02:51:48 PM PDT 24 46676108 ps
T94 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3286759079 May 26 02:51:28 PM PDT 24 May 26 02:51:31 PM PDT 24 447903113 ps
T234 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1052968445 May 26 02:51:46 PM PDT 24 May 26 02:51:52 PM PDT 24 419648730 ps
T58 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.3647136271 May 26 02:51:17 PM PDT 24 May 26 02:51:20 PM PDT 24 32193199 ps
T235 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2127674714 May 26 02:51:29 PM PDT 24 May 26 02:51:37 PM PDT 24 1578349894 ps
T236 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.1289204829 May 26 02:51:39 PM PDT 24 May 26 02:51:43 PM PDT 24 140666892 ps
T237 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2671362619 May 26 02:51:28 PM PDT 24 May 26 02:51:31 PM PDT 24 21434711 ps
T238 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2202323624 May 26 02:51:37 PM PDT 24 May 26 02:51:57 PM PDT 24 7557765198 ps
T95 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.2661079430 May 26 02:51:30 PM PDT 24 May 26 02:52:26 PM PDT 24 5396673562 ps
T63 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.100640798 May 26 02:51:26 PM PDT 24 May 26 02:51:37 PM PDT 24 340629393 ps
T239 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.4253868669 May 26 02:51:38 PM PDT 24 May 26 02:51:41 PM PDT 24 66441326 ps
T240 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.2887008336 May 26 02:51:18 PM PDT 24 May 26 02:51:24 PM PDT 24 1764785647 ps
T241 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3595303729 May 26 02:51:18 PM PDT 24 May 26 02:51:24 PM PDT 24 146681843 ps
T242 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.3722482602 May 26 02:51:22 PM PDT 24 May 26 02:51:24 PM PDT 24 50936185 ps
T243 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3087505187 May 26 02:51:42 PM PDT 24 May 26 02:51:43 PM PDT 24 328361155 ps
T244 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.2290492635 May 26 02:51:21 PM PDT 24 May 26 02:51:31 PM PDT 24 651842138 ps
T245 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.4286534460 May 26 02:51:36 PM PDT 24 May 26 02:51:42 PM PDT 24 517307086 ps
T246 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.3277902558 May 26 02:51:43 PM PDT 24 May 26 02:51:45 PM PDT 24 35337172 ps
T247 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.1700148253 May 26 02:51:55 PM PDT 24 May 26 02:52:09 PM PDT 24 1990291487 ps
T248 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.833129693 May 26 02:51:18 PM PDT 24 May 26 02:51:22 PM PDT 24 93694287 ps
T41 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.3005805621 May 26 02:51:16 PM PDT 24 May 26 02:51:20 PM PDT 24 1566115659 ps
T249 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.3030366747 May 26 02:51:55 PM PDT 24 May 26 02:52:05 PM PDT 24 2651690162 ps
T57 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.1848258259 May 26 02:51:46 PM PDT 24 May 26 02:52:10 PM PDT 24 5179418054 ps
T86 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.3389600902 May 26 02:51:21 PM PDT 24 May 26 02:52:42 PM PDT 24 8425265229 ps
T250 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.1893343344 May 26 02:51:55 PM PDT 24 May 26 02:51:59 PM PDT 24 302594440 ps
T251 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.3051988916 May 26 02:51:35 PM PDT 24 May 26 02:51:39 PM PDT 24 299258919 ps
T252 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.3480714930 May 26 02:51:25 PM PDT 24 May 26 02:51:31 PM PDT 24 648507176 ps
T113 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.620223058 May 26 02:51:45 PM PDT 24 May 26 02:51:59 PM PDT 24 1248639714 ps
T253 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.1768202038 May 26 02:51:24 PM PDT 24 May 26 02:51:28 PM PDT 24 1160103184 ps
T254 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2639354521 May 26 02:51:17 PM PDT 24 May 26 02:51:22 PM PDT 24 435023003 ps
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