Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
74.74 90.63 76.24 86.29 60.26 77.17 98.20 34.39


Total test records in report: 275
tests.html | tests1.html | tests2.html | tests3.html | tests4.html
T251 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3848019143 May 28 01:02:44 PM PDT 24 May 28 01:02:48 PM PDT 24 61400692 ps
T252 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.3346000371 May 28 01:02:44 PM PDT 24 May 28 01:02:48 PM PDT 24 380677976 ps
T253 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2557135011 May 28 01:02:30 PM PDT 24 May 28 01:02:34 PM PDT 24 75348589 ps
T254 /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.1796597116 May 28 01:02:57 PM PDT 24 May 28 01:03:20 PM PDT 24 4975654581 ps
T255 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.1263726545 May 28 01:02:50 PM PDT 24 May 28 01:02:58 PM PDT 24 138193115 ps
T256 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2919155129 May 28 01:02:44 PM PDT 24 May 28 01:02:48 PM PDT 24 166179806 ps
T257 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3985734415 May 28 01:03:04 PM PDT 24 May 28 01:03:09 PM PDT 24 58332734 ps
T258 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.508424842 May 28 01:02:53 PM PDT 24 May 28 01:03:00 PM PDT 24 91577201 ps
T259 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.458742420 May 28 01:02:57 PM PDT 24 May 28 01:03:03 PM PDT 24 68505769 ps
T260 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.1380756522 May 28 01:02:48 PM PDT 24 May 28 01:02:55 PM PDT 24 77675799 ps
T261 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1651874472 May 28 01:03:10 PM PDT 24 May 28 01:03:18 PM PDT 24 279307787 ps
T262 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1288941796 May 28 01:02:32 PM PDT 24 May 28 01:02:44 PM PDT 24 930828997 ps
T263 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.240704661 May 28 01:02:31 PM PDT 24 May 28 01:02:36 PM PDT 24 67247203 ps
T264 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.1186706166 May 28 01:03:03 PM PDT 24 May 28 01:03:09 PM PDT 24 111704129 ps
T265 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3701858222 May 28 01:03:01 PM PDT 24 May 28 01:03:09 PM PDT 24 212409645 ps
T266 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.1692563737 May 28 01:02:42 PM PDT 24 May 28 01:02:45 PM PDT 24 84629284 ps
T267 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.2051632939 May 28 01:03:16 PM PDT 24 May 28 01:03:30 PM PDT 24 259136901 ps
T268 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2061273626 May 28 01:02:58 PM PDT 24 May 28 01:03:10 PM PDT 24 4000957824 ps
T269 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.4170030679 May 28 01:03:04 PM PDT 24 May 28 01:03:12 PM PDT 24 1044437829 ps
T270 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.3760977881 May 28 01:03:05 PM PDT 24 May 28 01:03:11 PM PDT 24 96657985 ps
T271 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.1036379194 May 28 01:03:00 PM PDT 24 May 28 01:03:09 PM PDT 24 1883579870 ps
T272 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2231990074 May 28 01:02:56 PM PDT 24 May 28 01:03:09 PM PDT 24 388978678 ps
T273 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.989365552 May 28 01:02:40 PM PDT 24 May 28 01:02:43 PM PDT 24 19943840 ps
T274 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.2551504499 May 28 01:02:46 PM PDT 24 May 28 01:02:54 PM PDT 24 410229667 ps
T275 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.4283374351 May 28 01:03:00 PM PDT 24 May 28 01:03:06 PM PDT 24 44632416 ps

Test location /workspace/coverage/default/8.rv_dm_alert_test.3315515811
Short name T16
Test name
Test status
Simulation time 58606044 ps
CPU time 0.77 seconds
Started May 28 01:04:37 PM PDT 24
Finished May 28 01:04:44 PM PDT 24
Peak memory 204576 kb
Host smart-6d90f935-6140-4d53-98b5-31ee8afb6cc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315515811 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.3315515811
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all.426911935
Short name T7
Test name
Test status
Simulation time 7321228258 ps
CPU time 22.14 seconds
Started May 28 01:04:20 PM PDT 24
Finished May 28 01:04:48 PM PDT 24
Peak memory 204828 kb
Host smart-4aa810a8-b834-43bc-a9ab-7cad1f549001
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426911935 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.426911935
Directory /workspace/2.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/20.rv_dm_tap_fsm_rand_reset.1724675547
Short name T60
Test name
Test status
Simulation time 24776448950 ps
CPU time 26.53 seconds
Started May 28 01:03:13 PM PDT 24
Finished May 28 01:03:48 PM PDT 24
Peak memory 229704 kb
Host smart-e749b401-d0f2-47f7-a37f-5e7845d69fc8
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724675547 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 20.rv_dm_tap_fsm_rand_reset.1724675547
Directory /workspace/20.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/13.rv_dm_stress_all.938201681
Short name T9
Test name
Test status
Simulation time 2548161119 ps
CPU time 8.24 seconds
Started May 28 01:04:27 PM PDT 24
Finished May 28 01:04:44 PM PDT 24
Peak memory 204908 kb
Host smart-eacb02bf-5741-4283-84ec-dddd0601a269
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938201681 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.938201681
Directory /workspace/13.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1823336488
Short name T32
Test name
Test status
Simulation time 732645559 ps
CPU time 8.37 seconds
Started May 28 01:02:54 PM PDT 24
Finished May 28 01:03:08 PM PDT 24
Peak memory 213216 kb
Host smart-b71ce8e3-d6ab-4963-a468-440ec25e2560
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823336488 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.1823336488
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.3333134476
Short name T36
Test name
Test status
Simulation time 771111733 ps
CPU time 3.12 seconds
Started May 28 01:02:32 PM PDT 24
Finished May 28 01:02:38 PM PDT 24
Peak memory 205012 kb
Host smart-4f3e522e-de41-431d-a029-18087b4776cd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333134476 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.3333134476
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3698606175
Short name T71
Test name
Test status
Simulation time 109233509 ps
CPU time 4.42 seconds
Started May 28 01:02:57 PM PDT 24
Finished May 28 01:03:06 PM PDT 24
Peak memory 213280 kb
Host smart-fafc483e-d846-42f0-91bf-c1e6f21ca6de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698606175 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.3698606175
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.1756789970
Short name T12
Test name
Test status
Simulation time 34470198 ps
CPU time 0.76 seconds
Started May 28 01:04:04 PM PDT 24
Finished May 28 01:04:07 PM PDT 24
Peak memory 204456 kb
Host smart-68024398-ea25-40ac-83be-ff4ccba3a5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756789970 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.1756789970
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.1206388583
Short name T50
Test name
Test status
Simulation time 29663047844 ps
CPU time 27.92 seconds
Started May 28 01:02:52 PM PDT 24
Finished May 28 01:03:25 PM PDT 24
Peak memory 221528 kb
Host smart-2d5abf19-4232-4064-a064-3ed21e3296ab
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206388583 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.1206388583
Directory /workspace/9.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.311896411
Short name T72
Test name
Test status
Simulation time 9632942953 ps
CPU time 75.4 seconds
Started May 28 01:02:30 PM PDT 24
Finished May 28 01:03:48 PM PDT 24
Peak memory 205080 kb
Host smart-c8234e82-de72-4031-97ff-d5f26f013741
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311896411 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.311896411
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.56368757
Short name T21
Test name
Test status
Simulation time 57463692 ps
CPU time 0.74 seconds
Started May 28 01:04:15 PM PDT 24
Finished May 28 01:04:20 PM PDT 24
Peak memory 204576 kb
Host smart-cf2bd3ad-32c9-4f8f-9d05-a307535a20e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56368757 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.56368757
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.3006229748
Short name T108
Test name
Test status
Simulation time 773319876 ps
CPU time 15.68 seconds
Started May 28 01:02:45 PM PDT 24
Finished May 28 01:03:04 PM PDT 24
Peak memory 213260 kb
Host smart-12e707bd-ed1f-439c-9591-7917adff1a17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006229748 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.3006229748
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1754920360
Short name T40
Test name
Test status
Simulation time 23142979643 ps
CPU time 39.69 seconds
Started May 28 01:02:31 PM PDT 24
Finished May 28 01:03:14 PM PDT 24
Peak memory 205000 kb
Host smart-94f6e75c-d5eb-4cb7-bfbb-840c48452b71
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754920360 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.rv_dm_jtag_dmi_csr_bit_bash.1754920360
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.2734524749
Short name T22
Test name
Test status
Simulation time 127923043 ps
CPU time 1.05 seconds
Started May 28 01:04:06 PM PDT 24
Finished May 28 01:04:10 PM PDT 24
Peak memory 228176 kb
Host smart-ba884713-7f5b-4927-a154-e45f73ce1fd6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734524749 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.2734524749
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.3463810157
Short name T14
Test name
Test status
Simulation time 27859301 ps
CPU time 0.83 seconds
Started May 28 01:04:23 PM PDT 24
Finished May 28 01:04:40 PM PDT 24
Peak memory 212856 kb
Host smart-0abcd650-af46-453d-b4fa-4407c374fea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463810157 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.3463810157
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.1045256694
Short name T120
Test name
Test status
Simulation time 730157284 ps
CPU time 15.61 seconds
Started May 28 01:02:56 PM PDT 24
Finished May 28 01:03:17 PM PDT 24
Peak memory 221296 kb
Host smart-071becbf-fc44-4780-ad57-e56d4b602cd9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045256694 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.1045256694
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.2285225474
Short name T8
Test name
Test status
Simulation time 116051519 ps
CPU time 0.92 seconds
Started May 28 01:04:25 PM PDT 24
Finished May 28 01:04:35 PM PDT 24
Peak memory 204668 kb
Host smart-f82b73fd-80ef-4137-9524-751d4dd8ebff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285225474 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.2285225474
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.1592350369
Short name T29
Test name
Test status
Simulation time 3073675180 ps
CPU time 9 seconds
Started May 28 01:03:01 PM PDT 24
Finished May 28 01:03:14 PM PDT 24
Peak memory 221428 kb
Host smart-6139e78c-2f94-4adb-a534-28875451eaa3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592350369 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.1592350369
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.4294535282
Short name T89
Test name
Test status
Simulation time 16540529493 ps
CPU time 75.08 seconds
Started May 28 01:02:47 PM PDT 24
Finished May 28 01:04:07 PM PDT 24
Peak memory 213292 kb
Host smart-2d39010f-e202-4cc7-9ee5-fde6347b5615
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294535282 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.4294535282
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3509550833
Short name T62
Test name
Test status
Simulation time 1059109677 ps
CPU time 15.55 seconds
Started May 28 01:03:03 PM PDT 24
Finished May 28 01:03:23 PM PDT 24
Peak memory 213260 kb
Host smart-5f8b4829-4a6d-44c3-b52e-039a4392336a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509550833 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.3
509550833
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.4186606043
Short name T70
Test name
Test status
Simulation time 303838142 ps
CPU time 2.49 seconds
Started May 28 01:02:38 PM PDT 24
Finished May 28 01:02:43 PM PDT 24
Peak memory 213476 kb
Host smart-caf1f43c-d414-4acf-9397-3b3597a34d48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186606043 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.4186606043
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.2510967786
Short name T51
Test name
Test status
Simulation time 50542348 ps
CPU time 0.73 seconds
Started May 28 01:04:37 PM PDT 24
Finished May 28 01:04:44 PM PDT 24
Peak memory 204888 kb
Host smart-a6e380f3-a24f-49d8-92cd-7a437473d2fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510967786 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.2510967786
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.3144590188
Short name T86
Test name
Test status
Simulation time 159488967 ps
CPU time 3.86 seconds
Started May 28 01:02:59 PM PDT 24
Finished May 28 01:03:06 PM PDT 24
Peak memory 205068 kb
Host smart-870a37b7-10a4-4dbc-a6cb-5e2ce2411269
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144590188 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same
_csr_outstanding.3144590188
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.1178068711
Short name T38
Test name
Test status
Simulation time 1271734263 ps
CPU time 3.02 seconds
Started May 28 01:02:45 PM PDT 24
Finished May 28 01:02:53 PM PDT 24
Peak memory 204924 kb
Host smart-c685efed-6a14-4d62-9b06-b2bbf1225b79
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178068711 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.1178068711
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3916980045
Short name T117
Test name
Test status
Simulation time 1891521481 ps
CPU time 17.04 seconds
Started May 28 01:02:23 PM PDT 24
Finished May 28 01:02:41 PM PDT 24
Peak memory 213088 kb
Host smart-0ac0a29b-785e-4599-b86d-2e3ff0d652aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916980045 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.3916980045
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.3592368508
Short name T111
Test name
Test status
Simulation time 1211366253 ps
CPU time 19.84 seconds
Started May 28 01:02:36 PM PDT 24
Finished May 28 01:02:58 PM PDT 24
Peak memory 221288 kb
Host smart-f73f6039-40cc-46e8-acba-4b625fbc3cac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592368508 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.3592368508
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.2153691416
Short name T156
Test name
Test status
Simulation time 34540619 ps
CPU time 0.71 seconds
Started May 28 01:02:57 PM PDT 24
Finished May 28 01:03:02 PM PDT 24
Peak memory 204732 kb
Host smart-c6505148-a69d-4c2c-99e3-29e029441241
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153691416 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
2153691416
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all.262520158
Short name T6
Test name
Test status
Simulation time 867481682 ps
CPU time 3.6 seconds
Started May 28 01:04:19 PM PDT 24
Finished May 28 01:04:28 PM PDT 24
Peak memory 204760 kb
Host smart-44002a06-b79a-4e16-b777-c8e0ebfb9c18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262520158 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.262520158
Directory /workspace/0.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.602094787
Short name T37
Test name
Test status
Simulation time 800314834 ps
CPU time 2.44 seconds
Started May 28 01:02:28 PM PDT 24
Finished May 28 01:02:33 PM PDT 24
Peak memory 205012 kb
Host smart-2a0594ce-8a79-4139-9acd-f483399ecb39
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602094787 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr
_hw_reset.602094787
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1301346953
Short name T59
Test name
Test status
Simulation time 780241840 ps
CPU time 2.08 seconds
Started May 28 01:02:36 PM PDT 24
Finished May 28 01:02:40 PM PDT 24
Peak memory 204908 kb
Host smart-4f88f30a-96d7-4b43-9720-d38c6df9fd6d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301346953 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.1301346953
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.3484829077
Short name T61
Test name
Test status
Simulation time 217559763 ps
CPU time 2.29 seconds
Started May 28 01:02:51 PM PDT 24
Finished May 28 01:02:59 PM PDT 24
Peak memory 219116 kb
Host smart-22b6e38a-3305-4b2b-9be9-a39c78ed6ee5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484829077 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.3484829077
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.1116008675
Short name T228
Test name
Test status
Simulation time 1042681102 ps
CPU time 10.67 seconds
Started May 28 01:03:00 PM PDT 24
Finished May 28 01:03:14 PM PDT 24
Peak memory 213224 kb
Host smart-1f326ff4-a1cc-461c-8978-3da9d066717c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116008675 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.1
116008675
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.2708546413
Short name T218
Test name
Test status
Simulation time 1175310779 ps
CPU time 27.04 seconds
Started May 28 01:02:38 PM PDT 24
Finished May 28 01:03:08 PM PDT 24
Peak memory 213248 kb
Host smart-4d0cf63d-4d34-4cb1-88b9-93c8718383ea
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708546413 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.2708546413
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.137081985
Short name T77
Test name
Test status
Simulation time 22331257473 ps
CPU time 34.41 seconds
Started May 28 01:02:29 PM PDT 24
Finished May 28 01:03:06 PM PDT 24
Peak memory 205080 kb
Host smart-7dfb79f5-56a8-4efb-85e3-2546e0940d51
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137081985 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.137081985
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3773323450
Short name T73
Test name
Test status
Simulation time 146052989 ps
CPU time 1.47 seconds
Started May 28 01:02:37 PM PDT 24
Finished May 28 01:02:40 PM PDT 24
Peak memory 213192 kb
Host smart-e9cb2128-2f2d-470c-8dc6-8febfc315690
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773323450 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.3773323450
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.2606922511
Short name T185
Test name
Test status
Simulation time 2306951465 ps
CPU time 3.3 seconds
Started May 28 01:02:31 PM PDT 24
Finished May 28 01:02:37 PM PDT 24
Peak memory 217612 kb
Host smart-9c569161-f097-443b-a11d-7a0ea656b25d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606922511 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.2606922511
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2075520594
Short name T75
Test name
Test status
Simulation time 87420870 ps
CPU time 1.47 seconds
Started May 28 01:02:30 PM PDT 24
Finished May 28 01:02:34 PM PDT 24
Peak memory 213180 kb
Host smart-b520c93e-4821-4b5f-b752-713013721c98
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075520594 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.2075520594
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.635943838
Short name T207
Test name
Test status
Simulation time 18649825903 ps
CPU time 28 seconds
Started May 28 01:02:45 PM PDT 24
Finished May 28 01:03:16 PM PDT 24
Peak memory 204972 kb
Host smart-6c1f6dc6-c1cb-4a33-911a-fef690de4de8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635943838 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr
_aliasing.635943838
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.794469951
Short name T179
Test name
Test status
Simulation time 34849517232 ps
CPU time 67.69 seconds
Started May 28 01:02:34 PM PDT 24
Finished May 28 01:03:49 PM PDT 24
Peak memory 204904 kb
Host smart-18d18af3-0de2-4fe9-a5f5-dbaa815ce0f2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794469951 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.rv_dm_jtag_dmi_csr_bit_bash.794469951
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2200826493
Short name T159
Test name
Test status
Simulation time 244548200 ps
CPU time 1.7 seconds
Started May 28 01:02:33 PM PDT 24
Finished May 28 01:02:38 PM PDT 24
Peak memory 204924 kb
Host smart-f859002c-517e-4ee8-b572-8ca680fae127
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200826493 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.2
200826493
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2919155129
Short name T256
Test name
Test status
Simulation time 166179806 ps
CPU time 0.8 seconds
Started May 28 01:02:44 PM PDT 24
Finished May 28 01:02:48 PM PDT 24
Peak memory 204668 kb
Host smart-149da7f6-5cc8-4c9c-8fcc-e004dda78d42
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919155129 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.2919155129
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1239124035
Short name T161
Test name
Test status
Simulation time 578894782 ps
CPU time 1.34 seconds
Started May 28 01:02:52 PM PDT 24
Finished May 28 01:02:59 PM PDT 24
Peak memory 204888 kb
Host smart-f940238e-1d96-43dd-ae99-4e363fb8cd51
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239124035 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.1239124035
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3197857761
Short name T180
Test name
Test status
Simulation time 119537102 ps
CPU time 0.82 seconds
Started May 28 01:02:36 PM PDT 24
Finished May 28 01:02:39 PM PDT 24
Peak memory 204768 kb
Host smart-aef69d49-4405-4d29-94a9-3c8818ca7de6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197857761 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.3197857761
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3374955135
Short name T217
Test name
Test status
Simulation time 39251734 ps
CPU time 0.67 seconds
Started May 28 01:02:24 PM PDT 24
Finished May 28 01:02:26 PM PDT 24
Peak memory 204724 kb
Host smart-8c5958fa-6561-4f4d-8fe1-7e29c706c2ae
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374955135 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.3
374955135
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1847690808
Short name T147
Test name
Test status
Simulation time 45890028 ps
CPU time 0.71 seconds
Started May 28 01:02:37 PM PDT 24
Finished May 28 01:02:41 PM PDT 24
Peak memory 204708 kb
Host smart-1a6d71da-da14-48dc-889d-7b8cba04bada
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847690808 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.1847690808
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.1570243078
Short name T151
Test name
Test status
Simulation time 16861751 ps
CPU time 0.76 seconds
Started May 28 01:02:40 PM PDT 24
Finished May 28 01:02:43 PM PDT 24
Peak memory 204700 kb
Host smart-76061b33-b477-4ed7-9c9c-726118b3ccdf
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570243078 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.1570243078
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.3772857540
Short name T106
Test name
Test status
Simulation time 1554139943 ps
CPU time 7.79 seconds
Started May 28 01:02:27 PM PDT 24
Finished May 28 01:02:36 PM PDT 24
Peak memory 205328 kb
Host smart-3e019f21-1a1e-49d5-9fa9-602406359cfe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772857540 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.3772857540
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.638528410
Short name T95
Test name
Test status
Simulation time 4487466355 ps
CPU time 70.56 seconds
Started May 28 01:02:43 PM PDT 24
Finished May 28 01:03:55 PM PDT 24
Peak memory 213256 kb
Host smart-3e1496cd-876f-43c3-a06a-6ac8f14472a4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638528410 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.rv_dm_csr_aliasing.638528410
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.1661356445
Short name T232
Test name
Test status
Simulation time 1424195724 ps
CPU time 53.21 seconds
Started May 28 01:02:42 PM PDT 24
Finished May 28 01:03:37 PM PDT 24
Peak memory 204888 kb
Host smart-682fe86d-e653-4ad8-addf-32b874e0e957
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661356445 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.1661356445
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2013704097
Short name T91
Test name
Test status
Simulation time 57409299 ps
CPU time 1.55 seconds
Started May 28 01:02:34 PM PDT 24
Finished May 28 01:02:38 PM PDT 24
Peak memory 213220 kb
Host smart-3c306973-51bc-47a0-8ef4-94496df5814b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013704097 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.2013704097
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.341634585
Short name T177
Test name
Test status
Simulation time 578635251 ps
CPU time 4.18 seconds
Started May 28 01:02:53 PM PDT 24
Finished May 28 01:03:03 PM PDT 24
Peak memory 221532 kb
Host smart-8c8b706a-8c60-4d83-aeec-9d1f7cdcdd42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341634585 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.341634585
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.1529277663
Short name T223
Test name
Test status
Simulation time 54622286 ps
CPU time 1.46 seconds
Started May 28 01:03:08 PM PDT 24
Finished May 28 01:03:15 PM PDT 24
Peak memory 213276 kb
Host smart-e52db058-21d0-45a3-8bff-bdadfc065b14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529277663 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.1529277663
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2652767485
Short name T210
Test name
Test status
Simulation time 30492262347 ps
CPU time 90.86 seconds
Started May 28 01:02:34 PM PDT 24
Finished May 28 01:04:12 PM PDT 24
Peak memory 204956 kb
Host smart-4174e171-a546-4625-a4b2-329157e955f3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652767485 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.rv_dm_jtag_dmi_csr_bit_bash.2652767485
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.3672509237
Short name T196
Test name
Test status
Simulation time 1681331059 ps
CPU time 6.11 seconds
Started May 28 01:02:32 PM PDT 24
Finished May 28 01:02:41 PM PDT 24
Peak memory 204796 kb
Host smart-8908c286-4ad7-4ad7-871e-7c1e98cd08f0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672509237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.3
672509237
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2140295682
Short name T211
Test name
Test status
Simulation time 116560095 ps
CPU time 0.76 seconds
Started May 28 01:02:46 PM PDT 24
Finished May 28 01:02:52 PM PDT 24
Peak memory 204608 kb
Host smart-07ede206-bfab-4aef-9125-4d0957f593aa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140295682 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.2140295682
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2630725920
Short name T162
Test name
Test status
Simulation time 1089204783 ps
CPU time 3.19 seconds
Started May 28 01:02:29 PM PDT 24
Finished May 28 01:02:35 PM PDT 24
Peak memory 204924 kb
Host smart-10255e61-091d-4cd6-89b9-ac352b405c79
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630725920 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.2630725920
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1817740209
Short name T187
Test name
Test status
Simulation time 104875278 ps
CPU time 0.83 seconds
Started May 28 01:02:30 PM PDT 24
Finished May 28 01:02:34 PM PDT 24
Peak memory 204764 kb
Host smart-222b8768-e9e4-4bc9-b6f1-591c129ea0d7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817740209 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.1817740209
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.240704661
Short name T263
Test name
Test status
Simulation time 67247203 ps
CPU time 0.89 seconds
Started May 28 01:02:31 PM PDT 24
Finished May 28 01:02:36 PM PDT 24
Peak memory 204724 kb
Host smart-cacf3974-c5ba-43d9-8d53-da812dde9441
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240704661 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.240704661
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2651238212
Short name T172
Test name
Test status
Simulation time 17035514 ps
CPU time 0.66 seconds
Started May 28 01:02:39 PM PDT 24
Finished May 28 01:02:42 PM PDT 24
Peak memory 204708 kb
Host smart-b5891d6d-6a43-4b56-86df-252789e924da
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651238212 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.2651238212
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.989365552
Short name T273
Test name
Test status
Simulation time 19943840 ps
CPU time 0.71 seconds
Started May 28 01:02:40 PM PDT 24
Finished May 28 01:02:43 PM PDT 24
Peak memory 204708 kb
Host smart-3d8529e7-e427-42bd-abfe-06769ddc2238
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989365552 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.989365552
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.1497851640
Short name T226
Test name
Test status
Simulation time 797136261 ps
CPU time 3.87 seconds
Started May 28 01:02:31 PM PDT 24
Finished May 28 01:02:38 PM PDT 24
Peak memory 205060 kb
Host smart-af9705dd-76df-48dd-ac7f-b32b1facf792
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497851640 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_
csr_outstanding.1497851640
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.3554661712
Short name T110
Test name
Test status
Simulation time 7369817446 ps
CPU time 21.83 seconds
Started May 28 01:02:28 PM PDT 24
Finished May 28 01:02:53 PM PDT 24
Peak memory 220236 kb
Host smart-6d62756c-d63b-4ccc-8c4a-22e143170a0b
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554661712 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.3554661712
Directory /workspace/1.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1550092622
Short name T164
Test name
Test status
Simulation time 759781161 ps
CPU time 4.13 seconds
Started May 28 01:02:27 PM PDT 24
Finished May 28 01:02:32 PM PDT 24
Peak memory 213112 kb
Host smart-5a4673a9-f88e-40ea-9daa-a08884d5087d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550092622 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.1550092622
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.28624585
Short name T188
Test name
Test status
Simulation time 563116654 ps
CPU time 2.42 seconds
Started May 28 01:02:58 PM PDT 24
Finished May 28 01:03:05 PM PDT 24
Peak memory 217244 kb
Host smart-3878e885-0012-4ef6-bf84-09f730d9286c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28624585 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.28624585
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.4283374351
Short name T275
Test name
Test status
Simulation time 44632416 ps
CPU time 2.07 seconds
Started May 28 01:03:00 PM PDT 24
Finished May 28 01:03:06 PM PDT 24
Peak memory 218052 kb
Host smart-9f65350c-8d6f-4def-8fb6-7e5d199420e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283374351 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.4283374351
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.446289851
Short name T197
Test name
Test status
Simulation time 1073484085 ps
CPU time 3.04 seconds
Started May 28 01:03:00 PM PDT 24
Finished May 28 01:03:07 PM PDT 24
Peak memory 204896 kb
Host smart-e5ddac2f-e69f-4f4d-9a50-9733f5f6f0c0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446289851 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.446289851
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1569080788
Short name T239
Test name
Test status
Simulation time 54469243 ps
CPU time 0.73 seconds
Started May 28 01:03:11 PM PDT 24
Finished May 28 01:03:18 PM PDT 24
Peak memory 204704 kb
Host smart-41002605-ca6f-48f7-8bf1-2736a3d2a3b6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569080788 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
1569080788
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.909158828
Short name T88
Test name
Test status
Simulation time 208464244 ps
CPU time 3.55 seconds
Started May 28 01:03:00 PM PDT 24
Finished May 28 01:03:07 PM PDT 24
Peak memory 205004 kb
Host smart-34550ccf-7d21-4602-86de-2d74c6293913
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909158828 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same_
csr_outstanding.909158828
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.442585235
Short name T115
Test name
Test status
Simulation time 1055034069 ps
CPU time 15.89 seconds
Started May 28 01:03:03 PM PDT 24
Finished May 28 01:03:23 PM PDT 24
Peak memory 221292 kb
Host smart-c30222b9-0726-4e47-8274-fe5ef4645596
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442585235 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.442585235
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3099635039
Short name T199
Test name
Test status
Simulation time 3864271105 ps
CPU time 3.27 seconds
Started May 28 01:02:55 PM PDT 24
Finished May 28 01:03:03 PM PDT 24
Peak memory 218160 kb
Host smart-74a01d2c-4dda-421a-bf68-da9c3379365d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099635039 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.3099635039
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.1064859750
Short name T85
Test name
Test status
Simulation time 171344386 ps
CPU time 2.49 seconds
Started May 28 01:03:03 PM PDT 24
Finished May 28 01:03:10 PM PDT 24
Peak memory 213252 kb
Host smart-17cb8f47-9c64-481d-8000-ff7a30886afc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064859750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.1064859750
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3221379480
Short name T153
Test name
Test status
Simulation time 930286457 ps
CPU time 2.43 seconds
Started May 28 01:02:54 PM PDT 24
Finished May 28 01:03:02 PM PDT 24
Peak memory 204980 kb
Host smart-6c6d9486-03e6-4cf1-88f4-61190a6ba3f7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221379480 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
3221379480
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.456299372
Short name T166
Test name
Test status
Simulation time 62216847 ps
CPU time 0.84 seconds
Started May 28 01:02:51 PM PDT 24
Finished May 28 01:02:58 PM PDT 24
Peak memory 204712 kb
Host smart-3e2a36c2-b9bc-4efb-97ff-2ff2c23d36bc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456299372 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.456299372
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.3922418362
Short name T113
Test name
Test status
Simulation time 185077313 ps
CPU time 5.27 seconds
Started May 28 01:03:05 PM PDT 24
Finished May 28 01:03:14 PM PDT 24
Peak memory 213248 kb
Host smart-960e9eed-ad63-4ac8-ad81-52fd671bf5c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922418362 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.3922418362
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3477687326
Short name T119
Test name
Test status
Simulation time 1213054427 ps
CPU time 15.91 seconds
Started May 28 01:02:54 PM PDT 24
Finished May 28 01:03:15 PM PDT 24
Peak memory 221332 kb
Host smart-a279d194-27d2-45de-b9a0-dd0fddb9fa89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477687326 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.3
477687326
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.3047482160
Short name T174
Test name
Test status
Simulation time 5892336748 ps
CPU time 13.11 seconds
Started May 28 01:02:49 PM PDT 24
Finished May 28 01:03:09 PM PDT 24
Peak memory 218292 kb
Host smart-ade470f3-d78e-4ec9-a7fb-d450c762f406
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047482160 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.3047482160
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.233586462
Short name T76
Test name
Test status
Simulation time 113802680 ps
CPU time 1.56 seconds
Started May 28 01:02:44 PM PDT 24
Finished May 28 01:02:47 PM PDT 24
Peak memory 213204 kb
Host smart-86bdae29-af9c-480e-9362-7a8caeebad3f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233586462 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.233586462
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1651874472
Short name T261
Test name
Test status
Simulation time 279307787 ps
CPU time 1.36 seconds
Started May 28 01:03:10 PM PDT 24
Finished May 28 01:03:18 PM PDT 24
Peak memory 204888 kb
Host smart-88a032ab-5863-4352-811b-b6a9a0642f70
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651874472 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
1651874472
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.4101583037
Short name T92
Test name
Test status
Simulation time 161405401 ps
CPU time 3.68 seconds
Started May 28 01:02:58 PM PDT 24
Finished May 28 01:03:06 PM PDT 24
Peak memory 204988 kb
Host smart-83276af6-1f5f-4729-ac01-36c8d55e6868
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101583037 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.4101583037
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2231990074
Short name T272
Test name
Test status
Simulation time 388978678 ps
CPU time 8.2 seconds
Started May 28 01:02:56 PM PDT 24
Finished May 28 01:03:09 PM PDT 24
Peak memory 221392 kb
Host smart-51a6aabb-83a1-410e-8c07-4feb8ba3776b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231990074 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.2
231990074
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3701858222
Short name T265
Test name
Test status
Simulation time 212409645 ps
CPU time 4.14 seconds
Started May 28 01:03:01 PM PDT 24
Finished May 28 01:03:09 PM PDT 24
Peak memory 221492 kb
Host smart-3e69ae69-c757-4529-bb05-5e66706097e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701858222 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.3701858222
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.3201357587
Short name T152
Test name
Test status
Simulation time 1277747724 ps
CPU time 4.82 seconds
Started May 28 01:02:55 PM PDT 24
Finished May 28 01:03:05 PM PDT 24
Peak memory 204964 kb
Host smart-4b398115-6c40-480f-8bd3-d9e2c16af4c5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201357587 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
3201357587
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.508424842
Short name T258
Test name
Test status
Simulation time 91577201 ps
CPU time 0.72 seconds
Started May 28 01:02:53 PM PDT 24
Finished May 28 01:03:00 PM PDT 24
Peak memory 204720 kb
Host smart-114b364c-fc7a-4031-b681-f1a17726bceb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508424842 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.508424842
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.1148213488
Short name T249
Test name
Test status
Simulation time 99224045 ps
CPU time 3.53 seconds
Started May 28 01:02:59 PM PDT 24
Finished May 28 01:03:08 PM PDT 24
Peak memory 205052 kb
Host smart-a6806738-9e59-43a0-92b7-bb0d5aecc75d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148213488 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.1148213488
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.3035981835
Short name T242
Test name
Test status
Simulation time 59245701 ps
CPU time 3.65 seconds
Started May 28 01:03:13 PM PDT 24
Finished May 28 01:03:25 PM PDT 24
Peak memory 213316 kb
Host smart-ceb29875-374e-4c5d-8844-febc3965bb43
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035981835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.3035981835
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2574042860
Short name T116
Test name
Test status
Simulation time 2437730801 ps
CPU time 16.36 seconds
Started May 28 01:02:59 PM PDT 24
Finished May 28 01:03:19 PM PDT 24
Peak memory 221496 kb
Host smart-44997741-14de-4916-b1d6-31babe055f3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574042860 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.2
574042860
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.1186706166
Short name T264
Test name
Test status
Simulation time 111704129 ps
CPU time 2.34 seconds
Started May 28 01:03:03 PM PDT 24
Finished May 28 01:03:09 PM PDT 24
Peak memory 217112 kb
Host smart-61bbc966-390e-4935-a5d1-d524dba15760
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186706166 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.1186706166
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.3091160579
Short name T74
Test name
Test status
Simulation time 167618663 ps
CPU time 2.16 seconds
Started May 28 01:03:04 PM PDT 24
Finished May 28 01:03:10 PM PDT 24
Peak memory 221420 kb
Host smart-388ec7aa-3bc4-4cf6-ab28-c2b4849e623d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091160579 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.3091160579
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.3688638638
Short name T203
Test name
Test status
Simulation time 1696076777 ps
CPU time 2.41 seconds
Started May 28 01:03:08 PM PDT 24
Finished May 28 01:03:16 PM PDT 24
Peak memory 204920 kb
Host smart-29426ae0-0512-49ec-9821-4a77bfd56616
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688638638 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
3688638638
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.1813829572
Short name T155
Test name
Test status
Simulation time 36938343 ps
CPU time 0.68 seconds
Started May 28 01:03:15 PM PDT 24
Finished May 28 01:03:24 PM PDT 24
Peak memory 204704 kb
Host smart-7867c7c5-ec5a-4e32-befc-ba422b7e9c8b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813829572 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
1813829572
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2999294688
Short name T107
Test name
Test status
Simulation time 588074977 ps
CPU time 4.3 seconds
Started May 28 01:02:55 PM PDT 24
Finished May 28 01:03:05 PM PDT 24
Peak memory 205020 kb
Host smart-88808aa5-cca0-404c-b09b-a2feb655530a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999294688 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.2999294688
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.1608036469
Short name T69
Test name
Test status
Simulation time 317024325 ps
CPU time 2.58 seconds
Started May 28 01:03:09 PM PDT 24
Finished May 28 01:03:17 PM PDT 24
Peak memory 213288 kb
Host smart-328f8f42-3597-4c9d-914a-38e982a942fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608036469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.1608036469
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1199190568
Short name T109
Test name
Test status
Simulation time 1896645959 ps
CPU time 20.57 seconds
Started May 28 01:03:15 PM PDT 24
Finished May 28 01:03:44 PM PDT 24
Peak memory 221388 kb
Host smart-d8b93267-7b4c-4549-ad14-93754b921b0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199190568 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.1
199190568
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.843270852
Short name T195
Test name
Test status
Simulation time 200086685 ps
CPU time 2.34 seconds
Started May 28 01:03:04 PM PDT 24
Finished May 28 01:03:11 PM PDT 24
Peak memory 217560 kb
Host smart-5a53088f-d760-4d3f-b234-44a86e1052d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843270852 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.843270852
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2836679690
Short name T100
Test name
Test status
Simulation time 379512203 ps
CPU time 2.18 seconds
Started May 28 01:03:08 PM PDT 24
Finished May 28 01:03:16 PM PDT 24
Peak memory 219068 kb
Host smart-d42c5d15-236d-45d7-a427-318cc39f35a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836679690 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.2836679690
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.2588673206
Short name T235
Test name
Test status
Simulation time 798314632 ps
CPU time 3.13 seconds
Started May 28 01:03:18 PM PDT 24
Finished May 28 01:03:30 PM PDT 24
Peak memory 204880 kb
Host smart-0272310a-30f2-48a0-be29-6a9b16b8f28d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588673206 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
2588673206
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.499717355
Short name T157
Test name
Test status
Simulation time 97729487 ps
CPU time 0.74 seconds
Started May 28 01:03:09 PM PDT 24
Finished May 28 01:03:16 PM PDT 24
Peak memory 204720 kb
Host smart-97ba1c78-d9ef-4170-813b-32c3a6d06837
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499717355 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.499717355
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.3723908645
Short name T233
Test name
Test status
Simulation time 1475838078 ps
CPU time 4.15 seconds
Started May 28 01:03:00 PM PDT 24
Finished May 28 01:03:08 PM PDT 24
Peak memory 205012 kb
Host smart-7141ae34-8e4a-4ab1-af45-9a004cc2f3e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723908645 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.3723908645
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tap_fsm_rand_reset.3142729597
Short name T26
Test name
Test status
Simulation time 10784321965 ps
CPU time 21.65 seconds
Started May 28 01:03:10 PM PDT 24
Finished May 28 01:03:38 PM PDT 24
Peak memory 215000 kb
Host smart-43d9b3ba-d103-4538-a56a-7fede54e9a41
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142729597 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rv_dm_tap_fsm_rand_reset.3142729597
Directory /workspace/15.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.640427981
Short name T246
Test name
Test status
Simulation time 3232936816 ps
CPU time 19.11 seconds
Started May 28 01:03:02 PM PDT 24
Finished May 28 01:03:26 PM PDT 24
Peak memory 213320 kb
Host smart-4c5fc869-09f4-42a0-be62-d039b43a941b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640427981 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.640427981
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.1641304215
Short name T170
Test name
Test status
Simulation time 4585135650 ps
CPU time 5.37 seconds
Started May 28 01:02:53 PM PDT 24
Finished May 28 01:03:04 PM PDT 24
Peak memory 221036 kb
Host smart-353c58ef-01a6-49d2-9840-ced6bb4a6579
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641304215 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.1641304215
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.346761518
Short name T102
Test name
Test status
Simulation time 129681252 ps
CPU time 2.17 seconds
Started May 28 01:02:49 PM PDT 24
Finished May 28 01:02:57 PM PDT 24
Peak memory 213204 kb
Host smart-840beacb-13d1-4a1a-b0a3-5c48b7e27cbe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346761518 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.346761518
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.3231344418
Short name T154
Test name
Test status
Simulation time 613919692 ps
CPU time 1.06 seconds
Started May 28 01:03:07 PM PDT 24
Finished May 28 01:03:13 PM PDT 24
Peak memory 204920 kb
Host smart-722a7b6f-7266-42a0-bc34-a2b49eb169b1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231344418 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
3231344418
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3985734415
Short name T257
Test name
Test status
Simulation time 58332734 ps
CPU time 0.71 seconds
Started May 28 01:03:04 PM PDT 24
Finished May 28 01:03:09 PM PDT 24
Peak memory 204712 kb
Host smart-f29a6ad8-458b-4ad8-8e95-7c3af45bf6e9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985734415 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
3985734415
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3492838120
Short name T229
Test name
Test status
Simulation time 1536281932 ps
CPU time 7.51 seconds
Started May 28 01:03:11 PM PDT 24
Finished May 28 01:03:25 PM PDT 24
Peak memory 205016 kb
Host smart-4b9ccd4a-9887-4fb8-8367-95947e2b314d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492838120 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.3492838120
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.2051632939
Short name T267
Test name
Test status
Simulation time 259136901 ps
CPU time 5.44 seconds
Started May 28 01:03:16 PM PDT 24
Finished May 28 01:03:30 PM PDT 24
Peak memory 213580 kb
Host smart-20681735-16a1-459a-b151-0bcc655f0f31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051632939 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.2051632939
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.1230550962
Short name T30
Test name
Test status
Simulation time 3329084302 ps
CPU time 15.62 seconds
Started May 28 01:03:01 PM PDT 24
Finished May 28 01:03:20 PM PDT 24
Peak memory 221388 kb
Host smart-5c986420-b698-433f-9293-f06e47a306de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230550962 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.1
230550962
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.1529601573
Short name T205
Test name
Test status
Simulation time 4407129644 ps
CPU time 3.65 seconds
Started May 28 01:03:03 PM PDT 24
Finished May 28 01:03:10 PM PDT 24
Peak memory 217452 kb
Host smart-86be5e42-d13a-46c8-9147-4eeabd34514b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529601573 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.1529601573
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.3760977881
Short name T270
Test name
Test status
Simulation time 96657985 ps
CPU time 2.08 seconds
Started May 28 01:03:05 PM PDT 24
Finished May 28 01:03:11 PM PDT 24
Peak memory 218456 kb
Host smart-287b9cc7-44b5-4cc9-a1d6-fa7dbc93751a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760977881 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.3760977881
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.1183521345
Short name T181
Test name
Test status
Simulation time 227882899 ps
CPU time 1.18 seconds
Started May 28 01:03:19 PM PDT 24
Finished May 28 01:03:30 PM PDT 24
Peak memory 205208 kb
Host smart-653f4b70-2f94-40b1-b524-1e1d8e70f2d4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183521345 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
1183521345
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.3423752835
Short name T148
Test name
Test status
Simulation time 58533984 ps
CPU time 0.7 seconds
Started May 28 01:03:04 PM PDT 24
Finished May 28 01:03:09 PM PDT 24
Peak memory 204720 kb
Host smart-a82b8ba1-3ace-4c59-923f-d77507c84fa3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423752835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
3423752835
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3051364619
Short name T79
Test name
Test status
Simulation time 96694302 ps
CPU time 3.78 seconds
Started May 28 01:03:13 PM PDT 24
Finished May 28 01:03:25 PM PDT 24
Peak memory 205012 kb
Host smart-f95b35aa-c7f5-4d34-ab44-33f8116d895e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051364619 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.3051364619
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tap_fsm_rand_reset.608075631
Short name T219
Test name
Test status
Simulation time 16049077830 ps
CPU time 17.64 seconds
Started May 28 01:02:59 PM PDT 24
Finished May 28 01:03:20 PM PDT 24
Peak memory 215212 kb
Host smart-a91722cf-b822-41fc-a66a-4fa114358660
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608075631 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.rv_dm_tap_fsm_rand_reset.608075631
Directory /workspace/17.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.3415726441
Short name T209
Test name
Test status
Simulation time 591293159 ps
CPU time 4.27 seconds
Started May 28 01:03:04 PM PDT 24
Finished May 28 01:03:13 PM PDT 24
Peak memory 213332 kb
Host smart-86e979f5-0ebe-4f25-a794-9b9540ac783b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415726441 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.3415726441
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2395898238
Short name T83
Test name
Test status
Simulation time 1774409441 ps
CPU time 15.2 seconds
Started May 28 01:03:08 PM PDT 24
Finished May 28 01:03:29 PM PDT 24
Peak memory 221316 kb
Host smart-fe4c86d9-6d13-4403-a3c8-2d3efc156d42
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395898238 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.2
395898238
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.4170030679
Short name T269
Test name
Test status
Simulation time 1044437829 ps
CPU time 4.09 seconds
Started May 28 01:03:04 PM PDT 24
Finished May 28 01:03:12 PM PDT 24
Peak memory 218360 kb
Host smart-d1beea50-ac6c-4b80-8efc-9166332c1a49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170030679 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.4170030679
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.3400489857
Short name T80
Test name
Test status
Simulation time 91345736 ps
CPU time 2.19 seconds
Started May 28 01:03:17 PM PDT 24
Finished May 28 01:03:28 PM PDT 24
Peak memory 213208 kb
Host smart-0f48609b-bc7b-4f1e-9801-4ec4f736b4e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400489857 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.3400489857
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.3133758469
Short name T146
Test name
Test status
Simulation time 479150345 ps
CPU time 1.65 seconds
Started May 28 01:03:09 PM PDT 24
Finished May 28 01:03:16 PM PDT 24
Peak memory 204888 kb
Host smart-0175dd58-156c-402b-bac9-d2267d153384
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133758469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
3133758469
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2292824348
Short name T150
Test name
Test status
Simulation time 78037961 ps
CPU time 0.74 seconds
Started May 28 01:03:11 PM PDT 24
Finished May 28 01:03:18 PM PDT 24
Peak memory 204720 kb
Host smart-15cc93c6-f8a9-4678-a004-aad342eac49d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292824348 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
2292824348
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.2123179691
Short name T90
Test name
Test status
Simulation time 995933648 ps
CPU time 6.25 seconds
Started May 28 01:03:14 PM PDT 24
Finished May 28 01:03:28 PM PDT 24
Peak memory 204812 kb
Host smart-b2ce44a3-273c-454d-b3c3-dbdc45a705b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123179691 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.2123179691
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tap_fsm_rand_reset.3523465065
Short name T250
Test name
Test status
Simulation time 7455357113 ps
CPU time 27.74 seconds
Started May 28 01:03:15 PM PDT 24
Finished May 28 01:03:51 PM PDT 24
Peak memory 221568 kb
Host smart-0802216c-1a1b-4da3-a483-91c7d9fd7e6d
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523465065 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rv_dm_tap_fsm_rand_reset.3523465065
Directory /workspace/18.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2692109139
Short name T163
Test name
Test status
Simulation time 209189887 ps
CPU time 4.72 seconds
Started May 28 01:03:12 PM PDT 24
Finished May 28 01:03:25 PM PDT 24
Peak memory 213280 kb
Host smart-a425c1e7-2a28-441d-8f54-5c04c413d6d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692109139 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.2692109139
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1768008731
Short name T183
Test name
Test status
Simulation time 149196328 ps
CPU time 3.69 seconds
Started May 28 01:03:02 PM PDT 24
Finished May 28 01:03:10 PM PDT 24
Peak memory 221376 kb
Host smart-11848368-8058-4f00-a002-924a42a38c45
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768008731 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.1768008731
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.2883887104
Short name T84
Test name
Test status
Simulation time 151993019 ps
CPU time 2.08 seconds
Started May 28 01:03:20 PM PDT 24
Finished May 28 01:03:32 PM PDT 24
Peak memory 219192 kb
Host smart-621c2e56-7a4d-4a2e-a906-d9c70fd3009c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883887104 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.2883887104
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.3762261352
Short name T176
Test name
Test status
Simulation time 396096645 ps
CPU time 1.43 seconds
Started May 28 01:03:16 PM PDT 24
Finished May 28 01:03:26 PM PDT 24
Peak memory 204896 kb
Host smart-26569139-b838-4433-a485-72ec353323bb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762261352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
3762261352
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.3367694106
Short name T64
Test name
Test status
Simulation time 29790148 ps
CPU time 0.73 seconds
Started May 28 01:03:08 PM PDT 24
Finished May 28 01:03:15 PM PDT 24
Peak memory 204720 kb
Host smart-9fa55314-046c-40ea-a04d-ac38110b6406
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367694106 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
3367694106
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.3083132434
Short name T104
Test name
Test status
Simulation time 1016035454 ps
CPU time 4.14 seconds
Started May 28 01:03:00 PM PDT 24
Finished May 28 01:03:08 PM PDT 24
Peak memory 205016 kb
Host smart-b61ec93a-ce8d-481c-999a-ef8ecbd137ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083132434 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.3083132434
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.70914617
Short name T221
Test name
Test status
Simulation time 120945066 ps
CPU time 3.21 seconds
Started May 28 01:03:03 PM PDT 24
Finished May 28 01:03:11 PM PDT 24
Peak memory 213288 kb
Host smart-bb42a1f5-a338-49ef-b511-7689eadea218
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70914617 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.70914617
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.3629495277
Short name T97
Test name
Test status
Simulation time 3879812032 ps
CPU time 32.16 seconds
Started May 28 01:02:31 PM PDT 24
Finished May 28 01:03:06 PM PDT 24
Peak memory 214276 kb
Host smart-5616f53a-a7c4-4c8c-bbae-376690492e5e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629495277 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.3629495277
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.4288277898
Short name T78
Test name
Test status
Simulation time 93622953 ps
CPU time 1.51 seconds
Started May 28 01:02:28 PM PDT 24
Finished May 28 01:02:32 PM PDT 24
Peak memory 213216 kb
Host smart-777fed7b-76f1-4d6b-ab50-7f77cbfb9aaf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288277898 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.4288277898
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3000932016
Short name T245
Test name
Test status
Simulation time 68505966 ps
CPU time 2.21 seconds
Started May 28 01:02:47 PM PDT 24
Finished May 28 01:02:55 PM PDT 24
Peak memory 216848 kb
Host smart-d14d5757-d76e-403c-8a1f-ab7c931bed20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000932016 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.3000932016
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.3947557191
Short name T212
Test name
Test status
Simulation time 94401778 ps
CPU time 1.6 seconds
Started May 28 01:02:32 PM PDT 24
Finished May 28 01:02:37 PM PDT 24
Peak memory 213184 kb
Host smart-b91ece04-99eb-402a-92e9-2c74c70c7183
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947557191 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.3947557191
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2537482958
Short name T225
Test name
Test status
Simulation time 5238667094 ps
CPU time 14.8 seconds
Started May 28 01:02:38 PM PDT 24
Finished May 28 01:02:55 PM PDT 24
Peak memory 205012 kb
Host smart-41202cdf-a0d0-409a-be15-9fc35a35a39c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537482958 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.2537482958
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.3794480809
Short name T41
Test name
Test status
Simulation time 6130109668 ps
CPU time 29.02 seconds
Started May 28 01:02:33 PM PDT 24
Finished May 28 01:03:05 PM PDT 24
Peak memory 204960 kb
Host smart-5bdb8556-3dfa-4504-8147-46b1ab09fb4e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794480809 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.rv_dm_jtag_dmi_csr_bit_bash.3794480809
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.4172795486
Short name T39
Test name
Test status
Simulation time 1787341762 ps
CPU time 5.74 seconds
Started May 28 01:02:44 PM PDT 24
Finished May 28 01:02:54 PM PDT 24
Peak memory 204992 kb
Host smart-95e58d2c-993a-4267-86e5-b4a2488c4cd1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172795486 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.4172795486
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1531344478
Short name T238
Test name
Test status
Simulation time 410599512 ps
CPU time 1.35 seconds
Started May 28 01:02:32 PM PDT 24
Finished May 28 01:02:37 PM PDT 24
Peak memory 204924 kb
Host smart-a490c3eb-076f-49d5-a48e-e352525e1ff0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531344478 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.1
531344478
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.1380756522
Short name T260
Test name
Test status
Simulation time 77675799 ps
CPU time 0.87 seconds
Started May 28 01:02:48 PM PDT 24
Finished May 28 01:02:55 PM PDT 24
Peak memory 204712 kb
Host smart-299daefa-87e6-478e-b3b9-101cbe45bc09
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380756522 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_aliasing.1380756522
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.2239297603
Short name T204
Test name
Test status
Simulation time 5657988531 ps
CPU time 17.32 seconds
Started May 28 01:02:41 PM PDT 24
Finished May 28 01:03:00 PM PDT 24
Peak memory 204936 kb
Host smart-68b6a8a8-43c3-489b-bb7f-3acb9b35bd48
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239297603 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.2239297603
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2408413023
Short name T25
Test name
Test status
Simulation time 137365401 ps
CPU time 0.84 seconds
Started May 28 01:02:48 PM PDT 24
Finished May 28 01:02:55 PM PDT 24
Peak memory 204780 kb
Host smart-d58c1874-5156-44a6-a425-4767b8e3b3c1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408413023 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.2408413023
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2309869030
Short name T241
Test name
Test status
Simulation time 47948191 ps
CPU time 0.71 seconds
Started May 28 01:02:37 PM PDT 24
Finished May 28 01:02:40 PM PDT 24
Peak memory 204720 kb
Host smart-c95a5872-6766-499d-990e-e4b728a673e5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309869030 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.2
309869030
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1728525608
Short name T173
Test name
Test status
Simulation time 48106345 ps
CPU time 0.65 seconds
Started May 28 01:02:40 PM PDT 24
Finished May 28 01:02:43 PM PDT 24
Peak memory 204600 kb
Host smart-f569d4e9-79d5-4d13-95b8-8f2ca76cf9f6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728525608 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.1728525608
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.3754021361
Short name T182
Test name
Test status
Simulation time 49208717 ps
CPU time 0.67 seconds
Started May 28 01:02:48 PM PDT 24
Finished May 28 01:02:54 PM PDT 24
Peak memory 204724 kb
Host smart-ad5f4635-9199-467a-83b5-633562d853bd
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754021361 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.3754021361
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3702404085
Short name T231
Test name
Test status
Simulation time 230370709 ps
CPU time 4.11 seconds
Started May 28 01:02:53 PM PDT 24
Finished May 28 01:03:03 PM PDT 24
Peak memory 205016 kb
Host smart-7b8f6dfa-427b-4f68-81fe-17bb1753c268
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702404085 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.3702404085
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/21.rv_dm_tap_fsm_rand_reset.1079337009
Short name T82
Test name
Test status
Simulation time 20781478713 ps
CPU time 39.66 seconds
Started May 28 01:03:17 PM PDT 24
Finished May 28 01:04:05 PM PDT 24
Peak memory 229716 kb
Host smart-59155d1a-fbcb-4c79-8015-a936b21a2189
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079337009 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 21.rv_dm_tap_fsm_rand_reset.1079337009
Directory /workspace/21.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/22.rv_dm_tap_fsm_rand_reset.1155533233
Short name T213
Test name
Test status
Simulation time 7927776379 ps
CPU time 15.7 seconds
Started May 28 01:03:14 PM PDT 24
Finished May 28 01:03:38 PM PDT 24
Peak memory 220812 kb
Host smart-a5af3140-b464-4506-8876-56ff73866bf8
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155533233 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 22.rv_dm_tap_fsm_rand_reset.1155533233
Directory /workspace/22.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/24.rv_dm_tap_fsm_rand_reset.2256077616
Short name T206
Test name
Test status
Simulation time 7037204983 ps
CPU time 25.85 seconds
Started May 28 01:03:14 PM PDT 24
Finished May 28 01:03:49 PM PDT 24
Peak memory 221488 kb
Host smart-c05ab3cf-d847-4b92-be67-9eac56d49589
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256077616 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 24.rv_dm_tap_fsm_rand_reset.2256077616
Directory /workspace/24.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/27.rv_dm_tap_fsm_rand_reset.2715277644
Short name T28
Test name
Test status
Simulation time 5045884791 ps
CPU time 12.08 seconds
Started May 28 01:03:07 PM PDT 24
Finished May 28 01:03:26 PM PDT 24
Peak memory 218088 kb
Host smart-4dc276aa-6e60-4e9b-9bd9-71ed7a8869f7
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715277644 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 27.rv_dm_tap_fsm_rand_reset.2715277644
Directory /workspace/27.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.3367541115
Short name T240
Test name
Test status
Simulation time 7709598847 ps
CPU time 31.55 seconds
Started May 28 01:02:45 PM PDT 24
Finished May 28 01:03:22 PM PDT 24
Peak memory 205052 kb
Host smart-5d823490-05f1-4690-9f34-7125e228369d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367541115 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.3367541115
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.3904382344
Short name T214
Test name
Test status
Simulation time 1584322557 ps
CPU time 27.81 seconds
Started May 28 01:02:50 PM PDT 24
Finished May 28 01:03:24 PM PDT 24
Peak memory 204992 kb
Host smart-702b5c17-7065-4f8b-bf0b-d9ebba2435f4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904382344 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.3904382344
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.2937951500
Short name T191
Test name
Test status
Simulation time 122798482 ps
CPU time 2.41 seconds
Started May 28 01:02:38 PM PDT 24
Finished May 28 01:02:43 PM PDT 24
Peak memory 213092 kb
Host smart-5225d553-e364-4ee3-97a1-d252ea99200c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937951500 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.2937951500
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1975248722
Short name T171
Test name
Test status
Simulation time 261762204 ps
CPU time 3.78 seconds
Started May 28 01:02:49 PM PDT 24
Finished May 28 01:02:59 PM PDT 24
Peak memory 218596 kb
Host smart-5b8c1a84-e2de-41de-86b9-825e4642434d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975248722 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.1975248722
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.1263726545
Short name T255
Test name
Test status
Simulation time 138193115 ps
CPU time 2.05 seconds
Started May 28 01:02:50 PM PDT 24
Finished May 28 01:02:58 PM PDT 24
Peak memory 218104 kb
Host smart-1a46fb96-fce8-4fbc-968e-706847ed6c07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263726545 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.1263726545
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.3418056844
Short name T192
Test name
Test status
Simulation time 15421422286 ps
CPU time 52.26 seconds
Started May 28 01:02:32 PM PDT 24
Finished May 28 01:03:28 PM PDT 24
Peak memory 204924 kb
Host smart-7e0d151b-82f4-405c-8233-b844fb4704f8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418056844 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.3418056844
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.2551504499
Short name T274
Test name
Test status
Simulation time 410229667 ps
CPU time 2.55 seconds
Started May 28 01:02:46 PM PDT 24
Finished May 28 01:02:54 PM PDT 24
Peak memory 204896 kb
Host smart-a338089e-2105-4e65-8d4c-4cab65734aa4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551504499 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.2
551504499
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3848019143
Short name T251
Test name
Test status
Simulation time 61400692 ps
CPU time 0.75 seconds
Started May 28 01:02:44 PM PDT 24
Finished May 28 01:02:48 PM PDT 24
Peak memory 204708 kb
Host smart-93d79a86-a99c-4280-927f-acb4ba3c3156
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848019143 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.3848019143
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2083566652
Short name T175
Test name
Test status
Simulation time 3073332905 ps
CPU time 6.06 seconds
Started May 28 01:02:33 PM PDT 24
Finished May 28 01:02:43 PM PDT 24
Peak memory 204968 kb
Host smart-06eb400e-d694-4280-a74b-6ca98262d705
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083566652 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.2083566652
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1858496190
Short name T149
Test name
Test status
Simulation time 36632272 ps
CPU time 0.8 seconds
Started May 28 01:02:29 PM PDT 24
Finished May 28 01:02:33 PM PDT 24
Peak memory 204760 kb
Host smart-ab7f335f-79d5-476d-837d-37d49a4800f1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858496190 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.1858496190
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.3262952088
Short name T178
Test name
Test status
Simulation time 24052822 ps
CPU time 0.71 seconds
Started May 28 01:02:44 PM PDT 24
Finished May 28 01:02:47 PM PDT 24
Peak memory 204720 kb
Host smart-c758dc6b-0c3e-429a-b28d-5cfeeaff6357
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262952088 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.3
262952088
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.987820838
Short name T243
Test name
Test status
Simulation time 36205769 ps
CPU time 0.68 seconds
Started May 28 01:02:32 PM PDT 24
Finished May 28 01:02:37 PM PDT 24
Peak memory 204664 kb
Host smart-19ddc7da-8a5c-4ca4-bbf2-ddc3b4785af9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987820838 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_part
ial_access.987820838
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1766885375
Short name T247
Test name
Test status
Simulation time 44723264 ps
CPU time 0.72 seconds
Started May 28 01:02:45 PM PDT 24
Finished May 28 01:02:49 PM PDT 24
Peak memory 204724 kb
Host smart-1a2f321b-441e-46cd-b342-9b80221a1d7c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766885375 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.1766885375
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2801211823
Short name T94
Test name
Test status
Simulation time 972662617 ps
CPU time 6.48 seconds
Started May 28 01:02:49 PM PDT 24
Finished May 28 01:03:01 PM PDT 24
Peak memory 205020 kb
Host smart-9a0c2949-b6d2-4ba2-a554-bb34e9a496da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801211823 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_
csr_outstanding.2801211823
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2663218139
Short name T169
Test name
Test status
Simulation time 75362055 ps
CPU time 4.5 seconds
Started May 28 01:02:52 PM PDT 24
Finished May 28 01:03:03 PM PDT 24
Peak memory 213280 kb
Host smart-2e473dc8-59b7-4ec7-a27a-7a3ee15f4eca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663218139 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.2663218139
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2430386868
Short name T114
Test name
Test status
Simulation time 463275121 ps
CPU time 9.51 seconds
Started May 28 01:02:35 PM PDT 24
Finished May 28 01:02:47 PM PDT 24
Peak memory 213192 kb
Host smart-04a69057-d877-4ad6-a2db-169a9314dc4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430386868 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.2430386868
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/31.rv_dm_tap_fsm_rand_reset.1141926706
Short name T220
Test name
Test status
Simulation time 11028566136 ps
CPU time 19.97 seconds
Started May 28 01:03:07 PM PDT 24
Finished May 28 01:03:32 PM PDT 24
Peak memory 214724 kb
Host smart-e044d4df-1eec-491e-a44f-8d6dd8472622
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141926706 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 31.rv_dm_tap_fsm_rand_reset.1141926706
Directory /workspace/31.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/33.rv_dm_tap_fsm_rand_reset.3047869306
Short name T27
Test name
Test status
Simulation time 18382135153 ps
CPU time 36.77 seconds
Started May 28 01:03:09 PM PDT 24
Finished May 28 01:03:51 PM PDT 24
Peak memory 221208 kb
Host smart-d52be272-3372-4df9-9693-90a9379fedc3
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047869306 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 33.rv_dm_tap_fsm_rand_reset.3047869306
Directory /workspace/33.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/35.rv_dm_tap_fsm_rand_reset.3060812063
Short name T202
Test name
Test status
Simulation time 21636216223 ps
CPU time 23.13 seconds
Started May 28 01:03:15 PM PDT 24
Finished May 28 01:03:47 PM PDT 24
Peak memory 229640 kb
Host smart-1a4ce91c-3922-4394-981d-5526d81fee92
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060812063 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 35.rv_dm_tap_fsm_rand_reset.3060812063
Directory /workspace/35.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/36.rv_dm_tap_fsm_rand_reset.3409478090
Short name T224
Test name
Test status
Simulation time 14653558059 ps
CPU time 15.57 seconds
Started May 28 01:03:06 PM PDT 24
Finished May 28 01:03:26 PM PDT 24
Peak memory 215400 kb
Host smart-270e1c48-632c-4c60-a1d1-16cc3d025ae3
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409478090 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 36.rv_dm_tap_fsm_rand_reset.3409478090
Directory /workspace/36.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/37.rv_dm_tap_fsm_rand_reset.3591702187
Short name T216
Test name
Test status
Simulation time 30421677030 ps
CPU time 27.4 seconds
Started May 28 01:03:19 PM PDT 24
Finished May 28 01:03:56 PM PDT 24
Peak memory 221472 kb
Host smart-7bc9a8d2-673c-49a9-8340-0c2a2a79171e
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591702187 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 37.rv_dm_tap_fsm_rand_reset.3591702187
Directory /workspace/37.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.3403189598
Short name T99
Test name
Test status
Simulation time 17384141472 ps
CPU time 70.56 seconds
Started May 28 01:03:00 PM PDT 24
Finished May 28 01:04:14 PM PDT 24
Peak memory 204972 kb
Host smart-324a287e-42df-41ba-9a64-f6c389d49046
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403189598 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.3403189598
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.41253442
Short name T93
Test name
Test status
Simulation time 166743793 ps
CPU time 2.19 seconds
Started May 28 01:02:34 PM PDT 24
Finished May 28 01:02:39 PM PDT 24
Peak memory 213256 kb
Host smart-43365967-943a-4b38-b22a-c30f7fa59698
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41253442 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.41253442
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.3341280699
Short name T184
Test name
Test status
Simulation time 275483227 ps
CPU time 3.75 seconds
Started May 28 01:02:49 PM PDT 24
Finished May 28 01:02:59 PM PDT 24
Peak memory 221356 kb
Host smart-70d49d4e-62db-4008-8e77-c50ccdb637d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341280699 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.3341280699
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.3346000371
Short name T252
Test name
Test status
Simulation time 380677976 ps
CPU time 2.1 seconds
Started May 28 01:02:44 PM PDT 24
Finished May 28 01:02:48 PM PDT 24
Peak memory 213236 kb
Host smart-ffc0da98-d00c-48bc-8306-301a6134cdf1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346000371 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.3346000371
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.4279529650
Short name T158
Test name
Test status
Simulation time 14956728941 ps
CPU time 17.23 seconds
Started May 28 01:03:02 PM PDT 24
Finished May 28 01:03:23 PM PDT 24
Peak memory 204868 kb
Host smart-7d4635bb-7992-4289-aa91-c6c313f8bb13
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279529650 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.4279529650
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.4093102634
Short name T248
Test name
Test status
Simulation time 16063455165 ps
CPU time 38.1 seconds
Started May 28 01:02:50 PM PDT 24
Finished May 28 01:03:35 PM PDT 24
Peak memory 204892 kb
Host smart-10b268e4-d71c-4678-9e2d-349ac6c2c7cb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093102634 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.rv_dm_jtag_dmi_csr_bit_bash.4093102634
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.2026227514
Short name T42
Test name
Test status
Simulation time 333561803 ps
CPU time 1.62 seconds
Started May 28 01:02:46 PM PDT 24
Finished May 28 01:02:53 PM PDT 24
Peak memory 204956 kb
Host smart-46fa4a40-9638-4049-9c9b-07f0a94a49c1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026227514 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.2
026227514
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.3755440109
Short name T65
Test name
Test status
Simulation time 69767729 ps
CPU time 0.75 seconds
Started May 28 01:02:32 PM PDT 24
Finished May 28 01:02:37 PM PDT 24
Peak memory 204608 kb
Host smart-1b7c4e5c-7554-4dab-bf0f-6520a6d6975b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755440109 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.3755440109
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.3964738491
Short name T31
Test name
Test status
Simulation time 904961970 ps
CPU time 1.97 seconds
Started May 28 01:02:53 PM PDT 24
Finished May 28 01:03:01 PM PDT 24
Peak memory 204880 kb
Host smart-8d66c89e-bce0-49f2-a547-01c0b6ba0d06
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964738491 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.3964738491
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.4106766104
Short name T194
Test name
Test status
Simulation time 217008947 ps
CPU time 0.85 seconds
Started May 28 01:02:37 PM PDT 24
Finished May 28 01:02:40 PM PDT 24
Peak memory 204768 kb
Host smart-b19f1ef6-4b27-4073-b9ff-406ebf969030
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106766104 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.4106766104
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2557135011
Short name T253
Test name
Test status
Simulation time 75348589 ps
CPU time 0.7 seconds
Started May 28 01:02:30 PM PDT 24
Finished May 28 01:02:34 PM PDT 24
Peak memory 204672 kb
Host smart-3fa881e1-62fc-4719-977b-80e79476c491
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557135011 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.2
557135011
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.3028288325
Short name T198
Test name
Test status
Simulation time 19318341 ps
CPU time 0.69 seconds
Started May 28 01:02:45 PM PDT 24
Finished May 28 01:02:50 PM PDT 24
Peak memory 204524 kb
Host smart-65a95a45-3e06-4239-b963-62cd180b5d40
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028288325 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.3028288325
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.2538738485
Short name T200
Test name
Test status
Simulation time 29705097 ps
CPU time 0.79 seconds
Started May 28 01:02:43 PM PDT 24
Finished May 28 01:02:46 PM PDT 24
Peak memory 204712 kb
Host smart-12a685e3-1fa7-4495-b8a1-6b902b5876aa
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538738485 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.2538738485
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1288941796
Short name T262
Test name
Test status
Simulation time 930828997 ps
CPU time 7.78 seconds
Started May 28 01:02:32 PM PDT 24
Finished May 28 01:02:44 PM PDT 24
Peak memory 205008 kb
Host smart-8ae0e77b-e6a9-440b-ba5d-c286c6839606
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288941796 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.1288941796
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.3277671186
Short name T81
Test name
Test status
Simulation time 13750158449 ps
CPU time 24.01 seconds
Started May 28 01:02:50 PM PDT 24
Finished May 28 01:03:20 PM PDT 24
Peak memory 221320 kb
Host smart-0e6363d1-b51d-408b-9924-a2a08828f6f7
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277671186 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.3277671186
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2529540119
Short name T189
Test name
Test status
Simulation time 110496768 ps
CPU time 2.99 seconds
Started May 28 01:02:40 PM PDT 24
Finished May 28 01:02:46 PM PDT 24
Peak memory 213332 kb
Host smart-f8f89bfc-40da-4638-a7f4-519c5080bc5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529540119 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.2529540119
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3497394059
Short name T112
Test name
Test status
Simulation time 1307119287 ps
CPU time 2.38 seconds
Started May 28 01:02:54 PM PDT 24
Finished May 28 01:03:02 PM PDT 24
Peak memory 214156 kb
Host smart-68e0c763-6d88-4600-a23c-747d5251968c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497394059 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.3497394059
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.1692563737
Short name T266
Test name
Test status
Simulation time 84629284 ps
CPU time 1.43 seconds
Started May 28 01:02:42 PM PDT 24
Finished May 28 01:02:45 PM PDT 24
Peak memory 221380 kb
Host smart-fba5cfee-2133-4d51-94bd-9ecb008ab95e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692563737 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.1692563737
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3074820764
Short name T167
Test name
Test status
Simulation time 926163984 ps
CPU time 2.57 seconds
Started May 28 01:02:40 PM PDT 24
Finished May 28 01:02:45 PM PDT 24
Peak memory 204856 kb
Host smart-6ef585fc-aa62-440d-a85c-92f37bbf0bf1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074820764 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.3
074820764
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.1421066966
Short name T63
Test name
Test status
Simulation time 96855645 ps
CPU time 0.69 seconds
Started May 28 01:02:32 PM PDT 24
Finished May 28 01:02:36 PM PDT 24
Peak memory 204720 kb
Host smart-f29f4e9f-0ce6-44eb-b74e-8e126ea13c83
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421066966 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.1
421066966
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1010816129
Short name T103
Test name
Test status
Simulation time 218891219 ps
CPU time 3.61 seconds
Started May 28 01:02:52 PM PDT 24
Finished May 28 01:03:01 PM PDT 24
Peak memory 205032 kb
Host smart-4f577469-6638-4487-9df2-9d3f62d65950
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010816129 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.1010816129
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.1408201279
Short name T208
Test name
Test status
Simulation time 164633506 ps
CPU time 2.54 seconds
Started May 28 01:02:40 PM PDT 24
Finished May 28 01:02:44 PM PDT 24
Peak memory 213220 kb
Host smart-7aa83288-07a0-43c8-b5f9-bb4870f607c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408201279 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.1408201279
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2534871232
Short name T118
Test name
Test status
Simulation time 1466830014 ps
CPU time 9.83 seconds
Started May 28 01:02:30 PM PDT 24
Finished May 28 01:02:43 PM PDT 24
Peak memory 213196 kb
Host smart-5aae82cd-e017-4504-b204-015248e7cdaa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534871232 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.2534871232
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.1501262951
Short name T201
Test name
Test status
Simulation time 2053811386 ps
CPU time 5.44 seconds
Started May 28 01:03:02 PM PDT 24
Finished May 28 01:03:12 PM PDT 24
Peak memory 213264 kb
Host smart-88fba312-0041-4a11-9a84-4fea89ba0c9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501262951 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.1501262951
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.2397889526
Short name T98
Test name
Test status
Simulation time 86125519 ps
CPU time 2.22 seconds
Started May 28 01:02:50 PM PDT 24
Finished May 28 01:02:58 PM PDT 24
Peak memory 218444 kb
Host smart-dffd478b-62ae-4d31-9d2a-408aacc0e9b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397889526 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.2397889526
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.1417276061
Short name T230
Test name
Test status
Simulation time 506639741 ps
CPU time 2.45 seconds
Started May 28 01:02:55 PM PDT 24
Finished May 28 01:03:02 PM PDT 24
Peak memory 204896 kb
Host smart-847a4209-9d2e-4048-b622-27c7d9596bb5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417276061 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.1
417276061
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.1599048867
Short name T215
Test name
Test status
Simulation time 64142400 ps
CPU time 0.74 seconds
Started May 28 01:02:46 PM PDT 24
Finished May 28 01:02:57 PM PDT 24
Peak memory 204716 kb
Host smart-0edc6e5d-db34-4367-9e8f-b7c44cadf946
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599048867 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.1
599048867
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2209114291
Short name T244
Test name
Test status
Simulation time 150982804 ps
CPU time 6.15 seconds
Started May 28 01:02:54 PM PDT 24
Finished May 28 01:03:06 PM PDT 24
Peak memory 205016 kb
Host smart-d9575896-d1a2-414f-aa5b-04e167f56672
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209114291 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.2209114291
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.667112369
Short name T236
Test name
Test status
Simulation time 155629760 ps
CPU time 3.93 seconds
Started May 28 01:03:02 PM PDT 24
Finished May 28 01:03:10 PM PDT 24
Peak memory 213284 kb
Host smart-b383148e-64a0-4c84-9af8-0d510a122755
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667112369 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.667112369
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3254417266
Short name T237
Test name
Test status
Simulation time 87260112 ps
CPU time 4.59 seconds
Started May 28 01:03:01 PM PDT 24
Finished May 28 01:03:10 PM PDT 24
Peak memory 221464 kb
Host smart-cbdd3b27-8532-4f3a-a681-74e56bde1dfd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254417266 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.3254417266
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.3439576835
Short name T101
Test name
Test status
Simulation time 44292699 ps
CPU time 2.1 seconds
Started May 28 01:03:04 PM PDT 24
Finished May 28 01:03:11 PM PDT 24
Peak memory 213212 kb
Host smart-8146e31c-64d9-4ea4-8f5d-e9e953ad35db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439576835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.3439576835
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2874431388
Short name T160
Test name
Test status
Simulation time 1126419656 ps
CPU time 2.02 seconds
Started May 28 01:02:51 PM PDT 24
Finished May 28 01:02:59 PM PDT 24
Peak memory 204944 kb
Host smart-40c2c8c6-ca9e-4e4e-8756-bba01fe6a25d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874431388 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.2
874431388
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.458742420
Short name T259
Test name
Test status
Simulation time 68505769 ps
CPU time 0.75 seconds
Started May 28 01:02:57 PM PDT 24
Finished May 28 01:03:03 PM PDT 24
Peak memory 204696 kb
Host smart-a0d50f27-a705-4aac-b472-ff1d304cb4e6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458742420 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.458742420
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.754639401
Short name T87
Test name
Test status
Simulation time 674286772 ps
CPU time 4.06 seconds
Started May 28 01:03:06 PM PDT 24
Finished May 28 01:03:14 PM PDT 24
Peak memory 205012 kb
Host smart-1d80bf40-9b41-4c33-ba67-db9b60b331e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754639401 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_c
sr_outstanding.754639401
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.1796597116
Short name T254
Test name
Test status
Simulation time 4975654581 ps
CPU time 18.11 seconds
Started May 28 01:02:57 PM PDT 24
Finished May 28 01:03:20 PM PDT 24
Peak memory 219152 kb
Host smart-ec57860b-6ab3-45a7-b294-b2cfe89ea161
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796597116 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.1796597116
Directory /workspace/7.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.443209889
Short name T190
Test name
Test status
Simulation time 85400636 ps
CPU time 4.61 seconds
Started May 28 01:02:47 PM PDT 24
Finished May 28 01:02:58 PM PDT 24
Peak memory 213284 kb
Host smart-3ebd0d57-6d87-4623-821f-3991df627686
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443209889 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.443209889
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.2685365035
Short name T68
Test name
Test status
Simulation time 2102304865 ps
CPU time 5.31 seconds
Started May 28 01:03:01 PM PDT 24
Finished May 28 01:03:10 PM PDT 24
Peak memory 217852 kb
Host smart-74f143bb-6d54-4d7c-91ff-a2d2f56c75aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685365035 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.2685365035
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1441952487
Short name T227
Test name
Test status
Simulation time 46201601 ps
CPU time 1.38 seconds
Started May 28 01:02:53 PM PDT 24
Finished May 28 01:03:00 PM PDT 24
Peak memory 213200 kb
Host smart-dcb891a8-7056-4963-83f8-d8dec6c2a947
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441952487 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.1441952487
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.4204342134
Short name T234
Test name
Test status
Simulation time 576326172 ps
CPU time 1.46 seconds
Started May 28 01:03:02 PM PDT 24
Finished May 28 01:03:08 PM PDT 24
Peak memory 204900 kb
Host smart-71c2270d-f8ff-4df0-9d4d-a21736552857
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204342134 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.4
204342134
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2102212127
Short name T222
Test name
Test status
Simulation time 28881135 ps
CPU time 0.72 seconds
Started May 28 01:02:53 PM PDT 24
Finished May 28 01:03:00 PM PDT 24
Peak memory 204720 kb
Host smart-3fb14e3a-1540-411a-a7f3-01685bb73e71
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102212127 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.2
102212127
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2061273626
Short name T268
Test name
Test status
Simulation time 4000957824 ps
CPU time 7.88 seconds
Started May 28 01:02:58 PM PDT 24
Finished May 28 01:03:10 PM PDT 24
Peak memory 205072 kb
Host smart-8d86e163-8d63-46f0-b349-aab3f147772c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061273626 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_
csr_outstanding.2061273626
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.2868224567
Short name T168
Test name
Test status
Simulation time 51920357 ps
CPU time 3.01 seconds
Started May 28 01:03:18 PM PDT 24
Finished May 28 01:03:30 PM PDT 24
Peak memory 213288 kb
Host smart-96bbc248-a245-4548-ad7c-a2eaad7ebed3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868224567 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.2868224567
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.4092298550
Short name T121
Test name
Test status
Simulation time 973823581 ps
CPU time 8.64 seconds
Started May 28 01:02:49 PM PDT 24
Finished May 28 01:03:04 PM PDT 24
Peak memory 213208 kb
Host smart-d29afcd5-7243-47d6-a2dc-2d46962b5e4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092298550 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.4092298550
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.1036379194
Short name T271
Test name
Test status
Simulation time 1883579870 ps
CPU time 4.67 seconds
Started May 28 01:03:00 PM PDT 24
Finished May 28 01:03:09 PM PDT 24
Peak memory 217708 kb
Host smart-2f848156-5a5e-41a2-bcfe-d72d32cbecbd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036379194 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.1036379194
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.3256983325
Short name T96
Test name
Test status
Simulation time 84778728 ps
CPU time 1.5 seconds
Started May 28 01:02:49 PM PDT 24
Finished May 28 01:02:57 PM PDT 24
Peak memory 213212 kb
Host smart-c8661d9e-6f73-43c6-9166-57d757370c38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256983325 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.3256983325
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.2949223596
Short name T186
Test name
Test status
Simulation time 557904166 ps
CPU time 1.99 seconds
Started May 28 01:02:50 PM PDT 24
Finished May 28 01:02:58 PM PDT 24
Peak memory 204900 kb
Host smart-ef794f48-e307-4491-a121-95b9f137c5b8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949223596 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.2
949223596
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.590387551
Short name T165
Test name
Test status
Simulation time 20809794 ps
CPU time 0.71 seconds
Started May 28 01:03:10 PM PDT 24
Finished May 28 01:03:16 PM PDT 24
Peak memory 204724 kb
Host smart-fb522b00-71d3-48f9-9162-fee51e97fd65
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590387551 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.590387551
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.3203924591
Short name T105
Test name
Test status
Simulation time 1113967679 ps
CPU time 4.58 seconds
Started May 28 01:03:02 PM PDT 24
Finished May 28 01:03:11 PM PDT 24
Peak memory 205020 kb
Host smart-4b235d85-2e96-4d51-83c7-d51ef49142fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203924591 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.3203924591
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.3577732048
Short name T193
Test name
Test status
Simulation time 66865628 ps
CPU time 2.65 seconds
Started May 28 01:02:51 PM PDT 24
Finished May 28 01:02:59 PM PDT 24
Peak memory 215948 kb
Host smart-5f2c7d00-48f4-4c5d-854c-89f6e486948f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577732048 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.3577732048
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.69199436
Short name T122
Test name
Test status
Simulation time 1539155748 ps
CPU time 9.76 seconds
Started May 28 01:03:00 PM PDT 24
Finished May 28 01:03:13 PM PDT 24
Peak memory 213220 kb
Host smart-fa9efc65-05bc-41e9-ad1e-b5601ab06673
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69199436 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.69199436
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.662344810
Short name T129
Test name
Test status
Simulation time 16930552 ps
CPU time 0.72 seconds
Started May 28 01:04:31 PM PDT 24
Finished May 28 01:04:39 PM PDT 24
Peak memory 204588 kb
Host smart-533ffb72-8e3c-4891-ae21-101d201290ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662344810 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.662344810
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.1613837673
Short name T10
Test name
Test status
Simulation time 46421385 ps
CPU time 0.79 seconds
Started May 28 01:04:17 PM PDT 24
Finished May 28 01:04:23 PM PDT 24
Peak memory 204452 kb
Host smart-7a30efc1-0972-4915-842f-715e3f59368f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613837673 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.1613837673
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.1553941935
Short name T17
Test name
Test status
Simulation time 929410925 ps
CPU time 1.75 seconds
Started May 28 01:04:10 PM PDT 24
Finished May 28 01:04:16 PM PDT 24
Peak memory 204636 kb
Host smart-78b32025-a6c2-4422-8b86-bc1353cf141d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553941935 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.1553941935
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.3176158290
Short name T139
Test name
Test status
Simulation time 16650934 ps
CPU time 0.71 seconds
Started May 28 01:04:11 PM PDT 24
Finished May 28 01:04:16 PM PDT 24
Peak memory 204576 kb
Host smart-4f7f2bde-7f2f-4559-878f-f102c9d8bfef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176158290 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.3176158290
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.3387502323
Short name T5
Test name
Test status
Simulation time 78188666 ps
CPU time 0.84 seconds
Started May 28 01:04:10 PM PDT 24
Finished May 28 01:04:14 PM PDT 24
Peak memory 204600 kb
Host smart-708a5455-7d9e-4608-8cdc-cff4a2e32f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387502323 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.3387502323
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.1910454133
Short name T15
Test name
Test status
Simulation time 39545879 ps
CPU time 0.88 seconds
Started May 28 01:04:09 PM PDT 24
Finished May 28 01:04:13 PM PDT 24
Peak memory 212872 kb
Host smart-7b0770b3-dbe5-4eb0-b478-7208320dfa10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910454133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.1910454133
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.1396805132
Short name T56
Test name
Test status
Simulation time 480775508 ps
CPU time 1.11 seconds
Started May 28 01:04:06 PM PDT 24
Finished May 28 01:04:10 PM PDT 24
Peak memory 229132 kb
Host smart-0f0ef0c9-dae3-44da-927a-3e548e424d52
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396805132 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.1396805132
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.1495100512
Short name T45
Test name
Test status
Simulation time 23636767 ps
CPU time 0.7 seconds
Started May 28 01:04:34 PM PDT 24
Finished May 28 01:04:42 PM PDT 24
Peak memory 204584 kb
Host smart-2da8ac2e-7fb6-4a18-a94b-4e1424ae5394
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495100512 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.1495100512
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.3573188120
Short name T130
Test name
Test status
Simulation time 126946408 ps
CPU time 0.69 seconds
Started May 28 01:04:27 PM PDT 24
Finished May 28 01:04:37 PM PDT 24
Peak memory 204588 kb
Host smart-f91e3eef-fe16-4539-a71e-8563ce098788
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573188120 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.3573188120
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.2214541092
Short name T67
Test name
Test status
Simulation time 24534736 ps
CPU time 0.73 seconds
Started May 28 01:04:26 PM PDT 24
Finished May 28 01:04:36 PM PDT 24
Peak memory 204556 kb
Host smart-70e38dd9-5fc1-4f3e-a24e-2be04df084ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214541092 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.2214541092
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.2850750712
Short name T131
Test name
Test status
Simulation time 131808325 ps
CPU time 0.7 seconds
Started May 28 01:04:23 PM PDT 24
Finished May 28 01:04:32 PM PDT 24
Peak memory 204584 kb
Host smart-d2e2741c-5f06-425d-b329-ecc95f136c64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850750712 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.2850750712
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.2805688738
Short name T34
Test name
Test status
Simulation time 198370846 ps
CPU time 0.69 seconds
Started May 28 01:04:11 PM PDT 24
Finished May 28 01:04:16 PM PDT 24
Peak memory 204588 kb
Host smart-6109b20a-585e-4766-9992-de056c9e1029
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805688738 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.2805688738
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.1677024839
Short name T1
Test name
Test status
Simulation time 46490901 ps
CPU time 0.71 seconds
Started May 28 01:04:23 PM PDT 24
Finished May 28 01:04:32 PM PDT 24
Peak memory 204544 kb
Host smart-a23d4110-3eb0-4a6d-9506-5a79fdf5ca9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677024839 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.1677024839
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.855585385
Short name T140
Test name
Test status
Simulation time 106951815 ps
CPU time 0.71 seconds
Started May 28 01:04:19 PM PDT 24
Finished May 28 01:04:25 PM PDT 24
Peak memory 204580 kb
Host smart-33acb78b-160f-43e9-a42b-7de9f712b2c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855585385 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.855585385
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.2358201508
Short name T48
Test name
Test status
Simulation time 35023465 ps
CPU time 0.76 seconds
Started May 28 01:04:32 PM PDT 24
Finished May 28 01:04:41 PM PDT 24
Peak memory 204600 kb
Host smart-b6b4b4a0-b576-499e-8d3f-66c2f91b0510
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358201508 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.2358201508
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.2166805294
Short name T49
Test name
Test status
Simulation time 23748717 ps
CPU time 0.72 seconds
Started May 28 01:04:23 PM PDT 24
Finished May 28 01:04:32 PM PDT 24
Peak memory 204584 kb
Host smart-69084ac1-131e-4c9f-8cce-87758863f431
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166805294 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.2166805294
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.1710554889
Short name T2
Test name
Test status
Simulation time 53299539 ps
CPU time 0.71 seconds
Started May 28 01:04:15 PM PDT 24
Finished May 28 01:04:19 PM PDT 24
Peak memory 204504 kb
Host smart-ff10ecda-5bd2-4676-93ed-27f4e4bb86ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710554889 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.1710554889
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.2546430112
Short name T23
Test name
Test status
Simulation time 79344822 ps
CPU time 1.12 seconds
Started May 28 01:04:19 PM PDT 24
Finished May 28 01:04:25 PM PDT 24
Peak memory 229344 kb
Host smart-575ef670-fdaa-4673-a704-04ff1d4299ec
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546430112 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.2546430112
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.2541391922
Short name T137
Test name
Test status
Simulation time 25755093 ps
CPU time 0.73 seconds
Started May 28 01:04:24 PM PDT 24
Finished May 28 01:04:34 PM PDT 24
Peak memory 204556 kb
Host smart-9a371bfc-db5a-4527-b863-d09929120de3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541391922 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.2541391922
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.4191857466
Short name T58
Test name
Test status
Simulation time 63329754 ps
CPU time 0.74 seconds
Started May 28 01:04:16 PM PDT 24
Finished May 28 01:04:20 PM PDT 24
Peak memory 204588 kb
Host smart-b3af0668-8613-4553-93e0-ae6aa6063013
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191857466 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.4191857466
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_stress_all.3792078974
Short name T13
Test name
Test status
Simulation time 850078358 ps
CPU time 3.75 seconds
Started May 28 01:04:21 PM PDT 24
Finished May 28 01:04:31 PM PDT 24
Peak memory 204768 kb
Host smart-ee39a472-f3e0-405f-a383-47eaf247b155
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792078974 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.3792078974
Directory /workspace/21.rv_dm_stress_all/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.107537511
Short name T123
Test name
Test status
Simulation time 27944342 ps
CPU time 0.77 seconds
Started May 28 01:04:23 PM PDT 24
Finished May 28 01:04:32 PM PDT 24
Peak memory 204596 kb
Host smart-4aa1fc58-8a8f-4d78-a88f-da06cbe3ebd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107537511 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.107537511
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.4260587430
Short name T136
Test name
Test status
Simulation time 29809439 ps
CPU time 0.81 seconds
Started May 28 01:04:36 PM PDT 24
Finished May 28 01:04:43 PM PDT 24
Peak memory 204888 kb
Host smart-6486f14f-31db-4abc-ad13-48ca95d24998
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260587430 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.4260587430
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.2256181514
Short name T128
Test name
Test status
Simulation time 77052083 ps
CPU time 0.7 seconds
Started May 28 01:04:50 PM PDT 24
Finished May 28 01:04:52 PM PDT 24
Peak memory 204640 kb
Host smart-52686be4-0be8-493a-8669-5ed9f45a2d5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256181514 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.2256181514
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.2787778760
Short name T53
Test name
Test status
Simulation time 31105624 ps
CPU time 0.72 seconds
Started May 28 01:04:44 PM PDT 24
Finished May 28 01:04:49 PM PDT 24
Peak memory 204568 kb
Host smart-75f35545-c650-4112-a908-759a15b40d30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787778760 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.2787778760
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.4123140466
Short name T35
Test name
Test status
Simulation time 141452659 ps
CPU time 0.75 seconds
Started May 28 01:04:29 PM PDT 24
Finished May 28 01:04:38 PM PDT 24
Peak memory 204512 kb
Host smart-34798c57-a848-400a-9c76-bfa9a09534d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123140466 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.4123140466
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.3638622214
Short name T125
Test name
Test status
Simulation time 46607736 ps
CPU time 0.72 seconds
Started May 28 01:04:43 PM PDT 24
Finished May 28 01:04:48 PM PDT 24
Peak memory 204584 kb
Host smart-c9e6cb68-3a6a-43a7-b1c5-cb0321ad4bcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638622214 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.3638622214
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.1047970117
Short name T145
Test name
Test status
Simulation time 89338889 ps
CPU time 0.67 seconds
Started May 28 01:04:44 PM PDT 24
Finished May 28 01:04:48 PM PDT 24
Peak memory 204584 kb
Host smart-c84a06cd-bd35-40fc-98c7-b131f6ae7cec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047970117 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.1047970117
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.3506671496
Short name T3
Test name
Test status
Simulation time 33890188 ps
CPU time 0.71 seconds
Started May 28 01:04:29 PM PDT 24
Finished May 28 01:04:38 PM PDT 24
Peak memory 204580 kb
Host smart-8b50de01-cbc7-4dd7-befc-7be6fc90f24c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506671496 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.3506671496
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.3460934003
Short name T24
Test name
Test status
Simulation time 226901949 ps
CPU time 1.63 seconds
Started May 28 01:04:05 PM PDT 24
Finished May 28 01:04:10 PM PDT 24
Peak memory 228868 kb
Host smart-a3c61c43-3469-4954-af62-255b7a5dddb1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460934003 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.3460934003
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.419552371
Short name T20
Test name
Test status
Simulation time 20114553 ps
CPU time 0.77 seconds
Started May 28 01:04:30 PM PDT 24
Finished May 28 01:04:39 PM PDT 24
Peak memory 204580 kb
Host smart-4b041ff7-a0a2-4588-8dba-a8ecb894f131
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419552371 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.419552371
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.3232073059
Short name T66
Test name
Test status
Simulation time 54347632 ps
CPU time 0.74 seconds
Started May 28 01:04:32 PM PDT 24
Finished May 28 01:04:44 PM PDT 24
Peak memory 204584 kb
Host smart-132f3c83-e97d-42a6-924b-641cfb251a5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232073059 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.3232073059
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.1334267144
Short name T57
Test name
Test status
Simulation time 36297815 ps
CPU time 0.76 seconds
Started May 28 01:04:42 PM PDT 24
Finished May 28 01:04:48 PM PDT 24
Peak memory 204524 kb
Host smart-9fcca655-f544-4616-b24d-e8099e3955c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334267144 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.1334267144
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.651812488
Short name T54
Test name
Test status
Simulation time 29811632 ps
CPU time 0.68 seconds
Started May 28 01:04:51 PM PDT 24
Finished May 28 01:04:53 PM PDT 24
Peak memory 204580 kb
Host smart-a03d00cc-a09c-447a-931f-14cc50399ead
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651812488 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.651812488
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.193521205
Short name T4
Test name
Test status
Simulation time 56371392 ps
CPU time 0.71 seconds
Started May 28 01:04:37 PM PDT 24
Finished May 28 01:04:44 PM PDT 24
Peak memory 204560 kb
Host smart-85bcd27c-9f8f-42ff-b145-935912836ccf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193521205 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.193521205
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.2805796390
Short name T132
Test name
Test status
Simulation time 15912572 ps
CPU time 0.74 seconds
Started May 28 01:04:30 PM PDT 24
Finished May 28 01:04:39 PM PDT 24
Peak memory 204588 kb
Host smart-bcab6a14-50e1-451f-8d81-2ec833b075a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805796390 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.2805796390
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.2153126274
Short name T126
Test name
Test status
Simulation time 24181559 ps
CPU time 0.72 seconds
Started May 28 01:04:49 PM PDT 24
Finished May 28 01:04:51 PM PDT 24
Peak memory 204560 kb
Host smart-470b9c37-514d-4cb3-9e2b-f972e03ffa99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153126274 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.2153126274
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.2618312822
Short name T43
Test name
Test status
Simulation time 66277691 ps
CPU time 0.72 seconds
Started May 28 01:04:44 PM PDT 24
Finished May 28 01:04:49 PM PDT 24
Peak memory 204584 kb
Host smart-fbc7f31d-ea17-49b7-9127-4dbf6d1f604b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618312822 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.2618312822
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.1077303053
Short name T135
Test name
Test status
Simulation time 38768060 ps
CPU time 0.72 seconds
Started May 28 01:04:41 PM PDT 24
Finished May 28 01:04:47 PM PDT 24
Peak memory 204588 kb
Host smart-491016a7-f793-4298-a8f1-d21f968be470
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077303053 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.1077303053
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.514809051
Short name T52
Test name
Test status
Simulation time 53214881 ps
CPU time 0.76 seconds
Started May 28 01:04:27 PM PDT 24
Finished May 28 01:04:36 PM PDT 24
Peak memory 204556 kb
Host smart-2aba1817-d1e6-45a3-8a91-a61ba28a8e59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514809051 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.514809051
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.2430735599
Short name T138
Test name
Test status
Simulation time 21486098 ps
CPU time 0.76 seconds
Started May 28 01:04:32 PM PDT 24
Finished May 28 01:04:45 PM PDT 24
Peak memory 204544 kb
Host smart-7cd110e6-8a26-4737-935a-d8142071b96d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430735599 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.2430735599
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.2433969788
Short name T55
Test name
Test status
Simulation time 174898829 ps
CPU time 1.19 seconds
Started May 28 01:04:22 PM PDT 24
Finished May 28 01:04:31 PM PDT 24
Peak memory 229060 kb
Host smart-76ed32a9-9d14-4b3c-aaa5-bbcbfabb3d6a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433969788 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.2433969788
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.1488659804
Short name T143
Test name
Test status
Simulation time 18794201 ps
CPU time 0.71 seconds
Started May 28 01:04:39 PM PDT 24
Finished May 28 01:04:45 PM PDT 24
Peak memory 204524 kb
Host smart-9f86817a-49e8-47fb-9486-2c6efd82764d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488659804 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.1488659804
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.1805221973
Short name T144
Test name
Test status
Simulation time 121147853 ps
CPU time 0.73 seconds
Started May 28 01:04:34 PM PDT 24
Finished May 28 01:04:42 PM PDT 24
Peak memory 204580 kb
Host smart-7507d387-0855-4e7e-b614-ffe42c76b366
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805221973 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.1805221973
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.617699670
Short name T46
Test name
Test status
Simulation time 30697897 ps
CPU time 0.7 seconds
Started May 28 01:04:44 PM PDT 24
Finished May 28 01:04:49 PM PDT 24
Peak memory 204532 kb
Host smart-5cf6485f-2acb-490c-8d6e-fcdf65a067ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617699670 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.617699670
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.3252660771
Short name T47
Test name
Test status
Simulation time 117375797 ps
CPU time 0.7 seconds
Started May 28 01:04:39 PM PDT 24
Finished May 28 01:04:45 PM PDT 24
Peak memory 204588 kb
Host smart-439c61ea-1f83-4b3a-99bc-92315904f059
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252660771 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.3252660771
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.3087519198
Short name T141
Test name
Test status
Simulation time 30229376 ps
CPU time 0.68 seconds
Started May 28 01:04:51 PM PDT 24
Finished May 28 01:04:53 PM PDT 24
Peak memory 204536 kb
Host smart-9cf56ff5-28e5-4ef1-9a43-7d5d4c139db3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087519198 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.3087519198
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.2983434547
Short name T134
Test name
Test status
Simulation time 152110446 ps
CPU time 0.7 seconds
Started May 28 01:04:40 PM PDT 24
Finished May 28 01:04:46 PM PDT 24
Peak memory 204536 kb
Host smart-db032e14-3461-4a00-a11e-be66e4dbef80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983434547 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.2983434547
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.2388941645
Short name T124
Test name
Test status
Simulation time 59623188 ps
CPU time 0.73 seconds
Started May 28 01:04:37 PM PDT 24
Finished May 28 01:04:43 PM PDT 24
Peak memory 204588 kb
Host smart-94239a02-cabf-4ba5-9378-cc0d9cdaaed5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388941645 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.2388941645
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.2840819191
Short name T33
Test name
Test status
Simulation time 34680571 ps
CPU time 0.72 seconds
Started May 28 01:04:48 PM PDT 24
Finished May 28 01:04:51 PM PDT 24
Peak memory 204584 kb
Host smart-4b301735-304c-4129-81b9-c07952c28ca3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840819191 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.2840819191
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.2342020854
Short name T133
Test name
Test status
Simulation time 172372184 ps
CPU time 0.73 seconds
Started May 28 01:04:42 PM PDT 24
Finished May 28 01:04:47 PM PDT 24
Peak memory 204592 kb
Host smart-01b8aa55-1c02-4ab4-b341-9dc40c322712
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342020854 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.2342020854
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.489435828
Short name T142
Test name
Test status
Simulation time 61033031 ps
CPU time 0.72 seconds
Started May 28 01:04:29 PM PDT 24
Finished May 28 01:04:38 PM PDT 24
Peak memory 204668 kb
Host smart-4a1e1a17-5149-4010-a053-e9ac26631ee5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489435828 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.489435828
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_stress_all.3712928870
Short name T11
Test name
Test status
Simulation time 2927306958 ps
CPU time 3.76 seconds
Started May 28 01:04:37 PM PDT 24
Finished May 28 01:04:49 PM PDT 24
Peak memory 204872 kb
Host smart-203fd6fa-5ca8-4c98-a143-1b31fe80824e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712928870 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.3712928870
Directory /workspace/49.rv_dm_stress_all/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.2260157977
Short name T44
Test name
Test status
Simulation time 51862052 ps
CPU time 0.72 seconds
Started May 28 01:04:28 PM PDT 24
Finished May 28 01:04:37 PM PDT 24
Peak memory 204580 kb
Host smart-d94055fc-63b0-42d5-ad18-56a09528aa3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260157977 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.2260157977
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.874832561
Short name T19
Test name
Test status
Simulation time 35334064 ps
CPU time 0.71 seconds
Started May 28 01:04:26 PM PDT 24
Finished May 28 01:04:36 PM PDT 24
Peak memory 204592 kb
Host smart-0137b9c4-2646-4557-bbcb-4267be9d518f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874832561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.874832561
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.3438126294
Short name T127
Test name
Test status
Simulation time 45529391 ps
CPU time 0.71 seconds
Started May 28 01:04:14 PM PDT 24
Finished May 28 01:04:19 PM PDT 24
Peak memory 204528 kb
Host smart-4c6812c6-54fb-496f-b36f-e8167179ef85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438126294 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.3438126294
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.476791356
Short name T18
Test name
Test status
Simulation time 19488914 ps
CPU time 0.74 seconds
Started May 28 01:04:33 PM PDT 24
Finished May 28 01:04:41 PM PDT 24
Peak memory 204588 kb
Host smart-f187d109-7ea2-4bcb-ad5e-987281f62ee6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476791356 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.476791356
Directory /workspace/9.rv_dm_alert_test/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%