Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
74.74 90.63 76.24 86.29 60.26 77.17 98.20 34.39


Total tests in report: 275
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
48.52 48.52 80.77 80.77 46.29 46.29 35.33 35.33 28.21 28.21 56.17 56.17 91.76 91.76 1.09 1.09 /workspace/coverage/default/8.rv_dm_alert_test.3315515811
60.33 11.82 87.71 6.95 61.26 14.97 57.51 22.18 47.44 19.23 68.83 12.67 93.45 1.69 6.11 5.02 /workspace/coverage/default/2.rv_dm_stress_all.426911935
65.67 5.34 87.71 0.00 63.87 2.61 69.58 12.07 52.56 5.13 69.50 0.67 94.72 1.27 21.76 15.65 /workspace/coverage/cover_reg_top/20.rv_dm_tap_fsm_rand_reset.1724675547
68.40 2.72 89.73 2.01 69.37 5.49 70.30 0.72 58.97 6.41 73.83 4.33 94.72 0.00 21.84 0.08 /workspace/coverage/default/13.rv_dm_stress_all.938201681
69.90 1.51 90.08 0.35 73.08 3.71 71.02 0.72 58.97 0.00 75.33 1.50 94.72 0.00 26.11 4.27 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1823336488
70.94 1.04 90.08 0.00 73.63 0.55 75.66 4.64 58.97 0.00 75.50 0.17 96.30 1.58 26.44 0.33 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.3333134476
71.82 0.88 90.08 0.00 74.04 0.41 75.66 0.00 58.97 0.00 75.50 0.00 96.30 0.00 32.22 5.77 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3698606175
72.39 0.56 90.18 0.10 74.31 0.27 77.94 2.28 60.26 1.28 75.50 0.00 96.30 0.00 32.22 0.00 /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.1756789970
72.79 0.40 90.23 0.05 74.31 0.00 80.14 2.20 60.26 0.00 75.67 0.17 96.30 0.00 32.64 0.42 /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.1206388583
73.08 0.28 90.23 0.00 74.45 0.14 80.70 0.56 60.26 0.00 75.67 0.00 97.25 0.95 32.97 0.33 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.311896411
73.32 0.24 90.23 0.00 74.73 0.27 82.13 1.44 60.26 0.00 75.67 0.00 97.25 0.00 32.97 0.00 /workspace/coverage/default/12.rv_dm_alert_test.56368757
73.50 0.18 90.23 0.00 74.86 0.14 82.77 0.64 60.26 0.00 75.67 0.00 97.25 0.00 33.47 0.50 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.3006229748
73.66 0.16 90.23 0.00 74.86 0.00 83.89 1.12 60.26 0.00 75.67 0.00 97.25 0.00 33.47 0.00 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1754920360
73.79 0.13 90.23 0.00 75.27 0.41 84.13 0.24 60.26 0.00 75.67 0.00 97.36 0.11 33.64 0.17 /workspace/coverage/default/0.rv_dm_sec_cm.2734524749
73.92 0.13 90.33 0.10 75.41 0.14 84.13 0.00 60.26 0.00 76.33 0.67 97.36 0.00 33.64 0.00 /workspace/coverage/default/0.rv_dm_rom_read_access.3463810157
74.04 0.12 90.33 0.00 75.41 0.00 84.81 0.68 60.26 0.00 76.33 0.00 97.36 0.00 33.81 0.17 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.1045256694
74.15 0.11 90.43 0.10 75.41 0.00 85.13 0.32 60.26 0.00 76.67 0.33 97.36 0.00 33.81 0.00 /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.2285225474
74.25 0.09 90.48 0.05 75.69 0.27 85.13 0.00 60.26 0.00 76.83 0.17 97.36 0.00 33.97 0.17 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.1592350369
74.32 0.08 90.48 0.00 75.69 0.00 85.13 0.00 60.26 0.00 76.83 0.00 97.89 0.53 33.97 0.00 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.4294535282
74.39 0.07 90.48 0.00 75.69 0.00 85.45 0.32 60.26 0.00 76.83 0.00 97.89 0.00 34.14 0.17 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3509550833
74.44 0.05 90.48 0.00 75.96 0.27 85.45 0.00 60.26 0.00 76.83 0.00 97.89 0.00 34.23 0.08 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.4186606043
74.49 0.05 90.53 0.05 75.96 0.00 85.73 0.28 60.26 0.00 76.83 0.00 97.89 0.00 34.23 0.00 /workspace/coverage/default/24.rv_dm_alert_test.2510967786
74.54 0.05 90.53 0.00 75.96 0.00 85.73 0.00 60.26 0.00 76.83 0.00 98.20 0.32 34.23 0.00 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.3144590188
74.58 0.04 90.53 0.00 76.10 0.14 85.89 0.16 60.26 0.00 76.83 0.00 98.20 0.00 34.23 0.00 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.1178068711
74.61 0.03 90.53 0.00 76.10 0.00 86.05 0.16 60.26 0.00 76.83 0.00 98.20 0.00 34.31 0.08 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3916980045
74.64 0.03 90.53 0.00 76.24 0.14 86.05 0.00 60.26 0.00 76.83 0.00 98.20 0.00 34.39 0.08 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.3592368508
74.68 0.03 90.58 0.05 76.24 0.00 86.05 0.00 60.26 0.00 77.00 0.17 98.20 0.00 34.39 0.00 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.2153691416
74.71 0.03 90.63 0.05 76.24 0.00 86.05 0.00 60.26 0.00 77.17 0.17 98.20 0.00 34.39 0.00 /workspace/coverage/default/0.rv_dm_stress_all.262520158
74.72 0.01 90.63 0.00 76.24 0.00 86.13 0.08 60.26 0.00 77.17 0.00 98.20 0.00 34.39 0.00 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.602094787
74.73 0.01 90.63 0.00 76.24 0.00 86.21 0.08 60.26 0.00 77.17 0.00 98.20 0.00 34.39 0.00 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1301346953
74.73 0.01 90.63 0.00 76.24 0.00 86.25 0.04 60.26 0.00 77.17 0.00 98.20 0.00 34.39 0.00 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.3484829077
74.74 0.01 90.63 0.00 76.24 0.00 86.29 0.04 60.26 0.00 77.17 0.00 98.20 0.00 34.39 0.00 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.1116008675

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.2708546413
/workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.137081985
/workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3773323450
/workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.2606922511
/workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2075520594
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.635943838
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.794469951
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2200826493
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2919155129
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1239124035
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3197857761
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3374955135
/workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1847690808
/workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.1570243078
/workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.3772857540
/workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.638528410
/workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.1661356445
/workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2013704097
/workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.341634585
/workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.1529277663
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2652767485
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.3672509237
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2140295682
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2630725920
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1817740209
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.240704661
/workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2651238212
/workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.989365552
/workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.1497851640
/workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.3554661712
/workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1550092622
/workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.28624585
/workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.4283374351
/workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.446289851
/workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1569080788
/workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.909158828
/workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.442585235
/workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3099635039
/workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.1064859750
/workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3221379480
/workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.456299372
/workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.3922418362
/workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3477687326
/workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.3047482160
/workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.233586462
/workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1651874472
/workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.4101583037
/workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2231990074
/workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3701858222
/workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.3201357587
/workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.508424842
/workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.1148213488
/workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.3035981835
/workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2574042860
/workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.1186706166
/workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.3091160579
/workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.3688638638
/workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.1813829572
/workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2999294688
/workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.1608036469
/workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1199190568
/workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.843270852
/workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2836679690
/workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.2588673206
/workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.499717355
/workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.3723908645
/workspace/coverage/cover_reg_top/15.rv_dm_tap_fsm_rand_reset.3142729597
/workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.640427981
/workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.1641304215
/workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.346761518
/workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.3231344418
/workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3985734415
/workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3492838120
/workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.2051632939
/workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.1230550962
/workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.1529601573
/workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.3760977881
/workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.1183521345
/workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.3423752835
/workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3051364619
/workspace/coverage/cover_reg_top/17.rv_dm_tap_fsm_rand_reset.608075631
/workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.3415726441
/workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2395898238
/workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.4170030679
/workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.3400489857
/workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.3133758469
/workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2292824348
/workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.2123179691
/workspace/coverage/cover_reg_top/18.rv_dm_tap_fsm_rand_reset.3523465065
/workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2692109139
/workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1768008731
/workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.2883887104
/workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.3762261352
/workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.3367694106
/workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.3083132434
/workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.70914617
/workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.3629495277
/workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.4288277898
/workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3000932016
/workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.3947557191
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2537482958
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.3794480809
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.4172795486
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1531344478
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.1380756522
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.2239297603
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2408413023
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2309869030
/workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1728525608
/workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.3754021361
/workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3702404085
/workspace/coverage/cover_reg_top/21.rv_dm_tap_fsm_rand_reset.1079337009
/workspace/coverage/cover_reg_top/22.rv_dm_tap_fsm_rand_reset.1155533233
/workspace/coverage/cover_reg_top/24.rv_dm_tap_fsm_rand_reset.2256077616
/workspace/coverage/cover_reg_top/27.rv_dm_tap_fsm_rand_reset.2715277644
/workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.3367541115
/workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.3904382344
/workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.2937951500
/workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1975248722
/workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.1263726545
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.3418056844
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.2551504499
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3848019143
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2083566652
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1858496190
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.3262952088
/workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.987820838
/workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1766885375
/workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2801211823
/workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2663218139
/workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2430386868
/workspace/coverage/cover_reg_top/31.rv_dm_tap_fsm_rand_reset.1141926706
/workspace/coverage/cover_reg_top/33.rv_dm_tap_fsm_rand_reset.3047869306
/workspace/coverage/cover_reg_top/35.rv_dm_tap_fsm_rand_reset.3060812063
/workspace/coverage/cover_reg_top/36.rv_dm_tap_fsm_rand_reset.3409478090
/workspace/coverage/cover_reg_top/37.rv_dm_tap_fsm_rand_reset.3591702187
/workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.3403189598
/workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.41253442
/workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.3341280699
/workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.3346000371
/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.4279529650
/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.4093102634
/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.2026227514
/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.3755440109
/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.3964738491
/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.4106766104
/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2557135011
/workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.3028288325
/workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.2538738485
/workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1288941796
/workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.3277671186
/workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2529540119
/workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3497394059
/workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.1692563737
/workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3074820764
/workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.1421066966
/workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1010816129
/workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.1408201279
/workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2534871232
/workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.1501262951
/workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.2397889526
/workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.1417276061
/workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.1599048867
/workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2209114291
/workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.667112369
/workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3254417266
/workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.3439576835
/workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2874431388
/workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.458742420
/workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.754639401
/workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.1796597116
/workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.443209889
/workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.2685365035
/workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1441952487
/workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.4204342134
/workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2102212127
/workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2061273626
/workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.2868224567
/workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.4092298550
/workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.1036379194
/workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.3256983325
/workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.2949223596
/workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.590387551
/workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.3203924591
/workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.3577732048
/workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.69199436
/workspace/coverage/default/0.rv_dm_alert_test.662344810
/workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.1613837673
/workspace/coverage/default/0.rv_dm_smoke.1553941935
/workspace/coverage/default/1.rv_dm_alert_test.3176158290
/workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.3387502323
/workspace/coverage/default/1.rv_dm_rom_read_access.1910454133
/workspace/coverage/default/1.rv_dm_sec_cm.1396805132
/workspace/coverage/default/10.rv_dm_alert_test.1495100512
/workspace/coverage/default/11.rv_dm_alert_test.3573188120
/workspace/coverage/default/13.rv_dm_alert_test.2214541092
/workspace/coverage/default/14.rv_dm_alert_test.2850750712
/workspace/coverage/default/15.rv_dm_alert_test.2805688738
/workspace/coverage/default/16.rv_dm_alert_test.1677024839
/workspace/coverage/default/17.rv_dm_alert_test.855585385
/workspace/coverage/default/18.rv_dm_alert_test.2358201508
/workspace/coverage/default/19.rv_dm_alert_test.2166805294
/workspace/coverage/default/2.rv_dm_alert_test.1710554889
/workspace/coverage/default/2.rv_dm_sec_cm.2546430112
/workspace/coverage/default/20.rv_dm_alert_test.2541391922
/workspace/coverage/default/21.rv_dm_alert_test.4191857466
/workspace/coverage/default/21.rv_dm_stress_all.3792078974
/workspace/coverage/default/22.rv_dm_alert_test.107537511
/workspace/coverage/default/23.rv_dm_alert_test.4260587430
/workspace/coverage/default/25.rv_dm_alert_test.2256181514
/workspace/coverage/default/26.rv_dm_alert_test.2787778760
/workspace/coverage/default/27.rv_dm_alert_test.4123140466
/workspace/coverage/default/28.rv_dm_alert_test.3638622214
/workspace/coverage/default/29.rv_dm_alert_test.1047970117
/workspace/coverage/default/3.rv_dm_alert_test.3506671496
/workspace/coverage/default/3.rv_dm_sec_cm.3460934003
/workspace/coverage/default/30.rv_dm_alert_test.419552371
/workspace/coverage/default/31.rv_dm_alert_test.3232073059
/workspace/coverage/default/32.rv_dm_alert_test.1334267144
/workspace/coverage/default/33.rv_dm_alert_test.651812488
/workspace/coverage/default/34.rv_dm_alert_test.193521205
/workspace/coverage/default/35.rv_dm_alert_test.2805796390
/workspace/coverage/default/36.rv_dm_alert_test.2153126274
/workspace/coverage/default/37.rv_dm_alert_test.2618312822
/workspace/coverage/default/38.rv_dm_alert_test.1077303053
/workspace/coverage/default/39.rv_dm_alert_test.514809051
/workspace/coverage/default/4.rv_dm_alert_test.2430735599
/workspace/coverage/default/4.rv_dm_sec_cm.2433969788
/workspace/coverage/default/40.rv_dm_alert_test.1488659804
/workspace/coverage/default/41.rv_dm_alert_test.1805221973
/workspace/coverage/default/42.rv_dm_alert_test.617699670
/workspace/coverage/default/43.rv_dm_alert_test.3252660771
/workspace/coverage/default/44.rv_dm_alert_test.3087519198
/workspace/coverage/default/45.rv_dm_alert_test.2983434547
/workspace/coverage/default/46.rv_dm_alert_test.2388941645
/workspace/coverage/default/47.rv_dm_alert_test.2840819191
/workspace/coverage/default/48.rv_dm_alert_test.2342020854
/workspace/coverage/default/49.rv_dm_alert_test.489435828
/workspace/coverage/default/49.rv_dm_stress_all.3712928870
/workspace/coverage/default/5.rv_dm_alert_test.2260157977
/workspace/coverage/default/6.rv_dm_alert_test.874832561
/workspace/coverage/default/7.rv_dm_alert_test.3438126294
/workspace/coverage/default/9.rv_dm_alert_test.476791356



Total test records in report: 275
tests.html | tests1.html | tests2.html | tests3.html | tests4.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/16.rv_dm_alert_test.1677024839 May 28 01:04:23 PM PDT 24 May 28 01:04:32 PM PDT 24 46490901 ps
T2 /workspace/coverage/default/2.rv_dm_alert_test.1710554889 May 28 01:04:15 PM PDT 24 May 28 01:04:19 PM PDT 24 53299539 ps
T3 /workspace/coverage/default/3.rv_dm_alert_test.3506671496 May 28 01:04:29 PM PDT 24 May 28 01:04:38 PM PDT 24 33890188 ps
T4 /workspace/coverage/default/34.rv_dm_alert_test.193521205 May 28 01:04:37 PM PDT 24 May 28 01:04:44 PM PDT 24 56371392 ps
T16 /workspace/coverage/default/8.rv_dm_alert_test.3315515811 May 28 01:04:37 PM PDT 24 May 28 01:04:44 PM PDT 24 58606044 ps
T18 /workspace/coverage/default/9.rv_dm_alert_test.476791356 May 28 01:04:33 PM PDT 24 May 28 01:04:41 PM PDT 24 19488914 ps
T5 /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.3387502323 May 28 01:04:10 PM PDT 24 May 28 01:04:14 PM PDT 24 78188666 ps
T19 /workspace/coverage/default/6.rv_dm_alert_test.874832561 May 28 01:04:26 PM PDT 24 May 28 01:04:36 PM PDT 24 35334064 ps
T20 /workspace/coverage/default/30.rv_dm_alert_test.419552371 May 28 01:04:30 PM PDT 24 May 28 01:04:39 PM PDT 24 20114553 ps
T21 /workspace/coverage/default/12.rv_dm_alert_test.56368757 May 28 01:04:15 PM PDT 24 May 28 01:04:20 PM PDT 24 57463692 ps
T33 /workspace/coverage/default/47.rv_dm_alert_test.2840819191 May 28 01:04:48 PM PDT 24 May 28 01:04:51 PM PDT 24 34680571 ps
T66 /workspace/coverage/default/31.rv_dm_alert_test.3232073059 May 28 01:04:32 PM PDT 24 May 28 01:04:44 PM PDT 24 54347632 ps
T67 /workspace/coverage/default/13.rv_dm_alert_test.2214541092 May 28 01:04:26 PM PDT 24 May 28 01:04:36 PM PDT 24 24534736 ps
T6 /workspace/coverage/default/0.rv_dm_stress_all.262520158 May 28 01:04:19 PM PDT 24 May 28 01:04:28 PM PDT 24 867481682 ps
T22 /workspace/coverage/default/0.rv_dm_sec_cm.2734524749 May 28 01:04:06 PM PDT 24 May 28 01:04:10 PM PDT 24 127923043 ps
T12 /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.1756789970 May 28 01:04:04 PM PDT 24 May 28 01:04:07 PM PDT 24 34470198 ps
T35 /workspace/coverage/default/27.rv_dm_alert_test.4123140466 May 28 01:04:29 PM PDT 24 May 28 01:04:38 PM PDT 24 141452659 ps
T10 /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.1613837673 May 28 01:04:17 PM PDT 24 May 28 01:04:23 PM PDT 24 46421385 ps
T45 /workspace/coverage/default/10.rv_dm_alert_test.1495100512 May 28 01:04:34 PM PDT 24 May 28 01:04:42 PM PDT 24 23636767 ps
T34 /workspace/coverage/default/15.rv_dm_alert_test.2805688738 May 28 01:04:11 PM PDT 24 May 28 01:04:16 PM PDT 24 198370846 ps
T7 /workspace/coverage/default/2.rv_dm_stress_all.426911935 May 28 01:04:20 PM PDT 24 May 28 01:04:48 PM PDT 24 7321228258 ps
T51 /workspace/coverage/default/24.rv_dm_alert_test.2510967786 May 28 01:04:37 PM PDT 24 May 28 01:04:44 PM PDT 24 50542348 ps
T52 /workspace/coverage/default/39.rv_dm_alert_test.514809051 May 28 01:04:27 PM PDT 24 May 28 01:04:36 PM PDT 24 53214881 ps
T57 /workspace/coverage/default/32.rv_dm_alert_test.1334267144 May 28 01:04:42 PM PDT 24 May 28 01:04:48 PM PDT 24 36297815 ps
T8 /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.2285225474 May 28 01:04:25 PM PDT 24 May 28 01:04:35 PM PDT 24 116051519 ps
T138 /workspace/coverage/default/4.rv_dm_alert_test.2430735599 May 28 01:04:32 PM PDT 24 May 28 01:04:45 PM PDT 24 21486098 ps
T48 /workspace/coverage/default/18.rv_dm_alert_test.2358201508 May 28 01:04:32 PM PDT 24 May 28 01:04:41 PM PDT 24 35023465 ps
T14 /workspace/coverage/default/0.rv_dm_rom_read_access.3463810157 May 28 01:04:23 PM PDT 24 May 28 01:04:40 PM PDT 24 27859301 ps
T15 /workspace/coverage/default/1.rv_dm_rom_read_access.1910454133 May 28 01:04:09 PM PDT 24 May 28 01:04:13 PM PDT 24 39545879 ps
T125 /workspace/coverage/default/28.rv_dm_alert_test.3638622214 May 28 01:04:43 PM PDT 24 May 28 01:04:48 PM PDT 24 46607736 ps
T140 /workspace/coverage/default/17.rv_dm_alert_test.855585385 May 28 01:04:19 PM PDT 24 May 28 01:04:25 PM PDT 24 106951815 ps
T23 /workspace/coverage/default/2.rv_dm_sec_cm.2546430112 May 28 01:04:19 PM PDT 24 May 28 01:04:25 PM PDT 24 79344822 ps
T123 /workspace/coverage/default/22.rv_dm_alert_test.107537511 May 28 01:04:23 PM PDT 24 May 28 01:04:32 PM PDT 24 27944342 ps
T46 /workspace/coverage/default/42.rv_dm_alert_test.617699670 May 28 01:04:44 PM PDT 24 May 28 01:04:49 PM PDT 24 30697897 ps
T58 /workspace/coverage/default/21.rv_dm_alert_test.4191857466 May 28 01:04:16 PM PDT 24 May 28 01:04:20 PM PDT 24 63329754 ps
T53 /workspace/coverage/default/26.rv_dm_alert_test.2787778760 May 28 01:04:44 PM PDT 24 May 28 01:04:49 PM PDT 24 31105624 ps
T135 /workspace/coverage/default/38.rv_dm_alert_test.1077303053 May 28 01:04:41 PM PDT 24 May 28 01:04:47 PM PDT 24 38768060 ps
T24 /workspace/coverage/default/3.rv_dm_sec_cm.3460934003 May 28 01:04:05 PM PDT 24 May 28 01:04:10 PM PDT 24 226901949 ps
T43 /workspace/coverage/default/37.rv_dm_alert_test.2618312822 May 28 01:04:44 PM PDT 24 May 28 01:04:49 PM PDT 24 66277691 ps
T136 /workspace/coverage/default/23.rv_dm_alert_test.4260587430 May 28 01:04:36 PM PDT 24 May 28 01:04:43 PM PDT 24 29809439 ps
T9 /workspace/coverage/default/13.rv_dm_stress_all.938201681 May 28 01:04:27 PM PDT 24 May 28 01:04:44 PM PDT 24 2548161119 ps
T133 /workspace/coverage/default/48.rv_dm_alert_test.2342020854 May 28 01:04:42 PM PDT 24 May 28 01:04:47 PM PDT 24 172372184 ps
T55 /workspace/coverage/default/4.rv_dm_sec_cm.2433969788 May 28 01:04:22 PM PDT 24 May 28 01:04:31 PM PDT 24 174898829 ps
T141 /workspace/coverage/default/44.rv_dm_alert_test.3087519198 May 28 01:04:51 PM PDT 24 May 28 01:04:53 PM PDT 24 30229376 ps
T47 /workspace/coverage/default/43.rv_dm_alert_test.3252660771 May 28 01:04:39 PM PDT 24 May 28 01:04:45 PM PDT 24 117375797 ps
T17 /workspace/coverage/default/0.rv_dm_smoke.1553941935 May 28 01:04:10 PM PDT 24 May 28 01:04:16 PM PDT 24 929410925 ps
T142 /workspace/coverage/default/49.rv_dm_alert_test.489435828 May 28 01:04:29 PM PDT 24 May 28 01:04:38 PM PDT 24 61033031 ps
T128 /workspace/coverage/default/25.rv_dm_alert_test.2256181514 May 28 01:04:50 PM PDT 24 May 28 01:04:52 PM PDT 24 77052083 ps
T143 /workspace/coverage/default/40.rv_dm_alert_test.1488659804 May 28 01:04:39 PM PDT 24 May 28 01:04:45 PM PDT 24 18794201 ps
T54 /workspace/coverage/default/33.rv_dm_alert_test.651812488 May 28 01:04:51 PM PDT 24 May 28 01:04:53 PM PDT 24 29811632 ps
T137 /workspace/coverage/default/20.rv_dm_alert_test.2541391922 May 28 01:04:24 PM PDT 24 May 28 01:04:34 PM PDT 24 25755093 ps
T49 /workspace/coverage/default/19.rv_dm_alert_test.2166805294 May 28 01:04:23 PM PDT 24 May 28 01:04:32 PM PDT 24 23748717 ps
T11 /workspace/coverage/default/49.rv_dm_stress_all.3712928870 May 28 01:04:37 PM PDT 24 May 28 01:04:49 PM PDT 24 2927306958 ps
T126 /workspace/coverage/default/36.rv_dm_alert_test.2153126274 May 28 01:04:49 PM PDT 24 May 28 01:04:51 PM PDT 24 24181559 ps
T134 /workspace/coverage/default/45.rv_dm_alert_test.2983434547 May 28 01:04:40 PM PDT 24 May 28 01:04:46 PM PDT 24 152110446 ps
T44 /workspace/coverage/default/5.rv_dm_alert_test.2260157977 May 28 01:04:28 PM PDT 24 May 28 01:04:37 PM PDT 24 51862052 ps
T144 /workspace/coverage/default/41.rv_dm_alert_test.1805221973 May 28 01:04:34 PM PDT 24 May 28 01:04:42 PM PDT 24 121147853 ps
T145 /workspace/coverage/default/29.rv_dm_alert_test.1047970117 May 28 01:04:44 PM PDT 24 May 28 01:04:48 PM PDT 24 89338889 ps
T130 /workspace/coverage/default/11.rv_dm_alert_test.3573188120 May 28 01:04:27 PM PDT 24 May 28 01:04:37 PM PDT 24 126946408 ps
T127 /workspace/coverage/default/7.rv_dm_alert_test.3438126294 May 28 01:04:14 PM PDT 24 May 28 01:04:19 PM PDT 24 45529391 ps
T13 /workspace/coverage/default/21.rv_dm_stress_all.3792078974 May 28 01:04:21 PM PDT 24 May 28 01:04:31 PM PDT 24 850078358 ps
T132 /workspace/coverage/default/35.rv_dm_alert_test.2805796390 May 28 01:04:30 PM PDT 24 May 28 01:04:39 PM PDT 24 15912572 ps
T129 /workspace/coverage/default/0.rv_dm_alert_test.662344810 May 28 01:04:31 PM PDT 24 May 28 01:04:39 PM PDT 24 16930552 ps
T124 /workspace/coverage/default/46.rv_dm_alert_test.2388941645 May 28 01:04:37 PM PDT 24 May 28 01:04:43 PM PDT 24 59623188 ps
T131 /workspace/coverage/default/14.rv_dm_alert_test.2850750712 May 28 01:04:23 PM PDT 24 May 28 01:04:32 PM PDT 24 131808325 ps
T139 /workspace/coverage/default/1.rv_dm_alert_test.3176158290 May 28 01:04:11 PM PDT 24 May 28 01:04:16 PM PDT 24 16650934 ps
T56 /workspace/coverage/default/1.rv_dm_sec_cm.1396805132 May 28 01:04:06 PM PDT 24 May 28 01:04:10 PM PDT 24 480775508 ps
T26 /workspace/coverage/cover_reg_top/15.rv_dm_tap_fsm_rand_reset.3142729597 May 28 01:03:10 PM PDT 24 May 28 01:03:38 PM PDT 24 10784321965 ps
T63 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.1421066966 May 28 01:02:32 PM PDT 24 May 28 01:02:36 PM PDT 24 96855645 ps
T64 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.3367694106 May 28 01:03:08 PM PDT 24 May 28 01:03:15 PM PDT 24 29790148 ps
T146 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.3133758469 May 28 01:03:09 PM PDT 24 May 28 01:03:16 PM PDT 24 479150345 ps
T40 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1754920360 May 28 01:02:31 PM PDT 24 May 28 01:03:14 PM PDT 24 23142979643 ps
T32 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1823336488 May 28 01:02:54 PM PDT 24 May 28 01:03:08 PM PDT 24 732645559 ps
T65 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.3755440109 May 28 01:02:32 PM PDT 24 May 28 01:02:37 PM PDT 24 69767729 ps
T147 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1847690808 May 28 01:02:37 PM PDT 24 May 28 01:02:41 PM PDT 24 45890028 ps
T27 /workspace/coverage/cover_reg_top/33.rv_dm_tap_fsm_rand_reset.3047869306 May 28 01:03:09 PM PDT 24 May 28 01:03:51 PM PDT 24 18382135153 ps
T28 /workspace/coverage/cover_reg_top/27.rv_dm_tap_fsm_rand_reset.2715277644 May 28 01:03:07 PM PDT 24 May 28 01:03:26 PM PDT 24 5045884791 ps
T68 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.2685365035 May 28 01:03:01 PM PDT 24 May 28 01:03:10 PM PDT 24 2102304865 ps
T148 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.3423752835 May 28 01:03:04 PM PDT 24 May 28 01:03:09 PM PDT 24 58533984 ps
T42 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.2026227514 May 28 01:02:46 PM PDT 24 May 28 01:02:53 PM PDT 24 333561803 ps
T25 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2408413023 May 28 01:02:48 PM PDT 24 May 28 01:02:55 PM PDT 24 137365401 ps
T149 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1858496190 May 28 01:02:29 PM PDT 24 May 28 01:02:33 PM PDT 24 36632272 ps
T41 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.3794480809 May 28 01:02:33 PM PDT 24 May 28 01:03:05 PM PDT 24 6130109668 ps
T72 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.311896411 May 28 01:02:30 PM PDT 24 May 28 01:03:48 PM PDT 24 9632942953 ps
T61 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.3484829077 May 28 01:02:51 PM PDT 24 May 28 01:02:59 PM PDT 24 217559763 ps
T50 /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.1206388583 May 28 01:02:52 PM PDT 24 May 28 01:03:25 PM PDT 24 29663047844 ps
T73 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3773323450 May 28 01:02:37 PM PDT 24 May 28 01:02:40 PM PDT 24 146052989 ps
T69 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.1608036469 May 28 01:03:09 PM PDT 24 May 28 01:03:17 PM PDT 24 317024325 ps
T60 /workspace/coverage/cover_reg_top/20.rv_dm_tap_fsm_rand_reset.1724675547 May 28 01:03:13 PM PDT 24 May 28 01:03:48 PM PDT 24 24776448950 ps
T70 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.4186606043 May 28 01:02:38 PM PDT 24 May 28 01:02:43 PM PDT 24 303838142 ps
T74 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.3091160579 May 28 01:03:04 PM PDT 24 May 28 01:03:10 PM PDT 24 167618663 ps
T71 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3698606175 May 28 01:02:57 PM PDT 24 May 28 01:03:06 PM PDT 24 109233509 ps
T150 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2292824348 May 28 01:03:11 PM PDT 24 May 28 01:03:18 PM PDT 24 78037961 ps
T75 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2075520594 May 28 01:02:30 PM PDT 24 May 28 01:02:34 PM PDT 24 87420870 ps
T76 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.233586462 May 28 01:02:44 PM PDT 24 May 28 01:02:47 PM PDT 24 113802680 ps
T151 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.1570243078 May 28 01:02:40 PM PDT 24 May 28 01:02:43 PM PDT 24 16861751 ps
T29 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.1592350369 May 28 01:03:01 PM PDT 24 May 28 01:03:14 PM PDT 24 3073675180 ps
T152 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.3201357587 May 28 01:02:55 PM PDT 24 May 28 01:03:05 PM PDT 24 1277747724 ps
T81 /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.3277671186 May 28 01:02:50 PM PDT 24 May 28 01:03:20 PM PDT 24 13750158449 ps
T36 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.3333134476 May 28 01:02:32 PM PDT 24 May 28 01:02:38 PM PDT 24 771111733 ps
T30 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.1230550962 May 28 01:03:01 PM PDT 24 May 28 01:03:20 PM PDT 24 3329084302 ps
T153 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3221379480 May 28 01:02:54 PM PDT 24 May 28 01:03:02 PM PDT 24 930286457 ps
T154 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.3231344418 May 28 01:03:07 PM PDT 24 May 28 01:03:13 PM PDT 24 613919692 ps
T77 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.137081985 May 28 01:02:29 PM PDT 24 May 28 01:03:06 PM PDT 24 22331257473 ps
T37 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.602094787 May 28 01:02:28 PM PDT 24 May 28 01:02:33 PM PDT 24 800314834 ps
T83 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2395898238 May 28 01:03:08 PM PDT 24 May 28 01:03:29 PM PDT 24 1774409441 ps
T78 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.4288277898 May 28 01:02:28 PM PDT 24 May 28 01:02:32 PM PDT 24 93622953 ps
T155 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.1813829572 May 28 01:03:15 PM PDT 24 May 28 01:03:24 PM PDT 24 36938343 ps
T156 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.2153691416 May 28 01:02:57 PM PDT 24 May 28 01:03:02 PM PDT 24 34540619 ps
T117 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3916980045 May 28 01:02:23 PM PDT 24 May 28 01:02:41 PM PDT 24 1891521481 ps
T157 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.499717355 May 28 01:03:09 PM PDT 24 May 28 01:03:16 PM PDT 24 97729487 ps
T158 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.4279529650 May 28 01:03:02 PM PDT 24 May 28 01:03:23 PM PDT 24 14956728941 ps
T159 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2200826493 May 28 01:02:33 PM PDT 24 May 28 01:02:38 PM PDT 24 244548200 ps
T160 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2874431388 May 28 01:02:51 PM PDT 24 May 28 01:02:59 PM PDT 24 1126419656 ps
T82 /workspace/coverage/cover_reg_top/21.rv_dm_tap_fsm_rand_reset.1079337009 May 28 01:03:17 PM PDT 24 May 28 01:04:05 PM PDT 24 20781478713 ps
T112 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3497394059 May 28 01:02:54 PM PDT 24 May 28 01:03:02 PM PDT 24 1307119287 ps
T79 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3051364619 May 28 01:03:13 PM PDT 24 May 28 01:03:25 PM PDT 24 96694302 ps
T161 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1239124035 May 28 01:02:52 PM PDT 24 May 28 01:02:59 PM PDT 24 578894782 ps
T80 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.3400489857 May 28 01:03:17 PM PDT 24 May 28 01:03:28 PM PDT 24 91345736 ps
T162 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2630725920 May 28 01:02:29 PM PDT 24 May 28 01:02:35 PM PDT 24 1089204783 ps
T84 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.2883887104 May 28 01:03:20 PM PDT 24 May 28 01:03:32 PM PDT 24 151993019 ps
T163 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2692109139 May 28 01:03:12 PM PDT 24 May 28 01:03:25 PM PDT 24 209189887 ps
T164 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1550092622 May 28 01:02:27 PM PDT 24 May 28 01:02:32 PM PDT 24 759781161 ps
T165 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.590387551 May 28 01:03:10 PM PDT 24 May 28 01:03:16 PM PDT 24 20809794 ps
T85 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.1064859750 May 28 01:03:03 PM PDT 24 May 28 01:03:10 PM PDT 24 171344386 ps
T95 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.638528410 May 28 01:02:43 PM PDT 24 May 28 01:03:55 PM PDT 24 4487466355 ps
T166 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.456299372 May 28 01:02:51 PM PDT 24 May 28 01:02:58 PM PDT 24 62216847 ps
T167 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3074820764 May 28 01:02:40 PM PDT 24 May 28 01:02:45 PM PDT 24 926163984 ps
T103 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1010816129 May 28 01:02:52 PM PDT 24 May 28 01:03:01 PM PDT 24 218891219 ps
T168 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.2868224567 May 28 01:03:18 PM PDT 24 May 28 01:03:30 PM PDT 24 51920357 ps
T169 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2663218139 May 28 01:02:52 PM PDT 24 May 28 01:03:03 PM PDT 24 75362055 ps
T114 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2430386868 May 28 01:02:35 PM PDT 24 May 28 01:02:47 PM PDT 24 463275121 ps
T86 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.3144590188 May 28 01:02:59 PM PDT 24 May 28 01:03:06 PM PDT 24 159488967 ps
T170 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.1641304215 May 28 01:02:53 PM PDT 24 May 28 01:03:04 PM PDT 24 4585135650 ps
T171 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1975248722 May 28 01:02:49 PM PDT 24 May 28 01:02:59 PM PDT 24 261762204 ps
T172 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2651238212 May 28 01:02:39 PM PDT 24 May 28 01:02:42 PM PDT 24 17035514 ps
T173 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1728525608 May 28 01:02:40 PM PDT 24 May 28 01:02:43 PM PDT 24 48106345 ps
T113 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.3922418362 May 28 01:03:05 PM PDT 24 May 28 01:03:14 PM PDT 24 185077313 ps
T174 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.3047482160 May 28 01:02:49 PM PDT 24 May 28 01:03:09 PM PDT 24 5892336748 ps
T104 /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.3083132434 May 28 01:03:00 PM PDT 24 May 28 01:03:08 PM PDT 24 1016035454 ps
T175 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2083566652 May 28 01:02:33 PM PDT 24 May 28 01:02:43 PM PDT 24 3073332905 ps
T176 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.3762261352 May 28 01:03:16 PM PDT 24 May 28 01:03:26 PM PDT 24 396096645 ps
T177 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.341634585 May 28 01:02:53 PM PDT 24 May 28 01:03:03 PM PDT 24 578635251 ps
T39 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.4172795486 May 28 01:02:44 PM PDT 24 May 28 01:02:54 PM PDT 24 1787341762 ps
T87 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.754639401 May 28 01:03:06 PM PDT 24 May 28 01:03:14 PM PDT 24 674286772 ps
T115 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.442585235 May 28 01:03:03 PM PDT 24 May 28 01:03:23 PM PDT 24 1055034069 ps
T178 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.3262952088 May 28 01:02:44 PM PDT 24 May 28 01:02:47 PM PDT 24 24052822 ps
T179 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.794469951 May 28 01:02:34 PM PDT 24 May 28 01:03:49 PM PDT 24 34849517232 ps
T180 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3197857761 May 28 01:02:36 PM PDT 24 May 28 01:02:39 PM PDT 24 119537102 ps
T181 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.1183521345 May 28 01:03:19 PM PDT 24 May 28 01:03:30 PM PDT 24 227882899 ps
T182 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.3754021361 May 28 01:02:48 PM PDT 24 May 28 01:02:54 PM PDT 24 49208717 ps
T88 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.909158828 May 28 01:03:00 PM PDT 24 May 28 01:03:07 PM PDT 24 208464244 ps
T183 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1768008731 May 28 01:03:02 PM PDT 24 May 28 01:03:10 PM PDT 24 149196328 ps
T184 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.3341280699 May 28 01:02:49 PM PDT 24 May 28 01:02:59 PM PDT 24 275483227 ps
T185 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.2606922511 May 28 01:02:31 PM PDT 24 May 28 01:02:37 PM PDT 24 2306951465 ps
T186 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.2949223596 May 28 01:02:50 PM PDT 24 May 28 01:02:58 PM PDT 24 557904166 ps
T187 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1817740209 May 28 01:02:30 PM PDT 24 May 28 01:02:34 PM PDT 24 104875278 ps
T96 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.3256983325 May 28 01:02:49 PM PDT 24 May 28 01:02:57 PM PDT 24 84778728 ps
T118 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2534871232 May 28 01:02:30 PM PDT 24 May 28 01:02:43 PM PDT 24 1466830014 ps
T188 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.28624585 May 28 01:02:58 PM PDT 24 May 28 01:03:05 PM PDT 24 563116654 ps
T189 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2529540119 May 28 01:02:40 PM PDT 24 May 28 01:02:46 PM PDT 24 110496768 ps
T190 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.443209889 May 28 01:02:47 PM PDT 24 May 28 01:02:58 PM PDT 24 85400636 ps
T191 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.2937951500 May 28 01:02:38 PM PDT 24 May 28 01:02:43 PM PDT 24 122798482 ps
T119 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3477687326 May 28 01:02:54 PM PDT 24 May 28 01:03:15 PM PDT 24 1213054427 ps
T192 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.3418056844 May 28 01:02:32 PM PDT 24 May 28 01:03:28 PM PDT 24 15421422286 ps
T89 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.4294535282 May 28 01:02:47 PM PDT 24 May 28 01:04:07 PM PDT 24 16540529493 ps
T193 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.3577732048 May 28 01:02:51 PM PDT 24 May 28 01:02:59 PM PDT 24 66865628 ps
T97 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.3629495277 May 28 01:02:31 PM PDT 24 May 28 01:03:06 PM PDT 24 3879812032 ps
T90 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.2123179691 May 28 01:03:14 PM PDT 24 May 28 01:03:28 PM PDT 24 995933648 ps
T194 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.4106766104 May 28 01:02:37 PM PDT 24 May 28 01:02:40 PM PDT 24 217008947 ps
T195 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.843270852 May 28 01:03:04 PM PDT 24 May 28 01:03:11 PM PDT 24 200086685 ps
T196 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.3672509237 May 28 01:02:32 PM PDT 24 May 28 01:02:41 PM PDT 24 1681331059 ps
T197 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.446289851 May 28 01:03:00 PM PDT 24 May 28 01:03:07 PM PDT 24 1073484085 ps
T98 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.2397889526 May 28 01:02:50 PM PDT 24 May 28 01:02:58 PM PDT 24 86125519 ps
T198 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.3028288325 May 28 01:02:45 PM PDT 24 May 28 01:02:50 PM PDT 24 19318341 ps
T99 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.3403189598 May 28 01:03:00 PM PDT 24 May 28 01:04:14 PM PDT 24 17384141472 ps
T199 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3099635039 May 28 01:02:55 PM PDT 24 May 28 01:03:03 PM PDT 24 3864271105 ps
T200 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.2538738485 May 28 01:02:43 PM PDT 24 May 28 01:02:46 PM PDT 24 29705097 ps
T201 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.1501262951 May 28 01:03:02 PM PDT 24 May 28 01:03:12 PM PDT 24 2053811386 ps
T202 /workspace/coverage/cover_reg_top/35.rv_dm_tap_fsm_rand_reset.3060812063 May 28 01:03:15 PM PDT 24 May 28 01:03:47 PM PDT 24 21636216223 ps
T203 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.3688638638 May 28 01:03:08 PM PDT 24 May 28 01:03:16 PM PDT 24 1696076777 ps
T204 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.2239297603 May 28 01:02:41 PM PDT 24 May 28 01:03:00 PM PDT 24 5657988531 ps
T205 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.1529601573 May 28 01:03:03 PM PDT 24 May 28 01:03:10 PM PDT 24 4407129644 ps
T206 /workspace/coverage/cover_reg_top/24.rv_dm_tap_fsm_rand_reset.2256077616 May 28 01:03:14 PM PDT 24 May 28 01:03:49 PM PDT 24 7037204983 ps
T207 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.635943838 May 28 01:02:45 PM PDT 24 May 28 01:03:16 PM PDT 24 18649825903 ps
T62 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3509550833 May 28 01:03:03 PM PDT 24 May 28 01:03:23 PM PDT 24 1059109677 ps
T100 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2836679690 May 28 01:03:08 PM PDT 24 May 28 01:03:16 PM PDT 24 379512203 ps
T105 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.3203924591 May 28 01:03:02 PM PDT 24 May 28 01:03:11 PM PDT 24 1113967679 ps
T91 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2013704097 May 28 01:02:34 PM PDT 24 May 28 01:02:38 PM PDT 24 57409299 ps
T101 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.3439576835 May 28 01:03:04 PM PDT 24 May 28 01:03:11 PM PDT 24 44292699 ps
T92 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.4101583037 May 28 01:02:58 PM PDT 24 May 28 01:03:06 PM PDT 24 161405401 ps
T208 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.1408201279 May 28 01:02:40 PM PDT 24 May 28 01:02:44 PM PDT 24 164633506 ps
T209 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.3415726441 May 28 01:03:04 PM PDT 24 May 28 01:03:13 PM PDT 24 591293159 ps
T108 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.3006229748 May 28 01:02:45 PM PDT 24 May 28 01:03:04 PM PDT 24 773319876 ps
T210 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2652767485 May 28 01:02:34 PM PDT 24 May 28 01:04:12 PM PDT 24 30492262347 ps
T211 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2140295682 May 28 01:02:46 PM PDT 24 May 28 01:02:52 PM PDT 24 116560095 ps
T212 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.3947557191 May 28 01:02:32 PM PDT 24 May 28 01:02:37 PM PDT 24 94401778 ps
T109 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1199190568 May 28 01:03:15 PM PDT 24 May 28 01:03:44 PM PDT 24 1896645959 ps
T213 /workspace/coverage/cover_reg_top/22.rv_dm_tap_fsm_rand_reset.1155533233 May 28 01:03:14 PM PDT 24 May 28 01:03:38 PM PDT 24 7927776379 ps
T93 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.41253442 May 28 01:02:34 PM PDT 24 May 28 01:02:39 PM PDT 24 166743793 ps
T214 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.3904382344 May 28 01:02:50 PM PDT 24 May 28 01:03:24 PM PDT 24 1584322557 ps
T120 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.1045256694 May 28 01:02:56 PM PDT 24 May 28 01:03:17 PM PDT 24 730157284 ps
T215 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.1599048867 May 28 01:02:46 PM PDT 24 May 28 01:02:57 PM PDT 24 64142400 ps
T102 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.346761518 May 28 01:02:49 PM PDT 24 May 28 01:02:57 PM PDT 24 129681252 ps
T106 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.3772857540 May 28 01:02:27 PM PDT 24 May 28 01:02:36 PM PDT 24 1554139943 ps
T116 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2574042860 May 28 01:02:59 PM PDT 24 May 28 01:03:19 PM PDT 24 2437730801 ps
T216 /workspace/coverage/cover_reg_top/37.rv_dm_tap_fsm_rand_reset.3591702187 May 28 01:03:19 PM PDT 24 May 28 01:03:56 PM PDT 24 30421677030 ps
T217 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3374955135 May 28 01:02:24 PM PDT 24 May 28 01:02:26 PM PDT 24 39251734 ps
T218 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.2708546413 May 28 01:02:38 PM PDT 24 May 28 01:03:08 PM PDT 24 1175310779 ps
T219 /workspace/coverage/cover_reg_top/17.rv_dm_tap_fsm_rand_reset.608075631 May 28 01:02:59 PM PDT 24 May 28 01:03:20 PM PDT 24 16049077830 ps
T220 /workspace/coverage/cover_reg_top/31.rv_dm_tap_fsm_rand_reset.1141926706 May 28 01:03:07 PM PDT 24 May 28 01:03:32 PM PDT 24 11028566136 ps
T221 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.70914617 May 28 01:03:03 PM PDT 24 May 28 01:03:11 PM PDT 24 120945066 ps
T222 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2102212127 May 28 01:02:53 PM PDT 24 May 28 01:03:00 PM PDT 24 28881135 ps
T110 /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.3554661712 May 28 01:02:28 PM PDT 24 May 28 01:02:53 PM PDT 24 7369817446 ps
T223 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.1529277663 May 28 01:03:08 PM PDT 24 May 28 01:03:15 PM PDT 24 54622286 ps
T31 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.3964738491 May 28 01:02:53 PM PDT 24 May 28 01:03:01 PM PDT 24 904961970 ps
T122 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.69199436 May 28 01:03:00 PM PDT 24 May 28 01:03:13 PM PDT 24 1539155748 ps
T111 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.3592368508 May 28 01:02:36 PM PDT 24 May 28 01:02:58 PM PDT 24 1211366253 ps
T224 /workspace/coverage/cover_reg_top/36.rv_dm_tap_fsm_rand_reset.3409478090 May 28 01:03:06 PM PDT 24 May 28 01:03:26 PM PDT 24 14653558059 ps
T107 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2999294688 May 28 01:02:55 PM PDT 24 May 28 01:03:05 PM PDT 24 588074977 ps
T59 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1301346953 May 28 01:02:36 PM PDT 24 May 28 01:02:40 PM PDT 24 780241840 ps
T225 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2537482958 May 28 01:02:38 PM PDT 24 May 28 01:02:55 PM PDT 24 5238667094 ps
T38 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.1178068711 May 28 01:02:45 PM PDT 24 May 28 01:02:53 PM PDT 24 1271734263 ps
T226 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.1497851640 May 28 01:02:31 PM PDT 24 May 28 01:02:38 PM PDT 24 797136261 ps
T227 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1441952487 May 28 01:02:53 PM PDT 24 May 28 01:03:00 PM PDT 24 46201601 ps
T228 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.1116008675 May 28 01:03:00 PM PDT 24 May 28 01:03:14 PM PDT 24 1042681102 ps
T229 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3492838120 May 28 01:03:11 PM PDT 24 May 28 01:03:25 PM PDT 24 1536281932 ps
T230 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.1417276061 May 28 01:02:55 PM PDT 24 May 28 01:03:02 PM PDT 24 506639741 ps
T231 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3702404085 May 28 01:02:53 PM PDT 24 May 28 01:03:03 PM PDT 24 230370709 ps
T232 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.1661356445 May 28 01:02:42 PM PDT 24 May 28 01:03:37 PM PDT 24 1424195724 ps
T233 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.3723908645 May 28 01:03:00 PM PDT 24 May 28 01:03:08 PM PDT 24 1475838078 ps
T234 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.4204342134 May 28 01:03:02 PM PDT 24 May 28 01:03:08 PM PDT 24 576326172 ps
T94 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2801211823 May 28 01:02:49 PM PDT 24 May 28 01:03:01 PM PDT 24 972662617 ps
T235 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.2588673206 May 28 01:03:18 PM PDT 24 May 28 01:03:30 PM PDT 24 798314632 ps
T236 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.667112369 May 28 01:03:02 PM PDT 24 May 28 01:03:10 PM PDT 24 155629760 ps
T237 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3254417266 May 28 01:03:01 PM PDT 24 May 28 01:03:10 PM PDT 24 87260112 ps
T238 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1531344478 May 28 01:02:32 PM PDT 24 May 28 01:02:37 PM PDT 24 410599512 ps
T239 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1569080788 May 28 01:03:11 PM PDT 24 May 28 01:03:18 PM PDT 24 54469243 ps
T121 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.4092298550 May 28 01:02:49 PM PDT 24 May 28 01:03:04 PM PDT 24 973823581 ps
T240 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.3367541115 May 28 01:02:45 PM PDT 24 May 28 01:03:22 PM PDT 24 7709598847 ps
T241 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2309869030 May 28 01:02:37 PM PDT 24 May 28 01:02:40 PM PDT 24 47948191 ps
T242 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.3035981835 May 28 01:03:13 PM PDT 24 May 28 01:03:25 PM PDT 24 59245701 ps
T243 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.987820838 May 28 01:02:32 PM PDT 24 May 28 01:02:37 PM PDT 24 36205769 ps
T244 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2209114291 May 28 01:02:54 PM PDT 24 May 28 01:03:06 PM PDT 24 150982804 ps
T245 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3000932016 May 28 01:02:47 PM PDT 24 May 28 01:02:55 PM PDT 24 68505966 ps
T246 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.640427981 May 28 01:03:02 PM PDT 24 May 28 01:03:26 PM PDT 24 3232936816 ps
T247 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1766885375 May 28 01:02:45 PM PDT 24 May 28 01:02:49 PM PDT 24 44723264 ps
T248 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.4093102634 May 28 01:02:50 PM PDT 24 May 28 01:03:35 PM PDT 24 16063455165 ps
T249 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.1148213488 May 28 01:02:59 PM PDT 24 May 28 01:03:08 PM PDT 24 99224045 ps
T250 /workspace/coverage/cover_reg_top/18.rv_dm_tap_fsm_rand_reset.3523465065 May 28 01:03:15 PM PDT 24 May 28 01:03:51 PM PDT 24 7455357113 ps
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