Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	183074	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	561695	1		T8	7		T4	9		T9	5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	444290	1		T4	8		T9	6		T18	6
values[0x0]	147927	1		T8	23		T4	10		T9	3
values[0x1]	152552	1		T8	14		T4	16		T9	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	141491	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	603278	1		T8	10		T4	14		T9	6

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2575	1		T20	1		T12	1		T13	1
valid_sources[0x01]	2973	1		T33	1		T48	200		T49	7
valid_sources[0x02]	2821	1		T48	177		T49	77		T44	13
valid_sources[0x03]	2815	1		T8	1		T6	1		T131	2
valid_sources[0x04]	2613	1		T8	1		T19	1		T131	2
valid_sources[0x05]	2927	1		T20	1		T13	2		T132	1
valid_sources[0x06]	3216	1		T131	1		T48	210		T49	5
valid_sources[0x07]	2642	1		T6	1		T68	1		T31	3
valid_sources[0x08]	2774	1		T133	1		T134	3		T48	220
valid_sources[0x09]	2555	1		T20	1		T13	1		T29	1
valid_sources[0x0a]	3383	1		T48	221		T50	1		T49	24
valid_sources[0x0b]	2567	1		T133	1		T48	233		T49	40
valid_sources[0x0c]	2497	1		T8	1		T13	1		T48	200
valid_sources[0x0d]	2464	1		T19	1		T42	2		T28	1
valid_sources[0x0e]	3350	1		T7	1		T28	1		T132	1
valid_sources[0x0f]	2959	1		T68	1		T132	1		T135	1
valid_sources[0x10]	3074	1		T135	1		T29	1		T134	3
valid_sources[0x11]	2595	1		T6	1		T28	1		T133	1
valid_sources[0x12]	2571	1		T18	1		T20	1		T28	1
valid_sources[0x13]	2570	1		T28	1		T33	2		T48	223
valid_sources[0x14]	3571	1		T131	2		T38	1		T33	1
valid_sources[0x15]	2548	1		T28	1		T132	2		T33	2
valid_sources[0x16]	2560	1		T20	2		T48	211		T49	25
valid_sources[0x17]	3439	1		T28	1		T135	1		T136	1
valid_sources[0x18]	3057	1		T7	1		T13	1		T19	1
valid_sources[0x19]	3032	1		T19	1		T133	2		T48	191
valid_sources[0x1a]	4170	1		T13	1		T131	1		T29	4
valid_sources[0x1b]	3601	1		T9	1		T28	1		T136	1
valid_sources[0x1c]	3100	1		T6	1		T137	133		T48	214
valid_sources[0x1d]	2815	1		T33	2		T48	219		T49	18
valid_sources[0x1e]	2650	1		T7	1		T132	1		T48	241
valid_sources[0x1f]	3079	1		T28	2		T133	1		T48	230
valid_sources[0x20]	3044	1		T6	1		T12	1		T133	2
valid_sources[0x21]	3645	1		T68	1		T134	1		T48	212
valid_sources[0x22]	2524	1		T132	1		T48	201		T49	15
valid_sources[0x23]	2909	1		T6	1		T29	1		T48	222
valid_sources[0x24]	2725	1		T132	1		T133	1		T33	2
valid_sources[0x25]	2947	1		T132	1		T48	187		T50	1
valid_sources[0x26]	3397	1		T28	1		T30	1		T136	1
valid_sources[0x27]	2658	1		T7	1		T13	1		T33	2
valid_sources[0x28]	4103	1		T9	1		T28	1		T131	2
valid_sources[0x29]	2916	1		T13	2		T29	3		T48	204
valid_sources[0x2a]	2663	1		T6	2		T132	1		T136	1
valid_sources[0x2b]	2592	1		T8	2		T136	1		T134	2
valid_sources[0x2c]	2876	1		T131	1		T133	1		T134	2
valid_sources[0x2d]	3232	1		T8	1		T13	3		T133	2
valid_sources[0x2e]	2676	1		T48	220		T50	4		T49	14
valid_sources[0x2f]	3250	1		T132	2		T33	1		T48	196
valid_sources[0x30]	2981	1		T6	1		T12	1		T31	2
valid_sources[0x31]	3281	1		T31	2		T132	1		T134	1
valid_sources[0x32]	2332	1		T13	1		T48	215		T49	36
valid_sources[0x33]	2689	1		T132	1		T29	1		T48	198
valid_sources[0x34]	2731	1		T13	1		T132	1		T38	1
valid_sources[0x35]	3223	1		T7	1		T48	194		T49	18
valid_sources[0x36]	2812	1		T7	1		T12	1		T48	204
valid_sources[0x37]	3083	1		T6	1		T28	1		T29	1
valid_sources[0x38]	2505	1		T7	2		T12	2		T27	12
valid_sources[0x39]	2936	1		T132	2		T29	1		T134	1
valid_sources[0x3a]	2908	1		T68	1		T48	186		T50	7
valid_sources[0x3b]	3179	1		T133	2		T48	200		T49	16
valid_sources[0x3c]	2791	1		T13	1		T19	1		T28	1
valid_sources[0x3d]	2841	1		T7	1		T138	1		T48	227
valid_sources[0x3e]	2681	1		T28	1		T48	167		T50	24
valid_sources[0x3f]	3457	1		T32	1		T136	1		T133	4
valid_sources[0x40]	3057	1		T132	1		T131	1		T33	2
valid_sources[0x41]	2677	1		T12	1		T133	1		T48	215
valid_sources[0x42]	2890	1		T8	1		T131	1		T133	1
valid_sources[0x43]	2691	1		T9	3		T6	1		T132	1
valid_sources[0x44]	2679	1		T8	5		T132	1		T138	1
valid_sources[0x45]	2967	1		T135	1		T133	1		T33	1
valid_sources[0x46]	2606	1		T29	1		T134	2		T48	183
valid_sources[0x47]	3115	1		T33	2		T48	231		T49	41
valid_sources[0x48]	2854	1		T16	1		T37	2		T131	1
valid_sources[0x49]	2878	1		T4	34		T36	1		T48	194
valid_sources[0x4a]	2672	1		T8	1		T6	2		T7	1
valid_sources[0x4b]	3461	1		T6	1		T29	1		T134	1
valid_sources[0x4c]	2700	1		T131	1		T133	1		T48	180
valid_sources[0x4d]	2483	1		T28	3		T132	1		T33	1
valid_sources[0x4e]	2891	1		T20	3		T133	3		T48	242
valid_sources[0x4f]	2959	1		T13	1		T16	1		T133	1
valid_sources[0x50]	2866	1		T6	1		T28	2		T33	1
valid_sources[0x51]	2817	1		T42	1		T132	1		T131	2
valid_sources[0x52]	2587	1		T132	1		T135	1		T37	1
valid_sources[0x53]	2476	1		T12	1		T33	1		T48	208
valid_sources[0x54]	2715	1		T13	1		T28	1		T29	2
valid_sources[0x55]	2516	1		T12	1		T28	1		T132	2
valid_sources[0x56]	2694	1		T6	1		T7	1		T132	1
valid_sources[0x57]	3479	1		T9	1		T134	2		T48	193
valid_sources[0x58]	2826	1		T28	1		T29	1		T48	186
valid_sources[0x59]	2674	1		T6	1		T12	1		T48	179
valid_sources[0x5a]	3052	1		T13	1		T29	2		T134	1
valid_sources[0x5b]	2412	1		T20	1		T133	1		T134	1
valid_sources[0x5c]	3148	1		T12	2		T13	1		T28	1
valid_sources[0x5d]	3065	1		T132	1		T29	1		T48	208
valid_sources[0x5e]	2722	1		T8	2		T48	235		T49	42
valid_sources[0x5f]	2918	1		T20	1		T132	1		T29	1
valid_sources[0x60]	2905	1		T131	2		T48	196		T49	19
valid_sources[0x61]	3402	1		T9	2		T20	1		T132	1
valid_sources[0x62]	3401	1		T48	202		T50	2		T49	60
valid_sources[0x63]	2502	1		T19	1		T28	1		T132	4
valid_sources[0x64]	2963	1		T38	1		T48	190		T50	2
valid_sources[0x65]	2854	1		T6	2		T48	191		T50	1
valid_sources[0x66]	2641	1		T20	1		T13	1		T32	1
valid_sources[0x67]	2626	1		T12	2		T19	1		T28	1
valid_sources[0x68]	2706	1		T6	1		T42	3		T28	1
valid_sources[0x69]	2690	1		T139	14		T132	2		T133	1
valid_sources[0x6a]	2770	1		T8	1		T132	1		T133	1
valid_sources[0x6b]	2460	1		T131	1		T48	208		T44	19
valid_sources[0x6c]	2904	1		T20	1		T132	1		T135	1
valid_sources[0x6d]	2690	1		T13	2		T132	1		T33	2
valid_sources[0x6e]	2827	1		T6	1		T32	1		T28	1
valid_sources[0x6f]	2986	1		T8	1		T28	2		T29	1
valid_sources[0x70]	2810	1		T13	1		T140	1		T29	1
valid_sources[0x71]	2911	1		T134	2		T33	1		T48	226
valid_sources[0x72]	2677	1		T42	1		T140	1		T48	223
valid_sources[0x73]	2617	1		T9	2		T13	2		T48	203
valid_sources[0x74]	2761	1		T8	2		T20	1		T12	1
valid_sources[0x75]	2729	1		T6	1		T13	2		T28	1
valid_sources[0x76]	3171	1		T13	1		T132	2		T131	2
valid_sources[0x77]	2608	1		T20	1		T13	1		T28	1
valid_sources[0x78]	2851	1		T141	1		T135	1		T48	183
valid_sources[0x79]	3953	1		T131	1		T33	2		T48	193
valid_sources[0x7a]	2913	1		T13	2		T28	1		T132	1
valid_sources[0x7b]	2510	1		T6	2		T7	1		T12	1
valid_sources[0x7c]	3065	1		T28	1		T48	228		T50	1
valid_sources[0x7d]	2538	1		T28	1		T29	1		T133	1
valid_sources[0x7e]	3272	1		T8	1		T68	1		T29	1
valid_sources[0x7f]	3018	1		T134	1		T48	214		T50	7
valid_sources[0x80]	2384	1		T28	1		T132	1		T133	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

269598

1

T4

1

T9

2

T18

3

values[0x0]

all_enables

biggest_size

146006

1

T8

3

T4

3

T9

3

values[0x1]

all_enables

biggest_size

146091

1

T8

4

T4

5

T18

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4812	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	13673	1		T1	1		T23	1		T24	2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	7855	1		T48	1400		T50	3		T49	40
values[0x0]	5180	1		T1	8		T23	7		T24	5
values[0x1]	5450	1		T1	4		T23	4		T24	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3770	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	14715	1		T1	1		T23	1		T24	3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	77	1		T142	1		T48	3		T72	2
valid_sources[0x01]	77	1		T48	5		T47	2		T45	1
valid_sources[0x02]	70	1		T112	1		T48	3		T44	1
valid_sources[0x03]	69	1		T48	2		T75	9		T65	1
valid_sources[0x04]	90	1		T143	1		T48	1		T75	4
valid_sources[0x05]	84	1		T43	1		T113	1		T48	8
valid_sources[0x06]	68	1		T43	1		T48	4		T75	11
valid_sources[0x07]	60	1		T144	1		T48	2		T49	1
valid_sources[0x08]	61	1		T48	7		T49	1		T46	2
valid_sources[0x09]	59	1		T48	9		T75	3		T46	3
valid_sources[0x0a]	56	1		T113	2		T145	2		T146	3
valid_sources[0x0b]	57	1		T147	3		T48	9		T47	5
valid_sources[0x0c]	54	1		T48	2		T47	1		T75	11
valid_sources[0x0d]	70	1		T148	1		T48	4		T47	5
valid_sources[0x0e]	45	1		T48	3		T44	1		T75	1
valid_sources[0x0f]	50	1		T24	1		T48	6		T50	1
valid_sources[0x10]	62	1		T113	1		T48	5		T65	3
valid_sources[0x11]	116	1		T48	9		T75	8		T70	1
valid_sources[0x12]	78	1		T149	4		T48	9		T46	3
valid_sources[0x13]	69	1		T53	1		T150	2		T48	10
valid_sources[0x14]	88	1		T48	7		T49	5		T45	1
valid_sources[0x15]	97	1		T49	3		T75	2		T79	1
valid_sources[0x16]	48	1		T151	1		T48	2		T49	1
valid_sources[0x17]	116	1		T48	1		T47	5		T75	3
valid_sources[0x18]	55	1		T152	14		T150	1		T48	6
valid_sources[0x19]	77	1		T143	1		T48	7		T45	4
valid_sources[0x1a]	61	1		T48	10		T70	2		T124	2
valid_sources[0x1b]	74	1		T143	1		T48	5		T46	3
valid_sources[0x1c]	81	1		T147	1		T153	1		T48	18
valid_sources[0x1d]	56	1		T48	2		T49	1		T75	9
valid_sources[0x1e]	105	1		T146	3		T48	8		T46	7
valid_sources[0x1f]	49	1		T48	7		T75	2		T70	1
valid_sources[0x20]	51	1		T118	1		T147	1		T48	10
valid_sources[0x21]	78	1		T113	1		T143	1		T154	9
valid_sources[0x22]	53	1		T113	1		T155	1		T48	3
valid_sources[0x23]	88	1		T156	1		T157	1		T48	4
valid_sources[0x24]	77	1		T158	1		T48	9		T47	1
valid_sources[0x25]	45	1		T48	3		T49	1		T65	3
valid_sources[0x26]	57	1		T157	1		T150	1		T48	11
valid_sources[0x27]	71	1		T48	4		T45	1		T85	19
valid_sources[0x28]	35	1		T143	1		T48	8		T65	1
valid_sources[0x29]	139	1		T48	2		T75	3		T65	1
valid_sources[0x2a]	90	1		T159	17		T48	13		T75	7
valid_sources[0x2b]	57	1		T151	1		T48	5		T49	3
valid_sources[0x2c]	56	1		T147	1		T148	1		T146	1
valid_sources[0x2d]	97	1		T56	1		T150	1		T158	1
valid_sources[0x2e]	40	1		T151	1		T48	4		T75	4
valid_sources[0x2f]	76	1		T48	9		T44	1		T45	5
valid_sources[0x30]	100	1		T48	10		T45	6		T75	3
valid_sources[0x31]	102	1		T67	1		T56	8		T48	1
valid_sources[0x32]	60	1		T119	2		T48	4		T70	2
valid_sources[0x33]	80	1		T48	4		T44	1		T46	10
valid_sources[0x34]	72	1		T24	1		T48	6		T44	1
valid_sources[0x35]	78	1		T52	4		T160	1		T157	1
valid_sources[0x36]	58	1		T155	1		T48	11		T65	2
valid_sources[0x37]	64	1		T43	1		T158	1		T48	7
valid_sources[0x38]	61	1		T48	6		T75	15		T65	1
valid_sources[0x39]	88	1		T24	1		T142	1		T157	1
valid_sources[0x3a]	52	1		T143	1		T48	7		T49	1
valid_sources[0x3b]	39	1		T67	1		T48	6		T66	1
valid_sources[0x3c]	80	1		T48	3		T49	3		T44	2
valid_sources[0x3d]	44	1		T112	1		T145	4		T48	2
valid_sources[0x3e]	63	1		T142	1		T48	4		T46	1
valid_sources[0x3f]	50	1		T48	3		T47	5		T75	7
valid_sources[0x40]	49	1		T48	4		T65	1		T70	1
valid_sources[0x41]	69	1		T48	5		T45	2		T70	4
valid_sources[0x42]	60	1		T155	1		T48	8		T65	5
valid_sources[0x43]	84	1		T43	1		T48	6		T50	1
valid_sources[0x44]	51	1		T48	4		T75	2		T66	1
valid_sources[0x45]	76	1		T50	1		T44	1		T47	1
valid_sources[0x46]	55	1		T145	1		T48	3		T47	4
valid_sources[0x47]	48	1		T155	1		T48	4		T45	1
valid_sources[0x48]	65	1		T48	6		T47	3		T75	2
valid_sources[0x49]	60	1		T112	1		T48	4		T49	1
valid_sources[0x4a]	71	1		T118	1		T119	1		T155	1
valid_sources[0x4b]	129	1		T155	1		T48	4		T70	1
valid_sources[0x4c]	52	1		T153	1		T48	4		T47	1
valid_sources[0x4d]	74	1		T147	1		T48	6		T75	3
valid_sources[0x4e]	91	1		T48	3		T75	4		T46	1
valid_sources[0x4f]	79	1		T161	1		T156	2		T48	3
valid_sources[0x50]	98	1		T48	9		T75	16		T70	1
valid_sources[0x51]	107	1		T53	1		T156	6		T48	2
valid_sources[0x52]	91	1		T48	18		T44	1		T75	2
valid_sources[0x53]	75	1		T48	5		T49	2		T44	1
valid_sources[0x54]	54	1		T162	1		T48	10		T85	3
valid_sources[0x55]	57	1		T146	2		T48	6		T65	1
valid_sources[0x56]	41	1		T48	1		T44	2		T45	1
valid_sources[0x57]	50	1		T48	6		T44	2		T75	3
valid_sources[0x58]	76	1		T53	1		T151	1		T48	4
valid_sources[0x59]	56	1		T147	1		T48	11		T46	2
valid_sources[0x5a]	71	1		T163	9		T44	1		T46	2
valid_sources[0x5b]	72	1		T48	10		T47	7		T75	3
valid_sources[0x5c]	48	1		T24	1		T48	2		T44	1
valid_sources[0x5d]	32	1		T48	7		T70	2		T79	1
valid_sources[0x5e]	101	1		T45	2		T70	2		T83	1
valid_sources[0x5f]	84	1		T119	1		T48	7		T47	3
valid_sources[0x60]	61	1		T118	1		T65	1		T70	1
valid_sources[0x61]	181	1		T119	1		T48	9		T65	1
valid_sources[0x62]	71	1		T155	1		T48	1		T44	2
valid_sources[0x63]	41	1		T48	4		T47	1		T66	1
valid_sources[0x64]	70	1		T48	6		T49	4		T75	8
valid_sources[0x65]	44	1		T43	1		T75	2		T70	1
valid_sources[0x66]	86	1		T24	1		T48	5		T44	1
valid_sources[0x67]	94	1		T48	1		T47	2		T70	4
valid_sources[0x68]	87	1		T48	4		T47	1		T70	3
valid_sources[0x69]	46	1		T150	1		T49	1		T75	3
valid_sources[0x6a]	433	1		T48	18		T49	1		T47	2
valid_sources[0x6b]	63	1		T43	2		T157	1		T158	1
valid_sources[0x6c]	74	1		T147	1		T48	5		T47	3
valid_sources[0x6d]	95	1		T157	1		T48	5		T66	1
valid_sources[0x6e]	61	1		T48	4		T49	1		T45	1
valid_sources[0x6f]	62	1		T119	1		T48	5		T75	1
valid_sources[0x70]	118	1		T119	2		T157	1		T48	1
valid_sources[0x71]	68	1		T157	1		T48	3		T49	1
valid_sources[0x72]	70	1		T112	1		T164	1		T147	1
valid_sources[0x73]	81	1		T23	10		T142	1		T48	3
valid_sources[0x74]	48	1		T1	3		T48	7		T83	1
valid_sources[0x75]	54	1		T53	1		T48	3		T49	2
valid_sources[0x76]	60	1		T48	6		T44	1		T65	1
valid_sources[0x77]	50	1		T48	7		T75	9		T70	1
valid_sources[0x78]	98	1		T113	1		T48	5		T45	2
valid_sources[0x79]	55	1		T144	1		T48	5		T44	1
valid_sources[0x7a]	87	1		T51	9		T165	1		T48	5
valid_sources[0x7b]	52	1		T48	3		T75	1		T70	2
valid_sources[0x7c]	89	1		T48	15		T83	1		T72	3
valid_sources[0x7d]	126	1		T158	2		T48	4		T75	2
valid_sources[0x7e]	64	1		T48	5		T65	1		T70	6
valid_sources[0x7f]	94	1		T156	4		T48	10		T75	22
valid_sources[0x80]	110	1		T143	1		T48	5		T47	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

5102

1

T48

706

T50

1

T49

40

values[0x0]

all_enables

biggest_size

4347

1

T1

1

T23

1

T24

1

values[0x1]

all_enables

biggest_size

4224

1

T24

1

T53

1

T67

1