Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
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Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block] 100.00 1 100 1 64 64




Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
partial 217000 1 T8 30 T4 25 T9 9
full_word 562914 1 T8 7 T4 9 T9 5



Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 779584 1 T8 37 T4 34 T9 14
auto[TlIntgErrCmd] 109 1 T44 4 T45 2 T46 10
auto[TlIntgErrData] 123 1 T44 5 T45 4 T46 5
auto[TlIntgErrBoth] 98 1 T44 1 T45 4 T46 5



Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 445735 1 T4 8 T9 6 T18 6
auto[1] 334179 1 T8 37 T4 26 T9 8



Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 175858 1 T4 7 T9 4 T18 3
auto[TlIntgErrNone] partial auto[1] 40837 1 T8 30 T4 18 T9 5
auto[TlIntgErrNone] full_word auto[0] 269720 1 T4 1 T9 2 T18 3
auto[TlIntgErrNone] full_word auto[1] 293169 1 T8 7 T4 8 T9 3
auto[TlIntgErrCmd] partial auto[0] 43 1 T44 1 T45 2 T46 5
auto[TlIntgErrCmd] partial auto[1] 58 1 T44 3 T46 5 T83 1
auto[TlIntgErrCmd] full_word auto[0] 5 1 T125 2 T114 1 T122 1
auto[TlIntgErrCmd] full_word auto[1] 3 1 T122 1 T126 1 T127 1
auto[TlIntgErrData] partial auto[0] 59 1 T44 1 T45 2 T46 1
auto[TlIntgErrData] partial auto[1] 55 1 T44 3 T45 2 T46 4
auto[TlIntgErrData] full_word auto[0] 7 1 T72 1 T114 1 T128 1
auto[TlIntgErrData] full_word auto[1] 2 1 T44 1 T129 1 - -
auto[TlIntgErrBoth] partial auto[0] 39 1 T44 1 T45 2 T46 1
auto[TlIntgErrBoth] partial auto[1] 51 1 T45 2 T46 4 T85 3
auto[TlIntgErrBoth] full_word auto[0] 4 1 T85 1 T130 1 T125 1
auto[TlIntgErrBoth] full_word auto[1] 4 1 T130 1 T128 1 T122 1

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