Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
85.71	100.00	55.32	85.71		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	119175844	11855	0	0
late_debug_enable_rd_A	119175844	1900	0	0
late_debug_enable_regwen_rd_A	119175844	2654	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119175844	11855	0	0
T44	90467	5	0	0
T45	52598	5	0	0
T46	69300	3	0	0
T47	27565	781	0	0
T65	103565	81	0	0
T66	12205	24	0	0
T70	5188	689	0	0
T71	13533	52	0	0
T83	280524	2	0	0
T85	34577	1	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119175844	1900	0	0
T44	90467	55	0	0
T50	6935	4	0	0
T66	12205	15	0	0
T72	205494	114	0	0
T75	633461	312	0	0
T77	12647	3	0	0
T79	19748	20	0	0
T114	134641	82	0	0
T115	4429	5	0	0
T116	11469	22	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119175844	2654	0	0
T44	90467	27	0	0
T50	6935	2	0	0
T66	12205	15	0	0
T72	205494	108	0	0
T75	633461	316	0	0
T77	12647	9	0	0
T79	19748	8	0	0
T101	18098	9	0	0
T114	134641	72	0	0
T115	4429	6	0	0