Module Definition
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Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_clock_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_rst_n_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_scan.i_dft_tck_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT4,T18,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T18,T6
11CoveredT4,T18,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT4,T18,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 11650102 11649086 0 0
selKnown1 82223869 82222853 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 11650102 11649086 0 0
T1 216 214 0 0
T2 107520 107518 0 0
T3 376754 376750 0 0
T4 35237 35233 0 0
T5 376366 376362 0 0
T8 35234 35230 0 0
T10 38482 38478 0 0
T15 179682 179678 0 0
T17 0 36 0 0
T18 0 30 0 0
T21 0 32 0 0
T23 342 338 0 0
T24 244 240 0 0
T39 0 20 0 0
T40 0 20 0 0
T43 2 0 0 0
T53 2 0 0 0
T59 0 20 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 82223869 82222853 0 0
T1 4372 4370 0 0
T2 700136 700134 0 0
T3 753097 753093 0 0
T4 288118 288114 0 0
T5 1062651 1062647 0 0
T8 150253 150249 0 0
T10 798060 798056 0 0
T15 325012 325009 0 0
T17 0 36 0 0
T18 0 6 0 0
T21 0 32 0 0
T23 15309 15305 0 0
T24 3297 3293 0 0
T39 0 20 0 0
T40 0 20 0 0
T43 2 0 0 0
T53 2 0 0 0
T59 0 20 0 0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT4,T18,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T18,T6
11CoveredT4,T18,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT18,T6,T117
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 4688987 4688827 0 0
selKnown1 75262998 75262838 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 4688987 4688827 0 0
T1 108 107 0 0
T2 53760 53759 0 0
T3 188360 188359 0 0
T4 15819 15818 0 0
T5 188162 188161 0 0
T8 17616 17615 0 0
T10 19235 19234 0 0
T15 89840 89839 0 0
T23 170 169 0 0
T24 121 120 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 75262998 75262838 0 0
T1 4264 4263 0 0
T2 646376 646375 0 0
T3 564703 564702 0 0
T4 268701 268700 0 0
T5 874447 874446 0 0
T8 132635 132634 0 0
T10 778815 778814 0 0
T15 235170 235170 0 0
T23 15137 15136 0 0
T24 3174 3173 0 0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT4,T18,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T18,T6
11CoveredT4,T18,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT18,T6,T117
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 473 313 0 0
selKnown1 419 259 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 473 313 0 0
T3 17 16 0 0
T4 3 2 0 0
T5 21 20 0 0
T8 1 0 0 0
T10 5 4 0 0
T15 1 0 0 0
T17 0 18 0 0
T18 0 4 0 0
T21 0 16 0 0
T23 1 0 0 0
T24 1 0 0 0
T39 0 10 0 0
T40 0 10 0 0
T43 1 0 0 0
T53 1 0 0 0
T59 0 10 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 419 259 0 0
T3 17 16 0 0
T4 3 2 0 0
T5 21 20 0 0
T8 1 0 0 0
T10 5 4 0 0
T15 1 0 0 0
T17 0 18 0 0
T18 0 3 0 0
T21 0 16 0 0
T23 1 0 0 0
T24 1 0 0 0
T39 0 10 0 0
T40 0 10 0 0
T43 1 0 0 0
T53 1 0 0 0
T59 0 10 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT4,T18,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T18,T6
11CoveredT4,T18,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT4,T18,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 6959114 6958766 0 0
selKnown1 6959114 6958766 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 6959114 6958766 0 0
T1 108 107 0 0
T2 53760 53759 0 0
T3 188360 188359 0 0
T4 19411 19410 0 0
T5 188162 188161 0 0
T8 17616 17615 0 0
T10 19235 19234 0 0
T15 89840 89839 0 0
T23 170 169 0 0
T24 121 120 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 6959114 6958766 0 0
T1 108 107 0 0
T2 53760 53759 0 0
T3 188360 188359 0 0
T4 19411 19410 0 0
T5 188162 188161 0 0
T8 17616 17615 0 0
T10 19235 19234 0 0
T15 89840 89839 0 0
T23 170 169 0 0
T24 121 120 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT4,T18,T6

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T18,T6
11CoveredT4,T18,T6

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT4,T18,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 1528 1180 0 0
selKnown1 1338 990 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 1528 1180 0 0
T3 17 16 0 0
T4 4 3 0 0
T5 21 20 0 0
T8 1 0 0 0
T10 7 6 0 0
T15 1 0 0 0
T17 0 18 0 0
T18 0 26 0 0
T21 0 16 0 0
T23 1 0 0 0
T24 1 0 0 0
T39 0 10 0 0
T40 0 10 0 0
T43 1 0 0 0
T53 1 0 0 0
T59 0 10 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1338 990 0 0
T3 17 16 0 0
T4 3 2 0 0
T5 21 20 0 0
T8 1 0 0 0
T10 5 4 0 0
T15 1 0 0 0
T17 0 18 0 0
T18 0 3 0 0
T21 0 16 0 0
T23 1 0 0 0
T24 1 0 0 0
T39 0 10 0 0
T40 0 10 0 0
T43 1 0 0 0
T53 1 0 0 0
T59 0 10 0 0

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