Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
78.41 94.66 81.18 86.65 71.79 84.50 97.89 32.17


Total test records in report: 391
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html
T128 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.4179664157 Jun 02 12:51:07 PM PDT 24 Jun 02 12:51:20 PM PDT 24 1076445635 ps
T105 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.80205544 Jun 02 12:50:32 PM PDT 24 Jun 02 12:50:59 PM PDT 24 837023972 ps
T276 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.3930115420 Jun 02 12:50:41 PM PDT 24 Jun 02 12:50:48 PM PDT 24 402931359 ps
T277 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2125062734 Jun 02 12:50:56 PM PDT 24 Jun 02 12:51:08 PM PDT 24 1695606831 ps
T100 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.4252115204 Jun 02 12:50:27 PM PDT 24 Jun 02 12:51:04 PM PDT 24 7489216923 ps
T101 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1924949386 Jun 02 12:50:36 PM PDT 24 Jun 02 12:50:39 PM PDT 24 199571597 ps
T278 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.4104860023 Jun 02 12:50:34 PM PDT 24 Jun 02 12:50:36 PM PDT 24 105455033 ps
T95 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3137977040 Jun 02 12:51:05 PM PDT 24 Jun 02 12:51:14 PM PDT 24 893444870 ps
T279 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2947146352 Jun 02 12:51:03 PM PDT 24 Jun 02 12:51:13 PM PDT 24 6053956902 ps
T131 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3474137206 Jun 02 12:50:33 PM PDT 24 Jun 02 12:50:45 PM PDT 24 1204195660 ps
T280 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.2044742535 Jun 02 12:51:09 PM PDT 24 Jun 02 12:51:14 PM PDT 24 222047445 ps
T111 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2272071801 Jun 02 12:50:54 PM PDT 24 Jun 02 12:50:59 PM PDT 24 324333739 ps
T281 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2690930381 Jun 02 12:50:39 PM PDT 24 Jun 02 12:50:43 PM PDT 24 877340268 ps
T282 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.1482037716 Jun 02 12:50:17 PM PDT 24 Jun 02 12:50:28 PM PDT 24 3603461033 ps
T283 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2798085537 Jun 02 12:50:39 PM PDT 24 Jun 02 12:50:41 PM PDT 24 814574935 ps
T284 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.1780016268 Jun 02 12:51:01 PM PDT 24 Jun 02 12:51:02 PM PDT 24 226102659 ps
T285 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.3216169862 Jun 02 12:50:36 PM PDT 24 Jun 02 12:50:40 PM PDT 24 1343501199 ps
T286 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.752957471 Jun 02 12:50:24 PM PDT 24 Jun 02 12:50:26 PM PDT 24 874090128 ps
T287 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3302810069 Jun 02 12:50:35 PM PDT 24 Jun 02 12:50:39 PM PDT 24 1422996100 ps
T112 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.4284766327 Jun 02 12:50:50 PM PDT 24 Jun 02 12:50:57 PM PDT 24 163165744 ps
T288 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.3609510651 Jun 02 12:50:35 PM PDT 24 Jun 02 12:50:37 PM PDT 24 120181857 ps
T289 /workspace/coverage/cover_reg_top/29.rv_dm_tap_fsm_rand_reset.3864411060 Jun 02 12:51:07 PM PDT 24 Jun 02 12:51:49 PM PDT 24 50498781752 ps
T290 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.182935931 Jun 02 12:50:40 PM PDT 24 Jun 02 12:50:45 PM PDT 24 314152065 ps
T291 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.2344731643 Jun 02 12:50:34 PM PDT 24 Jun 02 12:50:37 PM PDT 24 715731370 ps
T292 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1681213331 Jun 02 12:50:36 PM PDT 24 Jun 02 12:51:07 PM PDT 24 1748691767 ps
T293 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.3156411951 Jun 02 12:50:24 PM PDT 24 Jun 02 12:50:42 PM PDT 24 7659260265 ps
T294 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.2260871567 Jun 02 12:50:27 PM PDT 24 Jun 02 12:50:30 PM PDT 24 60098778 ps
T295 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.1149182398 Jun 02 12:50:21 PM PDT 24 Jun 02 12:50:26 PM PDT 24 1591747153 ps
T96 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3159285819 Jun 02 12:51:07 PM PDT 24 Jun 02 12:51:16 PM PDT 24 4439393832 ps
T296 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.4110867561 Jun 02 12:50:57 PM PDT 24 Jun 02 12:51:04 PM PDT 24 1229246149 ps
T125 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1738683171 Jun 02 12:50:39 PM PDT 24 Jun 02 12:51:00 PM PDT 24 1407621545 ps
T97 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.3716305783 Jun 02 12:50:49 PM PDT 24 Jun 02 12:50:51 PM PDT 24 99396498 ps
T297 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1341176086 Jun 02 12:50:28 PM PDT 24 Jun 02 12:50:30 PM PDT 24 313704084 ps
T298 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.760427910 Jun 02 12:50:59 PM PDT 24 Jun 02 12:51:01 PM PDT 24 297380618 ps
T102 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.955663515 Jun 02 12:50:21 PM PDT 24 Jun 02 12:50:24 PM PDT 24 169940086 ps
T299 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2553676726 Jun 02 12:50:34 PM PDT 24 Jun 02 12:50:37 PM PDT 24 200187739 ps
T300 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.3746011508 Jun 02 12:50:49 PM PDT 24 Jun 02 12:50:56 PM PDT 24 836324231 ps
T301 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2731759024 Jun 02 12:50:26 PM PDT 24 Jun 02 12:50:39 PM PDT 24 4042775200 ps
T103 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1447686203 Jun 02 12:50:40 PM PDT 24 Jun 02 12:50:43 PM PDT 24 155279159 ps
T302 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.511660129 Jun 02 12:50:28 PM PDT 24 Jun 02 12:50:30 PM PDT 24 157526435 ps
T303 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1480511346 Jun 02 12:50:23 PM PDT 24 Jun 02 12:50:25 PM PDT 24 151538776 ps
T304 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2899233080 Jun 02 12:50:27 PM PDT 24 Jun 02 12:50:32 PM PDT 24 73418355 ps
T104 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2680849422 Jun 02 12:50:22 PM PDT 24 Jun 02 12:51:31 PM PDT 24 1184516912 ps
T305 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.3707110131 Jun 02 12:50:40 PM PDT 24 Jun 02 12:50:45 PM PDT 24 3253105617 ps
T306 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.4175098823 Jun 02 12:50:50 PM PDT 24 Jun 02 12:50:52 PM PDT 24 1758843353 ps
T307 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.1452630009 Jun 02 12:50:49 PM PDT 24 Jun 02 12:50:55 PM PDT 24 343246570 ps
T113 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1749504599 Jun 02 12:50:40 PM PDT 24 Jun 02 12:50:44 PM PDT 24 189011241 ps
T308 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.565798626 Jun 02 12:50:48 PM PDT 24 Jun 02 12:50:55 PM PDT 24 13565263435 ps
T309 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.2682188866 Jun 02 12:50:48 PM PDT 24 Jun 02 12:50:53 PM PDT 24 1672800527 ps
T310 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1659147281 Jun 02 12:50:47 PM PDT 24 Jun 02 12:50:49 PM PDT 24 124359769 ps
T126 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.1066010017 Jun 02 12:50:43 PM PDT 24 Jun 02 12:51:06 PM PDT 24 4078999801 ps
T311 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.786587684 Jun 02 12:50:51 PM PDT 24 Jun 02 12:50:56 PM PDT 24 2279854490 ps
T312 /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.804114127 Jun 02 12:50:41 PM PDT 24 Jun 02 12:51:01 PM PDT 24 40350510053 ps
T313 /workspace/coverage/cover_reg_top/27.rv_dm_tap_fsm_rand_reset.1716500398 Jun 02 12:51:08 PM PDT 24 Jun 02 12:52:37 PM PDT 24 52776745797 ps
T314 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.2277948597 Jun 02 12:50:28 PM PDT 24 Jun 02 12:52:19 PM PDT 24 84983323592 ps
T315 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.1683856248 Jun 02 12:50:59 PM PDT 24 Jun 02 12:51:03 PM PDT 24 271871832 ps
T316 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2237487202 Jun 02 12:50:57 PM PDT 24 Jun 02 12:51:00 PM PDT 24 577088197 ps
T106 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.1738758979 Jun 02 12:50:50 PM PDT 24 Jun 02 12:50:52 PM PDT 24 72563863 ps
T317 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.3157594082 Jun 02 12:51:04 PM PDT 24 Jun 02 12:51:07 PM PDT 24 332251342 ps
T127 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.2282523444 Jun 02 12:50:25 PM PDT 24 Jun 02 12:50:45 PM PDT 24 2484420870 ps
T318 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1945724194 Jun 02 12:50:49 PM PDT 24 Jun 02 12:51:03 PM PDT 24 2138355838 ps
T319 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2783110613 Jun 02 12:50:55 PM PDT 24 Jun 02 12:51:00 PM PDT 24 4243792522 ps
T320 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.304728746 Jun 02 12:50:23 PM PDT 24 Jun 02 12:50:26 PM PDT 24 864609028 ps
T321 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.2872495138 Jun 02 12:50:49 PM PDT 24 Jun 02 12:50:51 PM PDT 24 1407538669 ps
T322 /workspace/coverage/cover_reg_top/10.rv_dm_tap_fsm_rand_reset.737118502 Jun 02 12:50:51 PM PDT 24 Jun 02 12:51:38 PM PDT 24 43733838208 ps
T323 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.597255579 Jun 02 12:51:04 PM PDT 24 Jun 02 12:51:07 PM PDT 24 67756341 ps
T324 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2029742887 Jun 02 12:50:35 PM PDT 24 Jun 02 12:52:03 PM PDT 24 58416955675 ps
T325 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.3392352407 Jun 02 12:51:05 PM PDT 24 Jun 02 12:51:11 PM PDT 24 3031281099 ps
T326 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.561230132 Jun 02 12:50:34 PM PDT 24 Jun 02 12:50:35 PM PDT 24 81853928 ps
T107 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.298886331 Jun 02 12:50:58 PM PDT 24 Jun 02 12:50:59 PM PDT 24 206172730 ps
T327 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.506700159 Jun 02 12:50:55 PM PDT 24 Jun 02 12:51:08 PM PDT 24 3008202842 ps
T328 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.3515327516 Jun 02 12:50:59 PM PDT 24 Jun 02 12:51:01 PM PDT 24 250707806 ps
T329 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.2137477520 Jun 02 12:50:57 PM PDT 24 Jun 02 12:50:59 PM PDT 24 1416434517 ps
T330 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.3363216387 Jun 02 12:50:47 PM PDT 24 Jun 02 12:50:56 PM PDT 24 1092899308 ps
T331 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.1078409063 Jun 02 12:50:57 PM PDT 24 Jun 02 12:51:00 PM PDT 24 1099613984 ps
T332 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.1816128553 Jun 02 12:50:22 PM PDT 24 Jun 02 12:50:25 PM PDT 24 1006091800 ps
T108 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.1277374548 Jun 02 12:51:07 PM PDT 24 Jun 02 12:51:10 PM PDT 24 374600611 ps
T333 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3161882907 Jun 02 12:50:47 PM PDT 24 Jun 02 12:50:50 PM PDT 24 4586742067 ps
T334 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.741112697 Jun 02 12:50:33 PM PDT 24 Jun 02 12:51:10 PM PDT 24 18744695121 ps
T335 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.2005042237 Jun 02 12:50:48 PM PDT 24 Jun 02 12:50:49 PM PDT 24 1262023203 ps
T336 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3559399617 Jun 02 12:50:41 PM PDT 24 Jun 02 12:50:49 PM PDT 24 10204313143 ps
T109 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.2907477126 Jun 02 12:51:07 PM PDT 24 Jun 02 12:51:10 PM PDT 24 191772277 ps
T98 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.2703069539 Jun 02 12:50:41 PM PDT 24 Jun 02 12:50:46 PM PDT 24 254300281 ps
T89 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.4230813712 Jun 02 12:50:35 PM PDT 24 Jun 02 12:50:52 PM PDT 24 10831096466 ps
T337 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.1888864280 Jun 02 12:50:48 PM PDT 24 Jun 02 12:50:55 PM PDT 24 210121115 ps
T338 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.4238501487 Jun 02 12:50:22 PM PDT 24 Jun 02 12:51:29 PM PDT 24 10247498187 ps
T339 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.2730529880 Jun 02 12:50:41 PM PDT 24 Jun 02 12:50:43 PM PDT 24 105181954 ps
T340 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.1496750948 Jun 02 12:50:40 PM PDT 24 Jun 02 12:50:47 PM PDT 24 275584092 ps
T341 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.2447527530 Jun 02 12:50:50 PM PDT 24 Jun 02 12:50:52 PM PDT 24 450363774 ps
T342 /workspace/coverage/cover_reg_top/37.rv_dm_tap_fsm_rand_reset.128710119 Jun 02 12:51:14 PM PDT 24 Jun 02 12:51:39 PM PDT 24 48737045750 ps
T343 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.1387546866 Jun 02 12:50:48 PM PDT 24 Jun 02 12:50:56 PM PDT 24 887654237 ps
T344 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3110987102 Jun 02 12:50:27 PM PDT 24 Jun 02 12:50:29 PM PDT 24 184071666 ps
T345 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.4130159202 Jun 02 12:50:29 PM PDT 24 Jun 02 12:50:30 PM PDT 24 363870978 ps
T346 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.2424211350 Jun 02 12:50:27 PM PDT 24 Jun 02 12:50:32 PM PDT 24 2133554349 ps
T347 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.2312232597 Jun 02 12:50:49 PM PDT 24 Jun 02 12:50:50 PM PDT 24 302213118 ps
T348 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.2783315383 Jun 02 12:50:27 PM PDT 24 Jun 02 12:50:29 PM PDT 24 116656054 ps
T349 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.435439161 Jun 02 12:50:28 PM PDT 24 Jun 02 12:50:32 PM PDT 24 539457950 ps
T350 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.1158570140 Jun 02 12:50:21 PM PDT 24 Jun 02 12:50:24 PM PDT 24 2501318757 ps
T351 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.4146120274 Jun 02 12:50:28 PM PDT 24 Jun 02 12:50:54 PM PDT 24 2305859342 ps
T99 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.717866961 Jun 02 12:50:59 PM PDT 24 Jun 02 12:51:01 PM PDT 24 147439798 ps
T352 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.3528300640 Jun 02 12:50:58 PM PDT 24 Jun 02 12:51:04 PM PDT 24 207751227 ps
T353 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.363272160 Jun 02 12:51:05 PM PDT 24 Jun 02 12:51:10 PM PDT 24 3722557211 ps
T354 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.219988522 Jun 02 12:50:55 PM PDT 24 Jun 02 12:50:57 PM PDT 24 1281583053 ps
T355 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.2127345329 Jun 02 12:50:34 PM PDT 24 Jun 02 12:50:35 PM PDT 24 119106756 ps
T356 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.2556854186 Jun 02 12:50:56 PM PDT 24 Jun 02 12:51:00 PM PDT 24 517641016 ps
T357 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.3036078895 Jun 02 12:50:38 PM PDT 24 Jun 02 12:50:46 PM PDT 24 1710419758 ps
T358 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.875508530 Jun 02 12:50:36 PM PDT 24 Jun 02 12:51:03 PM PDT 24 101033067001 ps
T359 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2497892401 Jun 02 12:51:09 PM PDT 24 Jun 02 12:51:34 PM PDT 24 14343463586 ps
T360 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1082139623 Jun 02 12:50:47 PM PDT 24 Jun 02 12:50:52 PM PDT 24 3442897104 ps
T361 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2912322517 Jun 02 12:50:21 PM PDT 24 Jun 02 12:50:32 PM PDT 24 11358192088 ps
T362 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2463690111 Jun 02 12:50:21 PM PDT 24 Jun 02 12:50:29 PM PDT 24 907245236 ps
T363 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.778089420 Jun 02 12:50:38 PM PDT 24 Jun 02 12:50:53 PM PDT 24 4538210724 ps
T364 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3808257517 Jun 02 12:50:22 PM PDT 24 Jun 02 12:50:24 PM PDT 24 173455866 ps
T365 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.2627670905 Jun 02 12:50:17 PM PDT 24 Jun 02 12:50:18 PM PDT 24 258733949 ps
T366 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.3646638895 Jun 02 12:51:05 PM PDT 24 Jun 02 12:51:07 PM PDT 24 304142741 ps
T367 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.1100206540 Jun 02 12:50:36 PM PDT 24 Jun 02 12:50:43 PM PDT 24 364409031 ps
T368 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.2047079337 Jun 02 12:50:27 PM PDT 24 Jun 02 12:50:31 PM PDT 24 257673621 ps
T369 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2648566334 Jun 02 12:50:39 PM PDT 24 Jun 02 12:50:42 PM PDT 24 461397701 ps
T370 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3593250168 Jun 02 12:50:41 PM PDT 24 Jun 02 12:50:50 PM PDT 24 5781708735 ps
T371 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3548802985 Jun 02 12:50:57 PM PDT 24 Jun 02 12:51:00 PM PDT 24 104743382 ps
T372 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.3534369744 Jun 02 12:50:21 PM PDT 24 Jun 02 12:50:22 PM PDT 24 73816967 ps
T373 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3735208714 Jun 02 12:50:49 PM PDT 24 Jun 02 12:50:53 PM PDT 24 1847846250 ps
T374 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.3631561747 Jun 02 12:51:03 PM PDT 24 Jun 02 12:51:13 PM PDT 24 708781402 ps
T130 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3501398061 Jun 02 12:50:21 PM PDT 24 Jun 02 12:50:30 PM PDT 24 669085274 ps
T375 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.2123631390 Jun 02 12:50:36 PM PDT 24 Jun 02 12:50:37 PM PDT 24 56964546 ps
T376 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.629351816 Jun 02 12:50:33 PM PDT 24 Jun 02 12:50:34 PM PDT 24 218422903 ps
T377 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2078881198 Jun 02 12:50:26 PM PDT 24 Jun 02 12:50:27 PM PDT 24 110826605 ps
T378 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3969291833 Jun 02 12:50:51 PM PDT 24 Jun 02 12:51:05 PM PDT 24 1988356104 ps
T379 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.1887369377 Jun 02 12:50:41 PM PDT 24 Jun 02 12:50:47 PM PDT 24 135025157 ps
T380 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.3934361872 Jun 02 12:50:27 PM PDT 24 Jun 02 12:51:55 PM PDT 24 106665045536 ps
T381 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.285127264 Jun 02 12:50:22 PM PDT 24 Jun 02 12:50:56 PM PDT 24 39389544031 ps
T382 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.949477232 Jun 02 12:50:27 PM PDT 24 Jun 02 12:50:36 PM PDT 24 646099418 ps
T383 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.354427426 Jun 02 12:51:06 PM PDT 24 Jun 02 12:51:15 PM PDT 24 692930790 ps
T384 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.1288352845 Jun 02 12:50:39 PM PDT 24 Jun 02 12:50:42 PM PDT 24 154548639 ps
T385 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.838450302 Jun 02 12:50:23 PM PDT 24 Jun 02 12:50:25 PM PDT 24 347663668 ps
T386 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.3894230872 Jun 02 12:50:39 PM PDT 24 Jun 02 12:51:00 PM PDT 24 1918617368 ps
T387 /workspace/coverage/cover_reg_top/18.rv_dm_tap_fsm_rand_reset.697185162 Jun 02 12:51:05 PM PDT 24 Jun 02 12:51:48 PM PDT 24 49416225659 ps
T388 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1933951193 Jun 02 12:50:58 PM PDT 24 Jun 02 12:51:04 PM PDT 24 3729353043 ps
T389 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.2321959836 Jun 02 12:50:37 PM PDT 24 Jun 02 12:50:39 PM PDT 24 78576712 ps
T390 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.2032062713 Jun 02 12:50:50 PM PDT 24 Jun 02 12:50:54 PM PDT 24 1024288513 ps
T391 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.56602194 Jun 02 12:50:29 PM PDT 24 Jun 02 12:50:32 PM PDT 24 2987439322 ps

Test location /workspace/coverage/default/10.rv_dm_stress_all.608258187
Short name T4
Test name
Test status
Simulation time 7946503887 ps
CPU time 18.9 seconds
Started Jun 02 12:51:43 PM PDT 24
Finished Jun 02 12:52:02 PM PDT 24
Peak memory 213420 kb
Host smart-ab59d14a-3842-451f-9f91-43bffa3b727a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608258187 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.608258187
Directory /workspace/10.rv_dm_stress_all/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.1708527893
Short name T36
Test name
Test status
Simulation time 184811085 ps
CPU time 0.87 seconds
Started Jun 02 12:51:34 PM PDT 24
Finished Jun 02 12:51:36 PM PDT 24
Peak memory 204972 kb
Host smart-e51a19b7-12bc-4fb9-a422-71a624216850
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708527893 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.1708527893
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.1760303759
Short name T12
Test name
Test status
Simulation time 84831263224 ps
CPU time 69.3 seconds
Started Jun 02 12:51:46 PM PDT 24
Finished Jun 02 12:52:56 PM PDT 24
Peak memory 213600 kb
Host smart-cdefa79c-4e5f-44de-9bac-ecb14bee6412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760303759 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.1760303759
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/35.rv_dm_tap_fsm_rand_reset.1628225342
Short name T48
Test name
Test status
Simulation time 35244544519 ps
CPU time 38.64 seconds
Started Jun 02 12:51:18 PM PDT 24
Finished Jun 02 12:51:57 PM PDT 24
Peak memory 222116 kb
Host smart-c536672d-aceb-42ef-af4f-1629c4972d29
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628225342 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 35.rv_dm_tap_fsm_rand_reset.1628225342
Directory /workspace/35.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/12.rv_dm_stress_all.3405784337
Short name T9
Test name
Test status
Simulation time 29893843085 ps
CPU time 71.15 seconds
Started Jun 02 12:51:45 PM PDT 24
Finished Jun 02 12:52:56 PM PDT 24
Peak memory 213536 kb
Host smart-a2753f9d-2792-4bf6-a542-3eb3ea2bfeb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405784337 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.3405784337
Directory /workspace/12.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.1783080066
Short name T78
Test name
Test status
Simulation time 2835470608 ps
CPU time 28.77 seconds
Started Jun 02 12:50:21 PM PDT 24
Finished Jun 02 12:50:50 PM PDT 24
Peak memory 205640 kb
Host smart-ecd210f7-17d5-4fac-906d-e37973f0ad31
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783080066 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.1783080066
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3916882862
Short name T71
Test name
Test status
Simulation time 2003388049 ps
CPU time 20.62 seconds
Started Jun 02 12:51:00 PM PDT 24
Finished Jun 02 12:51:21 PM PDT 24
Peak memory 213860 kb
Host smart-91936e9b-b06d-44dd-8b72-ed3981591027
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916882862 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.3
916882862
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.2287524761
Short name T15
Test name
Test status
Simulation time 66885409649 ps
CPU time 123.78 seconds
Started Jun 02 12:51:45 PM PDT 24
Finished Jun 02 12:53:49 PM PDT 24
Peak memory 213636 kb
Host smart-7445ce95-46e3-4d0c-a32e-68982347344b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287524761 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.2287524761
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.114880408
Short name T132
Test name
Test status
Simulation time 29193256905 ps
CPU time 28.15 seconds
Started Jun 02 12:50:38 PM PDT 24
Finished Jun 02 12:51:07 PM PDT 24
Peak memory 222072 kb
Host smart-8c3b7624-8285-4960-809b-41b13d284d19
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114880408 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.114880408
Directory /workspace/6.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.3392488879
Short name T39
Test name
Test status
Simulation time 1517256621 ps
CPU time 2.39 seconds
Started Jun 02 12:51:29 PM PDT 24
Finished Jun 02 12:51:32 PM PDT 24
Peak memory 237480 kb
Host smart-801dfcae-6007-472b-8676-f0c9177f7051
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392488879 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.3392488879
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/30.rv_dm_stress_all.509600656
Short name T18
Test name
Test status
Simulation time 26317956506 ps
CPU time 22.67 seconds
Started Jun 02 12:51:54 PM PDT 24
Finished Jun 02 12:52:17 PM PDT 24
Peak memory 205300 kb
Host smart-f72e3e6d-05da-456f-be8e-e21c499ac259
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509600656 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.509600656
Directory /workspace/30.rv_dm_stress_all/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.1230265573
Short name T26
Test name
Test status
Simulation time 82822747 ps
CPU time 0.88 seconds
Started Jun 02 12:51:19 PM PDT 24
Finished Jun 02 12:51:21 PM PDT 24
Peak memory 213216 kb
Host smart-8f15d81b-deca-4f9b-bbb6-c9a3da5509c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230265573 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.1230265573
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.2953154739
Short name T35
Test name
Test status
Simulation time 105408028 ps
CPU time 0.84 seconds
Started Jun 02 12:51:35 PM PDT 24
Finished Jun 02 12:51:37 PM PDT 24
Peak memory 204992 kb
Host smart-4fe26bab-cc81-4cc2-8fc3-9ca2aa042485
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953154739 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.2953154739
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.1975576457
Short name T90
Test name
Test status
Simulation time 292030156 ps
CPU time 2.33 seconds
Started Jun 02 12:50:21 PM PDT 24
Finished Jun 02 12:50:24 PM PDT 24
Peak memory 213736 kb
Host smart-28e6d259-1637-4aca-b6e6-ba24f590430e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975576457 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.1975576457
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.1015715691
Short name T33
Test name
Test status
Simulation time 101043923 ps
CPU time 0.95 seconds
Started Jun 02 12:51:20 PM PDT 24
Finished Jun 02 12:51:21 PM PDT 24
Peak memory 205008 kb
Host smart-0633697c-e23c-4ac2-a02a-abcd626ceeed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015715691 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.1015715691
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.4191269516
Short name T30
Test name
Test status
Simulation time 577813318 ps
CPU time 2.33 seconds
Started Jun 02 12:51:15 PM PDT 24
Finished Jun 02 12:51:18 PM PDT 24
Peak memory 204924 kb
Host smart-6d409ab7-7fce-4ca7-8916-9c9070a61318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191269516 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.4191269516
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.1335633417
Short name T32
Test name
Test status
Simulation time 134675848 ps
CPU time 1.1 seconds
Started Jun 02 12:51:19 PM PDT 24
Finished Jun 02 12:51:21 PM PDT 24
Peak memory 204964 kb
Host smart-ec900ebf-1f06-496a-8784-a4a7db18b02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335633417 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.1335633417
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.2282523444
Short name T127
Test name
Test status
Simulation time 2484420870 ps
CPU time 20.16 seconds
Started Jun 02 12:50:25 PM PDT 24
Finished Jun 02 12:50:45 PM PDT 24
Peak memory 213780 kb
Host smart-47f44039-0d73-4695-84af-4ebdea644278
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282523444 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.2282523444
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.4128924912
Short name T82
Test name
Test status
Simulation time 334494593 ps
CPU time 3.56 seconds
Started Jun 02 12:50:48 PM PDT 24
Finished Jun 02 12:50:52 PM PDT 24
Peak memory 205508 kb
Host smart-5d2b29dd-026b-44e2-9b11-42b0c0202d9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128924912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same
_csr_outstanding.4128924912
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.3496717321
Short name T55
Test name
Test status
Simulation time 17112431177 ps
CPU time 49.29 seconds
Started Jun 02 12:50:17 PM PDT 24
Finished Jun 02 12:51:07 PM PDT 24
Peak memory 205468 kb
Host smart-1fff070d-0d6f-45c2-8d7e-79f1e003ee6b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496717321 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.3496717321
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.812355833
Short name T87
Test name
Test status
Simulation time 12707049478 ps
CPU time 35.32 seconds
Started Jun 02 12:50:29 PM PDT 24
Finished Jun 02 12:51:04 PM PDT 24
Peak memory 205528 kb
Host smart-a92b78b2-fea5-48df-b47a-dbec811ad1c8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812355833 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr
_hw_reset.812355833
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.1131389385
Short name T73
Test name
Test status
Simulation time 1090979167 ps
CPU time 5.72 seconds
Started Jun 02 12:51:02 PM PDT 24
Finished Jun 02 12:51:08 PM PDT 24
Peak memory 213896 kb
Host smart-0563b20b-c6cb-414c-9947-6c21577f8850
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131389385 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.1131389385
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.2916184048
Short name T22
Test name
Test status
Simulation time 515797171 ps
CPU time 2.45 seconds
Started Jun 02 12:51:15 PM PDT 24
Finished Jun 02 12:51:18 PM PDT 24
Peak memory 204880 kb
Host smart-742d47f0-fd82-4e55-8b5f-78616526db40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916184048 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.2916184048
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.3042281333
Short name T8
Test name
Test status
Simulation time 2758283199 ps
CPU time 2.81 seconds
Started Jun 02 12:51:21 PM PDT 24
Finished Jun 02 12:51:25 PM PDT 24
Peak memory 205300 kb
Host smart-f6545870-53cd-4f32-854d-e5e976407b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042281333 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.3042281333
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3138703506
Short name T76
Test name
Test status
Simulation time 4583468116 ps
CPU time 76.23 seconds
Started Jun 02 12:50:14 PM PDT 24
Finished Jun 02 12:51:31 PM PDT 24
Peak memory 205600 kb
Host smart-aa484ff7-d106-43e2-9324-590d9b73a4d7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138703506 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.3138703506
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3474137206
Short name T131
Test name
Test status
Simulation time 1204195660 ps
CPU time 11.5 seconds
Started Jun 02 12:50:33 PM PDT 24
Finished Jun 02 12:50:45 PM PDT 24
Peak memory 213764 kb
Host smart-fa250b2d-831d-4ebf-9050-6876abf79e7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474137206 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.3474137206
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2098254011
Short name T129
Test name
Test status
Simulation time 6143482249 ps
CPU time 30.3 seconds
Started Jun 02 12:50:43 PM PDT 24
Finished Jun 02 12:51:14 PM PDT 24
Peak memory 213836 kb
Host smart-85c03347-c06d-4412-b20c-368f50e01c20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098254011 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.2098254011
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3808257517
Short name T364
Test name
Test status
Simulation time 173455866 ps
CPU time 1.57 seconds
Started Jun 02 12:50:22 PM PDT 24
Finished Jun 02 12:50:24 PM PDT 24
Peak memory 213716 kb
Host smart-8b524537-7332-423f-bf61-bd1d7d9da16b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808257517 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.3808257517
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1705368130
Short name T46
Test name
Test status
Simulation time 206687298 ps
CPU time 2.21 seconds
Started Jun 02 12:50:29 PM PDT 24
Finished Jun 02 12:50:31 PM PDT 24
Peak memory 215064 kb
Host smart-138abd26-b4de-4c48-bfb0-2b5a8063b172
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705368130 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.1705368130
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.955663515
Short name T102
Test name
Test status
Simulation time 169940086 ps
CPU time 2.21 seconds
Started Jun 02 12:50:21 PM PDT 24
Finished Jun 02 12:50:24 PM PDT 24
Peak memory 213672 kb
Host smart-c3ca8759-b366-4df1-9431-41968cf66fad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955663515 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.955663515
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.2307993525
Short name T272
Test name
Test status
Simulation time 38150047953 ps
CPU time 47.91 seconds
Started Jun 02 12:50:14 PM PDT 24
Finished Jun 02 12:51:03 PM PDT 24
Peak memory 205572 kb
Host smart-927de999-9425-4839-ad5b-1f0c14151126
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307993525 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.2307993525
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2912322517
Short name T361
Test name
Test status
Simulation time 11358192088 ps
CPU time 10.55 seconds
Started Jun 02 12:50:21 PM PDT 24
Finished Jun 02 12:50:32 PM PDT 24
Peak memory 205500 kb
Host smart-13805aa8-7741-4236-b88a-057ffd25624d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912322517 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.2912322517
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.1482037716
Short name T282
Test name
Test status
Simulation time 3603461033 ps
CPU time 10.47 seconds
Started Jun 02 12:50:17 PM PDT 24
Finished Jun 02 12:50:28 PM PDT 24
Peak memory 205560 kb
Host smart-db92bb7d-7969-4a16-b6ac-8e5aac9025dc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482037716 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.1
482037716
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.1158570140
Short name T350
Test name
Test status
Simulation time 2501318757 ps
CPU time 2.5 seconds
Started Jun 02 12:50:21 PM PDT 24
Finished Jun 02 12:50:24 PM PDT 24
Peak memory 205256 kb
Host smart-02195f89-3448-48c5-8423-2ae62ab71460
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158570140 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.1158570140
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.1149182398
Short name T295
Test name
Test status
Simulation time 1591747153 ps
CPU time 4.75 seconds
Started Jun 02 12:50:21 PM PDT 24
Finished Jun 02 12:50:26 PM PDT 24
Peak memory 205192 kb
Host smart-7c682f87-8e60-437d-8e68-d103ea801c8f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149182398 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.1149182398
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.2627670905
Short name T365
Test name
Test status
Simulation time 258733949 ps
CPU time 0.97 seconds
Started Jun 02 12:50:17 PM PDT 24
Finished Jun 02 12:50:18 PM PDT 24
Peak memory 205168 kb
Host smart-b1822b9a-ceac-4e71-a019-56799c7aeae6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627670905 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.2
627670905
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.3534369744
Short name T372
Test name
Test status
Simulation time 73816967 ps
CPU time 0.67 seconds
Started Jun 02 12:50:21 PM PDT 24
Finished Jun 02 12:50:22 PM PDT 24
Peak memory 205220 kb
Host smart-1851dcc7-c38b-4e73-96fd-e31e34f8d5a2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534369744 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.3534369744
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.511660129
Short name T302
Test name
Test status
Simulation time 157526435 ps
CPU time 0.72 seconds
Started Jun 02 12:50:28 PM PDT 24
Finished Jun 02 12:50:30 PM PDT 24
Peak memory 205136 kb
Host smart-733eb41d-63b6-4208-9b5f-89cd28d1f12d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511660129 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.511660129
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.435439161
Short name T349
Test name
Test status
Simulation time 539457950 ps
CPU time 4.19 seconds
Started Jun 02 12:50:28 PM PDT 24
Finished Jun 02 12:50:32 PM PDT 24
Peak memory 205504 kb
Host smart-950bedd6-9ca5-46eb-8e11-43b168155af2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435439161 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_c
sr_outstanding.435439161
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.2815239905
Short name T116
Test name
Test status
Simulation time 113256059 ps
CPU time 2.93 seconds
Started Jun 02 12:50:21 PM PDT 24
Finished Jun 02 12:50:24 PM PDT 24
Peak memory 216292 kb
Host smart-95f19648-4d03-4c56-a950-b412dd3ad4fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815239905 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.2815239905
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3501398061
Short name T130
Test name
Test status
Simulation time 669085274 ps
CPU time 8.36 seconds
Started Jun 02 12:50:21 PM PDT 24
Finished Jun 02 12:50:30 PM PDT 24
Peak memory 213748 kb
Host smart-f44695b7-e094-4ec1-98ab-21ffd151baf7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501398061 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.3501398061
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.4146120274
Short name T351
Test name
Test status
Simulation time 2305859342 ps
CPU time 25.22 seconds
Started Jun 02 12:50:28 PM PDT 24
Finished Jun 02 12:50:54 PM PDT 24
Peak memory 213804 kb
Host smart-5fa27e41-97af-42b3-a168-97a0b80d7914
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146120274 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.4146120274
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.4238501487
Short name T338
Test name
Test status
Simulation time 10247498187 ps
CPU time 66.17 seconds
Started Jun 02 12:50:22 PM PDT 24
Finished Jun 02 12:51:29 PM PDT 24
Peak memory 213836 kb
Host smart-af0fdfca-b609-48ed-ba52-e6b5fe064a37
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238501487 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.4238501487
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2005007738
Short name T59
Test name
Test status
Simulation time 3056518767 ps
CPU time 6.21 seconds
Started Jun 02 12:50:23 PM PDT 24
Finished Jun 02 12:50:29 PM PDT 24
Peak memory 213936 kb
Host smart-55967424-f9c8-4b26-97b6-50bf890abc9a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005007738 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.2005007738
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.504762270
Short name T92
Test name
Test status
Simulation time 97856515 ps
CPU time 2.45 seconds
Started Jun 02 12:50:22 PM PDT 24
Finished Jun 02 12:50:25 PM PDT 24
Peak memory 213692 kb
Host smart-6c2dc140-a1bd-4e40-9f81-eb6a571fe557
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504762270 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.504762270
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.3429185889
Short name T264
Test name
Test status
Simulation time 7817588578 ps
CPU time 11.64 seconds
Started Jun 02 12:50:22 PM PDT 24
Finished Jun 02 12:50:34 PM PDT 24
Peak memory 205512 kb
Host smart-1fe7f2ec-0221-4bf3-bb5d-bfbcd3239b2b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429185889 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.3429185889
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.3156411951
Short name T293
Test name
Test status
Simulation time 7659260265 ps
CPU time 18.22 seconds
Started Jun 02 12:50:24 PM PDT 24
Finished Jun 02 12:50:42 PM PDT 24
Peak memory 205588 kb
Host smart-52bb756a-06d5-44ba-bb21-0fa1413d2f9f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156411951 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.3
156411951
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2803763557
Short name T275
Test name
Test status
Simulation time 3795895102 ps
CPU time 4.21 seconds
Started Jun 02 12:50:23 PM PDT 24
Finished Jun 02 12:50:27 PM PDT 24
Peak memory 205248 kb
Host smart-c9450329-2762-4425-a675-e4b0c4918805
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803763557 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.2803763557
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.285127264
Short name T381
Test name
Test status
Simulation time 39389544031 ps
CPU time 33.55 seconds
Started Jun 02 12:50:22 PM PDT 24
Finished Jun 02 12:50:56 PM PDT 24
Peak memory 205492 kb
Host smart-e060887f-e08e-401a-880e-4aeb7d08c77d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285127264 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_bit_bash.285127264
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1480511346
Short name T303
Test name
Test status
Simulation time 151538776 ps
CPU time 1.05 seconds
Started Jun 02 12:50:23 PM PDT 24
Finished Jun 02 12:50:25 PM PDT 24
Peak memory 205284 kb
Host smart-04d9fc6b-cf1f-4dd0-b776-310c6f65b599
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480511346 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.1480511346
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.1816128553
Short name T332
Test name
Test status
Simulation time 1006091800 ps
CPU time 1.96 seconds
Started Jun 02 12:50:22 PM PDT 24
Finished Jun 02 12:50:25 PM PDT 24
Peak memory 205212 kb
Host smart-79ab1c1f-81ca-4b34-94da-22635ca5615b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816128553 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.1
816128553
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1729502180
Short name T267
Test name
Test status
Simulation time 112637568 ps
CPU time 0.94 seconds
Started Jun 02 12:50:21 PM PDT 24
Finished Jun 02 12:50:22 PM PDT 24
Peak memory 205200 kb
Host smart-a719dd05-69bc-4dcc-bc54-26a1b9c395f5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729502180 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.1729502180
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.96305263
Short name T263
Test name
Test status
Simulation time 45404138 ps
CPU time 0.67 seconds
Started Jun 02 12:50:28 PM PDT 24
Finished Jun 02 12:50:30 PM PDT 24
Peak memory 205136 kb
Host smart-cdb01645-9ef9-47b5-9bde-5770ff810911
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96305263 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.96305263
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2463690111
Short name T362
Test name
Test status
Simulation time 907245236 ps
CPU time 7.7 seconds
Started Jun 02 12:50:21 PM PDT 24
Finished Jun 02 12:50:29 PM PDT 24
Peak memory 205592 kb
Host smart-c7c9ac2d-e688-4c21-bc51-f5484bbad847
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463690111 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_
csr_outstanding.2463690111
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.2260871567
Short name T294
Test name
Test status
Simulation time 60098778 ps
CPU time 2.3 seconds
Started Jun 02 12:50:27 PM PDT 24
Finished Jun 02 12:50:30 PM PDT 24
Peak memory 213808 kb
Host smart-dce9ba6e-a1d6-4076-809b-b511aeb83a6d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260871567 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.2260871567
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.2682188866
Short name T309
Test name
Test status
Simulation time 1672800527 ps
CPU time 5.13 seconds
Started Jun 02 12:50:48 PM PDT 24
Finished Jun 02 12:50:53 PM PDT 24
Peak memory 217492 kb
Host smart-6d76cd66-be71-46e5-a976-b4b5d3271ba4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682188866 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.2682188866
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.1738758979
Short name T106
Test name
Test status
Simulation time 72563863 ps
CPU time 1.64 seconds
Started Jun 02 12:50:50 PM PDT 24
Finished Jun 02 12:50:52 PM PDT 24
Peak memory 213648 kb
Host smart-b52c22f3-cda6-49f8-85a8-d813bb37de66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738758979 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.1738758979
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3161882907
Short name T333
Test name
Test status
Simulation time 4586742067 ps
CPU time 1.95 seconds
Started Jun 02 12:50:47 PM PDT 24
Finished Jun 02 12:50:50 PM PDT 24
Peak memory 205484 kb
Host smart-b99514e5-c6da-4a2e-935a-1b84560058d7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161882907 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
3161882907
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.2872495138
Short name T321
Test name
Test status
Simulation time 1407538669 ps
CPU time 1.96 seconds
Started Jun 02 12:50:49 PM PDT 24
Finished Jun 02 12:50:51 PM PDT 24
Peak memory 205212 kb
Host smart-d27a3400-70de-4389-ab6e-f969c1ddad47
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872495138 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
2872495138
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.1888864280
Short name T337
Test name
Test status
Simulation time 210121115 ps
CPU time 6.5 seconds
Started Jun 02 12:50:48 PM PDT 24
Finished Jun 02 12:50:55 PM PDT 24
Peak memory 205580 kb
Host smart-dc34dcb0-7aca-4612-b69a-fbd5d66e0f91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888864280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same
_csr_outstanding.1888864280
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tap_fsm_rand_reset.737118502
Short name T322
Test name
Test status
Simulation time 43733838208 ps
CPU time 46.75 seconds
Started Jun 02 12:50:51 PM PDT 24
Finished Jun 02 12:51:38 PM PDT 24
Peak memory 221528 kb
Host smart-1e7f9e8d-2af6-4085-8014-cd2195459583
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737118502 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.rv_dm_tap_fsm_rand_reset.737118502
Directory /workspace/10.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.1744494248
Short name T61
Test name
Test status
Simulation time 292200413 ps
CPU time 3.01 seconds
Started Jun 02 12:50:50 PM PDT 24
Finished Jun 02 12:50:54 PM PDT 24
Peak memory 213776 kb
Host smart-a443f19e-20b9-4aef-a69a-69512fec4594
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744494248 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.1744494248
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1945724194
Short name T318
Test name
Test status
Simulation time 2138355838 ps
CPU time 13.4 seconds
Started Jun 02 12:50:49 PM PDT 24
Finished Jun 02 12:51:03 PM PDT 24
Peak memory 213856 kb
Host smart-ac10fc76-e32b-4ecf-af28-38a0ead8c99b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945724194 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.1
945724194
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.786587684
Short name T311
Test name
Test status
Simulation time 2279854490 ps
CPU time 5.3 seconds
Started Jun 02 12:50:51 PM PDT 24
Finished Jun 02 12:50:56 PM PDT 24
Peak memory 221768 kb
Host smart-48cadeac-236e-4b7f-932f-8e41c5114d71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786587684 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.786587684
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.3252468391
Short name T94
Test name
Test status
Simulation time 128621091 ps
CPU time 1.7 seconds
Started Jun 02 12:50:50 PM PDT 24
Finished Jun 02 12:50:53 PM PDT 24
Peak memory 213672 kb
Host smart-75945a3f-eb77-447e-95fe-216c5b1cb917
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252468391 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.3252468391
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.565798626
Short name T308
Test name
Test status
Simulation time 13565263435 ps
CPU time 7.17 seconds
Started Jun 02 12:50:48 PM PDT 24
Finished Jun 02 12:50:55 PM PDT 24
Peak memory 205540 kb
Host smart-6a7cccd1-23d5-460b-8726-7e4b31e06859
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565798626 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.565798626
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.2005042237
Short name T335
Test name
Test status
Simulation time 1262023203 ps
CPU time 1.04 seconds
Started Jun 02 12:50:48 PM PDT 24
Finished Jun 02 12:50:49 PM PDT 24
Peak memory 205236 kb
Host smart-a0a71005-d792-455d-b006-3d622ce9f892
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005042237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.
2005042237
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.1452630009
Short name T307
Test name
Test status
Simulation time 343246570 ps
CPU time 5.89 seconds
Started Jun 02 12:50:49 PM PDT 24
Finished Jun 02 12:50:55 PM PDT 24
Peak memory 213820 kb
Host smart-4e92c2ea-ff04-4363-b8f9-85e12ec55e7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452630009 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.1452630009
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3969291833
Short name T378
Test name
Test status
Simulation time 1988356104 ps
CPU time 14.15 seconds
Started Jun 02 12:50:51 PM PDT 24
Finished Jun 02 12:51:05 PM PDT 24
Peak memory 213768 kb
Host smart-d9cf3612-3963-4e43-ac49-f34d580d7ba5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969291833 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.3
969291833
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1933951193
Short name T388
Test name
Test status
Simulation time 3729353043 ps
CPU time 5.33 seconds
Started Jun 02 12:50:58 PM PDT 24
Finished Jun 02 12:51:04 PM PDT 24
Peak memory 220236 kb
Host smart-8cc210db-f02c-453a-8eda-0c2d91696e2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933951193 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.1933951193
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.717866961
Short name T99
Test name
Test status
Simulation time 147439798 ps
CPU time 1.72 seconds
Started Jun 02 12:50:59 PM PDT 24
Finished Jun 02 12:51:01 PM PDT 24
Peak memory 213744 kb
Host smart-09a612ad-4ab2-47a1-adc9-cda067241b3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717866961 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.717866961
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.4175098823
Short name T306
Test name
Test status
Simulation time 1758843353 ps
CPU time 1.94 seconds
Started Jun 02 12:50:50 PM PDT 24
Finished Jun 02 12:50:52 PM PDT 24
Peak memory 205496 kb
Host smart-5c19cec8-61a0-4db1-814c-e44d8e1a2231
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175098823 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
4175098823
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.2312232597
Short name T347
Test name
Test status
Simulation time 302213118 ps
CPU time 1.11 seconds
Started Jun 02 12:50:49 PM PDT 24
Finished Jun 02 12:50:50 PM PDT 24
Peak memory 205224 kb
Host smart-c9f2f531-82d5-4d51-a9b5-41142005ae16
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312232597 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
2312232597
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.2556854186
Short name T356
Test name
Test status
Simulation time 517641016 ps
CPU time 4.14 seconds
Started Jun 02 12:50:56 PM PDT 24
Finished Jun 02 12:51:00 PM PDT 24
Peak memory 205576 kb
Host smart-3d604c4b-2baa-4bec-b1b4-4f0374833a74
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556854186 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.2556854186
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.2830870081
Short name T60
Test name
Test status
Simulation time 236956112 ps
CPU time 5.12 seconds
Started Jun 02 12:50:54 PM PDT 24
Finished Jun 02 12:50:59 PM PDT 24
Peak memory 213908 kb
Host smart-c72fa0df-efce-4812-b288-ef417483a70d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830870081 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.2830870081
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.506700159
Short name T327
Test name
Test status
Simulation time 3008202842 ps
CPU time 12.55 seconds
Started Jun 02 12:50:55 PM PDT 24
Finished Jun 02 12:51:08 PM PDT 24
Peak memory 213848 kb
Host smart-7e0ce770-a409-4408-8dca-7df77d34faf8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506700159 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.506700159
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.2079014219
Short name T273
Test name
Test status
Simulation time 280653135 ps
CPU time 2.36 seconds
Started Jun 02 12:50:59 PM PDT 24
Finished Jun 02 12:51:02 PM PDT 24
Peak memory 213816 kb
Host smart-1e198625-0603-4aa5-842a-4fb20797e660
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079014219 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.2079014219
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.3458746074
Short name T93
Test name
Test status
Simulation time 243985612 ps
CPU time 1.64 seconds
Started Jun 02 12:50:54 PM PDT 24
Finished Jun 02 12:50:56 PM PDT 24
Peak memory 213728 kb
Host smart-e0da8116-e4e2-43e8-afb2-15e4f292866d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458746074 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.3458746074
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.1078409063
Short name T331
Test name
Test status
Simulation time 1099613984 ps
CPU time 1.99 seconds
Started Jun 02 12:50:57 PM PDT 24
Finished Jun 02 12:51:00 PM PDT 24
Peak memory 205320 kb
Host smart-4a2b06db-cc66-4af6-85ea-6140a33867c3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078409063 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
1078409063
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.219988522
Short name T354
Test name
Test status
Simulation time 1281583053 ps
CPU time 1.05 seconds
Started Jun 02 12:50:55 PM PDT 24
Finished Jun 02 12:50:57 PM PDT 24
Peak memory 205204 kb
Host smart-52dc388c-1dd0-46f0-881d-f72285eabefb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219988522 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.219988522
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.1817759270
Short name T91
Test name
Test status
Simulation time 3364003111 ps
CPU time 4.7 seconds
Started Jun 02 12:50:57 PM PDT 24
Finished Jun 02 12:51:03 PM PDT 24
Peak memory 205736 kb
Host smart-80910b59-c4f4-49b9-af44-6f156e43331f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817759270 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.1817759270
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.1912201816
Short name T123
Test name
Test status
Simulation time 263442842 ps
CPU time 3.97 seconds
Started Jun 02 12:50:54 PM PDT 24
Finished Jun 02 12:50:59 PM PDT 24
Peak memory 213836 kb
Host smart-02a05458-fdf1-4bf3-ad2b-497f51f49386
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912201816 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.1912201816
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2125062734
Short name T277
Test name
Test status
Simulation time 1695606831 ps
CPU time 11.02 seconds
Started Jun 02 12:50:56 PM PDT 24
Finished Jun 02 12:51:08 PM PDT 24
Peak memory 213756 kb
Host smart-92a6d649-19f2-410f-aa86-7fca5583ea63
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125062734 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.2
125062734
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3548802985
Short name T371
Test name
Test status
Simulation time 104743382 ps
CPU time 2.42 seconds
Started Jun 02 12:50:57 PM PDT 24
Finished Jun 02 12:51:00 PM PDT 24
Peak memory 218772 kb
Host smart-629c2f55-ef17-4027-b535-e0834dccd0b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548802985 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.3548802985
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.3515327516
Short name T328
Test name
Test status
Simulation time 250707806 ps
CPU time 1.64 seconds
Started Jun 02 12:50:59 PM PDT 24
Finished Jun 02 12:51:01 PM PDT 24
Peak memory 213696 kb
Host smart-be481f90-7949-4863-a451-3968b8003998
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515327516 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.3515327516
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2783110613
Short name T319
Test name
Test status
Simulation time 4243792522 ps
CPU time 4.49 seconds
Started Jun 02 12:50:55 PM PDT 24
Finished Jun 02 12:51:00 PM PDT 24
Peak memory 205504 kb
Host smart-230a70c6-e687-496d-b4d6-9ea6f0f2a8f5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783110613 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
2783110613
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2237487202
Short name T316
Test name
Test status
Simulation time 577088197 ps
CPU time 2.19 seconds
Started Jun 02 12:50:57 PM PDT 24
Finished Jun 02 12:51:00 PM PDT 24
Peak memory 205200 kb
Host smart-2430888a-a150-45a3-aa9d-537f6eadfc22
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237487202 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
2237487202
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2272071801
Short name T111
Test name
Test status
Simulation time 324333739 ps
CPU time 3.74 seconds
Started Jun 02 12:50:54 PM PDT 24
Finished Jun 02 12:50:59 PM PDT 24
Peak memory 205572 kb
Host smart-027b775c-27ce-43ce-8cd1-d4718bd11bab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272071801 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.2272071801
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.4110867561
Short name T296
Test name
Test status
Simulation time 1229246149 ps
CPU time 6.43 seconds
Started Jun 02 12:50:57 PM PDT 24
Finished Jun 02 12:51:04 PM PDT 24
Peak memory 213788 kb
Host smart-a87395fa-fe3d-4cba-b279-cdea6d52f2a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110867561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.4110867561
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.3392352407
Short name T325
Test name
Test status
Simulation time 3031281099 ps
CPU time 5.26 seconds
Started Jun 02 12:51:05 PM PDT 24
Finished Jun 02 12:51:11 PM PDT 24
Peak memory 219544 kb
Host smart-7cb50113-66d3-4d13-8b5d-7fd40d299526
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392352407 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.3392352407
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.298886331
Short name T107
Test name
Test status
Simulation time 206172730 ps
CPU time 1.52 seconds
Started Jun 02 12:50:58 PM PDT 24
Finished Jun 02 12:50:59 PM PDT 24
Peak memory 213720 kb
Host smart-c405a770-fc59-4bae-873f-9e5a2a6f55e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298886331 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.298886331
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.2137477520
Short name T329
Test name
Test status
Simulation time 1416434517 ps
CPU time 1.62 seconds
Started Jun 02 12:50:57 PM PDT 24
Finished Jun 02 12:50:59 PM PDT 24
Peak memory 205420 kb
Host smart-9ec7839a-82f1-4384-8336-cc4115582fa3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137477520 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
2137477520
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.1856910093
Short name T56
Test name
Test status
Simulation time 444777828 ps
CPU time 0.75 seconds
Started Jun 02 12:50:54 PM PDT 24
Finished Jun 02 12:50:55 PM PDT 24
Peak memory 205228 kb
Host smart-ef2c699e-bf94-4232-89c0-dc4f26c93ea2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856910093 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
1856910093
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.1843761486
Short name T85
Test name
Test status
Simulation time 92635286 ps
CPU time 3.56 seconds
Started Jun 02 12:51:07 PM PDT 24
Finished Jun 02 12:51:11 PM PDT 24
Peak memory 205532 kb
Host smart-93198159-873c-48be-aceb-ca06e28107ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843761486 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.1843761486
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.3528300640
Short name T352
Test name
Test status
Simulation time 207751227 ps
CPU time 5.46 seconds
Started Jun 02 12:50:58 PM PDT 24
Finished Jun 02 12:51:04 PM PDT 24
Peak memory 213820 kb
Host smart-bf43903c-a375-466c-90f4-52174e852e64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528300640 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.3528300640
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2009473858
Short name T47
Test name
Test status
Simulation time 2874965093 ps
CPU time 10.51 seconds
Started Jun 02 12:50:57 PM PDT 24
Finished Jun 02 12:51:08 PM PDT 24
Peak memory 213892 kb
Host smart-0e1aebd9-c5c4-4857-9a9b-eaf147101522
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009473858 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.2
009473858
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.3157594082
Short name T317
Test name
Test status
Simulation time 332251342 ps
CPU time 2.53 seconds
Started Jun 02 12:51:04 PM PDT 24
Finished Jun 02 12:51:07 PM PDT 24
Peak memory 213768 kb
Host smart-f41b1b19-07f6-4236-86ee-f807549dd678
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157594082 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.3157594082
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.1277374548
Short name T108
Test name
Test status
Simulation time 374600611 ps
CPU time 2.75 seconds
Started Jun 02 12:51:07 PM PDT 24
Finished Jun 02 12:51:10 PM PDT 24
Peak memory 213676 kb
Host smart-d0b13390-ce51-494f-bedf-2896c21581fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277374548 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.1277374548
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.363272160
Short name T353
Test name
Test status
Simulation time 3722557211 ps
CPU time 4.08 seconds
Started Jun 02 12:51:05 PM PDT 24
Finished Jun 02 12:51:10 PM PDT 24
Peak memory 205568 kb
Host smart-2184c755-824f-4c39-9bc1-18cf6408e3f6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363272160 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.363272160
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.1780016268
Short name T284
Test name
Test status
Simulation time 226102659 ps
CPU time 0.94 seconds
Started Jun 02 12:51:01 PM PDT 24
Finished Jun 02 12:51:02 PM PDT 24
Peak memory 205172 kb
Host smart-204fc1e2-ba2c-480a-953c-e7b7b2f4554d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780016268 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
1780016268
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3159285819
Short name T96
Test name
Test status
Simulation time 4439393832 ps
CPU time 8.63 seconds
Started Jun 02 12:51:07 PM PDT 24
Finished Jun 02 12:51:16 PM PDT 24
Peak memory 205624 kb
Host smart-f148dabc-5802-4099-bcf0-eee17d153115
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159285819 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.3159285819
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.1683856248
Short name T315
Test name
Test status
Simulation time 271871832 ps
CPU time 3.45 seconds
Started Jun 02 12:50:59 PM PDT 24
Finished Jun 02 12:51:03 PM PDT 24
Peak memory 213836 kb
Host smart-b15b7fcb-09be-4470-98aa-b3b2521cd403
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683856248 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.1683856248
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.3631561747
Short name T374
Test name
Test status
Simulation time 708781402 ps
CPU time 9.82 seconds
Started Jun 02 12:51:03 PM PDT 24
Finished Jun 02 12:51:13 PM PDT 24
Peak memory 213800 kb
Host smart-c12f50ef-c31f-4bdb-856c-edbe29c5b8fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631561747 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.3
631561747
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.1541507848
Short name T117
Test name
Test status
Simulation time 2673611894 ps
CPU time 6.18 seconds
Started Jun 02 12:51:00 PM PDT 24
Finished Jun 02 12:51:07 PM PDT 24
Peak memory 219376 kb
Host smart-b71cf949-f3be-41aa-9c3e-768355362e03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541507848 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.1541507848
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.3800676424
Short name T84
Test name
Test status
Simulation time 188476555 ps
CPU time 2.08 seconds
Started Jun 02 12:51:07 PM PDT 24
Finished Jun 02 12:51:10 PM PDT 24
Peak memory 213696 kb
Host smart-7467839e-6131-438a-b4ca-ca9562adc82e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800676424 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.3800676424
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2947146352
Short name T279
Test name
Test status
Simulation time 6053956902 ps
CPU time 9.83 seconds
Started Jun 02 12:51:03 PM PDT 24
Finished Jun 02 12:51:13 PM PDT 24
Peak memory 205516 kb
Host smart-a3929174-f4d2-4ba8-84a1-17fa3799a6c0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947146352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
2947146352
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.1196921706
Short name T274
Test name
Test status
Simulation time 428022777 ps
CPU time 1.29 seconds
Started Jun 02 12:51:07 PM PDT 24
Finished Jun 02 12:51:09 PM PDT 24
Peak memory 205152 kb
Host smart-8b8de5e4-2a06-4129-8349-afa07c76564b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196921706 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
1196921706
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.1541798339
Short name T77
Test name
Test status
Simulation time 1000468639 ps
CPU time 3.6 seconds
Started Jun 02 12:51:00 PM PDT 24
Finished Jun 02 12:51:04 PM PDT 24
Peak memory 205840 kb
Host smart-c30484e8-a2e0-405d-8364-6d3a14b49c70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541798339 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.1541798339
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.354427426
Short name T383
Test name
Test status
Simulation time 692930790 ps
CPU time 8.96 seconds
Started Jun 02 12:51:06 PM PDT 24
Finished Jun 02 12:51:15 PM PDT 24
Peak memory 213828 kb
Host smart-c14c9361-3fda-480e-beb2-504dc8aeb092
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354427426 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.354427426
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.1221136132
Short name T68
Test name
Test status
Simulation time 341147062 ps
CPU time 3.79 seconds
Started Jun 02 12:51:07 PM PDT 24
Finished Jun 02 12:51:12 PM PDT 24
Peak memory 221944 kb
Host smart-ff7539cd-c00d-434e-a5b8-4b083fa15332
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221136132 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.1221136132
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.4183190355
Short name T80
Test name
Test status
Simulation time 80597911 ps
CPU time 1.65 seconds
Started Jun 02 12:51:02 PM PDT 24
Finished Jun 02 12:51:04 PM PDT 24
Peak memory 213704 kb
Host smart-6c96147c-6f6b-42fe-bf0d-4591c3660a00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183190355 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.4183190355
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2317847515
Short name T270
Test name
Test status
Simulation time 14665561227 ps
CPU time 11.68 seconds
Started Jun 02 12:51:04 PM PDT 24
Finished Jun 02 12:51:16 PM PDT 24
Peak memory 205460 kb
Host smart-cc66e3f8-22e4-48f7-8207-f4d7bfdcf83d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317847515 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
2317847515
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.760427910
Short name T298
Test name
Test status
Simulation time 297380618 ps
CPU time 0.94 seconds
Started Jun 02 12:50:59 PM PDT 24
Finished Jun 02 12:51:01 PM PDT 24
Peak memory 205120 kb
Host smart-521c14dc-224e-40ee-b9e5-eb701f014a66
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760427910 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.760427910
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3137977040
Short name T95
Test name
Test status
Simulation time 893444870 ps
CPU time 7.84 seconds
Started Jun 02 12:51:05 PM PDT 24
Finished Jun 02 12:51:14 PM PDT 24
Peak memory 205596 kb
Host smart-b3730e68-624f-4eca-9e5d-e8475e73b870
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137977040 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.3137977040
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tap_fsm_rand_reset.697185162
Short name T387
Test name
Test status
Simulation time 49416225659 ps
CPU time 41.66 seconds
Started Jun 02 12:51:05 PM PDT 24
Finished Jun 02 12:51:48 PM PDT 24
Peak memory 214056 kb
Host smart-2f0e2c49-2456-4a4f-a2f4-8a9f88823714
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697185162 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.rv_dm_tap_fsm_rand_reset.697185162
Directory /workspace/18.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.3890033383
Short name T118
Test name
Test status
Simulation time 469577259 ps
CPU time 4.71 seconds
Started Jun 02 12:51:06 PM PDT 24
Finished Jun 02 12:51:11 PM PDT 24
Peak memory 213820 kb
Host smart-302a684e-c1ca-42a3-b2ce-8e02c802b7c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890033383 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.3890033383
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3405819690
Short name T69
Test name
Test status
Simulation time 4234646239 ps
CPU time 10.41 seconds
Started Jun 02 12:51:07 PM PDT 24
Finished Jun 02 12:51:18 PM PDT 24
Peak memory 213904 kb
Host smart-d0a9123e-ae46-4ab9-94d3-e3a45444518f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405819690 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.3
405819690
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.597255579
Short name T323
Test name
Test status
Simulation time 67756341 ps
CPU time 2.11 seconds
Started Jun 02 12:51:04 PM PDT 24
Finished Jun 02 12:51:07 PM PDT 24
Peak memory 217424 kb
Host smart-061ebcd9-a6d4-45e8-9c27-b2b6646f8b94
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597255579 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.597255579
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.2907477126
Short name T109
Test name
Test status
Simulation time 191772277 ps
CPU time 2.14 seconds
Started Jun 02 12:51:07 PM PDT 24
Finished Jun 02 12:51:10 PM PDT 24
Peak memory 213664 kb
Host smart-f89c9d2a-4680-4a84-8f56-a83c2e94c9a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907477126 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.2907477126
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2497892401
Short name T359
Test name
Test status
Simulation time 14343463586 ps
CPU time 24.73 seconds
Started Jun 02 12:51:09 PM PDT 24
Finished Jun 02 12:51:34 PM PDT 24
Peak memory 205444 kb
Host smart-959a36b9-7cbd-4926-94c3-b08add51dd71
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497892401 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
2497892401
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.3646638895
Short name T366
Test name
Test status
Simulation time 304142741 ps
CPU time 1.43 seconds
Started Jun 02 12:51:05 PM PDT 24
Finished Jun 02 12:51:07 PM PDT 24
Peak memory 205152 kb
Host smart-469e30d1-ca1b-43b7-9b8f-f36aed135149
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646638895 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
3646638895
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.2374638673
Short name T110
Test name
Test status
Simulation time 708982992 ps
CPU time 6.72 seconds
Started Jun 02 12:51:08 PM PDT 24
Finished Jun 02 12:51:15 PM PDT 24
Peak memory 205588 kb
Host smart-72c5b4e5-170f-471d-80e2-caf28e9169eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374638673 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.2374638673
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.2044742535
Short name T280
Test name
Test status
Simulation time 222047445 ps
CPU time 4.32 seconds
Started Jun 02 12:51:09 PM PDT 24
Finished Jun 02 12:51:14 PM PDT 24
Peak memory 213820 kb
Host smart-bfb58b3b-d536-4705-b2a9-763985ff8658
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044742535 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.2044742535
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.4179664157
Short name T128
Test name
Test status
Simulation time 1076445635 ps
CPU time 11.75 seconds
Started Jun 02 12:51:07 PM PDT 24
Finished Jun 02 12:51:20 PM PDT 24
Peak memory 213816 kb
Host smart-008905c0-448a-4c8a-9d87-3a7983b29080
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179664157 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.4
179664157
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2680849422
Short name T104
Test name
Test status
Simulation time 1184516912 ps
CPU time 68.82 seconds
Started Jun 02 12:50:22 PM PDT 24
Finished Jun 02 12:51:31 PM PDT 24
Peak memory 213700 kb
Host smart-0416e541-bb48-43b8-8ffd-b0bb30af2ccb
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680849422 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.2680849422
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.4252115204
Short name T100
Test name
Test status
Simulation time 7489216923 ps
CPU time 36.2 seconds
Started Jun 02 12:50:27 PM PDT 24
Finished Jun 02 12:51:04 PM PDT 24
Peak memory 213832 kb
Host smart-210bc7c8-eb99-426a-857c-5f345c61dc4d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252115204 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.4252115204
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.400752130
Short name T79
Test name
Test status
Simulation time 284721819 ps
CPU time 2.23 seconds
Started Jun 02 12:50:28 PM PDT 24
Finished Jun 02 12:50:30 PM PDT 24
Peak memory 213732 kb
Host smart-9ca4b30f-3ece-465c-88e5-76e3475d388b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400752130 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.400752130
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.253532761
Short name T165
Test name
Test status
Simulation time 233624051 ps
CPU time 4.4 seconds
Started Jun 02 12:50:27 PM PDT 24
Finished Jun 02 12:50:32 PM PDT 24
Peak memory 219476 kb
Host smart-a52409e2-c8f9-480b-b930-bb463d2a790a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253532761 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.253532761
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1341176086
Short name T297
Test name
Test status
Simulation time 313704084 ps
CPU time 1.52 seconds
Started Jun 02 12:50:28 PM PDT 24
Finished Jun 02 12:50:30 PM PDT 24
Peak memory 213628 kb
Host smart-fd75a975-5d6e-4539-8982-3dac640b0650
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341176086 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.1341176086
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.3858029070
Short name T271
Test name
Test status
Simulation time 93646738536 ps
CPU time 41.18 seconds
Started Jun 02 12:50:27 PM PDT 24
Finished Jun 02 12:51:09 PM PDT 24
Peak memory 205516 kb
Host smart-691861bd-ba7e-4d01-a7cf-68ee5d3ab234
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858029070 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.3858029070
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.2277948597
Short name T314
Test name
Test status
Simulation time 84983323592 ps
CPU time 109.55 seconds
Started Jun 02 12:50:28 PM PDT 24
Finished Jun 02 12:52:19 PM PDT 24
Peak memory 205516 kb
Host smart-0d428e1a-943a-488f-ba11-6cbec6fc57f3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277948597 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.rv_dm_jtag_dmi_csr_bit_bash.2277948597
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.948781271
Short name T265
Test name
Test status
Simulation time 3357004653 ps
CPU time 6.38 seconds
Started Jun 02 12:50:28 PM PDT 24
Finished Jun 02 12:50:35 PM PDT 24
Peak memory 205408 kb
Host smart-be8116c1-3c1a-4789-b7f0-59f3723c7eaa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948781271 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.948781271
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.752957471
Short name T286
Test name
Test status
Simulation time 874090128 ps
CPU time 1.11 seconds
Started Jun 02 12:50:24 PM PDT 24
Finished Jun 02 12:50:26 PM PDT 24
Peak memory 205228 kb
Host smart-d0ae1672-6611-40c8-ab21-cfbb32c5c2ec
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752957471 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_aliasing.752957471
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.2032394675
Short name T268
Test name
Test status
Simulation time 10945154292 ps
CPU time 4.09 seconds
Started Jun 02 12:50:20 PM PDT 24
Finished Jun 02 12:50:25 PM PDT 24
Peak memory 205484 kb
Host smart-7343be2b-15e2-458c-bfb1-9cc2c204c6d8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032394675 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.2032394675
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.304728746
Short name T320
Test name
Test status
Simulation time 864609028 ps
CPU time 2.96 seconds
Started Jun 02 12:50:23 PM PDT 24
Finished Jun 02 12:50:26 PM PDT 24
Peak memory 205212 kb
Host smart-15f16ce4-5ee1-4492-9ca8-30f147b09277
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304728746 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_hw_reset.304728746
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.838450302
Short name T385
Test name
Test status
Simulation time 347663668 ps
CPU time 1.11 seconds
Started Jun 02 12:50:23 PM PDT 24
Finished Jun 02 12:50:25 PM PDT 24
Peak memory 205084 kb
Host smart-0d4fa6b3-0294-4612-8e96-f45f0a62de3a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838450302 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.838450302
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2078881198
Short name T377
Test name
Test status
Simulation time 110826605 ps
CPU time 0.66 seconds
Started Jun 02 12:50:26 PM PDT 24
Finished Jun 02 12:50:27 PM PDT 24
Peak memory 205224 kb
Host smart-4013a030-ddf6-4bf8-8373-7ffb176499bb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078881198 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.2078881198
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.2783315383
Short name T348
Test name
Test status
Simulation time 116656054 ps
CPU time 0.81 seconds
Started Jun 02 12:50:27 PM PDT 24
Finished Jun 02 12:50:29 PM PDT 24
Peak memory 205160 kb
Host smart-f8e19902-3e62-4e97-8857-9a2bad2126cf
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783315383 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.2783315383
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.2047079337
Short name T368
Test name
Test status
Simulation time 257673621 ps
CPU time 4.16 seconds
Started Jun 02 12:50:27 PM PDT 24
Finished Jun 02 12:50:31 PM PDT 24
Peak memory 205608 kb
Host smart-f1a06182-d29b-4f8d-90cd-b916a372d1ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047079337 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.2047079337
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.2424211350
Short name T346
Test name
Test status
Simulation time 2133554349 ps
CPU time 3.97 seconds
Started Jun 02 12:50:27 PM PDT 24
Finished Jun 02 12:50:32 PM PDT 24
Peak memory 213872 kb
Host smart-a09599f9-42a6-43c0-af42-82c5d0576127
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424211350 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.2424211350
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.949477232
Short name T382
Test name
Test status
Simulation time 646099418 ps
CPU time 8.99 seconds
Started Jun 02 12:50:27 PM PDT 24
Finished Jun 02 12:50:36 PM PDT 24
Peak memory 213756 kb
Host smart-4342ae64-0cad-4a87-b24d-574458ecfd8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949477232 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.949477232
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_dm_tap_fsm_rand_reset.3310710699
Short name T54
Test name
Test status
Simulation time 76759771242 ps
CPU time 66.13 seconds
Started Jun 02 12:51:06 PM PDT 24
Finished Jun 02 12:52:13 PM PDT 24
Peak memory 230704 kb
Host smart-08083933-15f0-4d23-a0eb-1f0116490234
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310710699 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 20.rv_dm_tap_fsm_rand_reset.3310710699
Directory /workspace/20.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/27.rv_dm_tap_fsm_rand_reset.1716500398
Short name T313
Test name
Test status
Simulation time 52776745797 ps
CPU time 88.06 seconds
Started Jun 02 12:51:08 PM PDT 24
Finished Jun 02 12:52:37 PM PDT 24
Peak memory 223492 kb
Host smart-aec8e8ed-0c11-4b3b-ab2d-0b02e99bc9c6
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716500398 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 27.rv_dm_tap_fsm_rand_reset.1716500398
Directory /workspace/27.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/29.rv_dm_tap_fsm_rand_reset.3864411060
Short name T289
Test name
Test status
Simulation time 50498781752 ps
CPU time 41.23 seconds
Started Jun 02 12:51:07 PM PDT 24
Finished Jun 02 12:51:49 PM PDT 24
Peak memory 219056 kb
Host smart-e17e3a95-8444-4f21-a52c-f5ec26a5c290
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864411060 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 29.rv_dm_tap_fsm_rand_reset.3864411060
Directory /workspace/29.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.575817125
Short name T83
Test name
Test status
Simulation time 6118057562 ps
CPU time 33.93 seconds
Started Jun 02 12:50:26 PM PDT 24
Finished Jun 02 12:51:01 PM PDT 24
Peak memory 213796 kb
Host smart-e5241b61-82f3-4d38-80cc-e694e6b8a1fd
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575817125 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.rv_dm_csr_aliasing.575817125
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.741112697
Short name T334
Test name
Test status
Simulation time 18744695121 ps
CPU time 36.51 seconds
Started Jun 02 12:50:33 PM PDT 24
Finished Jun 02 12:51:10 PM PDT 24
Peak memory 205632 kb
Host smart-11df09b2-31d6-4682-8d54-b2e98b2ecd4e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741112697 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.741112697
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1924949386
Short name T101
Test name
Test status
Simulation time 199571597 ps
CPU time 2.26 seconds
Started Jun 02 12:50:36 PM PDT 24
Finished Jun 02 12:50:39 PM PDT 24
Peak memory 213752 kb
Host smart-b26fef56-7661-4d87-beaa-0179fa676abf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924949386 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.1924949386
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.3216169862
Short name T285
Test name
Test status
Simulation time 1343501199 ps
CPU time 4.04 seconds
Started Jun 02 12:50:36 PM PDT 24
Finished Jun 02 12:50:40 PM PDT 24
Peak memory 218732 kb
Host smart-c0ca6568-3a2e-4d6b-bef5-b328322c3558
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216169862 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.3216169862
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2553676726
Short name T299
Test name
Test status
Simulation time 200187739 ps
CPU time 1.89 seconds
Started Jun 02 12:50:34 PM PDT 24
Finished Jun 02 12:50:37 PM PDT 24
Peak memory 213720 kb
Host smart-e17922c8-b0c9-4654-8091-251856f2be23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553676726 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.2553676726
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.3934361872
Short name T380
Test name
Test status
Simulation time 106665045536 ps
CPU time 87.61 seconds
Started Jun 02 12:50:27 PM PDT 24
Finished Jun 02 12:51:55 PM PDT 24
Peak memory 205504 kb
Host smart-436904ef-a495-4654-8384-4d95484500ec
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934361872 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.3934361872
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.4143672585
Short name T88
Test name
Test status
Simulation time 8025174955 ps
CPU time 5.43 seconds
Started Jun 02 12:50:28 PM PDT 24
Finished Jun 02 12:50:34 PM PDT 24
Peak memory 205592 kb
Host smart-23b6c2fa-9004-49ce-b253-3c662ac92648
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143672585 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.4143672585
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.2576553883
Short name T262
Test name
Test status
Simulation time 1287941296 ps
CPU time 1.19 seconds
Started Jun 02 12:50:28 PM PDT 24
Finished Jun 02 12:50:30 PM PDT 24
Peak memory 205428 kb
Host smart-a91d0115-4601-4277-9864-7064098bcea4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576553883 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.2
576553883
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.56602194
Short name T391
Test name
Test status
Simulation time 2987439322 ps
CPU time 2.57 seconds
Started Jun 02 12:50:29 PM PDT 24
Finished Jun 02 12:50:32 PM PDT 24
Peak memory 205324 kb
Host smart-240d76d3-59e6-4b58-8bac-666688ea24a1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56602194 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_
aliasing.56602194
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2731759024
Short name T301
Test name
Test status
Simulation time 4042775200 ps
CPU time 11.68 seconds
Started Jun 02 12:50:26 PM PDT 24
Finished Jun 02 12:50:39 PM PDT 24
Peak memory 205524 kb
Host smart-a774ab2c-24eb-4e7b-a2f6-114bae603ea4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731759024 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.2731759024
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3110987102
Short name T344
Test name
Test status
Simulation time 184071666 ps
CPU time 1.11 seconds
Started Jun 02 12:50:27 PM PDT 24
Finished Jun 02 12:50:29 PM PDT 24
Peak memory 205260 kb
Host smart-ee3c8345-e076-41b4-9ec8-5b0c70854e93
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110987102 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.3110987102
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.4130159202
Short name T345
Test name
Test status
Simulation time 363870978 ps
CPU time 0.84 seconds
Started Jun 02 12:50:29 PM PDT 24
Finished Jun 02 12:50:30 PM PDT 24
Peak memory 205136 kb
Host smart-32195332-1cd1-478c-9dde-1d1a5035aa4a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130159202 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.4
130159202
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.2123631390
Short name T375
Test name
Test status
Simulation time 56964546 ps
CPU time 0.77 seconds
Started Jun 02 12:50:36 PM PDT 24
Finished Jun 02 12:50:37 PM PDT 24
Peak memory 205268 kb
Host smart-07c0adbd-2fe0-4755-b2de-b2e993776444
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123631390 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.2123631390
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.561230132
Short name T326
Test name
Test status
Simulation time 81853928 ps
CPU time 0.89 seconds
Started Jun 02 12:50:34 PM PDT 24
Finished Jun 02 12:50:35 PM PDT 24
Peak memory 205184 kb
Host smart-95b16a2c-4c35-4bcb-badb-94821b4f343e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561230132 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.561230132
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.1100206540
Short name T367
Test name
Test status
Simulation time 364409031 ps
CPU time 6.76 seconds
Started Jun 02 12:50:36 PM PDT 24
Finished Jun 02 12:50:43 PM PDT 24
Peak memory 205524 kb
Host smart-d9792045-dfd4-47e6-86a1-688e74454b98
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100206540 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_
csr_outstanding.1100206540
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2899233080
Short name T304
Test name
Test status
Simulation time 73418355 ps
CPU time 4.01 seconds
Started Jun 02 12:50:27 PM PDT 24
Finished Jun 02 12:50:32 PM PDT 24
Peak memory 213776 kb
Host smart-c475b8dc-d22b-4b5f-a836-1a0a5ed457ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899233080 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.2899233080
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/37.rv_dm_tap_fsm_rand_reset.128710119
Short name T342
Test name
Test status
Simulation time 48737045750 ps
CPU time 23.94 seconds
Started Jun 02 12:51:14 PM PDT 24
Finished Jun 02 12:51:39 PM PDT 24
Peak memory 222072 kb
Host smart-9dfd4fb2-9f83-47ff-b05f-e8d80a72e5dd
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128710119 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 37.rv_dm_tap_fsm_rand_reset.128710119
Directory /workspace/37.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1681213331
Short name T292
Test name
Test status
Simulation time 1748691767 ps
CPU time 30.03 seconds
Started Jun 02 12:50:36 PM PDT 24
Finished Jun 02 12:51:07 PM PDT 24
Peak memory 213644 kb
Host smart-e6098d5e-0c1a-466f-bd30-4c9422a68a8f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681213331 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.1681213331
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.80205544
Short name T105
Test name
Test status
Simulation time 837023972 ps
CPU time 26.85 seconds
Started Jun 02 12:50:32 PM PDT 24
Finished Jun 02 12:50:59 PM PDT 24
Peak memory 213708 kb
Host smart-28863ddc-50a3-4df1-b3c3-32c432454cbc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80205544 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.80205544
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.3981230419
Short name T81
Test name
Test status
Simulation time 105541968 ps
CPU time 1.6 seconds
Started Jun 02 12:50:32 PM PDT 24
Finished Jun 02 12:50:34 PM PDT 24
Peak memory 213736 kb
Host smart-1d7d293e-b95c-489c-ab62-acb0593fda7c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981230419 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.3981230419
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.3707110131
Short name T305
Test name
Test status
Simulation time 3253105617 ps
CPU time 4.75 seconds
Started Jun 02 12:50:40 PM PDT 24
Finished Jun 02 12:50:45 PM PDT 24
Peak memory 220976 kb
Host smart-76212a02-5ffc-4d05-9490-5a1cff9375f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707110131 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.3707110131
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.4104860023
Short name T278
Test name
Test status
Simulation time 105455033 ps
CPU time 1.53 seconds
Started Jun 02 12:50:34 PM PDT 24
Finished Jun 02 12:50:36 PM PDT 24
Peak memory 213784 kb
Host smart-b5ad4c77-50b1-40b8-bbd3-7315e61a9d63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104860023 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.4104860023
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.875508530
Short name T358
Test name
Test status
Simulation time 101033067001 ps
CPU time 27.09 seconds
Started Jun 02 12:50:36 PM PDT 24
Finished Jun 02 12:51:03 PM PDT 24
Peak memory 205504 kb
Host smart-2340e5f7-8a25-4a1b-b1b8-df6aa55d09d8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875508530 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr
_aliasing.875508530
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.4230813712
Short name T89
Test name
Test status
Simulation time 10831096466 ps
CPU time 17.55 seconds
Started Jun 02 12:50:35 PM PDT 24
Finished Jun 02 12:50:52 PM PDT 24
Peak memory 205812 kb
Host smart-3c1ccdf2-49d9-4bcf-afcf-22c073e379da
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230813712 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.4230813712
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3302810069
Short name T287
Test name
Test status
Simulation time 1422996100 ps
CPU time 4.04 seconds
Started Jun 02 12:50:35 PM PDT 24
Finished Jun 02 12:50:39 PM PDT 24
Peak memory 205392 kb
Host smart-7392c558-f3e5-4c65-98cf-13f4e0cf2fce
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302810069 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.3
302810069
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.2344731643
Short name T291
Test name
Test status
Simulation time 715731370 ps
CPU time 2.49 seconds
Started Jun 02 12:50:34 PM PDT 24
Finished Jun 02 12:50:37 PM PDT 24
Peak memory 205204 kb
Host smart-6cd8f045-c1c4-4891-a7ed-ddf8be0102d5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344731643 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.2344731643
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2029742887
Short name T324
Test name
Test status
Simulation time 58416955675 ps
CPU time 87.78 seconds
Started Jun 02 12:50:35 PM PDT 24
Finished Jun 02 12:52:03 PM PDT 24
Peak memory 205504 kb
Host smart-b7f85142-504e-4ca1-b037-c5f275a32452
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029742887 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.2029742887
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.629351816
Short name T376
Test name
Test status
Simulation time 218422903 ps
CPU time 0.95 seconds
Started Jun 02 12:50:33 PM PDT 24
Finished Jun 02 12:50:34 PM PDT 24
Peak memory 205272 kb
Host smart-18f2473c-d6bc-47d2-a8a4-ade7fccb3df6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629351816 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr
_hw_reset.629351816
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.3609510651
Short name T288
Test name
Test status
Simulation time 120181857 ps
CPU time 0.83 seconds
Started Jun 02 12:50:35 PM PDT 24
Finished Jun 02 12:50:37 PM PDT 24
Peak memory 205156 kb
Host smart-2bd4957a-3cb4-4cb3-8991-63f7a5238d1f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609510651 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.3
609510651
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.2127345329
Short name T355
Test name
Test status
Simulation time 119106756 ps
CPU time 0.77 seconds
Started Jun 02 12:50:34 PM PDT 24
Finished Jun 02 12:50:35 PM PDT 24
Peak memory 205204 kb
Host smart-b13dda7e-f03e-4401-bee1-6959ac7e7c8d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127345329 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.2127345329
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.2321959836
Short name T389
Test name
Test status
Simulation time 78576712 ps
CPU time 0.84 seconds
Started Jun 02 12:50:37 PM PDT 24
Finished Jun 02 12:50:39 PM PDT 24
Peak memory 205180 kb
Host smart-daf788db-5bcd-4714-8cad-4607bfa814be
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321959836 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.2321959836
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1749504599
Short name T113
Test name
Test status
Simulation time 189011241 ps
CPU time 3.65 seconds
Started Jun 02 12:50:40 PM PDT 24
Finished Jun 02 12:50:44 PM PDT 24
Peak memory 205600 kb
Host smart-3a606de3-5d8a-4ada-939d-dde2f32dd5eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749504599 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.1749504599
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.3855558914
Short name T70
Test name
Test status
Simulation time 366913750 ps
CPU time 6.92 seconds
Started Jun 02 12:50:35 PM PDT 24
Finished Jun 02 12:50:42 PM PDT 24
Peak memory 213796 kb
Host smart-92058c37-ec03-45b8-a129-74b80efcfdb4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855558914 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.3855558914
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.8567450
Short name T124
Test name
Test status
Simulation time 1605873227 ps
CPU time 10.57 seconds
Started Jun 02 12:50:35 PM PDT 24
Finished Jun 02 12:50:46 PM PDT 24
Peak memory 213748 kb
Host smart-9bfde472-0184-4d7b-b420-e7fb950b1cbe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8567450 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.8567450
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.1957496858
Short name T72
Test name
Test status
Simulation time 372946924 ps
CPU time 2.33 seconds
Started Jun 02 12:50:39 PM PDT 24
Finished Jun 02 12:50:41 PM PDT 24
Peak memory 213904 kb
Host smart-3539c566-206a-4dae-87ed-c19bb9380058
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957496858 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.1957496858
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.1288352845
Short name T384
Test name
Test status
Simulation time 154548639 ps
CPU time 2.31 seconds
Started Jun 02 12:50:39 PM PDT 24
Finished Jun 02 12:50:42 PM PDT 24
Peak memory 213708 kb
Host smart-f6c48eb2-1c7c-4410-aaf4-29391e4ee399
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288352845 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.1288352845
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.2513158859
Short name T261
Test name
Test status
Simulation time 1124253271 ps
CPU time 3.79 seconds
Started Jun 02 12:50:41 PM PDT 24
Finished Jun 02 12:50:46 PM PDT 24
Peak memory 205332 kb
Host smart-022c2f1a-8d20-44ce-8a81-69c5e898884c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513158859 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.2
513158859
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.545982059
Short name T266
Test name
Test status
Simulation time 115892305 ps
CPU time 0.94 seconds
Started Jun 02 12:50:40 PM PDT 24
Finished Jun 02 12:50:42 PM PDT 24
Peak memory 205372 kb
Host smart-92260436-0929-4cc8-9917-8efea3840db1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545982059 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.545982059
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.2703069539
Short name T98
Test name
Test status
Simulation time 254300281 ps
CPU time 3.72 seconds
Started Jun 02 12:50:41 PM PDT 24
Finished Jun 02 12:50:46 PM PDT 24
Peak memory 205564 kb
Host smart-f50749ec-d492-49ab-95f2-3594e28fc601
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703069539 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.2703069539
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.3930115420
Short name T276
Test name
Test status
Simulation time 402931359 ps
CPU time 6.37 seconds
Started Jun 02 12:50:41 PM PDT 24
Finished Jun 02 12:50:48 PM PDT 24
Peak memory 213732 kb
Host smart-e92b765d-8f25-40c0-8a16-2721fe888f53
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930115420 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.3930115420
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.779991492
Short name T119
Test name
Test status
Simulation time 379282418 ps
CPU time 2.23 seconds
Started Jun 02 12:50:39 PM PDT 24
Finished Jun 02 12:50:42 PM PDT 24
Peak memory 213840 kb
Host smart-6e3eba7e-91e9-4bdb-a30d-2c49d9d8ce8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779991492 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.779991492
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1447686203
Short name T103
Test name
Test status
Simulation time 155279159 ps
CPU time 2.22 seconds
Started Jun 02 12:50:40 PM PDT 24
Finished Jun 02 12:50:43 PM PDT 24
Peak memory 213684 kb
Host smart-93a658b4-b63f-4d2b-ba8e-788c14277493
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447686203 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.1447686203
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.3982739807
Short name T269
Test name
Test status
Simulation time 5673455154 ps
CPU time 8.41 seconds
Started Jun 02 12:50:40 PM PDT 24
Finished Jun 02 12:50:49 PM PDT 24
Peak memory 205528 kb
Host smart-df2403b6-82af-4c9c-afd6-1218d46ef0e4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982739807 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.3
982739807
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2798085537
Short name T283
Test name
Test status
Simulation time 814574935 ps
CPU time 1.92 seconds
Started Jun 02 12:50:39 PM PDT 24
Finished Jun 02 12:50:41 PM PDT 24
Peak memory 205192 kb
Host smart-42e8c8c0-6c39-4a5e-882c-8b2c8301ebf6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798085537 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.2
798085537
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.3036078895
Short name T357
Test name
Test status
Simulation time 1710419758 ps
CPU time 7.83 seconds
Started Jun 02 12:50:38 PM PDT 24
Finished Jun 02 12:50:46 PM PDT 24
Peak memory 205516 kb
Host smart-4506acd4-d8ac-41b5-899d-2ca610a55719
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036078895 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.3036078895
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.1887369377
Short name T379
Test name
Test status
Simulation time 135025157 ps
CPU time 5.64 seconds
Started Jun 02 12:50:41 PM PDT 24
Finished Jun 02 12:50:47 PM PDT 24
Peak memory 213768 kb
Host smart-5dffae23-bfa4-4d83-8530-769a510308bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887369377 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.1887369377
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1738683171
Short name T125
Test name
Test status
Simulation time 1407621545 ps
CPU time 20.39 seconds
Started Jun 02 12:50:39 PM PDT 24
Finished Jun 02 12:51:00 PM PDT 24
Peak memory 213756 kb
Host smart-108dbc31-abe9-4f91-ae81-df5cfda76372
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738683171 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.1738683171
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2690930381
Short name T281
Test name
Test status
Simulation time 877340268 ps
CPU time 4.38 seconds
Started Jun 02 12:50:39 PM PDT 24
Finished Jun 02 12:50:43 PM PDT 24
Peak memory 221504 kb
Host smart-00f5d522-bfb1-43a3-adbd-99085a24620e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690930381 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.2690930381
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.2730529880
Short name T339
Test name
Test status
Simulation time 105181954 ps
CPU time 2.34 seconds
Started Jun 02 12:50:41 PM PDT 24
Finished Jun 02 12:50:43 PM PDT 24
Peak memory 213848 kb
Host smart-7a9bf753-69b0-4d6a-a9e8-29def3084183
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730529880 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.2730529880
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.778089420
Short name T363
Test name
Test status
Simulation time 4538210724 ps
CPU time 14.16 seconds
Started Jun 02 12:50:38 PM PDT 24
Finished Jun 02 12:50:53 PM PDT 24
Peak memory 205380 kb
Host smart-cf5cfc0c-afd6-460e-8a38-f151b8ea419d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778089420 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.778089420
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1627826916
Short name T57
Test name
Test status
Simulation time 118555921 ps
CPU time 0.87 seconds
Started Jun 02 12:50:39 PM PDT 24
Finished Jun 02 12:50:40 PM PDT 24
Peak memory 205232 kb
Host smart-5852a7d4-af31-4d5c-812f-986028ace845
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627826916 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.1
627826916
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3559399617
Short name T336
Test name
Test status
Simulation time 10204313143 ps
CPU time 8.01 seconds
Started Jun 02 12:50:41 PM PDT 24
Finished Jun 02 12:50:49 PM PDT 24
Peak memory 205748 kb
Host smart-5ba7768a-bd29-4c74-9fdf-8d24c633d32b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559399617 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.3559399617
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.182935931
Short name T290
Test name
Test status
Simulation time 314152065 ps
CPU time 4.9 seconds
Started Jun 02 12:50:40 PM PDT 24
Finished Jun 02 12:50:45 PM PDT 24
Peak memory 213832 kb
Host smart-8619dead-93d4-44c0-b578-4f4fc6519961
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182935931 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.182935931
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.3894230872
Short name T386
Test name
Test status
Simulation time 1918617368 ps
CPU time 20.53 seconds
Started Jun 02 12:50:39 PM PDT 24
Finished Jun 02 12:51:00 PM PDT 24
Peak memory 213732 kb
Host smart-ee72853c-d039-4620-aab5-4de7f99a470c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894230872 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.3894230872
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1082139623
Short name T360
Test name
Test status
Simulation time 3442897104 ps
CPU time 4.71 seconds
Started Jun 02 12:50:47 PM PDT 24
Finished Jun 02 12:50:52 PM PDT 24
Peak memory 222096 kb
Host smart-a8686866-4cfa-433b-ad14-fd1dafaee19e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082139623 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.1082139623
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1659147281
Short name T310
Test name
Test status
Simulation time 124359769 ps
CPU time 1.64 seconds
Started Jun 02 12:50:47 PM PDT 24
Finished Jun 02 12:50:49 PM PDT 24
Peak memory 213740 kb
Host smart-74a39dc2-c384-42c9-9d40-9f12434fcc10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659147281 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.1659147281
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3593250168
Short name T370
Test name
Test status
Simulation time 5781708735 ps
CPU time 8.71 seconds
Started Jun 02 12:50:41 PM PDT 24
Finished Jun 02 12:50:50 PM PDT 24
Peak memory 205504 kb
Host smart-f80146ab-ce26-4ee4-84c8-0d440b38b4fe
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593250168 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.3
593250168
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2648566334
Short name T369
Test name
Test status
Simulation time 461397701 ps
CPU time 1.81 seconds
Started Jun 02 12:50:39 PM PDT 24
Finished Jun 02 12:50:42 PM PDT 24
Peak memory 205468 kb
Host smart-7a3b6cf7-b699-4055-9588-854c6aeb8e09
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648566334 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.2
648566334
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.4284766327
Short name T112
Test name
Test status
Simulation time 163165744 ps
CPU time 6.44 seconds
Started Jun 02 12:50:50 PM PDT 24
Finished Jun 02 12:50:57 PM PDT 24
Peak memory 205484 kb
Host smart-eea3f1ec-ee15-4262-9be2-0a17efbbbc7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284766327 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_
csr_outstanding.4284766327
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.804114127
Short name T312
Test name
Test status
Simulation time 40350510053 ps
CPU time 18.91 seconds
Started Jun 02 12:50:41 PM PDT 24
Finished Jun 02 12:51:01 PM PDT 24
Peak memory 230356 kb
Host smart-af6336af-0de9-4f4f-b71a-a1cbb47827d3
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804114127 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.804114127
Directory /workspace/8.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.1496750948
Short name T340
Test name
Test status
Simulation time 275584092 ps
CPU time 6.54 seconds
Started Jun 02 12:50:40 PM PDT 24
Finished Jun 02 12:50:47 PM PDT 24
Peak memory 213772 kb
Host smart-dc1c2dd5-d8cb-4022-a48a-62967f6c839b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496750948 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.1496750948
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.1066010017
Short name T126
Test name
Test status
Simulation time 4078999801 ps
CPU time 22.13 seconds
Started Jun 02 12:50:43 PM PDT 24
Finished Jun 02 12:51:06 PM PDT 24
Peak memory 214652 kb
Host smart-00286add-1f9c-4c12-add7-d4801ef9781d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066010017 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.1066010017
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3735208714
Short name T373
Test name
Test status
Simulation time 1847846250 ps
CPU time 2.91 seconds
Started Jun 02 12:50:49 PM PDT 24
Finished Jun 02 12:50:53 PM PDT 24
Peak memory 213812 kb
Host smart-25c2d937-7cf8-4603-827a-4ecdb06473e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735208714 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.3735208714
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.3716305783
Short name T97
Test name
Test status
Simulation time 99396498 ps
CPU time 2.25 seconds
Started Jun 02 12:50:49 PM PDT 24
Finished Jun 02 12:50:51 PM PDT 24
Peak memory 213784 kb
Host smart-87b536ff-a697-434d-afdf-d307d77b9f97
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716305783 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.3716305783
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.2032062713
Short name T390
Test name
Test status
Simulation time 1024288513 ps
CPU time 3.55 seconds
Started Jun 02 12:50:50 PM PDT 24
Finished Jun 02 12:50:54 PM PDT 24
Peak memory 205396 kb
Host smart-7adfd8cb-6c09-46c6-908a-d535e6324eb9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032062713 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.2
032062713
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.2447527530
Short name T341
Test name
Test status
Simulation time 450363774 ps
CPU time 1.86 seconds
Started Jun 02 12:50:50 PM PDT 24
Finished Jun 02 12:50:52 PM PDT 24
Peak memory 205188 kb
Host smart-99694b80-0733-47c4-9a46-01f6e03dfae1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447527530 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.2
447527530
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.1387546866
Short name T343
Test name
Test status
Simulation time 887654237 ps
CPU time 7.51 seconds
Started Jun 02 12:50:48 PM PDT 24
Finished Jun 02 12:50:56 PM PDT 24
Peak memory 205644 kb
Host smart-6bc46654-5427-403e-bd3a-17c42503fb2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387546866 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.1387546866
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.3746011508
Short name T300
Test name
Test status
Simulation time 836324231 ps
CPU time 6.59 seconds
Started Jun 02 12:50:49 PM PDT 24
Finished Jun 02 12:50:56 PM PDT 24
Peak memory 213828 kb
Host smart-7b7b2390-4680-4cd0-94c6-972a5b35bdcc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746011508 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.3746011508
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.3363216387
Short name T330
Test name
Test status
Simulation time 1092899308 ps
CPU time 8.28 seconds
Started Jun 02 12:50:47 PM PDT 24
Finished Jun 02 12:50:56 PM PDT 24
Peak memory 213700 kb
Host smart-772e2b0e-bde1-4645-9ebb-0f5602b34f87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363216387 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.3363216387
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.637555812
Short name T160
Test name
Test status
Simulation time 176643678 ps
CPU time 0.77 seconds
Started Jun 02 12:51:21 PM PDT 24
Finished Jun 02 12:51:22 PM PDT 24
Peak memory 205172 kb
Host smart-d66b7b88-9e57-4b88-98d8-8d4aacd92898
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637555812 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.637555812
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.2135886591
Short name T141
Test name
Test status
Simulation time 15071476932 ps
CPU time 41.92 seconds
Started Jun 02 12:51:16 PM PDT 24
Finished Jun 02 12:51:58 PM PDT 24
Peak memory 205288 kb
Host smart-4ca98709-165b-4a66-b58d-c26a7ded37d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135886591 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.2135886591
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.3951458218
Short name T258
Test name
Test status
Simulation time 8266901055 ps
CPU time 6.81 seconds
Started Jun 02 12:51:13 PM PDT 24
Finished Jun 02 12:51:20 PM PDT 24
Peak memory 205284 kb
Host smart-7f0042be-c13b-4e8e-a354-b601c07fa117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951458218 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.3951458218
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.1237586202
Short name T183
Test name
Test status
Simulation time 88055702 ps
CPU time 0.91 seconds
Started Jun 02 12:51:13 PM PDT 24
Finished Jun 02 12:51:15 PM PDT 24
Peak memory 205016 kb
Host smart-93772cfe-7461-466b-bf50-05d63c3a6892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237586202 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.1237586202
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.2451342729
Short name T216
Test name
Test status
Simulation time 13715180708 ps
CPU time 20.88 seconds
Started Jun 02 12:51:16 PM PDT 24
Finished Jun 02 12:51:37 PM PDT 24
Peak memory 205392 kb
Host smart-30014a59-dcc4-4c8e-b0e5-2fb8dd90b02b
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2451342729 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t
l_access.2451342729
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.1098112423
Short name T148
Test name
Test status
Simulation time 935714665 ps
CPU time 1.09 seconds
Started Jun 02 12:51:17 PM PDT 24
Finished Jun 02 12:51:18 PM PDT 24
Peak memory 204928 kb
Host smart-04dab0e8-cd85-4a62-aed4-a66e465e46ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098112423 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.1098112423
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.3129535417
Short name T185
Test name
Test status
Simulation time 392463100 ps
CPU time 1.01 seconds
Started Jun 02 12:51:14 PM PDT 24
Finished Jun 02 12:51:16 PM PDT 24
Peak memory 204836 kb
Host smart-10dbab66-3c6c-4804-b126-25762a7ef9f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129535417 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.3129535417
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.2651403117
Short name T199
Test name
Test status
Simulation time 764986554 ps
CPU time 2.75 seconds
Started Jun 02 12:51:23 PM PDT 24
Finished Jun 02 12:51:26 PM PDT 24
Peak memory 204816 kb
Host smart-3434f72f-2f05-4c6f-ad39-5cb843754842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651403117 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.2651403117
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.294322108
Short name T198
Test name
Test status
Simulation time 999048499 ps
CPU time 2.13 seconds
Started Jun 02 12:51:22 PM PDT 24
Finished Jun 02 12:51:25 PM PDT 24
Peak memory 204828 kb
Host smart-530f8793-7959-4916-9567-3dccf24dca68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294322108 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.294322108
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.992279612
Short name T1
Test name
Test status
Simulation time 1549250627 ps
CPU time 5.02 seconds
Started Jun 02 12:51:22 PM PDT 24
Finished Jun 02 12:51:28 PM PDT 24
Peak memory 204984 kb
Host smart-bb09eb81-93c4-4b0b-b8b6-664aac334682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992279612 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.992279612
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.2544413519
Short name T227
Test name
Test status
Simulation time 542571745 ps
CPU time 1.05 seconds
Started Jun 02 12:51:15 PM PDT 24
Finished Jun 02 12:51:17 PM PDT 24
Peak memory 204808 kb
Host smart-1db83a63-c703-448f-a6e1-f3d0a6af7433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544413519 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.2544413519
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.3216598132
Short name T14
Test name
Test status
Simulation time 457752097 ps
CPU time 1.39 seconds
Started Jun 02 12:51:14 PM PDT 24
Finished Jun 02 12:51:16 PM PDT 24
Peak memory 204976 kb
Host smart-46e7d3c0-2343-40ee-9542-34429a0d233d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216598132 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.3216598132
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.2293542799
Short name T24
Test name
Test status
Simulation time 3249546243 ps
CPU time 2.51 seconds
Started Jun 02 12:51:15 PM PDT 24
Finished Jun 02 12:51:18 PM PDT 24
Peak memory 205404 kb
Host smart-2be06323-d6b0-4953-ac25-19550fab0387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293542799 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.2293542799
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.1609380309
Short name T75
Test name
Test status
Simulation time 2684033409 ps
CPU time 2.27 seconds
Started Jun 02 12:51:14 PM PDT 24
Finished Jun 02 12:51:17 PM PDT 24
Peak memory 205276 kb
Host smart-e1ea96b9-7c17-4bb4-a5dd-71ef0438bebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609380309 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.1609380309
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.4037742900
Short name T27
Test name
Test status
Simulation time 89890862 ps
CPU time 0.84 seconds
Started Jun 02 12:51:21 PM PDT 24
Finished Jun 02 12:51:22 PM PDT 24
Peak memory 213212 kb
Host smart-4b5bc897-b544-4b55-8d94-26319bd4b43b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037742900 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.4037742900
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.2364738166
Short name T215
Test name
Test status
Simulation time 28102567573 ps
CPU time 38.52 seconds
Started Jun 02 12:51:15 PM PDT 24
Finished Jun 02 12:51:54 PM PDT 24
Peak memory 213656 kb
Host smart-7086658f-84a3-49a2-8b84-9d23a7d90f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364738166 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.2364738166
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.568707928
Short name T38
Test name
Test status
Simulation time 1616665416 ps
CPU time 2.26 seconds
Started Jun 02 12:51:20 PM PDT 24
Finished Jun 02 12:51:23 PM PDT 24
Peak memory 229268 kb
Host smart-17a28dcc-6e7f-44cc-82ce-13d0865c4b19
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568707928 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.568707928
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.3978728460
Short name T213
Test name
Test status
Simulation time 3089936148 ps
CPU time 9.09 seconds
Started Jun 02 12:51:13 PM PDT 24
Finished Jun 02 12:51:22 PM PDT 24
Peak memory 204996 kb
Host smart-7bb454ef-6a39-4844-8c53-fcf0f8570aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978728460 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.3978728460
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all.3053522900
Short name T19
Test name
Test status
Simulation time 10015499641 ps
CPU time 8.87 seconds
Started Jun 02 12:51:19 PM PDT 24
Finished Jun 02 12:51:29 PM PDT 24
Peak memory 205356 kb
Host smart-d81d9003-16a3-453e-ba52-1a023ede4bfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053522900 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.3053522900
Directory /workspace/0.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.2843959355
Short name T17
Test name
Test status
Simulation time 10948092146 ps
CPU time 17.39 seconds
Started Jun 02 12:51:15 PM PDT 24
Finished Jun 02 12:51:33 PM PDT 24
Peak memory 205240 kb
Host smart-454f845c-f81d-4457-b88d-cc8e1b80a8b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843959355 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.2843959355
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.708291601
Short name T34
Test name
Test status
Simulation time 97897966 ps
CPU time 0.9 seconds
Started Jun 02 12:51:24 PM PDT 24
Finished Jun 02 12:51:25 PM PDT 24
Peak memory 204728 kb
Host smart-a4998e6d-4502-4c3d-b154-1ed82416c5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708291601 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.708291601
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.3782163891
Short name T169
Test name
Test status
Simulation time 135467839 ps
CPU time 0.99 seconds
Started Jun 02 12:51:26 PM PDT 24
Finished Jun 02 12:51:28 PM PDT 24
Peak memory 204872 kb
Host smart-39764446-c348-4142-8f56-aa0d04c6ffe9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782163891 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.3782163891
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.4214215844
Short name T209
Test name
Test status
Simulation time 57513263528 ps
CPU time 165.82 seconds
Started Jun 02 12:51:21 PM PDT 24
Finished Jun 02 12:54:07 PM PDT 24
Peak memory 213660 kb
Host smart-8b719c0c-8db2-41d3-beb7-4618f4370c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214215844 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.4214215844
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.1800037457
Short name T207
Test name
Test status
Simulation time 17751152803 ps
CPU time 26.69 seconds
Started Jun 02 12:51:28 PM PDT 24
Finished Jun 02 12:51:55 PM PDT 24
Peak memory 205260 kb
Host smart-d613dc01-5615-49b7-bc3d-fce2d25829c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800037457 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.1800037457
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.105349741
Short name T29
Test name
Test status
Simulation time 421296879 ps
CPU time 1.38 seconds
Started Jun 02 12:51:19 PM PDT 24
Finished Jun 02 12:51:21 PM PDT 24
Peak memory 204944 kb
Host smart-e2d82064-af84-4ec6-aebe-a78f207f2c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105349741 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.105349741
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.2653511565
Short name T23
Test name
Test status
Simulation time 2058044196 ps
CPU time 3.44 seconds
Started Jun 02 12:51:21 PM PDT 24
Finished Jun 02 12:51:25 PM PDT 24
Peak memory 204888 kb
Host smart-daf778bc-93fd-405a-921e-db43ff51f522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653511565 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.2653511565
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.2109658397
Short name T146
Test name
Test status
Simulation time 4968018137 ps
CPU time 4.88 seconds
Started Jun 02 12:51:22 PM PDT 24
Finished Jun 02 12:51:28 PM PDT 24
Peak memory 205444 kb
Host smart-6112331d-1774-4925-874a-a6077640ff0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109658397 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.2109658397
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.151749076
Short name T151
Test name
Test status
Simulation time 158234014 ps
CPU time 0.88 seconds
Started Jun 02 12:51:21 PM PDT 24
Finished Jun 02 12:51:23 PM PDT 24
Peak memory 205012 kb
Host smart-4d2fd70c-80cf-4faf-994e-7dd33f061f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151749076 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.151749076
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.2929966007
Short name T212
Test name
Test status
Simulation time 7396595143 ps
CPU time 13.36 seconds
Started Jun 02 12:51:21 PM PDT 24
Finished Jun 02 12:51:35 PM PDT 24
Peak memory 205416 kb
Host smart-94e803e8-c829-412d-8ab5-ecaa774874d9
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2929966007 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.2929966007
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.1640873105
Short name T150
Test name
Test status
Simulation time 356275779 ps
CPU time 1.07 seconds
Started Jun 02 12:51:22 PM PDT 24
Finished Jun 02 12:51:24 PM PDT 24
Peak memory 204940 kb
Host smart-499187a5-e979-406b-8a49-bd83ddb9ed29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640873105 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.1640873105
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.752820676
Short name T62
Test name
Test status
Simulation time 231838624 ps
CPU time 1.44 seconds
Started Jun 02 12:51:21 PM PDT 24
Finished Jun 02 12:51:23 PM PDT 24
Peak memory 204836 kb
Host smart-4389e844-a174-4df5-be3f-ac81315e3b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752820676 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.752820676
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.3619056880
Short name T248
Test name
Test status
Simulation time 331284047 ps
CPU time 1.1 seconds
Started Jun 02 12:51:28 PM PDT 24
Finished Jun 02 12:51:30 PM PDT 24
Peak memory 204420 kb
Host smart-8a4d8466-a083-4ff0-8141-eb85a8bb74f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619056880 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.3619056880
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.734207329
Short name T253
Test name
Test status
Simulation time 707719675 ps
CPU time 0.82 seconds
Started Jun 02 12:51:19 PM PDT 24
Finished Jun 02 12:51:20 PM PDT 24
Peak memory 204852 kb
Host smart-0d0c1926-b279-4a1a-9739-9d2b6e30f03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734207329 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.734207329
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.3527340336
Short name T204
Test name
Test status
Simulation time 894491798 ps
CPU time 1.35 seconds
Started Jun 02 12:51:21 PM PDT 24
Finished Jun 02 12:51:23 PM PDT 24
Peak memory 204888 kb
Host smart-036f64df-2919-4cfb-8221-a6ce6a6420e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527340336 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.3527340336
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.2792782107
Short name T41
Test name
Test status
Simulation time 516284523 ps
CPU time 1.55 seconds
Started Jun 02 12:51:20 PM PDT 24
Finished Jun 02 12:51:22 PM PDT 24
Peak memory 204900 kb
Host smart-c3c68ea5-be82-4ecb-bffe-b0e527605425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792782107 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.2792782107
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.3676476146
Short name T144
Test name
Test status
Simulation time 633576307 ps
CPU time 0.93 seconds
Started Jun 02 12:51:28 PM PDT 24
Finished Jun 02 12:51:30 PM PDT 24
Peak memory 204612 kb
Host smart-4fc23d26-a077-4e02-aedf-6291301daa9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676476146 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.3676476146
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.3330656108
Short name T143
Test name
Test status
Simulation time 978311392 ps
CPU time 1.47 seconds
Started Jun 02 12:51:27 PM PDT 24
Finished Jun 02 12:51:30 PM PDT 24
Peak memory 204944 kb
Host smart-681e6bfa-54ad-42c5-8376-cad25c17e45c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330656108 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.3330656108
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.240734951
Short name T149
Test name
Test status
Simulation time 944679538 ps
CPU time 3.61 seconds
Started Jun 02 12:51:24 PM PDT 24
Finished Jun 02 12:51:28 PM PDT 24
Peak memory 204968 kb
Host smart-67f374b3-8e5b-45f2-870e-05c9c7fbf2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240734951 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.240734951
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.4010417221
Short name T28
Test name
Test status
Simulation time 545369676 ps
CPU time 1.65 seconds
Started Jun 02 12:51:21 PM PDT 24
Finished Jun 02 12:51:23 PM PDT 24
Peak memory 205256 kb
Host smart-ec43a5a8-e743-4511-9017-ca50a13c2c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010417221 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.4010417221
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.1809647350
Short name T31
Test name
Test status
Simulation time 396348734 ps
CPU time 1.34 seconds
Started Jun 02 12:51:31 PM PDT 24
Finished Jun 02 12:51:33 PM PDT 24
Peak memory 204944 kb
Host smart-bfc763c8-0b39-482d-8482-cc5499c5445e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809647350 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.1809647350
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.2354274591
Short name T195
Test name
Test status
Simulation time 38816205817 ps
CPU time 23.26 seconds
Started Jun 02 12:51:20 PM PDT 24
Finished Jun 02 12:51:44 PM PDT 24
Peak memory 205476 kb
Host smart-7612c112-a318-47cb-9e0d-1f270f9e72df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354274591 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.2354274591
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.2750607593
Short name T52
Test name
Test status
Simulation time 817161554 ps
CPU time 1.86 seconds
Started Jun 02 12:51:29 PM PDT 24
Finished Jun 02 12:51:32 PM PDT 24
Peak memory 237188 kb
Host smart-da758d1a-7e09-4513-b580-58f7c98bcb5c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750607593 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.2750607593
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.2008479063
Short name T241
Test name
Test status
Simulation time 1034786235 ps
CPU time 2.52 seconds
Started Jun 02 12:51:24 PM PDT 24
Finished Jun 02 12:51:27 PM PDT 24
Peak memory 204972 kb
Host smart-9114cc19-69f6-439e-a679-82076f89a3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008479063 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.2008479063
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all.2971756962
Short name T138
Test name
Test status
Simulation time 8217639169 ps
CPU time 23.93 seconds
Started Jun 02 12:51:26 PM PDT 24
Finished Jun 02 12:51:51 PM PDT 24
Peak memory 205300 kb
Host smart-0e9edcdc-00bd-423d-88b5-5d4a8dd98ddd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971756962 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.2971756962
Directory /workspace/1.rv_dm_stress_all/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.2820787541
Short name T173
Test name
Test status
Simulation time 179440055 ps
CPU time 1.16 seconds
Started Jun 02 12:51:41 PM PDT 24
Finished Jun 02 12:51:43 PM PDT 24
Peak memory 204928 kb
Host smart-fb641df4-9c61-4fc4-a1f2-770c4ac12eb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820787541 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.2820787541
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.3352043891
Short name T222
Test name
Test status
Simulation time 146530931389 ps
CPU time 209.79 seconds
Started Jun 02 12:51:40 PM PDT 24
Finished Jun 02 12:55:11 PM PDT 24
Peak memory 217800 kb
Host smart-2fb19303-80d5-4100-97e7-58b6be3aa0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352043891 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.3352043891
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.3040133401
Short name T11
Test name
Test status
Simulation time 8179863088 ps
CPU time 23.51 seconds
Started Jun 02 12:51:42 PM PDT 24
Finished Jun 02 12:52:06 PM PDT 24
Peak memory 213640 kb
Host smart-cdf16efd-f893-452f-8c1e-a770ec93eee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040133401 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.3040133401
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.2121211005
Short name T86
Test name
Test status
Simulation time 42342326073 ps
CPU time 124.2 seconds
Started Jun 02 12:51:42 PM PDT 24
Finished Jun 02 12:53:46 PM PDT 24
Peak memory 213672 kb
Host smart-fc0f578a-c4cf-44ba-977c-0d232d781c88
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2121211005 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.2121211005
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.2516778075
Short name T53
Test name
Test status
Simulation time 40129721450 ps
CPU time 101.82 seconds
Started Jun 02 12:51:43 PM PDT 24
Finished Jun 02 12:53:25 PM PDT 24
Peak memory 205512 kb
Host smart-b5aa44d6-28e9-403d-bf36-f3f4a8f66986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516778075 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.2516778075
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.2422822962
Short name T163
Test name
Test status
Simulation time 184905966 ps
CPU time 0.84 seconds
Started Jun 02 12:51:41 PM PDT 24
Finished Jun 02 12:51:43 PM PDT 24
Peak memory 204984 kb
Host smart-7a4137d3-f0ba-459e-96f6-eb10098ba974
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422822962 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.2422822962
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.3794975199
Short name T256
Test name
Test status
Simulation time 85831395455 ps
CPU time 70.99 seconds
Started Jun 02 12:51:39 PM PDT 24
Finished Jun 02 12:52:50 PM PDT 24
Peak memory 213660 kb
Host smart-a274ed68-3978-4a44-aedf-703175c80a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794975199 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.3794975199
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.2054030050
Short name T44
Test name
Test status
Simulation time 14021489726 ps
CPU time 26.15 seconds
Started Jun 02 12:51:40 PM PDT 24
Finished Jun 02 12:52:07 PM PDT 24
Peak memory 221804 kb
Host smart-c66a3864-68d0-4ba7-9874-1982ee90f758
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2054030050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_
tl_access.2054030050
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.1490905311
Short name T20
Test name
Test status
Simulation time 140207121657 ps
CPU time 368.13 seconds
Started Jun 02 12:51:45 PM PDT 24
Finished Jun 02 12:57:53 PM PDT 24
Peak memory 210224 kb
Host smart-589471a6-8a9c-4254-a6bc-bafc48851fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490905311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.1490905311
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_stress_all.1214972564
Short name T147
Test name
Test status
Simulation time 17258354580 ps
CPU time 43.53 seconds
Started Jun 02 12:51:40 PM PDT 24
Finished Jun 02 12:52:24 PM PDT 24
Peak memory 213668 kb
Host smart-ed3221ec-1465-4675-a07a-2c0ba73641b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214972564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.1214972564
Directory /workspace/11.rv_dm_stress_all/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.2151467805
Short name T3
Test name
Test status
Simulation time 71183376 ps
CPU time 0.79 seconds
Started Jun 02 12:51:41 PM PDT 24
Finished Jun 02 12:51:42 PM PDT 24
Peak memory 205004 kb
Host smart-4f1ad059-3161-403a-812d-98b8533f9469
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151467805 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.2151467805
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.1087365723
Short name T191
Test name
Test status
Simulation time 89280966694 ps
CPU time 230.8 seconds
Started Jun 02 12:51:41 PM PDT 24
Finished Jun 02 12:55:33 PM PDT 24
Peak memory 213716 kb
Host smart-51f64112-6dce-426b-8be5-dd8e969c02dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087365723 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.1087365723
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.3441090803
Short name T238
Test name
Test status
Simulation time 36778090090 ps
CPU time 95.05 seconds
Started Jun 02 12:51:42 PM PDT 24
Finished Jun 02 12:53:18 PM PDT 24
Peak memory 213608 kb
Host smart-2ba1187b-05ad-4bb2-9b35-acaf8dee713a
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3441090803 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.3441090803
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.2354613074
Short name T245
Test name
Test status
Simulation time 42816865706 ps
CPU time 37.56 seconds
Started Jun 02 12:51:43 PM PDT 24
Finished Jun 02 12:52:21 PM PDT 24
Peak memory 213720 kb
Host smart-28f892b1-45a4-4861-98c1-b751c7de040b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354613074 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.2354613074
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.3879598033
Short name T190
Test name
Test status
Simulation time 81593503 ps
CPU time 0.84 seconds
Started Jun 02 12:51:46 PM PDT 24
Finished Jun 02 12:51:47 PM PDT 24
Peak memory 204956 kb
Host smart-86a9441a-e8fe-4a1b-a43e-8209e9d10119
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879598033 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.3879598033
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.1231867986
Short name T229
Test name
Test status
Simulation time 15934130108 ps
CPU time 9.49 seconds
Started Jun 02 12:51:42 PM PDT 24
Finished Jun 02 12:51:52 PM PDT 24
Peak memory 213712 kb
Host smart-0af71800-2d13-4e98-9c6a-3a10bcb842d1
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1231867986 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_
tl_access.1231867986
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.27262258
Short name T220
Test name
Test status
Simulation time 73080531715 ps
CPU time 196.04 seconds
Started Jun 02 12:51:43 PM PDT 24
Finished Jun 02 12:55:00 PM PDT 24
Peak memory 215388 kb
Host smart-cac74bf8-0b14-4c36-9c36-b095480c872f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27262258 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.27262258
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.3397277608
Short name T178
Test name
Test status
Simulation time 50611276 ps
CPU time 0.77 seconds
Started Jun 02 12:51:41 PM PDT 24
Finished Jun 02 12:51:43 PM PDT 24
Peak memory 204972 kb
Host smart-2e437914-4359-4983-9347-fd5ff8883a78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397277608 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.3397277608
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.1900034982
Short name T205
Test name
Test status
Simulation time 95572928586 ps
CPU time 205.75 seconds
Started Jun 02 12:51:41 PM PDT 24
Finished Jun 02 12:55:08 PM PDT 24
Peak memory 220896 kb
Host smart-0a649430-735b-44f3-b297-bd20f7c59e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900034982 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.1900034982
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.3755018652
Short name T208
Test name
Test status
Simulation time 30764649182 ps
CPU time 86.19 seconds
Started Jun 02 12:51:42 PM PDT 24
Finished Jun 02 12:53:08 PM PDT 24
Peak memory 213684 kb
Host smart-6143f19e-cd16-481d-bd94-475a5bb7d5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755018652 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.3755018652
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.3213091268
Short name T250
Test name
Test status
Simulation time 91618868125 ps
CPU time 148.92 seconds
Started Jun 02 12:51:40 PM PDT 24
Finished Jun 02 12:54:09 PM PDT 24
Peak memory 216952 kb
Host smart-1d68feed-63e0-444d-91d4-95245ed99306
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3213091268 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_
tl_access.3213091268
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.3701706067
Short name T244
Test name
Test status
Simulation time 64308232099 ps
CPU time 86.27 seconds
Started Jun 02 12:51:42 PM PDT 24
Finished Jun 02 12:53:09 PM PDT 24
Peak memory 205504 kb
Host smart-e5e38da8-1b15-4e27-8673-8fab6936c102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701706067 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.3701706067
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_stress_all.2932462390
Short name T140
Test name
Test status
Simulation time 12609158628 ps
CPU time 6.18 seconds
Started Jun 02 12:51:42 PM PDT 24
Finished Jun 02 12:51:49 PM PDT 24
Peak memory 205240 kb
Host smart-7f36fff8-7696-49e6-a153-a5cacb0132e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932462390 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.2932462390
Directory /workspace/14.rv_dm_stress_all/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.999389674
Short name T240
Test name
Test status
Simulation time 142238181 ps
CPU time 0.83 seconds
Started Jun 02 12:51:48 PM PDT 24
Finished Jun 02 12:51:49 PM PDT 24
Peak memory 205268 kb
Host smart-0035b7be-697d-4a4d-9e0f-d2adb2e1ace9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999389674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.999389674
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.2853057524
Short name T211
Test name
Test status
Simulation time 74278882298 ps
CPU time 67.74 seconds
Started Jun 02 12:51:47 PM PDT 24
Finished Jun 02 12:52:55 PM PDT 24
Peak memory 205424 kb
Host smart-7efe79c7-0f20-4a85-add2-9ddc214eef73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853057524 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.2853057524
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.1717381211
Short name T186
Test name
Test status
Simulation time 5627694542 ps
CPU time 9.21 seconds
Started Jun 02 12:51:47 PM PDT 24
Finished Jun 02 12:51:57 PM PDT 24
Peak memory 205420 kb
Host smart-5b7d6510-e2bb-4534-a23c-fe47c8c80425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717381211 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.1717381211
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.355643463
Short name T50
Test name
Test status
Simulation time 59681052011 ps
CPU time 24.65 seconds
Started Jun 02 12:51:48 PM PDT 24
Finished Jun 02 12:52:13 PM PDT 24
Peak memory 213884 kb
Host smart-f361c37e-57c6-4616-be92-b24a5eba845a
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=355643463 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_t
l_access.355643463
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.2224693807
Short name T233
Test name
Test status
Simulation time 37317583660 ps
CPU time 115.5 seconds
Started Jun 02 12:51:46 PM PDT 24
Finished Jun 02 12:53:42 PM PDT 24
Peak memory 205448 kb
Host smart-077ed0de-9e34-4998-a8f4-9891ec54912e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224693807 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.2224693807
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.1717072761
Short name T221
Test name
Test status
Simulation time 60453637 ps
CPU time 0.75 seconds
Started Jun 02 12:51:48 PM PDT 24
Finished Jun 02 12:51:50 PM PDT 24
Peak memory 204984 kb
Host smart-b5c2de84-abfc-4f62-bab5-213004346f8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717072761 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.1717072761
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.1467425144
Short name T252
Test name
Test status
Simulation time 83069399469 ps
CPU time 110.58 seconds
Started Jun 02 12:51:51 PM PDT 24
Finished Jun 02 12:53:41 PM PDT 24
Peak memory 221784 kb
Host smart-6a75219e-ee00-413b-ac7e-34ed04c6188b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467425144 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.1467425144
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.4039288185
Short name T232
Test name
Test status
Simulation time 15214016484 ps
CPU time 16.96 seconds
Started Jun 02 12:51:48 PM PDT 24
Finished Jun 02 12:52:06 PM PDT 24
Peak memory 213704 kb
Host smart-3e60679c-cf84-47b1-b10a-71af7f5e6a57
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4039288185 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_
tl_access.4039288185
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.1601427016
Short name T21
Test name
Test status
Simulation time 40008753741 ps
CPU time 36.95 seconds
Started Jun 02 12:51:49 PM PDT 24
Finished Jun 02 12:52:26 PM PDT 24
Peak memory 213628 kb
Host smart-485a3b89-dbdf-499f-a44e-94b65f8c3437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601427016 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.1601427016
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_stress_all.369562384
Short name T136
Test name
Test status
Simulation time 52025614438 ps
CPU time 32.77 seconds
Started Jun 02 12:51:48 PM PDT 24
Finished Jun 02 12:52:21 PM PDT 24
Peak memory 205340 kb
Host smart-b6ca1452-23e2-4cb9-a2f0-51496e5fe8f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369562384 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.369562384
Directory /workspace/16.rv_dm_stress_all/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.3989830327
Short name T156
Test name
Test status
Simulation time 131242429 ps
CPU time 0.7 seconds
Started Jun 02 12:51:49 PM PDT 24
Finished Jun 02 12:51:50 PM PDT 24
Peak memory 204984 kb
Host smart-9ede30fe-eaab-4ca8-bff6-9c923c5137a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989830327 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.3989830327
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.4055346759
Short name T251
Test name
Test status
Simulation time 105434616511 ps
CPU time 124.66 seconds
Started Jun 02 12:51:46 PM PDT 24
Finished Jun 02 12:53:51 PM PDT 24
Peak memory 218936 kb
Host smart-282ec308-57ad-435c-9193-94cd3bcd5a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055346759 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.4055346759
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.470554096
Short name T254
Test name
Test status
Simulation time 28488047841 ps
CPU time 80.75 seconds
Started Jun 02 12:51:48 PM PDT 24
Finished Jun 02 12:53:10 PM PDT 24
Peak memory 205440 kb
Host smart-50946d1b-246b-486f-b7a5-36a4ea799cc3
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=470554096 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_t
l_access.470554096
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.1370707821
Short name T226
Test name
Test status
Simulation time 22189411435 ps
CPU time 61.56 seconds
Started Jun 02 12:51:47 PM PDT 24
Finished Jun 02 12:52:49 PM PDT 24
Peak memory 221732 kb
Host smart-b3b96a72-3ecb-4cb3-828a-a258cb1f0fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370707821 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.1370707821
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.813804335
Short name T166
Test name
Test status
Simulation time 165037989 ps
CPU time 0.89 seconds
Started Jun 02 12:51:48 PM PDT 24
Finished Jun 02 12:51:49 PM PDT 24
Peak memory 205016 kb
Host smart-0e6305cc-0767-4ee0-b810-96a9fb90afa5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813804335 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.813804335
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.1668077301
Short name T197
Test name
Test status
Simulation time 78819575858 ps
CPU time 190.23 seconds
Started Jun 02 12:51:49 PM PDT 24
Finished Jun 02 12:55:00 PM PDT 24
Peak memory 214952 kb
Host smart-78810bb8-27ca-489f-9f60-1c3d9beab253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668077301 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.1668077301
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.2268619610
Short name T225
Test name
Test status
Simulation time 31460943752 ps
CPU time 52.37 seconds
Started Jun 02 12:51:47 PM PDT 24
Finished Jun 02 12:52:39 PM PDT 24
Peak memory 213688 kb
Host smart-48ede992-6da7-4ca7-b810-fe03b6c134bb
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2268619610 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_
tl_access.2268619610
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.695850814
Short name T242
Test name
Test status
Simulation time 25618770303 ps
CPU time 73.77 seconds
Started Jun 02 12:51:51 PM PDT 24
Finished Jun 02 12:53:05 PM PDT 24
Peak memory 205460 kb
Host smart-942511e4-b383-4d76-a4ab-8fe30253b21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695850814 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.695850814
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.1774023356
Short name T193
Test name
Test status
Simulation time 87247643 ps
CPU time 0.72 seconds
Started Jun 02 12:51:56 PM PDT 24
Finished Jun 02 12:51:57 PM PDT 24
Peak memory 204928 kb
Host smart-a2548ec5-14f6-444a-a276-2d00cf37c85f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774023356 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.1774023356
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.1309073913
Short name T13
Test name
Test status
Simulation time 32372839054 ps
CPU time 94.42 seconds
Started Jun 02 12:51:49 PM PDT 24
Finished Jun 02 12:53:24 PM PDT 24
Peak memory 213588 kb
Host smart-415f2d80-73f1-4454-b841-1222d3639453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309073913 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.1309073913
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.634363828
Short name T192
Test name
Test status
Simulation time 28936817826 ps
CPU time 96.67 seconds
Started Jun 02 12:51:46 PM PDT 24
Finished Jun 02 12:53:23 PM PDT 24
Peak memory 221800 kb
Host smart-600305d7-f383-4e28-b498-50005ce7630e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=634363828 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_t
l_access.634363828
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.3893284115
Short name T219
Test name
Test status
Simulation time 84097640466 ps
CPU time 59.64 seconds
Started Jun 02 12:51:46 PM PDT 24
Finished Jun 02 12:52:46 PM PDT 24
Peak memory 205784 kb
Host smart-ee4a7c48-91b3-4468-9ba1-cc9f994de73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893284115 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.3893284115
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.415480237
Short name T203
Test name
Test status
Simulation time 116837556 ps
CPU time 0.8 seconds
Started Jun 02 12:51:26 PM PDT 24
Finished Jun 02 12:51:27 PM PDT 24
Peak memory 204916 kb
Host smart-1fdd34c0-3ec8-4ff9-b88b-14fff0a9671e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415480237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.415480237
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.445441138
Short name T236
Test name
Test status
Simulation time 17990653969 ps
CPU time 17.12 seconds
Started Jun 02 12:51:34 PM PDT 24
Finished Jun 02 12:51:52 PM PDT 24
Peak memory 213616 kb
Host smart-85cd87f2-6064-41b9-bc0a-e36a94910bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445441138 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.445441138
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.2500960697
Short name T121
Test name
Test status
Simulation time 9375936399 ps
CPU time 29.32 seconds
Started Jun 02 12:51:32 PM PDT 24
Finished Jun 02 12:52:02 PM PDT 24
Peak memory 205404 kb
Host smart-29252f72-ff3f-4a40-9ef2-0f1f8cb0ed5a
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2500960697 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.2500960697
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.3655698372
Short name T45
Test name
Test status
Simulation time 341030472 ps
CPU time 1.68 seconds
Started Jun 02 12:51:27 PM PDT 24
Finished Jun 02 12:51:30 PM PDT 24
Peak memory 204768 kb
Host smart-01e2e844-f82a-4986-b37c-bd24d1ce4421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655698372 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.3655698372
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.1645933975
Short name T37
Test name
Test status
Simulation time 972112141 ps
CPU time 3.58 seconds
Started Jun 02 12:51:27 PM PDT 24
Finished Jun 02 12:51:31 PM PDT 24
Peak memory 229292 kb
Host smart-2f0e9d4c-4441-4606-a251-3103e5fbbb03
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645933975 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.1645933975
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all.3285143769
Short name T145
Test name
Test status
Simulation time 8829442088 ps
CPU time 24.55 seconds
Started Jun 02 12:51:28 PM PDT 24
Finished Jun 02 12:51:53 PM PDT 24
Peak memory 205228 kb
Host smart-5d3d4442-5799-4eef-9364-d28166440ccd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285143769 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.3285143769
Directory /workspace/2.rv_dm_stress_all/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.3767944188
Short name T64
Test name
Test status
Simulation time 126035621 ps
CPU time 0.87 seconds
Started Jun 02 12:51:53 PM PDT 24
Finished Jun 02 12:51:55 PM PDT 24
Peak memory 204912 kb
Host smart-07615d6b-c66f-4a02-a6b8-691a839dd30d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767944188 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.3767944188
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/20.rv_dm_stress_all.988790364
Short name T25
Test name
Test status
Simulation time 18517533150 ps
CPU time 25.1 seconds
Started Jun 02 12:51:57 PM PDT 24
Finished Jun 02 12:52:22 PM PDT 24
Peak memory 205224 kb
Host smart-a001f853-9f16-4a8c-8500-5040b199f09e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988790364 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.988790364
Directory /workspace/20.rv_dm_stress_all/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.3267204059
Short name T182
Test name
Test status
Simulation time 38683191 ps
CPU time 0.76 seconds
Started Jun 02 12:51:54 PM PDT 24
Finished Jun 02 12:51:55 PM PDT 24
Peak memory 204948 kb
Host smart-5c352fbb-4d80-46dd-b475-71c56f5af30d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267204059 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.3267204059
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.2310478579
Short name T194
Test name
Test status
Simulation time 151190081 ps
CPU time 0.74 seconds
Started Jun 02 12:51:53 PM PDT 24
Finished Jun 02 12:51:54 PM PDT 24
Peak memory 204992 kb
Host smart-216af630-383d-48c1-9be1-0535e710d1f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310478579 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.2310478579
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_stress_all.3429791660
Short name T10
Test name
Test status
Simulation time 26989315287 ps
CPU time 36.97 seconds
Started Jun 02 12:51:51 PM PDT 24
Finished Jun 02 12:52:29 PM PDT 24
Peak memory 216216 kb
Host smart-81f2df75-4bf3-4bc4-869f-d3f45c663e3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429791660 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.3429791660
Directory /workspace/22.rv_dm_stress_all/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.990935446
Short name T49
Test name
Test status
Simulation time 63684951 ps
CPU time 0.71 seconds
Started Jun 02 12:51:55 PM PDT 24
Finished Jun 02 12:51:56 PM PDT 24
Peak memory 204976 kb
Host smart-7da95f82-1d96-4d2d-b1ab-38ebb3d96d79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990935446 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.990935446
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.1167416520
Short name T164
Test name
Test status
Simulation time 32040087 ps
CPU time 0.76 seconds
Started Jun 02 12:51:55 PM PDT 24
Finished Jun 02 12:51:56 PM PDT 24
Peak memory 205020 kb
Host smart-5db25cda-b391-4706-9e1b-04ba7e8da0e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167416520 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.1167416520
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_stress_all.1014784167
Short name T139
Test name
Test status
Simulation time 25832903655 ps
CPU time 38.67 seconds
Started Jun 02 12:51:53 PM PDT 24
Finished Jun 02 12:52:32 PM PDT 24
Peak memory 205296 kb
Host smart-3dfc7835-0929-4c3d-a028-16466f090853
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014784167 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.1014784167
Directory /workspace/24.rv_dm_stress_all/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.404575970
Short name T66
Test name
Test status
Simulation time 66167104 ps
CPU time 0.85 seconds
Started Jun 02 12:51:58 PM PDT 24
Finished Jun 02 12:51:59 PM PDT 24
Peak memory 204912 kb
Host smart-ffe2253d-11d2-4ddc-9f6d-f109cf3088e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404575970 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.404575970
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_stress_all.1818297647
Short name T142
Test name
Test status
Simulation time 5995723149 ps
CPU time 16.18 seconds
Started Jun 02 12:51:53 PM PDT 24
Finished Jun 02 12:52:09 PM PDT 24
Peak memory 205320 kb
Host smart-ef002385-5f0e-451f-a01e-4f7f321e81fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818297647 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.1818297647
Directory /workspace/25.rv_dm_stress_all/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.3797599946
Short name T206
Test name
Test status
Simulation time 126038650 ps
CPU time 0.93 seconds
Started Jun 02 12:51:58 PM PDT 24
Finished Jun 02 12:51:59 PM PDT 24
Peak memory 204996 kb
Host smart-eb0a3f05-7689-45c6-9b22-53ac0c281e2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797599946 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.3797599946
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_stress_all.819361059
Short name T7
Test name
Test status
Simulation time 21277864096 ps
CPU time 55 seconds
Started Jun 02 12:51:58 PM PDT 24
Finished Jun 02 12:52:54 PM PDT 24
Peak memory 205276 kb
Host smart-b1933b4d-d7b0-456d-87a2-b774095ec77f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819361059 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.819361059
Directory /workspace/26.rv_dm_stress_all/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.1471973478
Short name T179
Test name
Test status
Simulation time 45789856 ps
CPU time 0.79 seconds
Started Jun 02 12:51:54 PM PDT 24
Finished Jun 02 12:51:55 PM PDT 24
Peak memory 204928 kb
Host smart-750bc2a8-a462-407c-b82f-4e0a818d7546
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471973478 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.1471973478
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_stress_all.2328433465
Short name T6
Test name
Test status
Simulation time 12053991402 ps
CPU time 10.34 seconds
Started Jun 02 12:51:52 PM PDT 24
Finished Jun 02 12:52:02 PM PDT 24
Peak memory 205336 kb
Host smart-84c27260-8796-456c-b893-d17bd0fb54b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328433465 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.2328433465
Directory /workspace/27.rv_dm_stress_all/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.2732150930
Short name T170
Test name
Test status
Simulation time 99819767 ps
CPU time 0.76 seconds
Started Jun 02 12:51:54 PM PDT 24
Finished Jun 02 12:51:55 PM PDT 24
Peak memory 204988 kb
Host smart-5d7fd55f-3de6-4be0-a9e9-649fb1f65a50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732150930 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.2732150930
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.3480968936
Short name T158
Test name
Test status
Simulation time 72132267 ps
CPU time 0.86 seconds
Started Jun 02 12:51:55 PM PDT 24
Finished Jun 02 12:51:56 PM PDT 24
Peak memory 204972 kb
Host smart-679b1a94-d6fd-4a10-a484-22b7223ad1ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480968936 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.3480968936
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.49903257
Short name T180
Test name
Test status
Simulation time 39760636 ps
CPU time 0.81 seconds
Started Jun 02 12:51:27 PM PDT 24
Finished Jun 02 12:51:29 PM PDT 24
Peak memory 204900 kb
Host smart-3e21c6ff-1f8f-45e9-9ed2-0e0cd33a8b93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49903257 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.49903257
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.633117085
Short name T16
Test name
Test status
Simulation time 39879247645 ps
CPU time 26.43 seconds
Started Jun 02 12:51:32 PM PDT 24
Finished Jun 02 12:51:59 PM PDT 24
Peak memory 205472 kb
Host smart-3d62438c-7dc4-4be6-8b2e-dd129ff8eb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633117085 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.633117085
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.1144966823
Short name T188
Test name
Test status
Simulation time 17061452188 ps
CPU time 45.38 seconds
Started Jun 02 12:51:29 PM PDT 24
Finished Jun 02 12:52:14 PM PDT 24
Peak memory 205244 kb
Host smart-2d9bf76d-ef66-4926-bd52-f17b391bf3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144966823 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.1144966823
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.119451373
Short name T200
Test name
Test status
Simulation time 22481106592 ps
CPU time 23.77 seconds
Started Jun 02 12:51:27 PM PDT 24
Finished Jun 02 12:51:51 PM PDT 24
Peak memory 213608 kb
Host smart-9d2fde8f-9e22-417a-95cb-f53e515830fa
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=119451373 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_tl
_access.119451373
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.2033660061
Short name T243
Test name
Test status
Simulation time 179874093 ps
CPU time 0.78 seconds
Started Jun 02 12:51:26 PM PDT 24
Finished Jun 02 12:51:27 PM PDT 24
Peak memory 204832 kb
Host smart-36ffa0e6-f8c7-494c-9301-18743c4ed9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033660061 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.2033660061
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.1133431333
Short name T234
Test name
Test status
Simulation time 16476542075 ps
CPU time 11.68 seconds
Started Jun 02 12:51:28 PM PDT 24
Finished Jun 02 12:51:40 PM PDT 24
Peak memory 213668 kb
Host smart-8b78a94c-93a0-4990-87b7-5d4dfde78283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133431333 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.1133431333
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.3516265479
Short name T51
Test name
Test status
Simulation time 667127593 ps
CPU time 1.76 seconds
Started Jun 02 12:51:25 PM PDT 24
Finished Jun 02 12:51:28 PM PDT 24
Peak memory 237132 kb
Host smart-e7cdac42-c18e-49e6-9193-847164f4e763
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516265479 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.3516265479
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.982709942
Short name T67
Test name
Test status
Simulation time 38671962 ps
CPU time 0.73 seconds
Started Jun 02 12:51:59 PM PDT 24
Finished Jun 02 12:52:01 PM PDT 24
Peak memory 205000 kb
Host smart-dfa10ef2-093c-4822-aa1a-daa1c84fd8c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982709942 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.982709942
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.3827221077
Short name T174
Test name
Test status
Simulation time 105782267 ps
CPU time 0.7 seconds
Started Jun 02 12:52:00 PM PDT 24
Finished Jun 02 12:52:02 PM PDT 24
Peak memory 204936 kb
Host smart-2b309da2-4db7-4573-9b75-4dc45e5c0c17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827221077 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.3827221077
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.3447685996
Short name T168
Test name
Test status
Simulation time 57720208 ps
CPU time 0.82 seconds
Started Jun 02 12:51:59 PM PDT 24
Finished Jun 02 12:52:01 PM PDT 24
Peak memory 204984 kb
Host smart-c95167d9-a2f1-40c9-a9f6-00f3fd7b50b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447685996 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.3447685996
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_stress_all.2605183692
Short name T63
Test name
Test status
Simulation time 33064329052 ps
CPU time 18.73 seconds
Started Jun 02 12:51:58 PM PDT 24
Finished Jun 02 12:52:18 PM PDT 24
Peak memory 205304 kb
Host smart-59163b85-dd54-42f7-a6d7-a4c1188d1b40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605183692 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.2605183692
Directory /workspace/32.rv_dm_stress_all/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.2473756277
Short name T74
Test name
Test status
Simulation time 61473181 ps
CPU time 0.89 seconds
Started Jun 02 12:52:00 PM PDT 24
Finished Jun 02 12:52:01 PM PDT 24
Peak memory 204976 kb
Host smart-b03a9a85-6a98-4844-aac7-d290eb456243
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473756277 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.2473756277
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.3374330888
Short name T162
Test name
Test status
Simulation time 190514116 ps
CPU time 0.82 seconds
Started Jun 02 12:52:01 PM PDT 24
Finished Jun 02 12:52:03 PM PDT 24
Peak memory 205020 kb
Host smart-f3e4978c-120f-4490-895a-02a2d9ef17f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374330888 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.3374330888
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_stress_all.998261416
Short name T42
Test name
Test status
Simulation time 3195864462 ps
CPU time 2.92 seconds
Started Jun 02 12:51:59 PM PDT 24
Finished Jun 02 12:52:03 PM PDT 24
Peak memory 205232 kb
Host smart-a1b2fcc8-b174-4b06-9e16-e29782f7cecd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998261416 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.998261416
Directory /workspace/34.rv_dm_stress_all/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.1808358759
Short name T257
Test name
Test status
Simulation time 72389694 ps
CPU time 0.77 seconds
Started Jun 02 12:51:59 PM PDT 24
Finished Jun 02 12:52:00 PM PDT 24
Peak memory 204944 kb
Host smart-4e089b57-7d8d-48d2-8b5a-2a1cbfd47b55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808358759 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.1808358759
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.1533429528
Short name T167
Test name
Test status
Simulation time 43331202 ps
CPU time 0.75 seconds
Started Jun 02 12:52:01 PM PDT 24
Finished Jun 02 12:52:03 PM PDT 24
Peak memory 205004 kb
Host smart-7803ff80-fdfd-4e3b-8b22-6e3d57edc3a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533429528 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.1533429528
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_stress_all.1396838641
Short name T120
Test name
Test status
Simulation time 29023705694 ps
CPU time 13.58 seconds
Started Jun 02 12:52:00 PM PDT 24
Finished Jun 02 12:52:15 PM PDT 24
Peak memory 213444 kb
Host smart-f430a45d-b258-4e42-aeb8-417f5fb3dd91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396838641 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.1396838641
Directory /workspace/36.rv_dm_stress_all/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.3011512718
Short name T181
Test name
Test status
Simulation time 160791094 ps
CPU time 0.92 seconds
Started Jun 02 12:51:59 PM PDT 24
Finished Jun 02 12:52:01 PM PDT 24
Peak memory 204952 kb
Host smart-3bec5a3e-d852-4d20-96d8-d8c443869067
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011512718 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.3011512718
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.2457500700
Short name T171
Test name
Test status
Simulation time 47213615 ps
CPU time 0.79 seconds
Started Jun 02 12:52:02 PM PDT 24
Finished Jun 02 12:52:04 PM PDT 24
Peak memory 204976 kb
Host smart-84e1f3d1-c09a-4120-8f76-e0718cd428ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457500700 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.2457500700
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.3248847897
Short name T114
Test name
Test status
Simulation time 59106470 ps
CPU time 0.88 seconds
Started Jun 02 12:52:02 PM PDT 24
Finished Jun 02 12:52:04 PM PDT 24
Peak memory 204980 kb
Host smart-d8a3e6ea-d21c-425b-af42-1673004855d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248847897 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.3248847897
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_stress_all.2495640285
Short name T154
Test name
Test status
Simulation time 6332703827 ps
CPU time 19.4 seconds
Started Jun 02 12:51:59 PM PDT 24
Finished Jun 02 12:52:19 PM PDT 24
Peak memory 213448 kb
Host smart-fbf70fed-c519-486f-8a69-269d96f14b12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495640285 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.2495640285
Directory /workspace/39.rv_dm_stress_all/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.1966047736
Short name T175
Test name
Test status
Simulation time 105817777 ps
CPU time 0.75 seconds
Started Jun 02 12:51:32 PM PDT 24
Finished Jun 02 12:51:34 PM PDT 24
Peak memory 204972 kb
Host smart-74cd0bc1-baae-402b-aaee-4a4b87bbaf7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966047736 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.1966047736
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.812240612
Short name T201
Test name
Test status
Simulation time 83432775142 ps
CPU time 79.35 seconds
Started Jun 02 12:51:27 PM PDT 24
Finished Jun 02 12:52:47 PM PDT 24
Peak memory 213724 kb
Host smart-575946a1-6013-4498-bc6a-96f834ec6034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812240612 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.812240612
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.3844416063
Short name T196
Test name
Test status
Simulation time 93918657978 ps
CPU time 141.63 seconds
Started Jun 02 12:51:27 PM PDT 24
Finished Jun 02 12:53:50 PM PDT 24
Peak memory 217608 kb
Host smart-8a902eaa-2ea8-4199-8f26-0aadd63098c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844416063 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.3844416063
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.3334095163
Short name T187
Test name
Test status
Simulation time 14007795948 ps
CPU time 40.68 seconds
Started Jun 02 12:51:32 PM PDT 24
Finished Jun 02 12:52:14 PM PDT 24
Peak memory 213620 kb
Host smart-d56d1493-4d88-43fc-9115-4c57b78d0a60
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3334095163 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.3334095163
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.2147634619
Short name T239
Test name
Test status
Simulation time 160832912 ps
CPU time 0.71 seconds
Started Jun 02 12:51:34 PM PDT 24
Finished Jun 02 12:51:35 PM PDT 24
Peak memory 204812 kb
Host smart-8b966777-0c97-4435-9613-503366d8b2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147634619 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.2147634619
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.3053516675
Short name T202
Test name
Test status
Simulation time 15874497461 ps
CPU time 52.89 seconds
Started Jun 02 12:51:29 PM PDT 24
Finished Jun 02 12:52:22 PM PDT 24
Peak memory 213728 kb
Host smart-30299bd0-f101-4872-adc2-eb2aa91a2e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053516675 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.3053516675
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_stress_all.3760408079
Short name T133
Test name
Test status
Simulation time 38942846164 ps
CPU time 114.29 seconds
Started Jun 02 12:51:29 PM PDT 24
Finished Jun 02 12:53:24 PM PDT 24
Peak memory 205332 kb
Host smart-5e549425-cab3-4c24-8971-f58dbd66b9ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760408079 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.3760408079
Directory /workspace/4.rv_dm_stress_all/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.3734881651
Short name T157
Test name
Test status
Simulation time 89448867 ps
CPU time 0.79 seconds
Started Jun 02 12:52:03 PM PDT 24
Finished Jun 02 12:52:04 PM PDT 24
Peak memory 205000 kb
Host smart-0767fff1-c6c8-4e2c-b3a2-944c26e9589d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734881651 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.3734881651
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.1663460802
Short name T172
Test name
Test status
Simulation time 57793749 ps
CPU time 0.68 seconds
Started Jun 02 12:52:08 PM PDT 24
Finished Jun 02 12:52:09 PM PDT 24
Peak memory 205012 kb
Host smart-776b7e54-7635-43ee-873a-aecdd36d50a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663460802 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.1663460802
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_stress_all.340390853
Short name T155
Test name
Test status
Simulation time 13203937121 ps
CPU time 12.03 seconds
Started Jun 02 12:52:01 PM PDT 24
Finished Jun 02 12:52:13 PM PDT 24
Peak memory 213484 kb
Host smart-648d9f88-4788-476d-9c72-df034b30b3c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340390853 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.340390853
Directory /workspace/41.rv_dm_stress_all/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.1902335905
Short name T218
Test name
Test status
Simulation time 37736743 ps
CPU time 0.77 seconds
Started Jun 02 12:52:06 PM PDT 24
Finished Jun 02 12:52:07 PM PDT 24
Peak memory 204992 kb
Host smart-21d64014-178b-4db8-81e7-583ca107b46b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902335905 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.1902335905
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.2026599181
Short name T159
Test name
Test status
Simulation time 111473628 ps
CPU time 0.73 seconds
Started Jun 02 12:52:09 PM PDT 24
Finished Jun 02 12:52:10 PM PDT 24
Peak memory 204968 kb
Host smart-07f2187d-74e9-4b1d-aa63-af29baee520a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026599181 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.2026599181
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_stress_all.3005934694
Short name T153
Test name
Test status
Simulation time 13175279271 ps
CPU time 21.1 seconds
Started Jun 02 12:52:08 PM PDT 24
Finished Jun 02 12:52:29 PM PDT 24
Peak memory 205324 kb
Host smart-4493d24a-7135-430e-8730-e9191eeec517
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005934694 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.3005934694
Directory /workspace/43.rv_dm_stress_all/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.469109007
Short name T176
Test name
Test status
Simulation time 45975280 ps
CPU time 0.82 seconds
Started Jun 02 12:52:06 PM PDT 24
Finished Jun 02 12:52:07 PM PDT 24
Peak memory 204932 kb
Host smart-1a15346b-7da3-45a2-b350-36bd63f09de3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469109007 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.469109007
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_stress_all.190108292
Short name T246
Test name
Test status
Simulation time 41839836339 ps
CPU time 24.33 seconds
Started Jun 02 12:52:10 PM PDT 24
Finished Jun 02 12:52:34 PM PDT 24
Peak memory 205280 kb
Host smart-755654ed-df63-4535-b9bb-6f7eb0f32775
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190108292 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.190108292
Directory /workspace/44.rv_dm_stress_all/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.1128495527
Short name T115
Test name
Test status
Simulation time 126552991 ps
CPU time 1.01 seconds
Started Jun 02 12:52:07 PM PDT 24
Finished Jun 02 12:52:08 PM PDT 24
Peak memory 204988 kb
Host smart-1dcd18ca-7a2f-4131-9145-997f64ff65e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128495527 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.1128495527
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_stress_all.2022612622
Short name T40
Test name
Test status
Simulation time 15673068878 ps
CPU time 37.24 seconds
Started Jun 02 12:52:07 PM PDT 24
Finished Jun 02 12:52:45 PM PDT 24
Peak memory 205316 kb
Host smart-7fea0eb2-28f2-49aa-b05d-a3919216c161
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022612622 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.2022612622
Directory /workspace/45.rv_dm_stress_all/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.3338103234
Short name T122
Test name
Test status
Simulation time 167809342 ps
CPU time 0.82 seconds
Started Jun 02 12:52:05 PM PDT 24
Finished Jun 02 12:52:06 PM PDT 24
Peak memory 205004 kb
Host smart-8cacd76c-46e1-446b-8e3b-6493aa89fdb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338103234 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.3338103234
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_stress_all.3753364230
Short name T134
Test name
Test status
Simulation time 25162429616 ps
CPU time 11.3 seconds
Started Jun 02 12:52:07 PM PDT 24
Finished Jun 02 12:52:19 PM PDT 24
Peak memory 213600 kb
Host smart-71041bc8-43e5-4a70-8d20-e31c9cf78b63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753364230 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.3753364230
Directory /workspace/46.rv_dm_stress_all/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.430754002
Short name T237
Test name
Test status
Simulation time 54176647 ps
CPU time 0.72 seconds
Started Jun 02 12:52:05 PM PDT 24
Finished Jun 02 12:52:06 PM PDT 24
Peak memory 204972 kb
Host smart-6d634176-ef85-4e41-97e0-53b718ca4e2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430754002 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.430754002
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.3556930897
Short name T65
Test name
Test status
Simulation time 79027982 ps
CPU time 0.74 seconds
Started Jun 02 12:52:09 PM PDT 24
Finished Jun 02 12:52:10 PM PDT 24
Peak memory 204916 kb
Host smart-da3c71a5-207f-459f-8670-cbe90f6375f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556930897 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.3556930897
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.1636852995
Short name T177
Test name
Test status
Simulation time 103008592 ps
CPU time 0.81 seconds
Started Jun 02 12:52:05 PM PDT 24
Finished Jun 02 12:52:06 PM PDT 24
Peak memory 204992 kb
Host smart-bf7cc720-4d17-413e-9802-007421c1c4ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636852995 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.1636852995
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.2067296203
Short name T235
Test name
Test status
Simulation time 8143150073 ps
CPU time 9.92 seconds
Started Jun 02 12:51:33 PM PDT 24
Finished Jun 02 12:51:43 PM PDT 24
Peak memory 213828 kb
Host smart-e13683fe-dc5f-4a71-a691-62b6eb9d1ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067296203 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.2067296203
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.994674118
Short name T210
Test name
Test status
Simulation time 19003898371 ps
CPU time 62.75 seconds
Started Jun 02 12:51:32 PM PDT 24
Finished Jun 02 12:52:35 PM PDT 24
Peak memory 213720 kb
Host smart-4957be8e-5d45-4885-9809-ab148064bda8
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=994674118 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_tl
_access.994674118
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.2586100455
Short name T260
Test name
Test status
Simulation time 19384744977 ps
CPU time 57.18 seconds
Started Jun 02 12:51:32 PM PDT 24
Finished Jun 02 12:52:30 PM PDT 24
Peak memory 213680 kb
Host smart-c3bf00d0-5bd7-4831-a55a-94cc40525c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586100455 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.2586100455
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_stress_all.2669824492
Short name T137
Test name
Test status
Simulation time 3974310173 ps
CPU time 6.18 seconds
Started Jun 02 12:51:33 PM PDT 24
Finished Jun 02 12:51:39 PM PDT 24
Peak memory 205624 kb
Host smart-80f53e21-4d75-439b-b8a7-93bf947b4c86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669824492 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.2669824492
Directory /workspace/5.rv_dm_stress_all/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.3524827469
Short name T43
Test name
Test status
Simulation time 60502488 ps
CPU time 0.77 seconds
Started Jun 02 12:51:35 PM PDT 24
Finished Jun 02 12:51:36 PM PDT 24
Peak memory 204924 kb
Host smart-b584c130-7aa8-4198-9f38-f3b17a2c06c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524827469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.3524827469
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.830514341
Short name T247
Test name
Test status
Simulation time 52274343794 ps
CPU time 27.68 seconds
Started Jun 02 12:51:34 PM PDT 24
Finished Jun 02 12:52:03 PM PDT 24
Peak memory 213700 kb
Host smart-60c0edbb-0d23-41cc-8207-348043622c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830514341 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.830514341
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.109626396
Short name T2
Test name
Test status
Simulation time 16514419696 ps
CPU time 9.6 seconds
Started Jun 02 12:51:34 PM PDT 24
Finished Jun 02 12:51:44 PM PDT 24
Peak memory 213760 kb
Host smart-a8fdbf41-786f-4f91-b93f-526f63d9b008
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=109626396 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_tl
_access.109626396
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.3459951386
Short name T214
Test name
Test status
Simulation time 6337410260 ps
CPU time 19.93 seconds
Started Jun 02 12:51:34 PM PDT 24
Finished Jun 02 12:51:55 PM PDT 24
Peak memory 205500 kb
Host smart-e479c240-1148-489e-94cf-788ec920c27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459951386 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.3459951386
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.3420491015
Short name T161
Test name
Test status
Simulation time 81111064 ps
CPU time 0.73 seconds
Started Jun 02 12:51:33 PM PDT 24
Finished Jun 02 12:51:35 PM PDT 24
Peak memory 205004 kb
Host smart-16f0fca5-37e2-4fa9-84c7-fb57fa72977f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420491015 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.3420491015
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.779465942
Short name T230
Test name
Test status
Simulation time 32199005403 ps
CPU time 30.81 seconds
Started Jun 02 12:51:32 PM PDT 24
Finished Jun 02 12:52:03 PM PDT 24
Peak memory 217264 kb
Host smart-609dd23f-9e4e-417b-b9db-f57f4845a1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779465942 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.779465942
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.3142619750
Short name T259
Test name
Test status
Simulation time 19808178772 ps
CPU time 21.71 seconds
Started Jun 02 12:51:38 PM PDT 24
Finished Jun 02 12:52:01 PM PDT 24
Peak memory 213664 kb
Host smart-84c66344-6bd7-4bdc-8d54-d3bf9384374e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142619750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.3142619750
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.2636082917
Short name T224
Test name
Test status
Simulation time 17300702000 ps
CPU time 27.46 seconds
Started Jun 02 12:51:33 PM PDT 24
Finished Jun 02 12:52:01 PM PDT 24
Peak memory 213604 kb
Host smart-2a23de44-2472-4fd3-9bf0-727968e1d324
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2636082917 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.2636082917
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.2233507914
Short name T184
Test name
Test status
Simulation time 99971589049 ps
CPU time 247.61 seconds
Started Jun 02 12:51:33 PM PDT 24
Finished Jun 02 12:55:42 PM PDT 24
Peak memory 208408 kb
Host smart-793203d2-404e-4679-8f6a-055ef1b34e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233507914 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.2233507914
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_stress_all.2435368196
Short name T5
Test name
Test status
Simulation time 16506532032 ps
CPU time 12.06 seconds
Started Jun 02 12:51:33 PM PDT 24
Finished Jun 02 12:51:46 PM PDT 24
Peak memory 213532 kb
Host smart-8ae3795a-0dd4-4126-ba98-28177325799f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435368196 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.2435368196
Directory /workspace/7.rv_dm_stress_all/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.2489694531
Short name T255
Test name
Test status
Simulation time 69316613063 ps
CPU time 76.06 seconds
Started Jun 02 12:51:32 PM PDT 24
Finished Jun 02 12:52:49 PM PDT 24
Peak memory 213672 kb
Host smart-6991d055-d3c5-4c26-8e25-1a9de5f122ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489694531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.2489694531
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.3139975311
Short name T217
Test name
Test status
Simulation time 47472365003 ps
CPU time 25.18 seconds
Started Jun 02 12:51:34 PM PDT 24
Finished Jun 02 12:52:00 PM PDT 24
Peak memory 213680 kb
Host smart-72badce6-6b53-4003-8401-ae7a48345cea
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3139975311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t
l_access.3139975311
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.718405459
Short name T223
Test name
Test status
Simulation time 26813172776 ps
CPU time 38.37 seconds
Started Jun 02 12:51:34 PM PDT 24
Finished Jun 02 12:52:13 PM PDT 24
Peak memory 205352 kb
Host smart-c262e049-87b2-4c71-b41f-5e77c1e07f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718405459 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.718405459
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_stress_all.3245620843
Short name T152
Test name
Test status
Simulation time 8229986499 ps
CPU time 20.23 seconds
Started Jun 02 12:51:33 PM PDT 24
Finished Jun 02 12:51:55 PM PDT 24
Peak memory 205364 kb
Host smart-4117fb07-1558-4ad5-bebb-f1f8f5b436a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245620843 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.3245620843
Directory /workspace/8.rv_dm_stress_all/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.972543383
Short name T58
Test name
Test status
Simulation time 120107464 ps
CPU time 0.76 seconds
Started Jun 02 12:51:40 PM PDT 24
Finished Jun 02 12:51:42 PM PDT 24
Peak memory 204952 kb
Host smart-2a9490d4-a431-4784-8f91-56a7d38e225d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972543383 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.972543383
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.3592858299
Short name T231
Test name
Test status
Simulation time 52976071411 ps
CPU time 153.99 seconds
Started Jun 02 12:51:42 PM PDT 24
Finished Jun 02 12:54:17 PM PDT 24
Peak memory 213664 kb
Host smart-f3bf9194-2daa-40b4-b353-6052aa0c294d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592858299 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.3592858299
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.2864508564
Short name T249
Test name
Test status
Simulation time 17514744917 ps
CPU time 17.98 seconds
Started Jun 02 12:51:41 PM PDT 24
Finished Jun 02 12:52:00 PM PDT 24
Peak memory 213644 kb
Host smart-4c0dd94f-b7f1-422c-babd-a3494e535e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864508564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.2864508564
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.874165550
Short name T189
Test name
Test status
Simulation time 107836051315 ps
CPU time 58.34 seconds
Started Jun 02 12:51:37 PM PDT 24
Finished Jun 02 12:52:36 PM PDT 24
Peak memory 218208 kb
Host smart-dda7b20a-2349-4e35-81cb-52f5da2e086d
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=874165550 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_tl
_access.874165550
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.624414313
Short name T228
Test name
Test status
Simulation time 37700746362 ps
CPU time 29.8 seconds
Started Jun 02 12:51:33 PM PDT 24
Finished Jun 02 12:52:03 PM PDT 24
Peak memory 205444 kb
Host smart-13e9de8d-b2f6-4a32-b93f-f88cabfe0b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624414313 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.624414313
Directory /workspace/9.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_stress_all.4200830971
Short name T135
Test name
Test status
Simulation time 42106557331 ps
CPU time 16.64 seconds
Started Jun 02 12:51:42 PM PDT 24
Finished Jun 02 12:51:59 PM PDT 24
Peak memory 213560 kb
Host smart-49662958-a6c3-4a50-b6e0-f2fe4afbaa1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200830971 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.4200830971
Directory /workspace/9.rv_dm_stress_all/latest
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