Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 228488 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 646465 1 T1 80 T6 35 T7 4



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 529196 1 T1 80 T6 20 T7 8
values[0x0] 169520 1 T6 28 T7 1 T9 16
values[0x1] 176237 1 T6 29 T9 23 T20 10



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 175383 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 699570 1 T1 80 T6 43 T7 5



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 3058 1 T9 1 T22 1 T13 1
valid_sources[0x01] 3582 1 T1 1 T125 1 T37 68
valid_sources[0x02] 3020 1 T13 1 T32 1 T46 41
valid_sources[0x03] 3647 1 T13 2 T34 11 T31 1
valid_sources[0x04] 3470 1 T13 1 T126 1 T127 1
valid_sources[0x05] 2788 1 T9 1 T128 3 T31 1
valid_sources[0x06] 2860 1 T1 2 T31 3 T38 1
valid_sources[0x07] 3725 1 T46 48 T47 148 T49 32
valid_sources[0x08] 3794 1 T13 1 T42 2 T129 1
valid_sources[0x09] 3419 1 T1 1 T31 2 T125 1
valid_sources[0x0a] 4142 1 T24 1 T13 3 T128 1
valid_sources[0x0b] 3521 1 T125 1 T32 1 T130 1
valid_sources[0x0c] 2845 1 T1 1 T126 1 T46 41
valid_sources[0x0d] 4838 1 T9 1 T22 1 T46 42
valid_sources[0x0e] 3138 1 T22 1 T128 1 T126 4
valid_sources[0x0f] 3209 1 T20 5 T13 1 T130 1
valid_sources[0x10] 3661 1 T6 77 T41 1 T128 1
valid_sources[0x11] 2941 1 T1 1 T31 1 T14 1
valid_sources[0x12] 3210 1 T1 1 T125 1 T33 1
valid_sources[0x13] 3030 1 T9 1 T20 15 T22 1
valid_sources[0x14] 2917 1 T1 1 T13 4 T128 1
valid_sources[0x15] 3270 1 T9 1 T13 1 T46 52
valid_sources[0x16] 3402 1 T1 1 T41 1 T128 1
valid_sources[0x17] 3537 1 T1 2 T8 9 T41 1
valid_sources[0x18] 3561 1 T9 1 T41 1 T13 2
valid_sources[0x19] 3068 1 T8 2 T22 2 T13 1
valid_sources[0x1a] 3117 1 T13 1 T46 51 T49 31
valid_sources[0x1b] 3425 1 T23 7 T41 1 T13 1
valid_sources[0x1c] 3035 1 T13 1 T131 1 T46 50
valid_sources[0x1d] 3846 1 T132 16 T133 4 T38 1
valid_sources[0x1e] 2932 1 T41 1 T46 46 T49 23
valid_sources[0x1f] 3478 1 T1 1 T13 1 T38 1
valid_sources[0x20] 2907 1 T9 1 T13 3 T134 1
valid_sources[0x21] 3070 1 T1 1 T13 1 T128 1
valid_sources[0x22] 3206 1 T22 1 T109 1 T13 2
valid_sources[0x23] 3205 1 T1 1 T41 1 T13 1
valid_sources[0x24] 4485 1 T13 1 T14 1 T38 2
valid_sources[0x25] 3139 1 T41 1 T38 1 T127 2
valid_sources[0x26] 4207 1 T125 1 T134 1 T46 45
valid_sources[0x27] 3361 1 T22 1 T13 1 T14 1
valid_sources[0x28] 3096 1 T13 1 T128 1 T133 5
valid_sources[0x29] 4107 1 T135 1 T31 3 T14 1
valid_sources[0x2a] 3024 1 T1 1 T109 1 T41 1
valid_sources[0x2b] 3072 1 T22 1 T109 1 T128 2
valid_sources[0x2c] 3335 1 T128 1 T125 2 T127 3
valid_sources[0x2d] 3607 1 T41 1 T13 1 T42 1
valid_sources[0x2e] 2876 1 T20 1 T14 2 T125 1
valid_sources[0x2f] 3289 1 T1 2 T13 1 T31 2
valid_sources[0x30] 3331 1 T9 1 T31 1 T127 1
valid_sources[0x31] 3616 1 T9 2 T13 1 T130 1
valid_sources[0x32] 3617 1 T9 1 T22 1 T109 2
valid_sources[0x33] 2806 1 T13 1 T127 2 T46 43
valid_sources[0x34] 3575 1 T9 1 T14 1 T46 34
valid_sources[0x35] 3551 1 T109 6 T42 1 T31 1
valid_sources[0x36] 2579 1 T1 1 T41 1 T127 1
valid_sources[0x37] 4063 1 T1 1 T126 1 T46 58
valid_sources[0x38] 3862 1 T136 9 T31 2 T126 2
valid_sources[0x39] 3216 1 T109 2 T41 1 T128 1
valid_sources[0x3a] 2764 1 T13 1 T46 58 T49 23
valid_sources[0x3b] 3672 1 T137 1 T38 1 T46 44
valid_sources[0x3c] 3563 1 T13 4 T31 1 T46 37
valid_sources[0x3d] 3319 1 T41 1 T13 1 T128 1
valid_sources[0x3e] 3376 1 T1 1 T13 1 T126 1
valid_sources[0x3f] 2862 1 T13 1 T127 2 T46 52
valid_sources[0x40] 3281 1 T1 1 T130 1 T126 7
valid_sources[0x41] 3327 1 T13 1 T31 1 T39 2
valid_sources[0x42] 3790 1 T1 1 T9 1 T41 1
valid_sources[0x43] 3213 1 T39 1 T133 7 T46 46
valid_sources[0x44] 3410 1 T1 1 T13 1 T31 1
valid_sources[0x45] 2919 1 T33 1 T38 1 T127 2
valid_sources[0x46] 3414 1 T9 2 T13 1 T31 1
valid_sources[0x47] 3149 1 T109 1 T41 1 T13 1
valid_sources[0x48] 3489 1 T22 3 T13 2 T31 1
valid_sources[0x49] 3216 1 T13 1 T31 1 T46 35
valid_sources[0x4a] 3002 1 T24 1 T41 1 T13 2
valid_sources[0x4b] 2771 1 T1 1 T41 1 T31 1
valid_sources[0x4c] 2640 1 T1 2 T13 2 T128 2
valid_sources[0x4d] 3505 1 T22 1 T46 45 T49 22
valid_sources[0x4e] 3246 1 T1 1 T9 1 T13 1
valid_sources[0x4f] 3143 1 T1 1 T10 76 T41 1
valid_sources[0x50] 3462 1 T9 2 T22 1 T13 1
valid_sources[0x51] 3680 1 T22 1 T41 1 T17 1
valid_sources[0x52] 3161 1 T134 1 T46 61 T49 29
valid_sources[0x53] 3502 1 T13 1 T14 1 T125 1
valid_sources[0x54] 3824 1 T128 1 T39 2 T46 50
valid_sources[0x55] 3251 1 T13 1 T128 1 T38 1
valid_sources[0x56] 3465 1 T13 1 T31 1 T14 1
valid_sources[0x57] 2844 1 T13 1 T134 1 T46 38
valid_sources[0x58] 3529 1 T1 1 T13 1 T128 1
valid_sources[0x59] 3636 1 T13 1 T128 3 T31 1
valid_sources[0x5a] 3363 1 T23 1 T22 1 T41 1
valid_sources[0x5b] 3829 1 T1 1 T8 3 T22 1
valid_sources[0x5c] 2981 1 T23 1 T13 2 T42 2
valid_sources[0x5d] 2876 1 T13 1 T128 1 T46 46
valid_sources[0x5e] 3624 1 T128 1 T125 1 T46 37
valid_sources[0x5f] 3182 1 T22 1 T41 1 T13 1
valid_sources[0x60] 2986 1 T22 1 T13 1 T128 2
valid_sources[0x61] 3197 1 T24 1 T130 1 T134 1
valid_sources[0x62] 3137 1 T1 1 T133 6 T38 1
valid_sources[0x63] 3545 1 T138 38 T38 1 T134 2
valid_sources[0x64] 3117 1 T22 1 T13 3 T31 1
valid_sources[0x65] 3117 1 T1 1 T109 3 T41 1
valid_sources[0x66] 3456 1 T1 2 T13 3 T128 1
valid_sources[0x67] 3360 1 T22 1 T130 4 T126 1
valid_sources[0x68] 3535 1 T13 3 T128 1 T31 1
valid_sources[0x69] 3083 1 T20 5 T13 1 T14 1
valid_sources[0x6a] 3088 1 T22 1 T109 1 T13 1
valid_sources[0x6b] 3095 1 T22 1 T46 64 T49 16
valid_sources[0x6c] 3388 1 T41 1 T128 1 T31 1
valid_sources[0x6d] 3217 1 T13 1 T14 1 T125 1
valid_sources[0x6e] 3756 1 T1 1 T109 2 T13 1
valid_sources[0x6f] 3116 1 T9 1 T139 1 T46 54
valid_sources[0x70] 3262 1 T13 1 T128 1 T31 2
valid_sources[0x71] 2786 1 T127 2 T46 51 T49 18
valid_sources[0x72] 3609 1 T31 1 T38 2 T139 1
valid_sources[0x73] 4017 1 T128 1 T129 1 T127 3
valid_sources[0x74] 3018 1 T9 3 T41 2 T31 1
valid_sources[0x75] 3049 1 T1 1 T13 1 T14 1
valid_sources[0x76] 3057 1 T61 1 T24 3 T41 1
valid_sources[0x77] 3244 1 T13 1 T126 3 T127 1
valid_sources[0x78] 4111 1 T13 1 T39 2 T126 1
valid_sources[0x79] 3387 1 T1 1 T9 1 T128 1
valid_sources[0x7a] 5051 1 T13 1 T35 10 T38 1
valid_sources[0x7b] 3639 1 T9 1 T13 1 T127 1
valid_sources[0x7c] 2990 1 T38 1 T127 2 T139 1
valid_sources[0x7d] 3445 1 T128 1 T31 1 T127 2
valid_sources[0x7e] 3248 1 T1 1 T13 1 T14 1
valid_sources[0x7f] 3358 1 T22 1 T41 1 T31 1
valid_sources[0x80] 3801 1 T1 1 T41 1 T126 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 312584 1 T1 80 T6 11 T7 4
values[0x0] all_enables biggest_size 166944 1 T6 13 T9 4 T20 10
values[0x1] all_enables biggest_size 166937 1 T6 11 T9 7 T20 10


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 5657 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 23606 1 T3 2 T26 3 T27 1



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 10949 1 T46 69 T47 36 T49 30
values[0x0] 9038 1 T3 3 T26 2 T27 3
values[0x1] 9276 1 T3 3 T26 4 T27 6



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 4299 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 24964 1 T3 4 T26 3 T27 1



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 184 1 T140 6 T141 1 T142 16
valid_sources[0x01] 98 1 T50 1 T63 1 T70 5
valid_sources[0x02] 82 1 T70 5 T75 4 T59 2
valid_sources[0x03] 72 1 T49 3 T70 2 T48 1
valid_sources[0x04] 98 1 T66 1 T48 3 T75 6
valid_sources[0x05] 79 1 T143 1 T70 2 T56 1
valid_sources[0x06] 105 1 T70 1 T56 1 T58 1
valid_sources[0x07] 85 1 T47 2 T70 4 T56 2
valid_sources[0x08] 109 1 T27 2 T143 1 T70 3
valid_sources[0x09] 177 1 T66 2 T144 1 T70 3
valid_sources[0x0a] 119 1 T70 2 T56 5 T58 1
valid_sources[0x0b] 90 1 T49 1 T70 2 T56 2
valid_sources[0x0c] 150 1 T75 5 T77 1 T59 1
valid_sources[0x0d] 122 1 T70 2 T48 2 T56 1
valid_sources[0x0e] 141 1 T46 12 T70 2 T73 17
valid_sources[0x0f] 107 1 T143 1 T46 3 T70 1
valid_sources[0x10] 155 1 T63 1 T70 2 T56 2
valid_sources[0x11] 164 1 T47 1 T49 5 T56 2
valid_sources[0x12] 174 1 T143 1 T69 6 T70 2
valid_sources[0x13] 91 1 T50 1 T49 1 T56 1
valid_sources[0x14] 115 1 T56 2 T75 4 T59 3
valid_sources[0x15] 51 1 T56 1 T58 1 T75 2
valid_sources[0x16] 70 1 T70 2 T75 4 T59 4
valid_sources[0x17] 218 1 T144 1 T70 4 T75 5
valid_sources[0x18] 166 1 T49 1 T75 4 T60 78
valid_sources[0x19] 159 1 T49 1 T70 2 T58 1
valid_sources[0x1a] 102 1 T46 3 T70 3 T56 3
valid_sources[0x1b] 82 1 T107 15 T145 3 T70 3
valid_sources[0x1c] 138 1 T56 2 T75 10 T67 2
valid_sources[0x1d] 119 1 T141 1 T70 2 T56 2
valid_sources[0x1e] 88 1 T70 3 T56 2 T75 1
valid_sources[0x1f] 99 1 T46 2 T70 1 T48 3
valid_sources[0x20] 121 1 T48 1 T56 2 T75 10
valid_sources[0x21] 59 1 T28 2 T47 3 T70 3
valid_sources[0x22] 88 1 T146 2 T145 2 T70 2
valid_sources[0x23] 180 1 T143 2 T70 3 T48 5
valid_sources[0x24] 70 1 T27 1 T49 1 T70 4
valid_sources[0x25] 118 1 T147 1 T148 1 T149 2
valid_sources[0x26] 50 1 T70 2 T56 7 T75 3
valid_sources[0x27] 189 1 T144 1 T150 1 T47 2
valid_sources[0x28] 64 1 T70 2 T75 3 T59 1
valid_sources[0x29] 87 1 T26 1 T66 3 T70 2
valid_sources[0x2a] 112 1 T70 2 T48 1 T58 4
valid_sources[0x2b] 168 1 T70 2 T56 3 T58 2
valid_sources[0x2c] 118 1 T62 1 T56 1 T75 4
valid_sources[0x2d] 93 1 T49 2 T48 2 T75 3
valid_sources[0x2e] 127 1 T28 1 T151 1 T70 4
valid_sources[0x2f] 95 1 T152 1 T141 1 T70 4
valid_sources[0x30] 94 1 T70 3 T56 2 T75 1
valid_sources[0x31] 73 1 T144 1 T147 1 T70 1
valid_sources[0x32] 207 1 T153 1 T70 1 T58 1
valid_sources[0x33] 74 1 T70 1 T56 4 T75 2
valid_sources[0x34] 92 1 T56 6 T58 1 T75 3
valid_sources[0x35] 215 1 T70 3 T48 4 T56 2
valid_sources[0x36] 58 1 T150 2 T70 2 T56 1
valid_sources[0x37] 114 1 T154 7 T46 3 T70 2
valid_sources[0x38] 156 1 T70 4 T56 1 T75 6
valid_sources[0x39] 114 1 T155 3 T70 4 T48 2
valid_sources[0x3a] 78 1 T156 3 T70 2 T56 4
valid_sources[0x3b] 188 1 T140 4 T157 3 T75 9
valid_sources[0x3c] 83 1 T47 9 T70 3 T56 2
valid_sources[0x3d] 103 1 T153 1 T150 1 T46 2
valid_sources[0x3e] 90 1 T70 2 T58 2 T75 7
valid_sources[0x3f] 76 1 T47 3 T70 6 T56 1
valid_sources[0x40] 169 1 T156 3 T70 6 T48 4
valid_sources[0x41] 83 1 T62 6 T70 3 T75 6
valid_sources[0x42] 130 1 T70 9 T48 2 T75 9
valid_sources[0x43] 124 1 T158 3 T159 1 T70 4
valid_sources[0x44] 88 1 T70 2 T56 2 T57 4
valid_sources[0x45] 107 1 T153 1 T46 3 T47 8
valid_sources[0x46] 74 1 T143 1 T70 4 T58 1
valid_sources[0x47] 220 1 T63 1 T70 1 T71 1
valid_sources[0x48] 76 1 T70 2 T71 2 T56 1
valid_sources[0x49] 122 1 T147 1 T70 1 T75 3
valid_sources[0x4a] 257 1 T150 1 T160 22 T47 1
valid_sources[0x4b] 89 1 T46 1 T70 3 T56 3
valid_sources[0x4c] 167 1 T151 1 T46 3 T70 1
valid_sources[0x4d] 167 1 T161 6 T70 3 T48 1
valid_sources[0x4e] 105 1 T162 4 T70 1 T71 1
valid_sources[0x4f] 118 1 T150 2 T70 1 T48 2
valid_sources[0x50] 57 1 T70 1 T75 5 T59 1
valid_sources[0x51] 98 1 T163 1 T164 11 T141 1
valid_sources[0x52] 159 1 T165 1 T70 1 T58 1
valid_sources[0x53] 104 1 T50 2 T49 1 T70 1
valid_sources[0x54] 232 1 T70 6 T56 3 T75 4
valid_sources[0x55] 90 1 T46 3 T70 3 T56 1
valid_sources[0x56] 162 1 T163 1 T166 5 T143 2
valid_sources[0x57] 102 1 T167 3 T70 2 T48 5
valid_sources[0x58] 92 1 T70 4 T56 1 T58 2
valid_sources[0x59] 89 1 T49 1 T70 2 T48 3
valid_sources[0x5a] 144 1 T70 3 T56 2 T58 1
valid_sources[0x5b] 103 1 T148 1 T70 1 T73 5
valid_sources[0x5c] 69 1 T155 4 T46 3 T70 1
valid_sources[0x5d] 115 1 T168 10 T70 1 T75 5
valid_sources[0x5e] 118 1 T163 1 T56 1 T58 1
valid_sources[0x5f] 133 1 T70 4 T58 1 T75 7
valid_sources[0x60] 80 1 T70 2 T56 1 T58 1
valid_sources[0x61] 169 1 T70 4 T56 1 T57 1
valid_sources[0x62] 226 1 T66 2 T70 3 T56 1
valid_sources[0x63] 109 1 T70 2 T48 1 T75 8
valid_sources[0x64] 92 1 T143 2 T150 2 T70 2
valid_sources[0x65] 149 1 T70 2 T48 1 T56 3
valid_sources[0x66] 162 1 T70 1 T48 1 T75 5
valid_sources[0x67] 100 1 T58 1 T75 2 T59 2
valid_sources[0x68] 92 1 T143 1 T70 2 T48 1
valid_sources[0x69] 111 1 T151 1 T141 2 T70 1
valid_sources[0x6a] 91 1 T70 3 T56 5 T58 1
valid_sources[0x6b] 92 1 T148 1 T70 2 T75 3
valid_sources[0x6c] 117 1 T66 5 T169 15 T70 2
valid_sources[0x6d] 230 1 T46 3 T70 3 T75 1
valid_sources[0x6e] 68 1 T49 2 T70 1 T75 3
valid_sources[0x6f] 96 1 T46 3 T47 6 T70 5
valid_sources[0x70] 132 1 T70 2 T48 1 T56 2
valid_sources[0x71] 93 1 T63 1 T70 2 T56 1
valid_sources[0x72] 114 1 T153 1 T70 4 T74 7
valid_sources[0x73] 100 1 T147 2 T70 2 T48 1
valid_sources[0x74] 162 1 T66 1 T70 1 T48 1
valid_sources[0x75] 68 1 T70 1 T58 1 T75 7
valid_sources[0x76] 226 1 T27 1 T70 4 T75 7
valid_sources[0x77] 89 1 T151 1 T48 3 T75 8
valid_sources[0x78] 75 1 T47 7 T49 1 T70 1
valid_sources[0x79] 141 1 T170 8 T162 4 T49 1
valid_sources[0x7a] 76 1 T70 5 T56 1 T75 7
valid_sources[0x7b] 114 1 T26 1 T165 2 T70 2
valid_sources[0x7c] 119 1 T163 1 T70 5 T75 5
valid_sources[0x7d] 141 1 T65 11 T46 1 T70 2
valid_sources[0x7e] 85 1 T48 1 T71 1 T57 11
valid_sources[0x7f] 131 1 T26 1 T70 1 T56 4
valid_sources[0x80] 306 1 T171 3 T49 2 T70 2



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 7735 1 T46 19 T47 15 T49 30
values[0x0] all_enables biggest_size 8128 1 T3 2 T26 2 T28 2
values[0x1] all_enables biggest_size 7743 1 T26 1 T27 1 T62 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%