Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	282187	1		T6	42		T7	5		T9	33
full_word	648661	1		T1	80		T6	35		T7	4

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	930518	1		T1	80		T6	77		T7	9
auto[TlIntgErrCmd]	109	1		T46	4		T47	3		T48	5
auto[TlIntgErrData]	103	1		T46	13		T47	3		T48	7
auto[TlIntgErrBoth]	118	1		T46	3		T47	4		T48	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	531704	1		T1	80		T6	20		T7	8
auto[1]	399144	1		T6	57		T7	1		T9	39

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	218729	1		T6	9		T7	4		T9	5
auto[TlIntgErrNone]	partial	auto[1]	63156	1		T6	33		T7	1		T9	28
auto[TlIntgErrNone]	full_word	auto[0]	312823	1		T1	80		T6	11		T7	4
auto[TlIntgErrNone]	full_word	auto[1]	335810	1		T6	24		T9	11		T20	20
auto[TlIntgErrCmd]	partial	auto[0]	42	1		T46	1		T47	3		T48	3
auto[TlIntgErrCmd]	partial	auto[1]	55	1		T46	3		T48	1		T67	6
auto[TlIntgErrCmd]	full_word	auto[0]	6	1		T117	1		T118	1		T119	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1		T48	1		T114	1		T120	2
auto[TlIntgErrData]	partial	auto[0]	50	1		T46	5		T47	2		T48	2
auto[TlIntgErrData]	partial	auto[1]	45	1		T46	7		T47	1		T48	4
auto[TlIntgErrData]	full_word	auto[0]	5	1		T46	1		T67	1		T121	2
auto[TlIntgErrData]	full_word	auto[1]	3	1		T48	1		T110	1		T121	1
auto[TlIntgErrBoth]	partial	auto[0]	46	1		T46	2		T48	4		T67	2
auto[TlIntgErrBoth]	partial	auto[1]	64	1		T47	4		T48	3		T67	5
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T46	1		T110	1		T122	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T48	1		T110	1		T120	1