Module Definition
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Module : rv_dm_regs_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.rv_dm_regs_csr_assert 100.00 100.00



Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
84.90 96.97 55.32 84.72 100.00 87.50 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : rv_dm_regs_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 138276581 20599 0 0
late_debug_enable_rd_A 138276581 2073 0 0
late_debug_enable_regwen_rd_A 138276581 2155 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 138276581 20599 0 0
T46 127821 4 0 0
T47 113881 3 0 0
T48 47793 8 0 0
T56 7542 495 0 0
T57 9663 9 0 0
T58 13604 30 0 0
T59 10438 675 0 0
T60 6509 612 0 0
T67 60707 4 0 0
T68 14706 97 0 0

late_debug_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 138276581 2073 0 0
T44 279547 179 0 0
T46 127821 73 0 0
T49 41513 22 0 0
T72 15723 1 0 0
T73 40020 20 0 0
T77 21689 32 0 0
T92 39780 4 0 0
T110 105635 51 0 0
T111 73764 9 0 0
T112 131081 185 0 0

late_debug_enable_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 138276581 2155 0 0
T44 279547 95 0 0
T46 127821 71 0 0
T49 41513 54 0 0
T72 15723 12 0 0
T73 40020 23 0 0
T77 21689 25 0 0
T92 39780 10 0 0
T110 105635 88 0 0
T111 73764 13 0 0
T112 131081 204 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%