SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
84.90 | 96.97 | 55.32 | 84.72 | 100.00 | 87.50 | dut |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 4 | 4 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 200 | 200 | 0 | 0 |
OutputsKnown_A | 57450698 | 57416228 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 57450698 | 57414659 | 0 | 600 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 200 | 200 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 57450698 | 57416228 | 0 | 0 |
T1 | 2403 | 2346 | 0 | 0 |
T2 | 25264 | 23858 | 0 | 0 |
T3 | 6544 | 6468 | 0 | 0 |
T4 | 34450 | 33737 | 0 | 0 |
T5 | 52629 | 52568 | 0 | 0 |
T11 | 16316 | 16261 | 0 | 0 |
T12 | 42973 | 42916 | 0 | 0 |
T26 | 1781 | 1724 | 0 | 0 |
T27 | 5434 | 5360 | 0 | 0 |
T28 | 2272 | 2219 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 57450698 | 57414659 | 0 | 600 |
T1 | 2403 | 2343 | 0 | 3 |
T2 | 25264 | 23795 | 0 | 3 |
T3 | 6544 | 6465 | 0 | 3 |
T4 | 34450 | 33704 | 0 | 3 |
T5 | 52629 | 52565 | 0 | 3 |
T11 | 16316 | 16258 | 0 | 3 |
T12 | 42973 | 42913 | 0 | 3 |
T26 | 1781 | 1721 | 0 | 3 |
T27 | 5434 | 5357 | 0 | 3 |
T28 | 2272 | 2216 | 0 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |