Line Coverage for Module :
prim_generic_clock_mux2
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Module :
prim_generic_clock_mux2
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Module :
prim_generic_clock_mux2
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
9903768 |
9902532 |
0 |
0 |
selKnown1 |
64198173 |
64196937 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9903768 |
9902532 |
0 |
0 |
T1 |
216 |
214 |
0 |
0 |
T2 |
5590 |
5586 |
0 |
0 |
T3 |
366 |
362 |
0 |
0 |
T4 |
2880 |
2876 |
0 |
0 |
T5 |
24134 |
24130 |
0 |
0 |
T6 |
0 |
12 |
0 |
0 |
T9 |
0 |
10 |
0 |
0 |
T10 |
0 |
26 |
0 |
0 |
T11 |
2518 |
2514 |
0 |
0 |
T12 |
5190 |
5186 |
0 |
0 |
T15 |
14 |
12 |
0 |
0 |
T16 |
0 |
12 |
0 |
0 |
T18 |
0 |
6 |
0 |
0 |
T25 |
0 |
10 |
0 |
0 |
T26 |
222 |
218 |
0 |
0 |
T27 |
222 |
218 |
0 |
0 |
T28 |
226 |
222 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
64198173 |
64196937 |
0 |
0 |
T1 |
2511 |
2509 |
0 |
0 |
T2 |
28080 |
28076 |
0 |
0 |
T3 |
6728 |
6724 |
0 |
0 |
T4 |
35901 |
35897 |
0 |
0 |
T5 |
64697 |
64693 |
0 |
0 |
T6 |
0 |
6 |
0 |
0 |
T9 |
0 |
10 |
0 |
0 |
T10 |
0 |
6 |
0 |
0 |
T11 |
17576 |
17572 |
0 |
0 |
T12 |
45563 |
45559 |
0 |
0 |
T15 |
14 |
12 |
0 |
0 |
T16 |
0 |
12 |
0 |
0 |
T18 |
0 |
6 |
0 |
0 |
T23 |
0 |
10 |
0 |
0 |
T25 |
0 |
8 |
0 |
0 |
T26 |
1893 |
1889 |
0 |
0 |
T27 |
5546 |
5542 |
0 |
0 |
T28 |
2386 |
2382 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
3155953 |
3155753 |
0 |
0 |
selKnown1 |
57450698 |
57450498 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3155953 |
3155753 |
0 |
0 |
T1 |
108 |
107 |
0 |
0 |
T2 |
2774 |
2773 |
0 |
0 |
T3 |
182 |
181 |
0 |
0 |
T4 |
1429 |
1428 |
0 |
0 |
T5 |
12066 |
12065 |
0 |
0 |
T11 |
1258 |
1257 |
0 |
0 |
T12 |
2588 |
2587 |
0 |
0 |
T26 |
110 |
109 |
0 |
0 |
T27 |
110 |
109 |
0 |
0 |
T28 |
112 |
111 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
57450698 |
57450498 |
0 |
0 |
T1 |
2403 |
2402 |
0 |
0 |
T2 |
25264 |
25263 |
0 |
0 |
T3 |
6544 |
6543 |
0 |
0 |
T4 |
34450 |
34449 |
0 |
0 |
T5 |
52629 |
52628 |
0 |
0 |
T11 |
16316 |
16315 |
0 |
0 |
T12 |
42973 |
42972 |
0 |
0 |
T26 |
1781 |
1780 |
0 |
0 |
T27 |
5434 |
5433 |
0 |
0 |
T28 |
2272 |
2271 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
613 |
413 |
0 |
0 |
T2 |
21 |
20 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
11 |
10 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
0 |
3 |
0 |
0 |
T9 |
0 |
5 |
0 |
0 |
T10 |
0 |
13 |
0 |
0 |
T11 |
1 |
0 |
0 |
0 |
T12 |
7 |
6 |
0 |
0 |
T15 |
7 |
6 |
0 |
0 |
T16 |
0 |
6 |
0 |
0 |
T18 |
0 |
3 |
0 |
0 |
T25 |
0 |
4 |
0 |
0 |
T26 |
1 |
0 |
0 |
0 |
T27 |
1 |
0 |
0 |
0 |
T28 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
523 |
323 |
0 |
0 |
T2 |
21 |
20 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
11 |
10 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
0 |
3 |
0 |
0 |
T9 |
0 |
5 |
0 |
0 |
T10 |
0 |
3 |
0 |
0 |
T11 |
1 |
0 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T15 |
7 |
6 |
0 |
0 |
T16 |
0 |
6 |
0 |
0 |
T18 |
0 |
3 |
0 |
0 |
T23 |
0 |
5 |
0 |
0 |
T25 |
0 |
4 |
0 |
0 |
T26 |
1 |
0 |
0 |
0 |
T27 |
1 |
0 |
0 |
0 |
T28 |
1 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
6745313 |
6744895 |
0 |
0 |
selKnown1 |
6745313 |
6744895 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6745313 |
6744895 |
0 |
0 |
T1 |
108 |
107 |
0 |
0 |
T2 |
2774 |
2773 |
0 |
0 |
T3 |
182 |
181 |
0 |
0 |
T4 |
1429 |
1428 |
0 |
0 |
T5 |
12066 |
12065 |
0 |
0 |
T11 |
1258 |
1257 |
0 |
0 |
T12 |
2588 |
2587 |
0 |
0 |
T26 |
110 |
109 |
0 |
0 |
T27 |
110 |
109 |
0 |
0 |
T28 |
112 |
111 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6745313 |
6744895 |
0 |
0 |
T1 |
108 |
107 |
0 |
0 |
T2 |
2774 |
2773 |
0 |
0 |
T3 |
182 |
181 |
0 |
0 |
T4 |
1429 |
1428 |
0 |
0 |
T5 |
12066 |
12065 |
0 |
0 |
T11 |
1258 |
1257 |
0 |
0 |
T12 |
2588 |
2587 |
0 |
0 |
T26 |
110 |
109 |
0 |
0 |
T27 |
110 |
109 |
0 |
0 |
T28 |
112 |
111 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
1889 |
1471 |
0 |
0 |
selKnown1 |
1639 |
1221 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1889 |
1471 |
0 |
0 |
T2 |
21 |
20 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
11 |
10 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
0 |
9 |
0 |
0 |
T9 |
0 |
5 |
0 |
0 |
T10 |
0 |
13 |
0 |
0 |
T11 |
1 |
0 |
0 |
0 |
T12 |
7 |
6 |
0 |
0 |
T15 |
7 |
6 |
0 |
0 |
T16 |
0 |
6 |
0 |
0 |
T18 |
0 |
3 |
0 |
0 |
T25 |
0 |
6 |
0 |
0 |
T26 |
1 |
0 |
0 |
0 |
T27 |
1 |
0 |
0 |
0 |
T28 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1639 |
1221 |
0 |
0 |
T2 |
21 |
20 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
11 |
10 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
0 |
3 |
0 |
0 |
T9 |
0 |
5 |
0 |
0 |
T10 |
0 |
3 |
0 |
0 |
T11 |
1 |
0 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T15 |
7 |
6 |
0 |
0 |
T16 |
0 |
6 |
0 |
0 |
T18 |
0 |
3 |
0 |
0 |
T23 |
0 |
5 |
0 |
0 |
T25 |
0 |
4 |
0 |
0 |
T26 |
1 |
0 |
0 |
0 |
T27 |
1 |
0 |
0 |
0 |
T28 |
1 |
0 |
0 |
0 |