Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	218927	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	609787	1		T2	12		T11	26		T5	18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	515793	1		T2	8		T11	18		T5	6
values[0x0]	153056	1		T2	3		T11	8		T5	23
values[0x1]	159865	1		T2	5		T11	10		T5	14

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	166442	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	662272	1		T2	13		T11	26		T5	22

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2910	1		T5	2		T122	10		T136	1
valid_sources[0x01]	3294	1		T14	1		T33	5		T55	15
valid_sources[0x02]	3606	1		T11	2		T5	1		T136	1
valid_sources[0x03]	3329	1		T13	2		T55	12		T51	17
valid_sources[0x04]	3109	1		T2	1		T38	1		T12	1
valid_sources[0x05]	3452	1		T7	2		T12	1		T136	1
valid_sources[0x06]	2967	1		T137	1		T136	1		T55	12
valid_sources[0x07]	3261	1		T7	1		T30	1		T36	3
valid_sources[0x08]	2823	1		T2	1		T9	1		T55	16
valid_sources[0x09]	3173	1		T9	3		T55	14		T51	26
valid_sources[0x0a]	2924	1		T2	1		T5	2		T55	10
valid_sources[0x0b]	3733	1		T13	1		T138	1		T55	15
valid_sources[0x0c]	3445	1		T12	1		T139	1		T55	6
valid_sources[0x0d]	3021	1		T11	3		T12	1		T55	14
valid_sources[0x0e]	2826	1		T12	1		T37	3		T140	1
valid_sources[0x0f]	2869	1		T55	21		T51	17		T52	3
valid_sources[0x10]	3390	1		T141	3		T142	1		T143	54
valid_sources[0x11]	2862	1		T5	1		T9	3		T12	2
valid_sources[0x12]	2370	1		T9	1		T55	6		T51	17
valid_sources[0x13]	3326	1		T137	1		T136	1		T55	21
valid_sources[0x14]	3056	1		T9	1		T12	1		T34	3
valid_sources[0x15]	4191	1		T30	3		T140	1		T55	15
valid_sources[0x16]	3801	1		T136	1		T138	1		T55	10
valid_sources[0x17]	2882	1		T9	2		T55	10		T51	13
valid_sources[0x18]	2998	1		T6	1		T34	2		T31	50
valid_sources[0x19]	3043	1		T8	1		T12	1		T122	10
valid_sources[0x1a]	3065	1		T5	2		T55	11		T51	23
valid_sources[0x1b]	2389	1		T55	14		T51	31		T52	1
valid_sources[0x1c]	3124	1		T33	1		T41	1		T37	1
valid_sources[0x1d]	2954	1		T12	1		T55	11		T51	19
valid_sources[0x1e]	3523	1		T2	2		T5	1		T40	1
valid_sources[0x1f]	3225	1		T9	1		T12	1		T34	1
valid_sources[0x20]	2625	1		T55	11		T51	33		T80	142
valid_sources[0x21]	4082	1		T136	1		T55	13		T51	12
valid_sources[0x22]	2942	1		T41	2		T140	1		T55	8
valid_sources[0x23]	2967	1		T40	6		T55	17		T51	21
valid_sources[0x24]	3509	1		T37	1		T55	13		T51	22
valid_sources[0x25]	4130	1		T34	3		T55	6		T51	26
valid_sources[0x26]	2976	1		T55	13		T51	14		T52	7
valid_sources[0x27]	2747	1		T140	1		T55	17		T51	26
valid_sources[0x28]	3719	1		T140	3		T55	15		T51	29
valid_sources[0x29]	3091	1		T12	2		T30	2		T122	10
valid_sources[0x2a]	2899	1		T12	1		T139	1		T55	12
valid_sources[0x2b]	3660	1		T55	17		T51	23		T52	4
valid_sources[0x2c]	3107	1		T6	1		T9	1		T33	5
valid_sources[0x2d]	3355	1		T9	1		T13	2		T136	1
valid_sources[0x2e]	3287	1		T9	1		T55	20		T51	15
valid_sources[0x2f]	3730	1		T12	1		T138	1		T55	7
valid_sources[0x30]	2672	1		T8	5		T9	1		T55	14
valid_sources[0x31]	3274	1		T8	1		T6	1		T144	1
valid_sources[0x32]	3344	1		T9	2		T12	2		T13	2
valid_sources[0x33]	3168	1		T55	8		T51	37		T52	4
valid_sources[0x34]	2538	1		T5	1		T9	1		T140	1
valid_sources[0x35]	3139	1		T122	3		T145	6		T137	4
valid_sources[0x36]	2830	1		T9	1		T137	1		T55	21
valid_sources[0x37]	2676	1		T11	3		T55	20		T51	20
valid_sources[0x38]	3283	1		T11	2		T6	1		T122	3
valid_sources[0x39]	3147	1		T6	1		T12	1		T55	15
valid_sources[0x3a]	3447	1		T5	1		T34	2		T55	11
valid_sources[0x3b]	3672	1		T13	1		T140	1		T55	11
valid_sources[0x3c]	3004	1		T9	1		T33	4		T7	1
valid_sources[0x3d]	3110	1		T9	1		T33	1		T12	1
valid_sources[0x3e]	6047	1		T13	1		T40	1		T55	12
valid_sources[0x3f]	3746	1		T55	9		T51	19		T52	3
valid_sources[0x40]	3135	1		T8	1		T10	16		T34	2
valid_sources[0x41]	2670	1		T136	1		T55	11		T51	24
valid_sources[0x42]	3137	1		T9	1		T7	1		T140	1
valid_sources[0x43]	3002	1		T138	2		T55	10		T51	26
valid_sources[0x44]	3346	1		T9	1		T55	19		T51	17
valid_sources[0x45]	3567	1		T9	1		T13	1		T55	9
valid_sources[0x46]	2782	1		T37	5		T138	1		T55	13
valid_sources[0x47]	3342	1		T9	1		T136	1		T55	13
valid_sources[0x48]	3145	1		T9	1		T55	18		T51	12
valid_sources[0x49]	3595	1		T40	2		T55	15		T51	31
valid_sources[0x4a]	3208	1		T140	1		T138	3		T55	14
valid_sources[0x4b]	3170	1		T140	1		T55	12		T51	30
valid_sources[0x4c]	3348	1		T9	1		T136	1		T138	1
valid_sources[0x4d]	2994	1		T8	1		T55	9		T51	12
valid_sources[0x4e]	3028	1		T5	1		T136	1		T138	1
valid_sources[0x4f]	3265	1		T9	2		T136	1		T140	2
valid_sources[0x50]	3398	1		T34	6		T139	1		T55	7
valid_sources[0x51]	3052	1		T11	1		T34	3		T136	1
valid_sources[0x52]	2888	1		T141	10		T146	1		T55	12
valid_sources[0x53]	2536	1		T8	1		T9	1		T122	2
valid_sources[0x54]	3045	1		T12	1		T136	2		T55	12
valid_sources[0x55]	3040	1		T9	1		T141	2		T55	13
valid_sources[0x56]	3164	1		T33	2		T30	1		T34	1
valid_sources[0x57]	3090	1		T5	1		T9	1		T140	1
valid_sources[0x58]	2747	1		T9	2		T136	1		T55	14
valid_sources[0x59]	12293	1		T142	1		T55	17		T51	13
valid_sources[0x5a]	3043	1		T17	2		T138	1		T55	11
valid_sources[0x5b]	2888	1		T5	4		T33	3		T12	1
valid_sources[0x5c]	3288	1		T11	3		T138	1		T55	7
valid_sources[0x5d]	3118	1		T13	1		T147	2		T55	11
valid_sources[0x5e]	3072	1		T2	1		T38	1		T65	1
valid_sources[0x5f]	4115	1		T12	1		T13	1		T55	8
valid_sources[0x60]	2715	1		T38	2		T139	1		T55	15
valid_sources[0x61]	3384	1		T8	2		T55	15		T51	18
valid_sources[0x62]	2911	1		T9	1		T13	1		T136	1
valid_sources[0x63]	3451	1		T9	1		T33	1		T7	1
valid_sources[0x64]	2958	1		T5	1		T30	1		T55	12
valid_sources[0x65]	3301	1		T9	1		T36	1		T55	13
valid_sources[0x66]	2732	1		T140	1		T138	1		T55	15
valid_sources[0x67]	2869	1		T136	1		T55	19		T51	17
valid_sources[0x68]	2757	1		T33	5		T41	1		T55	11
valid_sources[0x69]	3322	1		T33	3		T12	1		T34	1
valid_sources[0x6a]	4339	1		T8	3		T7	1		T17	2
valid_sources[0x6b]	3284	1		T17	1		T12	1		T37	1
valid_sources[0x6c]	2693	1		T5	1		T37	1		T55	6
valid_sources[0x6d]	2924	1		T12	1		T34	1		T55	12
valid_sources[0x6e]	2675	1		T9	1		T33	2		T146	8
valid_sources[0x6f]	3714	1		T139	1		T140	1		T55	10
valid_sources[0x70]	3409	1		T13	1		T55	14		T51	17
valid_sources[0x71]	3182	1		T9	1		T34	2		T55	16
valid_sources[0x72]	2980	1		T9	2		T55	18		T51	19
valid_sources[0x73]	3302	1		T140	1		T55	17		T51	16
valid_sources[0x74]	2790	1		T9	1		T140	1		T55	12
valid_sources[0x75]	3079	1		T55	15		T51	28		T52	6
valid_sources[0x76]	2748	1		T38	3		T55	10		T51	20
valid_sources[0x77]	2747	1		T141	5		T136	1		T146	2
valid_sources[0x78]	3436	1		T8	1		T9	2		T12	1
valid_sources[0x79]	3192	1		T9	1		T136	1		T55	13
valid_sources[0x7a]	2771	1		T12	2		T34	10		T13	1
valid_sources[0x7b]	2766	1		T9	1		T55	10		T51	20
valid_sources[0x7c]	2756	1		T12	1		T13	1		T55	12
valid_sources[0x7d]	2909	1		T55	10		T51	22		T80	58
valid_sources[0x7e]	4510	1		T5	1		T9	1		T33	2
valid_sources[0x7f]	2955	1		T12	2		T136	1		T138	1
valid_sources[0x80]	3001	1		T9	3		T30	1		T36	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

308193

1

T2

4

T11

8

T5

5

values[0x0]

all_enables

biggest_size

150849

1

T2

3

T11

8

T5

9

values[0x1]

all_enables

biggest_size

150745

1

T2

5

T11

10

T5

4

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5312	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	27123	1		T21	2		T22	2		T23	3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	11676	1		T55	11		T51	34		T52	18
values[0x0]	10049	1		T21	5		T22	5		T23	6
values[0x1]	10710	1		T21	2		T22	10		T23	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3972	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	28463	1		T21	2		T22	4		T23	3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	301	1		T148	1		T80	10		T54	10
valid_sources[0x01]	126	1		T149	5		T80	2		T71	5
valid_sources[0x02]	105	1		T150	3		T80	1		T54	2
valid_sources[0x03]	119	1		T51	2		T80	2		T83	1
valid_sources[0x04]	95	1		T50	1		T57	2		T80	2
valid_sources[0x05]	105	1		T148	1		T80	2		T54	8
valid_sources[0x06]	95	1		T151	3		T80	6		T71	8
valid_sources[0x07]	106	1		T64	1		T148	2		T152	1
valid_sources[0x08]	136	1		T148	2		T80	1		T54	8
valid_sources[0x09]	110	1		T153	1		T80	5		T54	2
valid_sources[0x0a]	98	1		T154	1		T80	7		T54	4
valid_sources[0x0b]	108	1		T80	5		T54	4		T71	4
valid_sources[0x0c]	280	1		T149	1		T55	2		T80	1
valid_sources[0x0d]	89	1		T155	1		T80	1		T54	1
valid_sources[0x0e]	89	1		T80	2		T54	2		T83	2
valid_sources[0x0f]	127	1		T57	1		T72	1		T54	1
valid_sources[0x10]	86	1		T156	3		T80	5		T54	7
valid_sources[0x11]	98	1		T51	1		T80	3		T54	1
valid_sources[0x12]	106	1		T155	1		T80	2		T54	4
valid_sources[0x13]	118	1		T64	1		T157	1		T152	1
valid_sources[0x14]	94	1		T158	2		T159	1		T155	1
valid_sources[0x15]	226	1		T24	1		T80	2		T54	3
valid_sources[0x16]	141	1		T152	2		T80	7		T54	2
valid_sources[0x17]	138	1		T52	7		T80	4		T71	8
valid_sources[0x18]	114	1		T80	2		T54	2		T71	5
valid_sources[0x19]	123	1		T155	1		T51	1		T52	1
valid_sources[0x1a]	108	1		T57	1		T160	1		T161	1
valid_sources[0x1b]	88	1		T22	1		T80	3		T71	5
valid_sources[0x1c]	89	1		T159	1		T149	2		T51	2
valid_sources[0x1d]	73	1		T80	1		T54	1		T83	2
valid_sources[0x1e]	153	1		T162	1		T52	1		T80	3
valid_sources[0x1f]	111	1		T50	1		T159	1		T163	3
valid_sources[0x20]	138	1		T164	1		T51	1		T80	4
valid_sources[0x21]	135	1		T149	1		T154	1		T80	8
valid_sources[0x22]	119	1		T26	9		T159	1		T51	1
valid_sources[0x23]	196	1		T165	1		T154	1		T80	6
valid_sources[0x24]	105	1		T154	1		T80	2		T54	1
valid_sources[0x25]	140	1		T22	1		T166	2		T80	3
valid_sources[0x26]	96	1		T72	1		T80	7		T54	2
valid_sources[0x27]	134	1		T80	8		T71	5		T96	1
valid_sources[0x28]	114	1		T80	3		T71	2		T83	1
valid_sources[0x29]	96	1		T148	1		T52	1		T54	1
valid_sources[0x2a]	82	1		T80	5		T54	1		T71	2
valid_sources[0x2b]	116	1		T51	1		T80	2		T71	4
valid_sources[0x2c]	142	1		T148	1		T167	3		T51	1
valid_sources[0x2d]	109	1		T51	1		T80	4		T54	3
valid_sources[0x2e]	898	1		T22	1		T80	2		T54	1
valid_sources[0x2f]	124	1		T168	1		T155	1		T80	5
valid_sources[0x30]	84	1		T80	3		T54	2		T71	2
valid_sources[0x31]	93	1		T64	1		T80	5		T54	3
valid_sources[0x32]	78	1		T169	2		T80	3		T54	4
valid_sources[0x33]	113	1		T159	1		T80	10		T54	1
valid_sources[0x34]	179	1		T170	2		T80	2		T71	3
valid_sources[0x35]	117	1		T79	8		T51	1		T80	1
valid_sources[0x36]	90	1		T52	1		T80	2		T54	3
valid_sources[0x37]	99	1		T72	1		T82	2		T71	4
valid_sources[0x38]	99	1		T54	3		T71	10		T83	1
valid_sources[0x39]	81	1		T165	1		T162	1		T51	1
valid_sources[0x3a]	144	1		T117	13		T80	5		T71	1
valid_sources[0x3b]	139	1		T171	6		T80	1		T54	9
valid_sources[0x3c]	153	1		T24	5		T80	6		T54	1
valid_sources[0x3d]	82	1		T80	2		T71	6		T85	2
valid_sources[0x3e]	100	1		T155	1		T51	1		T54	2
valid_sources[0x3f]	133	1		T52	2		T80	3		T54	5
valid_sources[0x40]	145	1		T157	1		T52	7		T80	2
valid_sources[0x41]	94	1		T148	1		T80	1		T54	6
valid_sources[0x42]	81	1		T23	1		T57	1		T162	1
valid_sources[0x43]	113	1		T51	1		T80	2		T54	1
valid_sources[0x44]	93	1		T72	1		T162	1		T51	1
valid_sources[0x45]	99	1		T159	2		T51	1		T80	1
valid_sources[0x46]	96	1		T167	1		T54	3		T71	2
valid_sources[0x47]	135	1		T157	2		T80	4		T54	2
valid_sources[0x48]	87	1		T22	1		T80	1		T71	2
valid_sources[0x49]	128	1		T162	2		T80	8		T54	1
valid_sources[0x4a]	215	1		T152	2		T51	1		T80	4
valid_sources[0x4b]	88	1		T121	11		T80	3		T54	3
valid_sources[0x4c]	113	1		T22	1		T168	1		T155	2
valid_sources[0x4d]	99	1		T148	1		T71	2		T83	3
valid_sources[0x4e]	101	1		T80	10		T83	2		T118	1
valid_sources[0x4f]	118	1		T52	5		T80	8		T54	1
valid_sources[0x50]	95	1		T23	1		T80	7		T54	2
valid_sources[0x51]	305	1		T57	1		T156	1		T52	1
valid_sources[0x52]	199	1		T80	1		T54	1		T76	1
valid_sources[0x53]	150	1		T51	1		T80	4		T54	1
valid_sources[0x54]	114	1		T152	1		T170	1		T80	2
valid_sources[0x55]	94	1		T167	2		T80	4		T71	3
valid_sources[0x56]	118	1		T22	1		T64	1		T172	3
valid_sources[0x57]	75	1		T52	1		T54	2		T71	1
valid_sources[0x58]	104	1		T54	3		T71	7		T83	5
valid_sources[0x59]	108	1		T167	2		T51	1		T80	6
valid_sources[0x5a]	69	1		T152	1		T80	1		T71	5
valid_sources[0x5b]	119	1		T80	4		T54	4		T71	3
valid_sources[0x5c]	92	1		T173	4		T52	1		T80	4
valid_sources[0x5d]	114	1		T80	4		T54	1		T83	2
valid_sources[0x5e]	124	1		T168	2		T152	1		T51	1
valid_sources[0x5f]	134	1		T167	1		T80	4		T71	2
valid_sources[0x60]	92	1		T174	1		T51	2		T80	3
valid_sources[0x61]	97	1		T22	1		T172	1		T80	3
valid_sources[0x62]	136	1		T26	2		T165	1		T154	1
valid_sources[0x63]	122	1		T159	1		T52	1		T80	1
valid_sources[0x64]	87	1		T152	1		T80	5		T54	1
valid_sources[0x65]	123	1		T157	1		T80	6		T54	3
valid_sources[0x66]	102	1		T162	1		T80	3		T54	2
valid_sources[0x67]	133	1		T165	1		T51	1		T80	2
valid_sources[0x68]	129	1		T56	1		T162	1		T51	1
valid_sources[0x69]	238	1		T80	4		T71	2		T83	4
valid_sources[0x6a]	96	1		T80	8		T54	8		T83	1
valid_sources[0x6b]	99	1		T80	3		T54	1		T71	4
valid_sources[0x6c]	83	1		T51	1		T80	3		T54	2
valid_sources[0x6d]	131	1		T80	4		T54	4		T71	1
valid_sources[0x6e]	94	1		T51	1		T80	3		T54	2
valid_sources[0x6f]	112	1		T51	1		T80	4		T54	2
valid_sources[0x70]	118	1		T80	3		T54	1		T71	5
valid_sources[0x71]	109	1		T80	3		T71	2		T85	3
valid_sources[0x72]	111	1		T22	1		T175	3		T51	1
valid_sources[0x73]	94	1		T152	2		T176	1		T51	2
valid_sources[0x74]	74	1		T80	1		T71	1		T53	1
valid_sources[0x75]	89	1		T80	6		T54	1		T83	2
valid_sources[0x76]	136	1		T80	3		T54	2		T71	3
valid_sources[0x77]	89	1		T23	1		T162	1		T80	5
valid_sources[0x78]	169	1		T72	2		T51	1		T80	2
valid_sources[0x79]	96	1		T148	1		T51	1		T80	6
valid_sources[0x7a]	142	1		T177	1		T80	1		T71	1
valid_sources[0x7b]	133	1		T52	1		T80	2		T54	7
valid_sources[0x7c]	122	1		T149	1		T164	2		T80	1
valid_sources[0x7d]	117	1		T51	1		T80	4		T54	7
valid_sources[0x7e]	125	1		T22	1		T80	7		T54	1
valid_sources[0x7f]	326	1		T168	4		T154	1		T80	5
valid_sources[0x80]	125	1		T25	1		T72	2		T51	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

8575

1

T55

11

T51

13

T52

16

values[0x0]

all_enables

biggest_size

9214

1

T21

2

T22

2

T23

2

values[0x1]

all_enables

biggest_size

9334

1

T23

1

T26

1

T56

2