SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[rv_dm_mem_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[rv_dm_regs_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 858606 | 1 | T2 | 16 | T11 | 36 | T5 | 43 | |||
auto[1] | 27179 | 1 | T33 | 80 | T34 | 80 | T51 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 885574 | 1 | T2 | 16 | T11 | 36 | T5 | 43 | |||
values[1] | 23 | 1 | T51 | 2 | T53 | 2 | T78 | 2 | |||
values[2] | 2 | 1 | T125 | 1 | T126 | 1 | - | - | |||
values[3] | 123 | 1 | T51 | 4 | T53 | 5 | T78 | 12 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 885578 | 1 | T2 | 16 | T11 | 36 | T5 | 43 | |||
values[1] | 20 | 1 | T51 | 2 | T53 | 2 | T78 | 2 | |||
values[2] | 3 | 1 | T127 | 2 | T128 | 1 | - | - | |||
values[3] | 104 | 1 | T51 | 3 | T53 | 6 | T78 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 885475 | 1 | T2 | 16 | T11 | 36 | T5 | 43 | |||
auto[TlIntgErrCmd] | 103 | 1 | T51 | 3 | T53 | 8 | T78 | 7 | |||
auto[TlIntgErrData] | 99 | 1 | T51 | 1 | T53 | 9 | T78 | 4 | |||
auto[TlIntgErrBoth] | 108 | 1 | T51 | 6 | T53 | 3 | T78 | 9 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | |||
auto[0] | 57003 | 0 | T21 | 7 | T22 | 15 | T23 | 10 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 56804 | 1 | T21 | 7 | T22 | 15 | T23 | 10 | |||
values[1] | 23 | 1 | T53 | 1 | T119 | 1 | T120 | 3 | |||
values[2] | 6 | 1 | T120 | 1 | T129 | 1 | T130 | 1 | |||
values[3] | 92 | 1 | T51 | 7 | T53 | 6 | T78 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 56785 | 1 | T21 | 7 | T22 | 15 | T23 | 10 | |||
values[1] | 24 | 1 | T51 | 2 | T53 | 2 | T119 | 1 | |||
values[2] | 7 | 1 | T51 | 1 | T129 | 2 | T125 | 1 | |||
values[3] | 116 | 1 | T51 | 2 | T53 | 5 | T78 | 9 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 56693 | 1 | T21 | 7 | T22 | 15 | T23 | 10 | |||
auto[TlIntgErrCmd] | 92 | 1 | T51 | 2 | T53 | 8 | T78 | 7 | |||
auto[TlIntgErrData] | 111 | 1 | T51 | 3 | T53 | 8 | T78 | 9 | |||
auto[TlIntgErrBoth] | 107 | 1 | T51 | 5 | T53 | 4 | T78 | 4 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |