Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	273809	1		T2	4		T11	10		T5	25
full_word	611976	1		T2	12		T11	26		T5	18

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	885475	1		T2	16		T11	36		T5	43
auto[TlIntgErrCmd]	103	1		T51	3		T53	8		T78	7
auto[TlIntgErrData]	99	1		T51	1		T53	9		T78	4
auto[TlIntgErrBoth]	108	1		T51	6		T53	3		T78	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	518328	1		T2	8		T11	18		T5	6
auto[1]	367457	1		T2	8		T11	18		T5	37

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	209754	1		T2	4		T11	10		T5	1
auto[TlIntgErrNone]	partial	auto[1]	63769	1		T5	24		T8	32		T6	7
auto[TlIntgErrNone]	full_word	auto[0]	308432	1		T2	4		T11	8		T5	5
auto[TlIntgErrNone]	full_word	auto[1]	303520	1		T2	8		T11	18		T5	13
auto[TlIntgErrCmd]	partial	auto[0]	49	1		T51	1		T53	1		T78	3
auto[TlIntgErrCmd]	partial	auto[1]	48	1		T51	2		T53	6		T78	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T53	1		T119	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T78	1		T119	1		T125	1
auto[TlIntgErrData]	partial	auto[0]	44	1		T53	3		T78	1		T119	3
auto[TlIntgErrData]	partial	auto[1]	48	1		T51	1		T53	5		T78	3
auto[TlIntgErrData]	full_word	auto[0]	4	1		T131	1		T132	1		T133	1
auto[TlIntgErrData]	full_word	auto[1]	3	1		T53	1		T120	1		T131	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1		T51	3		T78	4		T119	3
auto[TlIntgErrBoth]	partial	auto[1]	59	1		T51	2		T53	2		T78	4
auto[TlIntgErrBoth]	full_word	auto[0]	5	1		T53	1		T78	1		T131	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1		T51	1		T134	1		T129	1