Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.90	96.97	55.32	84.72		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	144994477	20726	0	0
late_debug_enable_rd_A	144994477	2893	0	0
late_debug_enable_regwen_rd_A	144994477	2609	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144994477	20726	0	0
T51	73129	2	0	0
T52	25636	18	0	0
T53	264390	4	0	0
T54	6683	282	0	0
T71	18878	481	0	0
T73	14349	384	0	0
T74	23376	704	0	0
T75	291988	27	0	0
T76	16978	176	0	0
T77	8914	7	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144994477	2893	0	0
T53	264390	48	0	0
T55	37103	6	0	0
T75	291988	39	0	0
T82	27526	33	0	0
T88	15628	5	0	0
T98	50160	25	0	0
T115	61960	46	0	0
T118	21662	229	0	0
T119	113156	112	0	0
T120	98861	87	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144994477	2609	0	0
T53	264390	36	0	0
T55	37103	11	0	0
T75	291988	25	0	0
T77	8914	18	0	0
T82	27526	24	0	0
T85	20466	6	0	0
T88	15628	13	0	0
T98	50160	67	0	0
T115	61960	19	0	0
T118	21662	181	0	0