Line Coverage for Module :
prim_generic_clock_mux2
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Module :
prim_generic_clock_mux2
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Module :
prim_generic_clock_mux2
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
9992153 |
9990943 |
0 |
0 |
selKnown1 |
76082148 |
76080938 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9992153 |
9990943 |
0 |
0 |
T1 |
26642 |
26638 |
0 |
0 |
T2 |
9572 |
9568 |
0 |
0 |
T3 |
30928 |
30924 |
0 |
0 |
T4 |
19192 |
19188 |
0 |
0 |
T5 |
0 |
23 |
0 |
0 |
T8 |
0 |
30 |
0 |
0 |
T9 |
0 |
24 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
T16 |
0 |
22 |
0 |
0 |
T19 |
0 |
2 |
0 |
0 |
T20 |
0 |
18 |
0 |
0 |
T21 |
218 |
214 |
0 |
0 |
T22 |
218 |
214 |
0 |
0 |
T23 |
218 |
214 |
0 |
0 |
T24 |
278 |
274 |
0 |
0 |
T25 |
222 |
218 |
0 |
0 |
T26 |
218 |
214 |
0 |
0 |
T67 |
0 |
10 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
76082148 |
76080938 |
0 |
0 |
T1 |
102350 |
102346 |
0 |
0 |
T2 |
65064 |
65060 |
0 |
0 |
T3 |
80801 |
80797 |
0 |
0 |
T4 |
215961 |
215957 |
0 |
0 |
T5 |
0 |
4 |
0 |
0 |
T8 |
0 |
4 |
0 |
0 |
T9 |
0 |
14 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
T16 |
0 |
22 |
0 |
0 |
T19 |
0 |
2 |
0 |
0 |
T20 |
0 |
18 |
0 |
0 |
T21 |
3522 |
3518 |
0 |
0 |
T22 |
5054 |
5050 |
0 |
0 |
T23 |
2570 |
2566 |
0 |
0 |
T24 |
2901 |
2897 |
0 |
0 |
T25 |
8931 |
8927 |
0 |
0 |
T26 |
2147 |
2143 |
0 |
0 |
T67 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
2927337 |
2927144 |
0 |
0 |
selKnown1 |
69017667 |
69017474 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2927337 |
2927144 |
0 |
0 |
T1 |
13315 |
13314 |
0 |
0 |
T2 |
4785 |
4784 |
0 |
0 |
T3 |
15463 |
15462 |
0 |
0 |
T4 |
9595 |
9594 |
0 |
0 |
T21 |
108 |
107 |
0 |
0 |
T22 |
108 |
107 |
0 |
0 |
T23 |
108 |
107 |
0 |
0 |
T24 |
138 |
137 |
0 |
0 |
T25 |
110 |
109 |
0 |
0 |
T26 |
108 |
107 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
69017667 |
69017474 |
0 |
0 |
T1 |
89023 |
89022 |
0 |
0 |
T2 |
60277 |
60276 |
0 |
0 |
T3 |
65336 |
65335 |
0 |
0 |
T4 |
206364 |
206363 |
0 |
0 |
T21 |
3412 |
3411 |
0 |
0 |
T22 |
4944 |
4943 |
0 |
0 |
T23 |
2460 |
2459 |
0 |
0 |
T24 |
2761 |
2760 |
0 |
0 |
T25 |
8819 |
8818 |
0 |
0 |
T26 |
2037 |
2036 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
551 |
358 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
0 |
2 |
0 |
0 |
T8 |
0 |
15 |
0 |
0 |
T9 |
0 |
7 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
0 |
11 |
0 |
0 |
T19 |
0 |
1 |
0 |
0 |
T20 |
0 |
9 |
0 |
0 |
T21 |
1 |
0 |
0 |
0 |
T22 |
1 |
0 |
0 |
0 |
T23 |
1 |
0 |
0 |
0 |
T24 |
1 |
0 |
0 |
0 |
T25 |
1 |
0 |
0 |
0 |
T26 |
1 |
0 |
0 |
0 |
T67 |
0 |
5 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
495 |
302 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
0 |
2 |
0 |
0 |
T8 |
0 |
2 |
0 |
0 |
T9 |
0 |
7 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
0 |
11 |
0 |
0 |
T19 |
0 |
1 |
0 |
0 |
T20 |
0 |
9 |
0 |
0 |
T21 |
1 |
0 |
0 |
0 |
T22 |
1 |
0 |
0 |
0 |
T23 |
1 |
0 |
0 |
0 |
T24 |
1 |
0 |
0 |
0 |
T25 |
1 |
0 |
0 |
0 |
T26 |
1 |
0 |
0 |
0 |
T67 |
0 |
5 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
7062266 |
7061854 |
0 |
0 |
selKnown1 |
7062266 |
7061854 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7062266 |
7061854 |
0 |
0 |
T1 |
13315 |
13314 |
0 |
0 |
T2 |
4785 |
4784 |
0 |
0 |
T3 |
15463 |
15462 |
0 |
0 |
T4 |
9595 |
9594 |
0 |
0 |
T21 |
108 |
107 |
0 |
0 |
T22 |
108 |
107 |
0 |
0 |
T23 |
108 |
107 |
0 |
0 |
T24 |
138 |
137 |
0 |
0 |
T25 |
110 |
109 |
0 |
0 |
T26 |
108 |
107 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7062266 |
7061854 |
0 |
0 |
T1 |
13315 |
13314 |
0 |
0 |
T2 |
4785 |
4784 |
0 |
0 |
T3 |
15463 |
15462 |
0 |
0 |
T4 |
9595 |
9594 |
0 |
0 |
T21 |
108 |
107 |
0 |
0 |
T22 |
108 |
107 |
0 |
0 |
T23 |
108 |
107 |
0 |
0 |
T24 |
138 |
137 |
0 |
0 |
T25 |
110 |
109 |
0 |
0 |
T26 |
108 |
107 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
1999 |
1587 |
0 |
0 |
selKnown1 |
1720 |
1308 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1999 |
1587 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
0 |
21 |
0 |
0 |
T8 |
0 |
15 |
0 |
0 |
T9 |
0 |
17 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
0 |
11 |
0 |
0 |
T19 |
0 |
1 |
0 |
0 |
T20 |
0 |
9 |
0 |
0 |
T21 |
1 |
0 |
0 |
0 |
T22 |
1 |
0 |
0 |
0 |
T23 |
1 |
0 |
0 |
0 |
T24 |
1 |
0 |
0 |
0 |
T25 |
1 |
0 |
0 |
0 |
T26 |
1 |
0 |
0 |
0 |
T67 |
0 |
5 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1720 |
1308 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
0 |
2 |
0 |
0 |
T8 |
0 |
2 |
0 |
0 |
T9 |
0 |
7 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
0 |
11 |
0 |
0 |
T19 |
0 |
1 |
0 |
0 |
T20 |
0 |
9 |
0 |
0 |
T21 |
1 |
0 |
0 |
0 |
T22 |
1 |
0 |
0 |
0 |
T23 |
1 |
0 |
0 |
0 |
T24 |
1 |
0 |
0 |
0 |
T25 |
1 |
0 |
0 |
0 |
T26 |
1 |
0 |
0 |
0 |
T67 |
0 |
5 |
0 |
0 |