Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
77.95 94.66 79.12 86.17 71.79 84.67 98.52 30.69


Total test records in report: 410
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html
T283 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.3056186995 Jun 06 02:16:45 PM PDT 24 Jun 06 02:16:59 PM PDT 24 3904440019 ps
T126 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3673294388 Jun 06 02:17:00 PM PDT 24 Jun 06 02:17:08 PM PDT 24 4211964168 ps
T284 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2028645200 Jun 06 02:16:57 PM PDT 24 Jun 06 02:16:59 PM PDT 24 488365674 ps
T285 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.1080518278 Jun 06 02:16:29 PM PDT 24 Jun 06 02:16:32 PM PDT 24 128601997 ps
T46 /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.3916998464 Jun 06 02:16:42 PM PDT 24 Jun 06 02:17:49 PM PDT 24 45811221326 ps
T110 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.3123445689 Jun 06 02:16:27 PM PDT 24 Jun 06 02:17:42 PM PDT 24 7602636610 ps
T286 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.4238569679 Jun 06 02:16:39 PM PDT 24 Jun 06 02:16:41 PM PDT 24 516165762 ps
T287 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.3497837612 Jun 06 02:16:38 PM PDT 24 Jun 06 02:16:40 PM PDT 24 369740995 ps
T288 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.3864601825 Jun 06 02:16:39 PM PDT 24 Jun 06 02:16:44 PM PDT 24 1193722854 ps
T289 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.1446111038 Jun 06 02:16:43 PM PDT 24 Jun 06 02:16:46 PM PDT 24 108457617 ps
T290 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.1611484145 Jun 06 02:17:01 PM PDT 24 Jun 06 02:17:03 PM PDT 24 545106191 ps
T291 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2509027418 Jun 06 02:16:57 PM PDT 24 Jun 06 02:17:03 PM PDT 24 1646703308 ps
T292 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.1948851786 Jun 06 02:16:50 PM PDT 24 Jun 06 02:16:59 PM PDT 24 3480271465 ps
T96 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.1864492833 Jun 06 02:16:40 PM PDT 24 Jun 06 02:16:44 PM PDT 24 7202057927 ps
T293 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.4150097348 Jun 06 02:16:29 PM PDT 24 Jun 06 02:16:38 PM PDT 24 7351644676 ps
T111 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.2608528272 Jun 06 02:16:48 PM PDT 24 Jun 06 02:16:53 PM PDT 24 191000590 ps
T294 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.2876753758 Jun 06 02:16:48 PM PDT 24 Jun 06 02:17:44 PM PDT 24 35075029843 ps
T295 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1632447568 Jun 06 02:16:43 PM PDT 24 Jun 06 02:16:45 PM PDT 24 100090902 ps
T296 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.1016345887 Jun 06 02:16:58 PM PDT 24 Jun 06 02:17:47 PM PDT 24 16692484748 ps
T297 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.4054299835 Jun 06 02:16:37 PM PDT 24 Jun 06 02:16:46 PM PDT 24 6568893889 ps
T101 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.4001779245 Jun 06 02:16:28 PM PDT 24 Jun 06 02:16:37 PM PDT 24 464435285 ps
T97 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.1855964710 Jun 06 02:16:28 PM PDT 24 Jun 06 02:16:32 PM PDT 24 2813721110 ps
T298 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.664265100 Jun 06 02:17:01 PM PDT 24 Jun 06 02:17:04 PM PDT 24 447758522 ps
T299 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.369161390 Jun 06 02:16:56 PM PDT 24 Jun 06 02:17:12 PM PDT 24 4987618283 ps
T300 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.702913394 Jun 06 02:16:28 PM PDT 24 Jun 06 02:17:08 PM PDT 24 10196465685 ps
T301 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.2168503295 Jun 06 02:16:57 PM PDT 24 Jun 06 02:17:03 PM PDT 24 81982674 ps
T302 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1521656743 Jun 06 02:16:40 PM PDT 24 Jun 06 02:17:03 PM PDT 24 25839836114 ps
T127 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.515993092 Jun 06 02:16:46 PM PDT 24 Jun 06 02:17:09 PM PDT 24 1618635598 ps
T303 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.532871069 Jun 06 02:16:28 PM PDT 24 Jun 06 02:16:31 PM PDT 24 134552320 ps
T304 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.3312918866 Jun 06 02:16:40 PM PDT 24 Jun 06 02:17:21 PM PDT 24 30056182940 ps
T305 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.3947677939 Jun 06 02:16:38 PM PDT 24 Jun 06 02:16:40 PM PDT 24 516022193 ps
T128 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.371171545 Jun 06 02:16:41 PM PDT 24 Jun 06 02:16:50 PM PDT 24 2403580633 ps
T306 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.313765548 Jun 06 02:16:57 PM PDT 24 Jun 06 02:17:00 PM PDT 24 178198769 ps
T307 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.263435304 Jun 06 02:16:49 PM PDT 24 Jun 06 02:16:53 PM PDT 24 2006033151 ps
T308 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.3325689972 Jun 06 02:16:41 PM PDT 24 Jun 06 02:16:43 PM PDT 24 58978029 ps
T139 /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.3028062338 Jun 06 02:16:42 PM PDT 24 Jun 06 02:18:02 PM PDT 24 25213756269 ps
T309 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.1199824448 Jun 06 02:16:47 PM PDT 24 Jun 06 02:16:52 PM PDT 24 384809943 ps
T138 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2012183566 Jun 06 02:16:48 PM PDT 24 Jun 06 02:17:00 PM PDT 24 833784757 ps
T112 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.3857087413 Jun 06 02:16:41 PM PDT 24 Jun 06 02:17:51 PM PDT 24 9875830757 ps
T310 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1208525877 Jun 06 02:17:02 PM PDT 24 Jun 06 02:17:07 PM PDT 24 4360721077 ps
T311 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.1833642373 Jun 06 02:16:50 PM PDT 24 Jun 06 02:16:58 PM PDT 24 1479605949 ps
T312 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.2092721955 Jun 06 02:16:53 PM PDT 24 Jun 06 02:16:58 PM PDT 24 158637810 ps
T313 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.3541912652 Jun 06 02:16:40 PM PDT 24 Jun 06 02:16:49 PM PDT 24 8704815406 ps
T314 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.30450694 Jun 06 02:16:44 PM PDT 24 Jun 06 02:16:51 PM PDT 24 5037522149 ps
T315 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3812837646 Jun 06 02:17:01 PM PDT 24 Jun 06 02:17:13 PM PDT 24 6819827493 ps
T118 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.274422891 Jun 06 02:16:48 PM PDT 24 Jun 06 02:16:54 PM PDT 24 768655476 ps
T316 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3200349271 Jun 06 02:16:28 PM PDT 24 Jun 06 02:16:38 PM PDT 24 7412880502 ps
T317 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.77830528 Jun 06 02:16:26 PM PDT 24 Jun 06 02:17:58 PM PDT 24 99925564534 ps
T318 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.1333734007 Jun 06 02:16:26 PM PDT 24 Jun 06 02:16:28 PM PDT 24 135897803 ps
T119 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1874553243 Jun 06 02:17:09 PM PDT 24 Jun 06 02:17:16 PM PDT 24 1417467555 ps
T319 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.791791459 Jun 06 02:17:00 PM PDT 24 Jun 06 02:17:04 PM PDT 24 812021547 ps
T120 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.1178156127 Jun 06 02:16:42 PM PDT 24 Jun 06 02:16:51 PM PDT 24 1031247204 ps
T320 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.72988960 Jun 06 02:16:59 PM PDT 24 Jun 06 02:17:05 PM PDT 24 270198406 ps
T113 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.742905211 Jun 06 02:17:00 PM PDT 24 Jun 06 02:17:03 PM PDT 24 394213743 ps
T321 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3054595549 Jun 06 02:16:42 PM PDT 24 Jun 06 02:16:48 PM PDT 24 1469943371 ps
T322 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.2617407736 Jun 06 02:16:40 PM PDT 24 Jun 06 02:16:42 PM PDT 24 214770432 ps
T323 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3077922665 Jun 06 02:16:30 PM PDT 24 Jun 06 02:16:32 PM PDT 24 124234071 ps
T324 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.3126619043 Jun 06 02:16:56 PM PDT 24 Jun 06 02:17:45 PM PDT 24 18418296322 ps
T325 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.2891771150 Jun 06 02:16:26 PM PDT 24 Jun 06 02:16:29 PM PDT 24 955054538 ps
T326 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3581752180 Jun 06 02:16:28 PM PDT 24 Jun 06 02:16:30 PM PDT 24 1356967509 ps
T327 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.2635963213 Jun 06 02:16:59 PM PDT 24 Jun 06 02:17:08 PM PDT 24 433622622 ps
T328 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.921700960 Jun 06 02:16:40 PM PDT 24 Jun 06 02:16:45 PM PDT 24 554444859 ps
T130 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.1881351461 Jun 06 02:17:00 PM PDT 24 Jun 06 02:17:12 PM PDT 24 2140384097 ps
T329 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.659754485 Jun 06 02:16:52 PM PDT 24 Jun 06 02:16:54 PM PDT 24 681936757 ps
T330 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.2288824526 Jun 06 02:16:46 PM PDT 24 Jun 06 02:17:13 PM PDT 24 29861506306 ps
T134 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3059236653 Jun 06 02:16:59 PM PDT 24 Jun 06 02:17:12 PM PDT 24 855394504 ps
T331 /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.1821164784 Jun 06 02:16:46 PM PDT 24 Jun 06 02:17:31 PM PDT 24 29798645997 ps
T114 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.192354020 Jun 06 02:17:02 PM PDT 24 Jun 06 02:17:05 PM PDT 24 711081944 ps
T332 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.236747749 Jun 06 02:16:40 PM PDT 24 Jun 06 02:16:44 PM PDT 24 401549755 ps
T133 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.773729111 Jun 06 02:16:45 PM PDT 24 Jun 06 02:17:11 PM PDT 24 7260983701 ps
T333 /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.2766114849 Jun 06 02:17:01 PM PDT 24 Jun 06 02:17:06 PM PDT 24 2067812428 ps
T102 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.3555238549 Jun 06 02:16:46 PM PDT 24 Jun 06 02:16:50 PM PDT 24 125326521 ps
T334 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.269985464 Jun 06 02:16:43 PM PDT 24 Jun 06 02:16:48 PM PDT 24 65280136 ps
T103 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.1971343317 Jun 06 02:16:38 PM PDT 24 Jun 06 02:16:45 PM PDT 24 544142207 ps
T131 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1402795074 Jun 06 02:16:46 PM PDT 24 Jun 06 02:17:11 PM PDT 24 3222983166 ps
T335 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.430935249 Jun 06 02:16:46 PM PDT 24 Jun 06 02:16:53 PM PDT 24 979337283 ps
T336 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.632545460 Jun 06 02:16:45 PM PDT 24 Jun 06 02:16:50 PM PDT 24 503382856 ps
T337 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3216113177 Jun 06 02:16:57 PM PDT 24 Jun 06 02:17:00 PM PDT 24 1445282622 ps
T104 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3545950931 Jun 06 02:16:56 PM PDT 24 Jun 06 02:17:04 PM PDT 24 1018968755 ps
T338 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.2401078630 Jun 06 02:16:44 PM PDT 24 Jun 06 02:16:47 PM PDT 24 47202697 ps
T339 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.3023753966 Jun 06 02:16:58 PM PDT 24 Jun 06 02:17:02 PM PDT 24 161978082 ps
T340 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.1627534463 Jun 06 02:16:43 PM PDT 24 Jun 06 02:17:20 PM PDT 24 9809331943 ps
T341 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.423533388 Jun 06 02:17:01 PM PDT 24 Jun 06 02:18:02 PM PDT 24 20968815208 ps
T342 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.367499193 Jun 06 02:16:28 PM PDT 24 Jun 06 02:17:46 PM PDT 24 8725094386 ps
T343 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2569660399 Jun 06 02:16:29 PM PDT 24 Jun 06 02:16:42 PM PDT 24 12478999343 ps
T344 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.200383948 Jun 06 02:16:30 PM PDT 24 Jun 06 02:16:48 PM PDT 24 7189638890 ps
T105 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.921439102 Jun 06 02:16:47 PM PDT 24 Jun 06 02:16:52 PM PDT 24 116991868 ps
T345 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.472355010 Jun 06 02:16:43 PM PDT 24 Jun 06 02:16:47 PM PDT 24 822794715 ps
T346 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.1039377300 Jun 06 02:16:43 PM PDT 24 Jun 06 02:17:12 PM PDT 24 3671528483 ps
T347 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.2005589941 Jun 06 02:16:41 PM PDT 24 Jun 06 02:16:44 PM PDT 24 87246049 ps
T106 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.1485519289 Jun 06 02:17:00 PM PDT 24 Jun 06 02:17:04 PM PDT 24 208588031 ps
T348 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2980575669 Jun 06 02:17:01 PM PDT 24 Jun 06 02:17:05 PM PDT 24 828967773 ps
T349 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3005088711 Jun 06 02:17:02 PM PDT 24 Jun 06 02:17:11 PM PDT 24 976853608 ps
T350 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2545981714 Jun 06 02:16:41 PM PDT 24 Jun 06 02:16:44 PM PDT 24 256133425 ps
T137 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.12439996 Jun 06 02:16:27 PM PDT 24 Jun 06 02:16:38 PM PDT 24 1281141938 ps
T351 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3722647394 Jun 06 02:16:28 PM PDT 24 Jun 06 02:16:30 PM PDT 24 331868148 ps
T352 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.123818444 Jun 06 02:16:43 PM PDT 24 Jun 06 02:17:52 PM PDT 24 25718012837 ps
T353 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.583326522 Jun 06 02:16:42 PM PDT 24 Jun 06 02:16:53 PM PDT 24 1364281214 ps
T354 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3679867026 Jun 06 02:16:30 PM PDT 24 Jun 06 02:16:44 PM PDT 24 4332637841 ps
T355 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.3831575844 Jun 06 02:16:58 PM PDT 24 Jun 06 02:17:13 PM PDT 24 9036748110 ps
T356 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.1660153343 Jun 06 02:16:58 PM PDT 24 Jun 06 02:17:03 PM PDT 24 464576173 ps
T357 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.3393141002 Jun 06 02:16:46 PM PDT 24 Jun 06 02:16:51 PM PDT 24 797917590 ps
T358 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.1098656516 Jun 06 02:16:58 PM PDT 24 Jun 06 02:17:30 PM PDT 24 19820260051 ps
T359 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.3965805190 Jun 06 02:16:43 PM PDT 24 Jun 06 02:17:50 PM PDT 24 80119122270 ps
T360 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.1249062967 Jun 06 02:16:48 PM PDT 24 Jun 06 02:16:53 PM PDT 24 141282840 ps
T361 /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.3421809770 Jun 06 02:16:40 PM PDT 24 Jun 06 02:17:52 PM PDT 24 25026635111 ps
T362 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.2307610747 Jun 06 02:16:47 PM PDT 24 Jun 06 02:16:51 PM PDT 24 290912105 ps
T363 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.2587104855 Jun 06 02:16:43 PM PDT 24 Jun 06 02:16:46 PM PDT 24 169496432 ps
T364 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.2377396645 Jun 06 02:16:40 PM PDT 24 Jun 06 02:17:16 PM PDT 24 44305431480 ps
T365 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1480633536 Jun 06 02:16:27 PM PDT 24 Jun 06 02:16:34 PM PDT 24 5833168951 ps
T366 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.1267079031 Jun 06 02:16:59 PM PDT 24 Jun 06 02:17:02 PM PDT 24 175758744 ps
T367 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.4065049421 Jun 06 02:16:38 PM PDT 24 Jun 06 02:19:43 PM PDT 24 68555937633 ps
T368 /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.484248231 Jun 06 02:16:46 PM PDT 24 Jun 06 02:18:21 PM PDT 24 64055997629 ps
T369 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.599409140 Jun 06 02:16:40 PM PDT 24 Jun 06 02:17:00 PM PDT 24 1670654419 ps
T370 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.157190198 Jun 06 02:16:29 PM PDT 24 Jun 06 02:16:38 PM PDT 24 2093046939 ps
T371 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.3063387088 Jun 06 02:17:07 PM PDT 24 Jun 06 02:17:12 PM PDT 24 591081939 ps
T107 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.837413823 Jun 06 02:16:39 PM PDT 24 Jun 06 02:17:46 PM PDT 24 2327203540 ps
T372 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.256900696 Jun 06 02:16:46 PM PDT 24 Jun 06 02:16:54 PM PDT 24 1548802330 ps
T135 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.1684680253 Jun 06 02:16:58 PM PDT 24 Jun 06 02:17:25 PM PDT 24 3380129466 ps
T373 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2028358357 Jun 06 02:16:27 PM PDT 24 Jun 06 02:16:29 PM PDT 24 232187204 ps
T374 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.514027408 Jun 06 02:16:46 PM PDT 24 Jun 06 02:16:52 PM PDT 24 653548931 ps
T375 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.3642921532 Jun 06 02:17:00 PM PDT 24 Jun 06 02:17:16 PM PDT 24 13193234603 ps
T376 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.737109976 Jun 06 02:17:01 PM PDT 24 Jun 06 02:17:23 PM PDT 24 75932030456 ps
T377 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.947244772 Jun 06 02:16:59 PM PDT 24 Jun 06 02:17:03 PM PDT 24 150522843 ps
T378 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.873559298 Jun 06 02:17:17 PM PDT 24 Jun 06 02:17:27 PM PDT 24 1298916946 ps
T379 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.4069033938 Jun 06 02:16:38 PM PDT 24 Jun 06 02:16:41 PM PDT 24 274496136 ps
T380 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3947429428 Jun 06 02:16:28 PM PDT 24 Jun 06 02:16:31 PM PDT 24 229936717 ps
T381 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2259039614 Jun 06 02:16:58 PM PDT 24 Jun 06 02:17:02 PM PDT 24 1387250956 ps
T382 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3748897816 Jun 06 02:16:59 PM PDT 24 Jun 06 02:17:06 PM PDT 24 673568982 ps
T383 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.22140730 Jun 06 02:16:40 PM PDT 24 Jun 06 02:16:42 PM PDT 24 425122198 ps
T98 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.240997412 Jun 06 02:16:43 PM PDT 24 Jun 06 02:17:29 PM PDT 24 15944552935 ps
T384 /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.3268359933 Jun 06 02:16:47 PM PDT 24 Jun 06 02:17:59 PM PDT 24 56154715090 ps
T385 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.2926550955 Jun 06 02:16:44 PM PDT 24 Jun 06 02:16:47 PM PDT 24 44310934 ps
T386 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.133563229 Jun 06 02:17:04 PM PDT 24 Jun 06 02:17:21 PM PDT 24 10644692805 ps
T387 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.60815868 Jun 06 02:17:02 PM PDT 24 Jun 06 02:18:20 PM PDT 24 55541477593 ps
T388 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.3454179963 Jun 06 02:16:46 PM PDT 24 Jun 06 02:16:50 PM PDT 24 1116385588 ps
T389 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2537357176 Jun 06 02:17:02 PM PDT 24 Jun 06 02:17:22 PM PDT 24 10382392071 ps
T390 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.3124322198 Jun 06 02:16:57 PM PDT 24 Jun 06 02:18:40 PM PDT 24 73300047098 ps
T391 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2695949043 Jun 06 02:16:38 PM PDT 24 Jun 06 02:16:39 PM PDT 24 133545635 ps
T392 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.1654139424 Jun 06 02:16:45 PM PDT 24 Jun 06 02:17:13 PM PDT 24 32581162258 ps
T393 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.33800264 Jun 06 02:16:59 PM PDT 24 Jun 06 02:17:07 PM PDT 24 6224955865 ps
T394 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.3834937159 Jun 06 02:17:02 PM PDT 24 Jun 06 02:17:06 PM PDT 24 1297623732 ps
T395 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.3478867385 Jun 06 02:16:47 PM PDT 24 Jun 06 02:16:51 PM PDT 24 412564413 ps
T132 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.367918316 Jun 06 02:16:53 PM PDT 24 Jun 06 02:17:04 PM PDT 24 1051323770 ps
T396 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.748590035 Jun 06 02:16:53 PM PDT 24 Jun 06 02:17:02 PM PDT 24 193587140 ps
T397 /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.1338760427 Jun 06 02:16:29 PM PDT 24 Jun 06 02:17:40 PM PDT 24 35977627445 ps
T398 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1243549070 Jun 06 02:16:56 PM PDT 24 Jun 06 02:17:01 PM PDT 24 386407773 ps
T399 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3198387206 Jun 06 02:16:45 PM PDT 24 Jun 06 02:16:54 PM PDT 24 2228431611 ps
T400 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.1521889191 Jun 06 02:16:57 PM PDT 24 Jun 06 02:17:02 PM PDT 24 801384860 ps
T401 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3148333215 Jun 06 02:16:29 PM PDT 24 Jun 06 02:18:48 PM PDT 24 48014017937 ps
T402 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.3719989599 Jun 06 02:17:00 PM PDT 24 Jun 06 02:17:32 PM PDT 24 41217456811 ps
T403 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2972764098 Jun 06 02:16:40 PM PDT 24 Jun 06 02:16:45 PM PDT 24 774102418 ps
T136 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.4193012016 Jun 06 02:16:59 PM PDT 24 Jun 06 02:17:11 PM PDT 24 2319666873 ps
T404 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.3103541213 Jun 06 02:16:55 PM PDT 24 Jun 06 02:17:01 PM PDT 24 2768966394 ps
T405 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.903998672 Jun 06 02:16:26 PM PDT 24 Jun 06 02:17:15 PM PDT 24 30673722871 ps
T406 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3506208551 Jun 06 02:16:57 PM PDT 24 Jun 06 02:17:07 PM PDT 24 3781591276 ps
T407 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1934330202 Jun 06 02:16:28 PM PDT 24 Jun 06 02:16:30 PM PDT 24 46199650 ps
T408 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.1546469026 Jun 06 02:16:46 PM PDT 24 Jun 06 02:17:07 PM PDT 24 3934024143 ps
T409 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.1481754331 Jun 06 02:16:59 PM PDT 24 Jun 06 02:18:10 PM PDT 24 26888803786 ps
T410 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.1967575338 Jun 06 02:16:47 PM PDT 24 Jun 06 02:17:15 PM PDT 24 9621676207 ps

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.863092869
Short name T2
Test name
Test status
Simulation time 81992610621 ps
CPU time 84.32 seconds
Started Jun 06 01:56:29 PM PDT 24
Finished Jun 06 01:57:55 PM PDT 24
Peak memory 221556 kb
Host smart-1b9927e1-a224-48c0-95fd-9be0b22ccdf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863092869 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.863092869
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/40.rv_dm_stress_all.260704938
Short name T7
Test name
Test status
Simulation time 16584585278 ps
CPU time 48.9 seconds
Started Jun 06 01:56:57 PM PDT 24
Finished Jun 06 01:57:47 PM PDT 24
Peak memory 205056 kb
Host smart-80a4352e-3c98-4730-abb2-5013dd063d04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260704938 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.260704938
Directory /workspace/40.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.3938369906
Short name T45
Test name
Test status
Simulation time 52673342495 ps
CPU time 166.67 seconds
Started Jun 06 02:16:43 PM PDT 24
Finished Jun 06 02:19:31 PM PDT 24
Peak memory 222068 kb
Host smart-2bc1813d-066e-41a9-90c9-0b9724ecec8e
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938369906 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.3938369906
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.3795620577
Short name T61
Test name
Test status
Simulation time 145869523 ps
CPU time 0.81 seconds
Started Jun 06 01:56:45 PM PDT 24
Finished Jun 06 01:56:47 PM PDT 24
Peak memory 204864 kb
Host smart-843a4b04-8ee4-4e1f-842a-75448f5a3d54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795620577 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.3795620577
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_stress_all.1683285038
Short name T14
Test name
Test status
Simulation time 11920373569 ps
CPU time 10.94 seconds
Started Jun 06 01:56:24 PM PDT 24
Finished Jun 06 01:56:36 PM PDT 24
Peak memory 205100 kb
Host smart-776d56cd-72b4-4314-9780-0ea5d081c4b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683285038 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.1683285038
Directory /workspace/7.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.819318554
Short name T55
Test name
Test status
Simulation time 3642031181 ps
CPU time 11.04 seconds
Started Jun 06 02:16:56 PM PDT 24
Finished Jun 06 02:17:08 PM PDT 24
Peak memory 213328 kb
Host smart-6ab525a3-f7b3-4896-b679-6f4da0954bc3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819318554 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.819318554
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.3805155731
Short name T71
Test name
Test status
Simulation time 131101230483 ps
CPU time 206.56 seconds
Started Jun 06 01:56:22 PM PDT 24
Finished Jun 06 01:59:50 PM PDT 24
Peak memory 221584 kb
Host smart-41d74da9-bb81-485b-ae7c-b69923b5752f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805155731 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.3805155731
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.3085709280
Short name T30
Test name
Test status
Simulation time 70165352 ps
CPU time 0.85 seconds
Started Jun 06 01:56:49 PM PDT 24
Finished Jun 06 01:56:51 PM PDT 24
Peak memory 204884 kb
Host smart-5be654ca-5dd0-4176-a81e-58e911f0330c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085709280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.3085709280
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1562164127
Short name T89
Test name
Test status
Simulation time 9907392833 ps
CPU time 32.03 seconds
Started Jun 06 02:16:41 PM PDT 24
Finished Jun 06 02:17:14 PM PDT 24
Peak memory 205152 kb
Host smart-525e75a8-2bec-4af9-bfc2-af8cf767474b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562164127 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.1562164127
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/default/15.rv_dm_stress_all.1598559382
Short name T15
Test name
Test status
Simulation time 19568158745 ps
CPU time 30.95 seconds
Started Jun 06 01:57:06 PM PDT 24
Finished Jun 06 01:57:38 PM PDT 24
Peak memory 213220 kb
Host smart-5e02f1f9-42b5-4aeb-bcf8-dd1891403f57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598559382 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.1598559382
Directory /workspace/15.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.78941606
Short name T58
Test name
Test status
Simulation time 856908180 ps
CPU time 6.15 seconds
Started Jun 06 02:16:30 PM PDT 24
Finished Jun 06 02:16:37 PM PDT 24
Peak memory 213392 kb
Host smart-c6c31099-bde3-4413-93b7-9e31cee4fa2e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78941606 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.78941606
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.248255290
Short name T25
Test name
Test status
Simulation time 103796375 ps
CPU time 0.79 seconds
Started Jun 06 01:56:26 PM PDT 24
Finished Jun 06 01:56:30 PM PDT 24
Peak memory 212948 kb
Host smart-7312d24e-f354-41a6-a5a4-2de1ebae7129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248255290 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.248255290
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.1948228404
Short name T65
Test name
Test status
Simulation time 574163120 ps
CPU time 1.42 seconds
Started Jun 06 01:56:29 PM PDT 24
Finished Jun 06 01:56:32 PM PDT 24
Peak memory 229084 kb
Host smart-eef204be-e65d-468c-8ceb-0eec1bae4e92
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948228404 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.1948228404
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.1234488368
Short name T39
Test name
Test status
Simulation time 206602512 ps
CPU time 1.32 seconds
Started Jun 06 01:56:22 PM PDT 24
Finished Jun 06 01:56:25 PM PDT 24
Peak memory 204720 kb
Host smart-e50b9914-336a-4787-a73a-e94e13c384a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234488368 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.1234488368
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.448778709
Short name T10
Test name
Test status
Simulation time 186270702 ps
CPU time 0.8 seconds
Started Jun 06 01:56:12 PM PDT 24
Finished Jun 06 01:56:14 PM PDT 24
Peak memory 204692 kb
Host smart-4c0306fb-b31a-4cdd-8ea5-39e135a823fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448778709 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.448778709
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.4098065596
Short name T93
Test name
Test status
Simulation time 2784600454 ps
CPU time 8.02 seconds
Started Jun 06 02:16:47 PM PDT 24
Finished Jun 06 02:16:57 PM PDT 24
Peak memory 205160 kb
Host smart-c92252df-ad44-4903-b8f9-810878a36bb3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098065596 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.4098065596
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.995227732
Short name T9
Test name
Test status
Simulation time 235833098 ps
CPU time 0.86 seconds
Started Jun 06 01:56:19 PM PDT 24
Finished Jun 06 01:56:21 PM PDT 24
Peak memory 204656 kb
Host smart-cd43e6b7-d592-4eff-8392-06bca5e2473c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995227732 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.995227732
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1402795074
Short name T131
Test name
Test status
Simulation time 3222983166 ps
CPU time 22.67 seconds
Started Jun 06 02:16:46 PM PDT 24
Finished Jun 06 02:17:11 PM PDT 24
Peak memory 213396 kb
Host smart-ccdb23b9-c191-4915-8a18-80072fcc2d83
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402795074 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.1
402795074
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.4246019972
Short name T57
Test name
Test status
Simulation time 284086169 ps
CPU time 6.46 seconds
Started Jun 06 02:16:27 PM PDT 24
Finished Jun 06 02:16:34 PM PDT 24
Peak memory 213400 kb
Host smart-6fdc48db-fb9e-4530-9852-873909151a4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246019972 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.4246019972
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2597930242
Short name T269
Test name
Test status
Simulation time 1337434309 ps
CPU time 1.45 seconds
Started Jun 06 02:16:29 PM PDT 24
Finished Jun 06 02:16:32 PM PDT 24
Peak memory 204728 kb
Host smart-b2833140-46e4-4a05-8c59-1e9e8153fa1e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597930242 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.2597930242
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.1855964710
Short name T97
Test name
Test status
Simulation time 2813721110 ps
CPU time 2.6 seconds
Started Jun 06 02:16:28 PM PDT 24
Finished Jun 06 02:16:32 PM PDT 24
Peak memory 205168 kb
Host smart-01a5619f-fbfb-4784-8876-79f4dba4ab7b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855964710 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.1855964710
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.515993092
Short name T127
Test name
Test status
Simulation time 1618635598 ps
CPU time 20.3 seconds
Started Jun 06 02:16:46 PM PDT 24
Finished Jun 06 02:17:09 PM PDT 24
Peak memory 213272 kb
Host smart-9ef9572a-1b2e-47e3-a0c1-5d7dc3a7f32c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515993092 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.515993092
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.2960907487
Short name T31
Test name
Test status
Simulation time 1542909815 ps
CPU time 5.23 seconds
Started Jun 06 01:56:22 PM PDT 24
Finished Jun 06 01:56:28 PM PDT 24
Peak memory 204572 kb
Host smart-2abc5580-866f-4d4b-95c5-000db6f80f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960907487 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.2960907487
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.2362449234
Short name T149
Test name
Test status
Simulation time 910900808 ps
CPU time 2.92 seconds
Started Jun 06 01:56:12 PM PDT 24
Finished Jun 06 01:56:16 PM PDT 24
Peak memory 204672 kb
Host smart-4b61c3cc-e6be-4a2e-bdcd-a788af907cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362449234 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.2362449234
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.2622131135
Short name T16
Test name
Test status
Simulation time 2681348651 ps
CPU time 2.46 seconds
Started Jun 06 01:56:17 PM PDT 24
Finished Jun 06 01:56:20 PM PDT 24
Peak memory 205048 kb
Host smart-28c9fc6d-edc4-4b4d-981d-3e927b110397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622131135 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.2622131135
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.1390996345
Short name T6
Test name
Test status
Simulation time 5951814784 ps
CPU time 16.51 seconds
Started Jun 06 01:56:24 PM PDT 24
Finished Jun 06 01:56:42 PM PDT 24
Peak memory 205040 kb
Host smart-17133bd9-9f5a-4eae-a153-6aa809e4378d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390996345 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.1390996345
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1965349058
Short name T99
Test name
Test status
Simulation time 3530361997 ps
CPU time 78.07 seconds
Started Jun 06 02:16:26 PM PDT 24
Finished Jun 06 02:17:45 PM PDT 24
Peak memory 213260 kb
Host smart-c7f620d1-425c-4d67-b737-0d362ef9741a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965349058 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.1965349058
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.1485519289
Short name T106
Test name
Test status
Simulation time 208588031 ps
CPU time 2.55 seconds
Started Jun 06 02:17:00 PM PDT 24
Finished Jun 06 02:17:04 PM PDT 24
Peak memory 213180 kb
Host smart-e9c46bcf-9674-42f9-bf38-cbf622b5ec53
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485519289 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.1485519289
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.4193012016
Short name T136
Test name
Test status
Simulation time 2319666873 ps
CPU time 10.47 seconds
Started Jun 06 02:16:59 PM PDT 24
Finished Jun 06 02:17:11 PM PDT 24
Peak memory 213400 kb
Host smart-3c747777-e069-45e4-9d88-5b81097ef9ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193012016 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.4
193012016
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.367499193
Short name T342
Test name
Test status
Simulation time 8725094386 ps
CPU time 76.8 seconds
Started Jun 06 02:16:28 PM PDT 24
Finished Jun 06 02:17:46 PM PDT 24
Peak memory 213336 kb
Host smart-55345136-6634-47c1-a099-78cbd118b318
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367499193 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.rv_dm_csr_aliasing.367499193
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.702913394
Short name T300
Test name
Test status
Simulation time 10196465685 ps
CPU time 38.35 seconds
Started Jun 06 02:16:28 PM PDT 24
Finished Jun 06 02:17:08 PM PDT 24
Peak memory 205160 kb
Host smart-8e80006f-310f-4db7-b3c9-e1f27689e7d9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702913394 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.702913394
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3947429428
Short name T380
Test name
Test status
Simulation time 229936717 ps
CPU time 1.84 seconds
Started Jun 06 02:16:28 PM PDT 24
Finished Jun 06 02:16:31 PM PDT 24
Peak memory 213236 kb
Host smart-8f5942b9-7a6e-4db1-8d23-3779e0ac6cf8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947429428 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.3947429428
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.2891771150
Short name T325
Test name
Test status
Simulation time 955054538 ps
CPU time 2.28 seconds
Started Jun 06 02:16:26 PM PDT 24
Finished Jun 06 02:16:29 PM PDT 24
Peak memory 216204 kb
Host smart-df761865-d249-44ec-9bae-b64af394e490
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891771150 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.2891771150
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.532871069
Short name T303
Test name
Test status
Simulation time 134552320 ps
CPU time 1.79 seconds
Started Jun 06 02:16:28 PM PDT 24
Finished Jun 06 02:16:31 PM PDT 24
Peak memory 213212 kb
Host smart-062c3b01-4c37-4ff1-9f97-96a2ab320bbb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532871069 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.532871069
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3148333215
Short name T401
Test name
Test status
Simulation time 48014017937 ps
CPU time 137.79 seconds
Started Jun 06 02:16:29 PM PDT 24
Finished Jun 06 02:18:48 PM PDT 24
Peak memory 204988 kb
Host smart-05bd608b-6fc9-49a7-bff3-9b87ed87cd6f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148333215 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.3148333215
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.903998672
Short name T405
Test name
Test status
Simulation time 30673722871 ps
CPU time 47.68 seconds
Started Jun 06 02:16:26 PM PDT 24
Finished Jun 06 02:17:15 PM PDT 24
Peak memory 205036 kb
Host smart-0f695fec-e7ae-4a1a-9cfc-931ba58cbc72
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903998672 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.r
v_dm_jtag_dmi_csr_bit_bash.903998672
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.200383948
Short name T344
Test name
Test status
Simulation time 7189638890 ps
CPU time 16.85 seconds
Started Jun 06 02:16:30 PM PDT 24
Finished Jun 06 02:16:48 PM PDT 24
Peak memory 204996 kb
Host smart-354d2ae6-4a9b-41ae-8eaf-2e2ff70853dc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200383948 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.200383948
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1480633536
Short name T365
Test name
Test status
Simulation time 5833168951 ps
CPU time 5.82 seconds
Started Jun 06 02:16:27 PM PDT 24
Finished Jun 06 02:16:34 PM PDT 24
Peak memory 205044 kb
Host smart-1f653458-e2fe-417c-ba8a-cadd13091c1f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480633536 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.1480633536
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.228064485
Short name T75
Test name
Test status
Simulation time 287907455 ps
CPU time 1.44 seconds
Started Jun 06 02:16:28 PM PDT 24
Finished Jun 06 02:16:31 PM PDT 24
Peak memory 204776 kb
Host smart-36773fde-7a98-40c9-82bf-5e0ee5de455e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228064485 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr
_hw_reset.228064485
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3581752180
Short name T326
Test name
Test status
Simulation time 1356967509 ps
CPU time 1.46 seconds
Started Jun 06 02:16:28 PM PDT 24
Finished Jun 06 02:16:30 PM PDT 24
Peak memory 204740 kb
Host smart-92da344d-4391-442f-aca4-af730f0a3d2b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581752180 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.3
581752180
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1934330202
Short name T407
Test name
Test status
Simulation time 46199650 ps
CPU time 0.73 seconds
Started Jun 06 02:16:28 PM PDT 24
Finished Jun 06 02:16:30 PM PDT 24
Peak memory 204716 kb
Host smart-990af386-94a3-4a43-a161-cb10908ab83a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934330202 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.1934330202
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.1333734007
Short name T318
Test name
Test status
Simulation time 135897803 ps
CPU time 0.74 seconds
Started Jun 06 02:16:26 PM PDT 24
Finished Jun 06 02:16:28 PM PDT 24
Peak memory 204688 kb
Host smart-450bb404-2756-4a12-9617-366c2f6c84da
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333734007 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.1333734007
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.157190198
Short name T370
Test name
Test status
Simulation time 2093046939 ps
CPU time 8.04 seconds
Started Jun 06 02:16:29 PM PDT 24
Finished Jun 06 02:16:38 PM PDT 24
Peak memory 205096 kb
Host smart-a2f97a68-3742-47eb-bc42-d113ae7cdbe3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157190198 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_c
sr_outstanding.157190198
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.12439996
Short name T137
Test name
Test status
Simulation time 1281141938 ps
CPU time 10.15 seconds
Started Jun 06 02:16:27 PM PDT 24
Finished Jun 06 02:16:38 PM PDT 24
Peak memory 213316 kb
Host smart-5b1fd530-3cab-4acd-a35d-67e831511343
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12439996 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.12439996
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.3123445689
Short name T110
Test name
Test status
Simulation time 7602636610 ps
CPU time 74.03 seconds
Started Jun 06 02:16:27 PM PDT 24
Finished Jun 06 02:17:42 PM PDT 24
Peak memory 213324 kb
Host smart-4675a513-0027-48fe-86ca-f80a7be9db90
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123445689 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.3123445689
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.868121075
Short name T59
Test name
Test status
Simulation time 285608164 ps
CPU time 1.73 seconds
Started Jun 06 02:16:27 PM PDT 24
Finished Jun 06 02:16:29 PM PDT 24
Peak memory 213312 kb
Host smart-07fbf5d6-935e-47bc-8029-dbed0cb01649
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868121075 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.868121075
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3200349271
Short name T316
Test name
Test status
Simulation time 7412880502 ps
CPU time 8.84 seconds
Started Jun 06 02:16:28 PM PDT 24
Finished Jun 06 02:16:38 PM PDT 24
Peak memory 218292 kb
Host smart-f00eddaf-d45a-4e5c-b7bc-12eca06accd5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200349271 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.3200349271
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.1080518278
Short name T285
Test name
Test status
Simulation time 128601997 ps
CPU time 1.64 seconds
Started Jun 06 02:16:29 PM PDT 24
Finished Jun 06 02:16:32 PM PDT 24
Peak memory 213536 kb
Host smart-29c2ff44-2161-4ff1-9f5e-b560c2656ade
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080518278 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.1080518278
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.77830528
Short name T317
Test name
Test status
Simulation time 99925564534 ps
CPU time 90.58 seconds
Started Jun 06 02:16:26 PM PDT 24
Finished Jun 06 02:17:58 PM PDT 24
Peak memory 205048 kb
Host smart-35a7162a-f802-4d8d-936c-3c709b3ccc04
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77830528 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_
aliasing.77830528
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3679867026
Short name T354
Test name
Test status
Simulation time 4332637841 ps
CPU time 13.52 seconds
Started Jun 06 02:16:30 PM PDT 24
Finished Jun 06 02:16:44 PM PDT 24
Peak memory 205248 kb
Host smart-14dec529-c60c-4813-b4f1-d857ba82ced6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679867026 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
rv_dm_jtag_dmi_csr_bit_bash.3679867026
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1791186521
Short name T95
Test name
Test status
Simulation time 5073038406 ps
CPU time 8.06 seconds
Started Jun 06 02:16:30 PM PDT 24
Finished Jun 06 02:16:39 PM PDT 24
Peak memory 205176 kb
Host smart-27521f31-5ec5-4f91-ad16-930a906f5ed0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791186521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.1791186521
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.4150097348
Short name T293
Test name
Test status
Simulation time 7351644676 ps
CPU time 8.34 seconds
Started Jun 06 02:16:29 PM PDT 24
Finished Jun 06 02:16:38 PM PDT 24
Peak memory 204988 kb
Host smart-34b589d8-1888-4be5-a6d9-afcdb9e6fda9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150097348 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.4
150097348
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2295336453
Short name T272
Test name
Test status
Simulation time 734838649 ps
CPU time 1.09 seconds
Started Jun 06 02:16:30 PM PDT 24
Finished Jun 06 02:16:32 PM PDT 24
Peak memory 204656 kb
Host smart-4df4067a-dbdb-4c10-acc0-4e04fff17bf6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295336453 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.2295336453
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2569660399
Short name T343
Test name
Test status
Simulation time 12478999343 ps
CPU time 11.97 seconds
Started Jun 06 02:16:29 PM PDT 24
Finished Jun 06 02:16:42 PM PDT 24
Peak memory 205048 kb
Host smart-fbfbfb06-4bac-48da-8cc4-c4bf9b8b5c37
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569660399 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.2569660399
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.305027553
Short name T274
Test name
Test status
Simulation time 383063100 ps
CPU time 0.89 seconds
Started Jun 06 02:16:27 PM PDT 24
Finished Jun 06 02:16:29 PM PDT 24
Peak memory 204740 kb
Host smart-4c71fc4b-f0ef-4d22-9a70-d5ed986a5458
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305027553 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_hw_reset.305027553
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3722647394
Short name T351
Test name
Test status
Simulation time 331868148 ps
CPU time 0.91 seconds
Started Jun 06 02:16:28 PM PDT 24
Finished Jun 06 02:16:30 PM PDT 24
Peak memory 204728 kb
Host smart-ab08f6f8-efb3-45c4-93f6-c7758646fa5c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722647394 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.3
722647394
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3077922665
Short name T323
Test name
Test status
Simulation time 124234071 ps
CPU time 0.92 seconds
Started Jun 06 02:16:30 PM PDT 24
Finished Jun 06 02:16:32 PM PDT 24
Peak memory 204716 kb
Host smart-87023b62-7a31-417b-9c65-5597cf4afa77
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077922665 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.3077922665
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.3120814394
Short name T267
Test name
Test status
Simulation time 131260278 ps
CPU time 0.74 seconds
Started Jun 06 02:16:27 PM PDT 24
Finished Jun 06 02:16:28 PM PDT 24
Peak memory 204672 kb
Host smart-3869e45a-5630-48ad-ace6-a13e1014e06f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120814394 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.3120814394
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.4001779245
Short name T101
Test name
Test status
Simulation time 464435285 ps
CPU time 7.54 seconds
Started Jun 06 02:16:28 PM PDT 24
Finished Jun 06 02:16:37 PM PDT 24
Peak memory 205104 kb
Host smart-fe1ff936-9139-4a19-b3c7-cc407c65660f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001779245 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_
csr_outstanding.4001779245
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.1338760427
Short name T397
Test name
Test status
Simulation time 35977627445 ps
CPU time 69.95 seconds
Started Jun 06 02:16:29 PM PDT 24
Finished Jun 06 02:17:40 PM PDT 24
Peak memory 221700 kb
Host smart-41014f79-ff86-42db-b723-b1c19640a869
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338760427 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.1338760427
Directory /workspace/1.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.74157321
Short name T54
Test name
Test status
Simulation time 2704300048 ps
CPU time 11.14 seconds
Started Jun 06 02:16:28 PM PDT 24
Finished Jun 06 02:16:41 PM PDT 24
Peak memory 213384 kb
Host smart-4366333f-5867-42a7-99b3-614fb88bffeb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74157321 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.74157321
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.1948851786
Short name T292
Test name
Test status
Simulation time 3480271465 ps
CPU time 7.83 seconds
Started Jun 06 02:16:50 PM PDT 24
Finished Jun 06 02:16:59 PM PDT 24
Peak memory 220144 kb
Host smart-b309fdf5-6aeb-4323-a6aa-7202221bed37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948851786 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.1948851786
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.2809290160
Short name T60
Test name
Test status
Simulation time 81097108 ps
CPU time 1.62 seconds
Started Jun 06 02:16:48 PM PDT 24
Finished Jun 06 02:16:51 PM PDT 24
Peak memory 213208 kb
Host smart-adb2c66e-2b09-4fa9-9179-2965ce8579f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809290160 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.2809290160
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.1016345887
Short name T296
Test name
Test status
Simulation time 16692484748 ps
CPU time 48.31 seconds
Started Jun 06 02:16:58 PM PDT 24
Finished Jun 06 02:17:47 PM PDT 24
Peak memory 205040 kb
Host smart-d46a34eb-7a23-40e1-8b3a-bed835acfc15
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016345887 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.rv_dm_jtag_dmi_csr_bit_bash.1016345887
Directory /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2505738901
Short name T261
Test name
Test status
Simulation time 3404661072 ps
CPU time 4.97 seconds
Started Jun 06 02:16:47 PM PDT 24
Finished Jun 06 02:16:54 PM PDT 24
Peak memory 204944 kb
Host smart-9cc112a8-d47e-49cf-a885-52db09e792ee
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505738901 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
2505738901
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.659754485
Short name T329
Test name
Test status
Simulation time 681936757 ps
CPU time 1.19 seconds
Started Jun 06 02:16:52 PM PDT 24
Finished Jun 06 02:16:54 PM PDT 24
Peak memory 204712 kb
Host smart-3e278ae3-f820-48f6-ba13-8ae0aa5cfc3b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659754485 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.659754485
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.274422891
Short name T118
Test name
Test status
Simulation time 768655476 ps
CPU time 4.44 seconds
Started Jun 06 02:16:48 PM PDT 24
Finished Jun 06 02:16:54 PM PDT 24
Peak memory 205120 kb
Host smart-e40c1eca-67c3-4e44-9e16-653d3cbe2325
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274422891 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same_
csr_outstanding.274422891
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.2404070993
Short name T281
Test name
Test status
Simulation time 337132110 ps
CPU time 5.14 seconds
Started Jun 06 02:16:46 PM PDT 24
Finished Jun 06 02:16:54 PM PDT 24
Peak memory 221508 kb
Host smart-0408a2e5-e602-4f40-be17-ee08326e927a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404070993 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.2404070993
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.714679231
Short name T275
Test name
Test status
Simulation time 350822721 ps
CPU time 4.62 seconds
Started Jun 06 02:16:49 PM PDT 24
Finished Jun 06 02:16:56 PM PDT 24
Peak memory 220140 kb
Host smart-f6977854-13c8-4ece-8899-8e6cef5b9d2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714679231 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.714679231
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.2547961232
Short name T108
Test name
Test status
Simulation time 66530788 ps
CPU time 2.22 seconds
Started Jun 06 02:16:46 PM PDT 24
Finished Jun 06 02:16:51 PM PDT 24
Peak memory 213300 kb
Host smart-bf73e701-b9c8-4a71-b540-709564c2de78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547961232 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.2547961232
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.3719989599
Short name T402
Test name
Test status
Simulation time 41217456811 ps
CPU time 30.2 seconds
Started Jun 06 02:17:00 PM PDT 24
Finished Jun 06 02:17:32 PM PDT 24
Peak memory 204976 kb
Host smart-e4fc57f6-5350-40e2-a88f-8b9995f3696b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719989599 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.rv_dm_jtag_dmi_csr_bit_bash.3719989599
Directory /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.256900696
Short name T372
Test name
Test status
Simulation time 1548802330 ps
CPU time 4.77 seconds
Started Jun 06 02:16:46 PM PDT 24
Finished Jun 06 02:16:54 PM PDT 24
Peak memory 205160 kb
Host smart-01c252e4-e84a-4e7d-8114-1c6f04eb054e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256900696 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.256900696
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.1201684621
Short name T271
Test name
Test status
Simulation time 566596520 ps
CPU time 0.82 seconds
Started Jun 06 02:16:49 PM PDT 24
Finished Jun 06 02:16:52 PM PDT 24
Peak memory 204748 kb
Host smart-4879bc0b-b609-4b1f-90a1-56b58fea62f3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201684621 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.
1201684621
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.1660153343
Short name T356
Test name
Test status
Simulation time 464576173 ps
CPU time 4.2 seconds
Started Jun 06 02:16:58 PM PDT 24
Finished Jun 06 02:17:03 PM PDT 24
Peak memory 205160 kb
Host smart-fe6693cf-0198-4152-a06e-219c46291a72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660153343 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same
_csr_outstanding.1660153343
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.2307610747
Short name T362
Test name
Test status
Simulation time 290912105 ps
CPU time 2.13 seconds
Started Jun 06 02:16:47 PM PDT 24
Finished Jun 06 02:16:51 PM PDT 24
Peak memory 213672 kb
Host smart-bfd86f44-fbc4-4a4c-ae77-b33d197d22d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307610747 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.2307610747
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.367918316
Short name T132
Test name
Test status
Simulation time 1051323770 ps
CPU time 9.21 seconds
Started Jun 06 02:16:53 PM PDT 24
Finished Jun 06 02:17:04 PM PDT 24
Peak memory 213272 kb
Host smart-766db0db-bf5a-41df-90cf-e9a9d17ea583
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367918316 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.367918316
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1080703310
Short name T277
Test name
Test status
Simulation time 1050532807 ps
CPU time 5.03 seconds
Started Jun 06 02:16:58 PM PDT 24
Finished Jun 06 02:17:04 PM PDT 24
Peak memory 218540 kb
Host smart-4f2e2d46-c72a-4f83-9b84-097eae55cf24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080703310 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.1080703310
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.1288400014
Short name T62
Test name
Test status
Simulation time 773431171 ps
CPU time 1.55 seconds
Started Jun 06 02:16:48 PM PDT 24
Finished Jun 06 02:16:52 PM PDT 24
Peak memory 213312 kb
Host smart-80ee585c-799b-4111-84bc-8e97acdc388d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288400014 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.1288400014
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.3126619043
Short name T324
Test name
Test status
Simulation time 18418296322 ps
CPU time 47.76 seconds
Started Jun 06 02:16:56 PM PDT 24
Finished Jun 06 02:17:45 PM PDT 24
Peak memory 205048 kb
Host smart-58c8133f-af5b-4788-8548-7db7fda20141
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126619043 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.rv_dm_jtag_dmi_csr_bit_bash.3126619043
Directory /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.371040337
Short name T273
Test name
Test status
Simulation time 2154100693 ps
CPU time 3.82 seconds
Started Jun 06 02:16:48 PM PDT 24
Finished Jun 06 02:16:54 PM PDT 24
Peak memory 204968 kb
Host smart-c52910c1-f853-4ce4-93c6-6dc376be4460
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371040337 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.371040337
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3216113177
Short name T337
Test name
Test status
Simulation time 1445282622 ps
CPU time 2.65 seconds
Started Jun 06 02:16:57 PM PDT 24
Finished Jun 06 02:17:00 PM PDT 24
Peak memory 204696 kb
Host smart-36b5e521-ef81-418e-9cb2-14907c437e10
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216113177 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
3216113177
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3545950931
Short name T104
Test name
Test status
Simulation time 1018968755 ps
CPU time 6.94 seconds
Started Jun 06 02:16:56 PM PDT 24
Finished Jun 06 02:17:04 PM PDT 24
Peak memory 205092 kb
Host smart-aa91fe97-2aa2-4bcf-921b-5705936a9b26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545950931 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.3545950931
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.3023753966
Short name T339
Test name
Test status
Simulation time 161978082 ps
CPU time 2.5 seconds
Started Jun 06 02:16:58 PM PDT 24
Finished Jun 06 02:17:02 PM PDT 24
Peak memory 213452 kb
Host smart-631ca3c1-7761-42c7-982d-926337da74f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023753966 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.3023753966
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3673294388
Short name T126
Test name
Test status
Simulation time 4211964168 ps
CPU time 6.8 seconds
Started Jun 06 02:17:00 PM PDT 24
Finished Jun 06 02:17:08 PM PDT 24
Peak memory 220592 kb
Host smart-64072b86-496a-4284-b7d6-bb58d14a7fae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673294388 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.3673294388
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.2608528272
Short name T111
Test name
Test status
Simulation time 191000590 ps
CPU time 2.61 seconds
Started Jun 06 02:16:48 PM PDT 24
Finished Jun 06 02:16:53 PM PDT 24
Peak memory 213224 kb
Host smart-625ae9b3-cd0a-49b6-9cfb-d7c06fe05ed9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608528272 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.2608528272
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.369161390
Short name T299
Test name
Test status
Simulation time 4987618283 ps
CPU time 15 seconds
Started Jun 06 02:16:56 PM PDT 24
Finished Jun 06 02:17:12 PM PDT 24
Peak memory 205028 kb
Host smart-dc70628a-d6f5-4856-8e92-6c20a7469671
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369161390 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
rv_dm_jtag_dmi_csr_bit_bash.369161390
Directory /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.3103541213
Short name T404
Test name
Test status
Simulation time 2768966394 ps
CPU time 4.93 seconds
Started Jun 06 02:16:55 PM PDT 24
Finished Jun 06 02:17:01 PM PDT 24
Peak memory 204944 kb
Host smart-e15dcaf9-889c-4970-9821-dabd67e8a5a9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103541213 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
3103541213
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2028645200
Short name T284
Test name
Test status
Simulation time 488365674 ps
CPU time 1.1 seconds
Started Jun 06 02:16:57 PM PDT 24
Finished Jun 06 02:16:59 PM PDT 24
Peak memory 204720 kb
Host smart-ff15e89c-2430-4cb7-ab57-aeb6eca16e99
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028645200 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
2028645200
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2431497780
Short name T115
Test name
Test status
Simulation time 321401896 ps
CPU time 6.3 seconds
Started Jun 06 02:16:55 PM PDT 24
Finished Jun 06 02:17:02 PM PDT 24
Peak memory 205060 kb
Host smart-3a1d9b77-5b33-462d-9a69-b6dee1ed31de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431497780 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.2431497780
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.2365994506
Short name T85
Test name
Test status
Simulation time 155755488 ps
CPU time 4.71 seconds
Started Jun 06 02:16:48 PM PDT 24
Finished Jun 06 02:16:55 PM PDT 24
Peak memory 213452 kb
Host smart-308c4fed-7a18-4d98-9aa4-06f2e296728f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365994506 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.2365994506
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3506208551
Short name T406
Test name
Test status
Simulation time 3781591276 ps
CPU time 9.12 seconds
Started Jun 06 02:16:57 PM PDT 24
Finished Jun 06 02:17:07 PM PDT 24
Peak memory 219844 kb
Host smart-846488e0-57db-4d23-9059-68ec67cabcaf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506208551 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.3506208551
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.1267079031
Short name T366
Test name
Test status
Simulation time 175758744 ps
CPU time 1.71 seconds
Started Jun 06 02:16:59 PM PDT 24
Finished Jun 06 02:17:02 PM PDT 24
Peak memory 213180 kb
Host smart-bae42b00-15b0-4ad6-a47f-ab1c993bfe46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267079031 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.1267079031
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.2876753758
Short name T294
Test name
Test status
Simulation time 35075029843 ps
CPU time 53.97 seconds
Started Jun 06 02:16:48 PM PDT 24
Finished Jun 06 02:17:44 PM PDT 24
Peak memory 205032 kb
Host smart-f3ff19c2-c646-4421-912d-f1b3b0f03d0e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876753758 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.rv_dm_jtag_dmi_csr_bit_bash.2876753758
Directory /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1020521405
Short name T268
Test name
Test status
Simulation time 17769849850 ps
CPU time 12.87 seconds
Started Jun 06 02:16:54 PM PDT 24
Finished Jun 06 02:17:08 PM PDT 24
Peak memory 205008 kb
Host smart-b2404f70-eb9f-44b9-84f7-77eb227dc600
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020521405 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
1020521405
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2259039614
Short name T381
Test name
Test status
Simulation time 1387250956 ps
CPU time 2.42 seconds
Started Jun 06 02:16:58 PM PDT 24
Finished Jun 06 02:17:02 PM PDT 24
Peak memory 204724 kb
Host smart-3ed38c6a-315a-4613-8044-bbb04e9b701a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259039614 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
2259039614
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3520859514
Short name T91
Test name
Test status
Simulation time 530696384 ps
CPU time 8.01 seconds
Started Jun 06 02:17:00 PM PDT 24
Finished Jun 06 02:17:09 PM PDT 24
Peak memory 205148 kb
Host smart-6cd31f04-8e56-45db-b4ba-d8e80adc2767
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520859514 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.3520859514
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.1199824448
Short name T309
Test name
Test status
Simulation time 384809943 ps
CPU time 2.74 seconds
Started Jun 06 02:16:47 PM PDT 24
Finished Jun 06 02:16:52 PM PDT 24
Peak memory 213408 kb
Host smart-6f848633-6bbe-4ad8-a626-6cc15a3d1730
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199824448 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.1199824448
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3059236653
Short name T134
Test name
Test status
Simulation time 855394504 ps
CPU time 11.54 seconds
Started Jun 06 02:16:59 PM PDT 24
Finished Jun 06 02:17:12 PM PDT 24
Peak memory 221468 kb
Host smart-e4e1ca0e-7b49-45fa-b752-5c0c1d8c0924
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059236653 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.3
059236653
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1208525877
Short name T310
Test name
Test status
Simulation time 4360721077 ps
CPU time 3.93 seconds
Started Jun 06 02:17:02 PM PDT 24
Finished Jun 06 02:17:07 PM PDT 24
Peak memory 213496 kb
Host smart-3f5a42cb-fc49-4779-a8a6-761e3c40e5f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208525877 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.1208525877
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.192354020
Short name T114
Test name
Test status
Simulation time 711081944 ps
CPU time 1.86 seconds
Started Jun 06 02:17:02 PM PDT 24
Finished Jun 06 02:17:05 PM PDT 24
Peak memory 213176 kb
Host smart-ea2b7a96-801a-4e6d-8ff5-9aac8fc1fd31
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192354020 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.192354020
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.3642921532
Short name T375
Test name
Test status
Simulation time 13193234603 ps
CPU time 14.17 seconds
Started Jun 06 02:17:00 PM PDT 24
Finished Jun 06 02:17:16 PM PDT 24
Peak memory 205040 kb
Host smart-3fcd69ec-f241-4bea-a703-1708b7501254
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642921532 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.rv_dm_jtag_dmi_csr_bit_bash.3642921532
Directory /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3812837646
Short name T315
Test name
Test status
Simulation time 6819827493 ps
CPU time 10.21 seconds
Started Jun 06 02:17:01 PM PDT 24
Finished Jun 06 02:17:13 PM PDT 24
Peak memory 205012 kb
Host smart-c6303b02-cb14-487d-88cb-622a62d9970f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812837646 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
3812837646
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.2374597435
Short name T278
Test name
Test status
Simulation time 468045720 ps
CPU time 1.04 seconds
Started Jun 06 02:17:01 PM PDT 24
Finished Jun 06 02:17:04 PM PDT 24
Peak memory 204696 kb
Host smart-b88d95fa-e1a4-49ae-b95c-1bfdce0be5b2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374597435 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
2374597435
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.2635963213
Short name T327
Test name
Test status
Simulation time 433622622 ps
CPU time 7.54 seconds
Started Jun 06 02:16:59 PM PDT 24
Finished Jun 06 02:17:08 PM PDT 24
Peak memory 205116 kb
Host smart-8bcf2e63-dea6-4e14-ae60-f21f4f3092e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635963213 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.2635963213
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.2168503295
Short name T301
Test name
Test status
Simulation time 81982674 ps
CPU time 4.61 seconds
Started Jun 06 02:16:57 PM PDT 24
Finished Jun 06 02:17:03 PM PDT 24
Peak memory 213352 kb
Host smart-87b0b9b0-3557-4e87-965a-df945d07706d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168503295 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.2168503295
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.873559298
Short name T378
Test name
Test status
Simulation time 1298916946 ps
CPU time 9.95 seconds
Started Jun 06 02:17:17 PM PDT 24
Finished Jun 06 02:17:27 PM PDT 24
Peak memory 213300 kb
Host smart-29ce6f8e-d849-4152-9405-5c27cd1f9d17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873559298 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.873559298
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.313765548
Short name T306
Test name
Test status
Simulation time 178198769 ps
CPU time 2.42 seconds
Started Jun 06 02:16:57 PM PDT 24
Finished Jun 06 02:17:00 PM PDT 24
Peak memory 215496 kb
Host smart-018ddf2e-d668-48ab-8cf9-ec77ff95c5ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313765548 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.313765548
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.742905211
Short name T113
Test name
Test status
Simulation time 394213743 ps
CPU time 1.81 seconds
Started Jun 06 02:17:00 PM PDT 24
Finished Jun 06 02:17:03 PM PDT 24
Peak memory 213224 kb
Host smart-3f5c7183-1c71-42ea-96c3-023e68e18b44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742905211 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.742905211
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.60815868
Short name T387
Test name
Test status
Simulation time 55541477593 ps
CPU time 76.48 seconds
Started Jun 06 02:17:02 PM PDT 24
Finished Jun 06 02:18:20 PM PDT 24
Peak memory 205032 kb
Host smart-235a13f9-ed19-41e6-aec0-c90cee0d9a46
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60815868 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.r
v_dm_jtag_dmi_csr_bit_bash.60815868
Directory /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.33800264
Short name T393
Test name
Test status
Simulation time 6224955865 ps
CPU time 6.92 seconds
Started Jun 06 02:16:59 PM PDT 24
Finished Jun 06 02:17:07 PM PDT 24
Peak memory 205000 kb
Host smart-85e1a7ab-1b3e-4117-a3c5-1d833063cde2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33800264 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.33800264
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.791791459
Short name T319
Test name
Test status
Simulation time 812021547 ps
CPU time 2.81 seconds
Started Jun 06 02:17:00 PM PDT 24
Finished Jun 06 02:17:04 PM PDT 24
Peak memory 204688 kb
Host smart-821769f4-04a6-46b1-9fe2-6d56606eb7bb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791791459 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.791791459
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1874553243
Short name T119
Test name
Test status
Simulation time 1417467555 ps
CPU time 6.4 seconds
Started Jun 06 02:17:09 PM PDT 24
Finished Jun 06 02:17:16 PM PDT 24
Peak memory 205064 kb
Host smart-bca0d85a-81fd-4888-a0b9-625d47f1ac52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874553243 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.1874553243
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.72988960
Short name T320
Test name
Test status
Simulation time 270198406 ps
CPU time 4.09 seconds
Started Jun 06 02:16:59 PM PDT 24
Finished Jun 06 02:17:05 PM PDT 24
Peak memory 213304 kb
Host smart-1027463d-fefd-4103-b99e-df0641b5f57d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72988960 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.72988960
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.1014435697
Short name T282
Test name
Test status
Simulation time 3858239562 ps
CPU time 6.29 seconds
Started Jun 06 02:16:58 PM PDT 24
Finished Jun 06 02:17:06 PM PDT 24
Peak memory 221596 kb
Host smart-755d9352-34ec-47ab-87aa-d1081d262f31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014435697 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.1014435697
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.1481754331
Short name T409
Test name
Test status
Simulation time 26888803786 ps
CPU time 69.7 seconds
Started Jun 06 02:16:59 PM PDT 24
Finished Jun 06 02:18:10 PM PDT 24
Peak memory 205008 kb
Host smart-f3a3efb1-aad8-4d49-a05b-c5a71847ca3a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481754331 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.rv_dm_jtag_dmi_csr_bit_bash.1481754331
Directory /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2509027418
Short name T291
Test name
Test status
Simulation time 1646703308 ps
CPU time 4.68 seconds
Started Jun 06 02:16:57 PM PDT 24
Finished Jun 06 02:17:03 PM PDT 24
Peak memory 204916 kb
Host smart-891633ed-5c3d-4d2e-97c9-3f745327852d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509027418 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
2509027418
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.1611484145
Short name T290
Test name
Test status
Simulation time 545106191 ps
CPU time 0.93 seconds
Started Jun 06 02:17:01 PM PDT 24
Finished Jun 06 02:17:03 PM PDT 24
Peak memory 204716 kb
Host smart-ed775f07-74bd-40fa-86c2-e23ac3af0b35
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611484145 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
1611484145
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.1521889191
Short name T400
Test name
Test status
Simulation time 801384860 ps
CPU time 3.73 seconds
Started Jun 06 02:16:57 PM PDT 24
Finished Jun 06 02:17:02 PM PDT 24
Peak memory 205116 kb
Host smart-47da0b4e-3c4e-442d-a11b-ac9f423f0775
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521889191 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.1521889191
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.3822194874
Short name T279
Test name
Test status
Simulation time 83697339 ps
CPU time 3.01 seconds
Started Jun 06 02:16:59 PM PDT 24
Finished Jun 06 02:17:04 PM PDT 24
Peak memory 213488 kb
Host smart-6a4ebdc8-1a71-4861-943e-e294eeaa1762
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822194874 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.3822194874
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2537357176
Short name T389
Test name
Test status
Simulation time 10382392071 ps
CPU time 18.81 seconds
Started Jun 06 02:17:02 PM PDT 24
Finished Jun 06 02:17:22 PM PDT 24
Peak memory 213436 kb
Host smart-21b64ab5-4b9e-4f40-807f-2074a9a9087b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537357176 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.2
537357176
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.3063387088
Short name T371
Test name
Test status
Simulation time 591081939 ps
CPU time 4.21 seconds
Started Jun 06 02:17:07 PM PDT 24
Finished Jun 06 02:17:12 PM PDT 24
Peak memory 221356 kb
Host smart-bbdf2f6c-8d9f-49fb-be43-a39a5d3df616
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063387088 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.3063387088
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2679240525
Short name T100
Test name
Test status
Simulation time 133842857 ps
CPU time 2.43 seconds
Started Jun 06 02:16:59 PM PDT 24
Finished Jun 06 02:17:02 PM PDT 24
Peak memory 213208 kb
Host smart-b2bda9d8-f3b4-4898-aa1b-7ffa6a9f7f75
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679240525 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.2679240525
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.1098656516
Short name T358
Test name
Test status
Simulation time 19820260051 ps
CPU time 31.02 seconds
Started Jun 06 02:16:58 PM PDT 24
Finished Jun 06 02:17:30 PM PDT 24
Peak memory 205028 kb
Host smart-8139b752-76dc-441b-9cc2-1db6ecf690a5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098656516 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.rv_dm_jtag_dmi_csr_bit_bash.1098656516
Directory /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.133563229
Short name T386
Test name
Test status
Simulation time 10644692805 ps
CPU time 15.4 seconds
Started Jun 06 02:17:04 PM PDT 24
Finished Jun 06 02:17:21 PM PDT 24
Peak memory 205048 kb
Host smart-2c3cf119-7638-4335-8ae4-65937a7202a4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133563229 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.133563229
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.3834937159
Short name T394
Test name
Test status
Simulation time 1297623732 ps
CPU time 2.55 seconds
Started Jun 06 02:17:02 PM PDT 24
Finished Jun 06 02:17:06 PM PDT 24
Peak memory 204672 kb
Host smart-ed1be1bf-a1be-4aab-81b0-e19692161b6a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834937159 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
3834937159
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3005088711
Short name T349
Test name
Test status
Simulation time 976853608 ps
CPU time 8.55 seconds
Started Jun 06 02:17:02 PM PDT 24
Finished Jun 06 02:17:11 PM PDT 24
Peak memory 205088 kb
Host smart-4a3e645f-95db-48de-929a-4eba85b589e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005088711 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.3005088711
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.1276978039
Short name T84
Test name
Test status
Simulation time 104233306 ps
CPU time 5.81 seconds
Started Jun 06 02:16:59 PM PDT 24
Finished Jun 06 02:17:07 PM PDT 24
Peak memory 213348 kb
Host smart-17860c84-3394-4ed1-9166-93e1166e57eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276978039 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.1276978039
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.1881351461
Short name T130
Test name
Test status
Simulation time 2140384097 ps
CPU time 10.61 seconds
Started Jun 06 02:17:00 PM PDT 24
Finished Jun 06 02:17:12 PM PDT 24
Peak memory 221460 kb
Host smart-6f3a8ae3-a4ce-4939-a1bc-6c92dde3324b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881351461 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.1
881351461
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2980575669
Short name T348
Test name
Test status
Simulation time 828967773 ps
CPU time 2.7 seconds
Started Jun 06 02:17:01 PM PDT 24
Finished Jun 06 02:17:05 PM PDT 24
Peak memory 217748 kb
Host smart-031c8963-3c62-43b3-9c59-0ccffdcd673b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980575669 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.2980575669
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.947244772
Short name T377
Test name
Test status
Simulation time 150522843 ps
CPU time 2.25 seconds
Started Jun 06 02:16:59 PM PDT 24
Finished Jun 06 02:17:03 PM PDT 24
Peak memory 213284 kb
Host smart-19648aeb-61f6-4c73-8dcd-0b61adba1f8d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947244772 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.947244772
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.423533388
Short name T341
Test name
Test status
Simulation time 20968815208 ps
CPU time 59.66 seconds
Started Jun 06 02:17:01 PM PDT 24
Finished Jun 06 02:18:02 PM PDT 24
Peak memory 205056 kb
Host smart-aa784545-6adf-4488-b31f-126d2497efc8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423533388 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
rv_dm_jtag_dmi_csr_bit_bash.423533388
Directory /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.3831575844
Short name T355
Test name
Test status
Simulation time 9036748110 ps
CPU time 14.03 seconds
Started Jun 06 02:16:58 PM PDT 24
Finished Jun 06 02:17:13 PM PDT 24
Peak memory 205012 kb
Host smart-c4e4dbe5-aafb-43b5-a7f5-6748a6911b64
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831575844 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
3831575844
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.664265100
Short name T298
Test name
Test status
Simulation time 447758522 ps
CPU time 1.83 seconds
Started Jun 06 02:17:01 PM PDT 24
Finished Jun 06 02:17:04 PM PDT 24
Peak memory 204740 kb
Host smart-f246695d-f24f-4bfc-8420-3c372eec8630
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664265100 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.664265100
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.2766114849
Short name T333
Test name
Test status
Simulation time 2067812428 ps
CPU time 4.1 seconds
Started Jun 06 02:17:01 PM PDT 24
Finished Jun 06 02:17:06 PM PDT 24
Peak memory 205132 kb
Host smart-61b56ecf-1d39-4124-a266-82ac7b1f1e6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766114849 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.2766114849
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3748897816
Short name T382
Test name
Test status
Simulation time 673568982 ps
CPU time 5.6 seconds
Started Jun 06 02:16:59 PM PDT 24
Finished Jun 06 02:17:06 PM PDT 24
Peak memory 213328 kb
Host smart-d1325f48-ff87-408c-bbde-13ab8c3b3dd5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748897816 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.3748897816
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2955979953
Short name T83
Test name
Test status
Simulation time 1546129638 ps
CPU time 11.01 seconds
Started Jun 06 02:17:01 PM PDT 24
Finished Jun 06 02:17:13 PM PDT 24
Peak memory 213304 kb
Host smart-33459e0e-38a5-4d6f-b783-ae4ea746237d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955979953 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.2
955979953
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.3880785660
Short name T92
Test name
Test status
Simulation time 6949170231 ps
CPU time 70.82 seconds
Started Jun 06 02:16:28 PM PDT 24
Finished Jun 06 02:17:40 PM PDT 24
Peak memory 213364 kb
Host smart-4d64a675-862f-401b-9866-e18a031c6446
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880785660 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.3880785660
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.1627534463
Short name T340
Test name
Test status
Simulation time 9809331943 ps
CPU time 35 seconds
Started Jun 06 02:16:43 PM PDT 24
Finished Jun 06 02:17:20 PM PDT 24
Peak memory 213340 kb
Host smart-66c768cf-6c22-41d6-9af2-54816a3a7f97
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627534463 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.1627534463
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.2587104855
Short name T363
Test name
Test status
Simulation time 169496432 ps
CPU time 1.54 seconds
Started Jun 06 02:16:43 PM PDT 24
Finished Jun 06 02:16:46 PM PDT 24
Peak memory 213184 kb
Host smart-5b972577-4115-4156-83a3-2deab66a995d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587104855 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.2587104855
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.371171545
Short name T128
Test name
Test status
Simulation time 2403580633 ps
CPU time 7.74 seconds
Started Jun 06 02:16:41 PM PDT 24
Finished Jun 06 02:16:50 PM PDT 24
Peak memory 220416 kb
Host smart-d4972edc-a78d-40a1-b00e-5baa027a8dca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371171545 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.371171545
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.2005589941
Short name T347
Test name
Test status
Simulation time 87246049 ps
CPU time 1.53 seconds
Started Jun 06 02:16:41 PM PDT 24
Finished Jun 06 02:16:44 PM PDT 24
Peak memory 213200 kb
Host smart-edbc6fca-94ef-40b9-8826-976907cc8d24
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005589941 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.2005589941
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.4065049421
Short name T367
Test name
Test status
Simulation time 68555937633 ps
CPU time 184.69 seconds
Started Jun 06 02:16:38 PM PDT 24
Finished Jun 06 02:19:43 PM PDT 24
Peak memory 205064 kb
Host smart-8a887b36-37b6-4627-b26f-f3c7f461e4ed
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065049421 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.4065049421
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.3325689972
Short name T308
Test name
Test status
Simulation time 58978029 ps
CPU time 0.71 seconds
Started Jun 06 02:16:41 PM PDT 24
Finished Jun 06 02:16:43 PM PDT 24
Peak memory 204688 kb
Host smart-ccd70ef8-94a5-4bff-9089-cec2cc927fee
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325689972 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
rv_dm_jtag_dmi_csr_bit_bash.3325689972
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.3499371406
Short name T262
Test name
Test status
Simulation time 2248914040 ps
CPU time 6.77 seconds
Started Jun 06 02:16:40 PM PDT 24
Finished Jun 06 02:16:48 PM PDT 24
Peak memory 204984 kb
Host smart-2e647f78-4c0e-4ee4-ab62-f8773b5925d6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499371406 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.3499371406
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.3376748596
Short name T265
Test name
Test status
Simulation time 6174587507 ps
CPU time 9.3 seconds
Started Jun 06 02:16:43 PM PDT 24
Finished Jun 06 02:16:53 PM PDT 24
Peak memory 205044 kb
Host smart-ef9e9934-df1b-40d0-a584-c7600089a491
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376748596 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.3
376748596
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.472355010
Short name T345
Test name
Test status
Simulation time 822794715 ps
CPU time 3.14 seconds
Started Jun 06 02:16:43 PM PDT 24
Finished Jun 06 02:16:47 PM PDT 24
Peak memory 204664 kb
Host smart-0cc1677f-b71d-4768-a1a0-129a4eb080ca
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472355010 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_aliasing.472355010
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1521656743
Short name T302
Test name
Test status
Simulation time 25839836114 ps
CPU time 21.08 seconds
Started Jun 06 02:16:40 PM PDT 24
Finished Jun 06 02:17:03 PM PDT 24
Peak memory 204964 kb
Host smart-02279556-b9cf-424d-931d-ca02c72ff7ad
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521656743 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.1521656743
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2028358357
Short name T373
Test name
Test status
Simulation time 232187204 ps
CPU time 1.31 seconds
Started Jun 06 02:16:27 PM PDT 24
Finished Jun 06 02:16:29 PM PDT 24
Peak memory 204752 kb
Host smart-a3f00a1c-3b3d-42ba-88a8-ce23f7a43cfb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028358357 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.2028358357
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.22140730
Short name T383
Test name
Test status
Simulation time 425122198 ps
CPU time 1.33 seconds
Started Jun 06 02:16:40 PM PDT 24
Finished Jun 06 02:16:42 PM PDT 24
Peak memory 204732 kb
Host smart-4bee516a-f418-4ede-8290-289b7de0d08b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22140730 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.22140730
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2695949043
Short name T391
Test name
Test status
Simulation time 133545635 ps
CPU time 0.92 seconds
Started Jun 06 02:16:38 PM PDT 24
Finished Jun 06 02:16:39 PM PDT 24
Peak memory 204756 kb
Host smart-470d91e1-22e2-402f-a378-555ae17bbfea
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695949043 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.2695949043
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.2923657652
Short name T263
Test name
Test status
Simulation time 110077015 ps
CPU time 0.69 seconds
Started Jun 06 02:16:44 PM PDT 24
Finished Jun 06 02:16:47 PM PDT 24
Peak memory 204772 kb
Host smart-94e228b6-721b-4151-a857-a1e8aa79d7e8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923657652 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.2923657652
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.1178156127
Short name T120
Test name
Test status
Simulation time 1031247204 ps
CPU time 8.31 seconds
Started Jun 06 02:16:42 PM PDT 24
Finished Jun 06 02:16:51 PM PDT 24
Peak memory 205072 kb
Host smart-ba23aa23-5356-48c3-87e0-900c7ed291fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178156127 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.1178156127
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.3916998464
Short name T46
Test name
Test status
Simulation time 45811221326 ps
CPU time 65.87 seconds
Started Jun 06 02:16:42 PM PDT 24
Finished Jun 06 02:17:49 PM PDT 24
Peak memory 221668 kb
Host smart-70cf1145-5169-48ce-bf3d-f0a614e422f4
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916998464 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.3916998464
Directory /workspace/2.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.3249812981
Short name T280
Test name
Test status
Simulation time 232895104 ps
CPU time 4.92 seconds
Started Jun 06 02:16:44 PM PDT 24
Finished Jun 06 02:16:51 PM PDT 24
Peak memory 213380 kb
Host smart-a8779f63-2a09-4051-a8bc-089881831e76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249812981 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.3249812981
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.583326522
Short name T353
Test name
Test status
Simulation time 1364281214 ps
CPU time 10.25 seconds
Started Jun 06 02:16:42 PM PDT 24
Finished Jun 06 02:16:53 PM PDT 24
Peak memory 213280 kb
Host smart-5e8972d5-d586-4b89-a7b4-ce9db6cdb26f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583326522 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.583326522
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.837413823
Short name T107
Test name
Test status
Simulation time 2327203540 ps
CPU time 66.63 seconds
Started Jun 06 02:16:39 PM PDT 24
Finished Jun 06 02:17:46 PM PDT 24
Peak memory 205132 kb
Host smart-3816fe26-d159-4d30-bdef-80182bb038cf
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837413823 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.rv_dm_csr_aliasing.837413823
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.3857087413
Short name T112
Test name
Test status
Simulation time 9875830757 ps
CPU time 69.29 seconds
Started Jun 06 02:16:41 PM PDT 24
Finished Jun 06 02:17:51 PM PDT 24
Peak memory 213372 kb
Host smart-9aa6a870-f8b0-4d1c-bf34-534839b74edd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857087413 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.3857087413
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.2839202712
Short name T88
Test name
Test status
Simulation time 1140983139 ps
CPU time 1.64 seconds
Started Jun 06 02:16:43 PM PDT 24
Finished Jun 06 02:16:47 PM PDT 24
Peak memory 213204 kb
Host smart-3adacd15-c088-43f4-b524-e05af21d0dd5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839202712 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.2839202712
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.782841025
Short name T86
Test name
Test status
Simulation time 2414862154 ps
CPU time 4.32 seconds
Started Jun 06 02:16:40 PM PDT 24
Finished Jun 06 02:16:45 PM PDT 24
Peak memory 220028 kb
Host smart-fffe7921-0b30-44e8-afca-1ffb16ad761e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782841025 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.782841025
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2545981714
Short name T350
Test name
Test status
Simulation time 256133425 ps
CPU time 1.72 seconds
Started Jun 06 02:16:41 PM PDT 24
Finished Jun 06 02:16:44 PM PDT 24
Peak memory 213208 kb
Host smart-2170621d-65bc-45fe-a7d4-8635c625643c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545981714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.2545981714
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.3312918866
Short name T304
Test name
Test status
Simulation time 30056182940 ps
CPU time 39.55 seconds
Started Jun 06 02:16:40 PM PDT 24
Finished Jun 06 02:17:21 PM PDT 24
Peak memory 205048 kb
Host smart-f1e9fb9f-8843-4a54-a69d-d860eb255603
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312918866 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.3312918866
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.737109976
Short name T376
Test name
Test status
Simulation time 75932030456 ps
CPU time 20.28 seconds
Started Jun 06 02:17:01 PM PDT 24
Finished Jun 06 02:17:23 PM PDT 24
Peak memory 205036 kb
Host smart-bea82f19-d706-4e3f-8b06-8875a3c448fd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737109976 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.r
v_dm_jtag_dmi_csr_bit_bash.737109976
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.240997412
Short name T98
Test name
Test status
Simulation time 15944552935 ps
CPU time 44.1 seconds
Started Jun 06 02:16:43 PM PDT 24
Finished Jun 06 02:17:29 PM PDT 24
Peak memory 205212 kb
Host smart-bf240015-6d96-402d-9a9f-314d2e182d87
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240997412 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr
_hw_reset.240997412
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.4054299835
Short name T297
Test name
Test status
Simulation time 6568893889 ps
CPU time 9.03 seconds
Started Jun 06 02:16:37 PM PDT 24
Finished Jun 06 02:16:46 PM PDT 24
Peak memory 205032 kb
Host smart-d78c3061-2b1d-44e5-b035-427bba26edc5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054299835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.4
054299835
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3054595549
Short name T321
Test name
Test status
Simulation time 1469943371 ps
CPU time 4.65 seconds
Started Jun 06 02:16:42 PM PDT 24
Finished Jun 06 02:16:48 PM PDT 24
Peak memory 204712 kb
Host smart-e44e9548-ba8d-4e75-9460-704f1ceb494c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054595549 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.3054595549
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.30450694
Short name T314
Test name
Test status
Simulation time 5037522149 ps
CPU time 4.43 seconds
Started Jun 06 02:16:44 PM PDT 24
Finished Jun 06 02:16:51 PM PDT 24
Peak memory 205084 kb
Host smart-81f7db35-62c4-41ca-9248-61a66b6a6306
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30450694 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_
bit_bash.30450694
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.2617407736
Short name T322
Test name
Test status
Simulation time 214770432 ps
CPU time 1.21 seconds
Started Jun 06 02:16:40 PM PDT 24
Finished Jun 06 02:16:42 PM PDT 24
Peak memory 204744 kb
Host smart-3eaa92e6-741c-4fc9-9b57-5192263b821b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617407736 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.2617407736
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.3947677939
Short name T305
Test name
Test status
Simulation time 516022193 ps
CPU time 1.37 seconds
Started Jun 06 02:16:38 PM PDT 24
Finished Jun 06 02:16:40 PM PDT 24
Peak memory 204716 kb
Host smart-25d1add1-4a16-4c6b-b636-a6a58ee40c30
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947677939 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.3
947677939
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.2926550955
Short name T385
Test name
Test status
Simulation time 44310934 ps
CPU time 0.71 seconds
Started Jun 06 02:16:44 PM PDT 24
Finished Jun 06 02:16:47 PM PDT 24
Peak memory 204796 kb
Host smart-acbfc003-8a80-404d-9f8e-d5392a518574
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926550955 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.2926550955
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1632447568
Short name T295
Test name
Test status
Simulation time 100090902 ps
CPU time 0.71 seconds
Started Jun 06 02:16:43 PM PDT 24
Finished Jun 06 02:16:45 PM PDT 24
Peak memory 204740 kb
Host smart-83575721-394f-43e0-a40d-803e72b76337
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632447568 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.1632447568
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.1971343317
Short name T103
Test name
Test status
Simulation time 544142207 ps
CPU time 6.74 seconds
Started Jun 06 02:16:38 PM PDT 24
Finished Jun 06 02:16:45 PM PDT 24
Peak memory 205100 kb
Host smart-40a9bddb-7713-4432-b900-6188484fc34f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971343317 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_
csr_outstanding.1971343317
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.3028062338
Short name T139
Test name
Test status
Simulation time 25213756269 ps
CPU time 78.82 seconds
Started Jun 06 02:16:42 PM PDT 24
Finished Jun 06 02:18:02 PM PDT 24
Peak memory 221560 kb
Host smart-f6048282-2e5d-42e3-9d1b-21205e2ec734
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028062338 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.3028062338
Directory /workspace/3.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.3864601825
Short name T288
Test name
Test status
Simulation time 1193722854 ps
CPU time 4.32 seconds
Started Jun 06 02:16:39 PM PDT 24
Finished Jun 06 02:16:44 PM PDT 24
Peak memory 215768 kb
Host smart-39b59e3d-8477-493c-9050-6c00f389905b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864601825 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.3864601825
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.1039377300
Short name T346
Test name
Test status
Simulation time 3671528483 ps
CPU time 27.65 seconds
Started Jun 06 02:16:43 PM PDT 24
Finished Jun 06 02:17:12 PM PDT 24
Peak memory 213316 kb
Host smart-ca7565b2-ef29-40a8-a337-babcd291d66e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039377300 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.1039377300
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.123818444
Short name T352
Test name
Test status
Simulation time 25718012837 ps
CPU time 67.76 seconds
Started Jun 06 02:16:43 PM PDT 24
Finished Jun 06 02:17:52 PM PDT 24
Peak memory 213364 kb
Host smart-69c7688f-9e55-4140-b4d9-0e6b69b24c8c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123818444 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.123818444
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.236747749
Short name T332
Test name
Test status
Simulation time 401549755 ps
CPU time 2.62 seconds
Started Jun 06 02:16:40 PM PDT 24
Finished Jun 06 02:16:44 PM PDT 24
Peak memory 213632 kb
Host smart-4430c0bf-1c16-4ef3-b8f5-22c3e50661e9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236747749 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.236747749
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.4180211687
Short name T82
Test name
Test status
Simulation time 4118271540 ps
CPU time 6.83 seconds
Started Jun 06 02:16:41 PM PDT 24
Finished Jun 06 02:16:49 PM PDT 24
Peak memory 221520 kb
Host smart-68f4f9e2-9957-4ed5-a2e8-8ecc6b1affcd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180211687 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.4180211687
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.3393141002
Short name T357
Test name
Test status
Simulation time 797917590 ps
CPU time 2.18 seconds
Started Jun 06 02:16:46 PM PDT 24
Finished Jun 06 02:16:51 PM PDT 24
Peak memory 213192 kb
Host smart-576ccda4-2e7a-4468-955f-9e1084df3b7c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393141002 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.3393141002
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.3965805190
Short name T359
Test name
Test status
Simulation time 80119122270 ps
CPU time 65.46 seconds
Started Jun 06 02:16:43 PM PDT 24
Finished Jun 06 02:17:50 PM PDT 24
Peak memory 204964 kb
Host smart-0d580531-a568-4b02-9fba-49d53392b40e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965805190 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.3965805190
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.1654139424
Short name T392
Test name
Test status
Simulation time 32581162258 ps
CPU time 25.75 seconds
Started Jun 06 02:16:45 PM PDT 24
Finished Jun 06 02:17:13 PM PDT 24
Peak memory 205044 kb
Host smart-b6974c41-7147-4200-b264-4411fe18cb59
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654139424 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
rv_dm_jtag_dmi_csr_bit_bash.1654139424
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.1864492833
Short name T96
Test name
Test status
Simulation time 7202057927 ps
CPU time 3.28 seconds
Started Jun 06 02:16:40 PM PDT 24
Finished Jun 06 02:16:44 PM PDT 24
Peak memory 205216 kb
Host smart-f74f73ce-99fd-4996-969d-f14638841fde
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864492833 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.1864492833
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.69721173
Short name T264
Test name
Test status
Simulation time 8218103872 ps
CPU time 7.43 seconds
Started Jun 06 02:16:40 PM PDT 24
Finished Jun 06 02:16:49 PM PDT 24
Peak memory 205012 kb
Host smart-08b87836-6b98-4735-b53f-5f152204ec51
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69721173 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.69721173
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.3497837612
Short name T287
Test name
Test status
Simulation time 369740995 ps
CPU time 1.18 seconds
Started Jun 06 02:16:38 PM PDT 24
Finished Jun 06 02:16:40 PM PDT 24
Peak memory 204724 kb
Host smart-314b7598-e62c-416a-9cf0-d4a9f5597709
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497837612 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.3497837612
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.3541912652
Short name T313
Test name
Test status
Simulation time 8704815406 ps
CPU time 6.88 seconds
Started Jun 06 02:16:40 PM PDT 24
Finished Jun 06 02:16:49 PM PDT 24
Peak memory 204964 kb
Host smart-9c1fd543-6f49-4f80-9709-2daffe7e9102
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541912652 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.3541912652
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.4238569679
Short name T286
Test name
Test status
Simulation time 516165762 ps
CPU time 2.09 seconds
Started Jun 06 02:16:39 PM PDT 24
Finished Jun 06 02:16:41 PM PDT 24
Peak memory 204752 kb
Host smart-102e7c49-fbb2-4b4c-a105-8642e709ccbb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238569679 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.4238569679
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.3478867385
Short name T395
Test name
Test status
Simulation time 412564413 ps
CPU time 1.7 seconds
Started Jun 06 02:16:47 PM PDT 24
Finished Jun 06 02:16:51 PM PDT 24
Peak memory 204688 kb
Host smart-d3aeae38-4912-4313-bd28-d2b2fc2c1481
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478867385 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.3
478867385
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.3712025196
Short name T260
Test name
Test status
Simulation time 141001330 ps
CPU time 0.94 seconds
Started Jun 06 02:16:40 PM PDT 24
Finished Jun 06 02:16:43 PM PDT 24
Peak memory 204676 kb
Host smart-e959aee4-d957-45c1-ad9e-59ca8d810090
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712025196 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.3712025196
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.2401078630
Short name T338
Test name
Test status
Simulation time 47202697 ps
CPU time 0.78 seconds
Started Jun 06 02:16:44 PM PDT 24
Finished Jun 06 02:16:47 PM PDT 24
Peak memory 204772 kb
Host smart-6c989c7e-0c22-48ef-ac35-baec848ec516
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401078630 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.2401078630
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1774584856
Short name T117
Test name
Test status
Simulation time 190435044 ps
CPU time 3.7 seconds
Started Jun 06 02:16:46 PM PDT 24
Finished Jun 06 02:16:52 PM PDT 24
Peak memory 205056 kb
Host smart-53a52bbe-fbe4-4463-895f-981d8e9ab655
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774584856 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.1774584856
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.460956658
Short name T56
Test name
Test status
Simulation time 1300039259 ps
CPU time 5.04 seconds
Started Jun 06 02:16:42 PM PDT 24
Finished Jun 06 02:16:48 PM PDT 24
Peak memory 221496 kb
Host smart-fb958c98-7561-40a7-9dc8-20f127cc48c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460956658 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.460956658
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1236010308
Short name T81
Test name
Test status
Simulation time 3629909224 ps
CPU time 21.35 seconds
Started Jun 06 02:16:37 PM PDT 24
Finished Jun 06 02:16:59 PM PDT 24
Peak memory 213352 kb
Host smart-10185b4e-cfbb-41f9-8190-b348bd52c183
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236010308 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.1236010308
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.632545460
Short name T336
Test name
Test status
Simulation time 503382856 ps
CPU time 2.54 seconds
Started Jun 06 02:16:45 PM PDT 24
Finished Jun 06 02:16:50 PM PDT 24
Peak memory 213448 kb
Host smart-bc5397d2-05f9-40d0-876f-f3e73fa2ff1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632545460 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.632545460
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.4069033938
Short name T379
Test name
Test status
Simulation time 274496136 ps
CPU time 2.2 seconds
Started Jun 06 02:16:38 PM PDT 24
Finished Jun 06 02:16:41 PM PDT 24
Peak memory 213304 kb
Host smart-fb192087-f7f1-427a-b1a4-534a4903ecaf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069033938 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.4069033938
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.2852550361
Short name T266
Test name
Test status
Simulation time 11495030974 ps
CPU time 31.15 seconds
Started Jun 06 02:16:46 PM PDT 24
Finished Jun 06 02:17:20 PM PDT 24
Peak memory 205036 kb
Host smart-4d2f85cf-38f4-4c12-a8c6-97de395d1353
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852550361 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
rv_dm_jtag_dmi_csr_bit_bash.2852550361
Directory /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.2727849889
Short name T276
Test name
Test status
Simulation time 2502174553 ps
CPU time 2.79 seconds
Started Jun 06 02:16:45 PM PDT 24
Finished Jun 06 02:16:50 PM PDT 24
Peak memory 204984 kb
Host smart-0cea1ff5-327d-49b3-a12b-15ada03292de
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727849889 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.2
727849889
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.1446111038
Short name T289
Test name
Test status
Simulation time 108457617 ps
CPU time 0.94 seconds
Started Jun 06 02:16:43 PM PDT 24
Finished Jun 06 02:16:46 PM PDT 24
Peak memory 204744 kb
Host smart-4ea33a65-b765-44a1-9c29-c46d9e01d08b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446111038 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.1
446111038
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.514027408
Short name T374
Test name
Test status
Simulation time 653548931 ps
CPU time 4.33 seconds
Started Jun 06 02:16:46 PM PDT 24
Finished Jun 06 02:16:52 PM PDT 24
Peak memory 205108 kb
Host smart-0081fde2-4d1e-47de-9d30-c8a70be4b535
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514027408 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_c
sr_outstanding.514027408
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.3421809770
Short name T361
Test name
Test status
Simulation time 25026635111 ps
CPU time 70.06 seconds
Started Jun 06 02:16:40 PM PDT 24
Finished Jun 06 02:17:52 PM PDT 24
Peak memory 220580 kb
Host smart-de2e7b3a-c4e6-49ae-b937-dc11dfba5b21
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421809770 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.3421809770
Directory /workspace/5.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.921700960
Short name T328
Test name
Test status
Simulation time 554444859 ps
CPU time 4.58 seconds
Started Jun 06 02:16:40 PM PDT 24
Finished Jun 06 02:16:45 PM PDT 24
Peak memory 213292 kb
Host smart-33b405ba-b3fd-43c2-81b3-497ccb1f2fc5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921700960 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.921700960
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.599409140
Short name T369
Test name
Test status
Simulation time 1670654419 ps
CPU time 17.93 seconds
Started Jun 06 02:16:40 PM PDT 24
Finished Jun 06 02:17:00 PM PDT 24
Peak memory 213284 kb
Host smart-17e0f4f4-5cd6-4d2d-b192-ccb7431a69f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599409140 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.599409140
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.4081062101
Short name T80
Test name
Test status
Simulation time 1222584985 ps
CPU time 4.22 seconds
Started Jun 06 02:16:58 PM PDT 24
Finished Jun 06 02:17:03 PM PDT 24
Peak memory 219872 kb
Host smart-830ce8a6-7476-4333-a6c8-2f3e88a35e4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081062101 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.4081062101
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1125931795
Short name T90
Test name
Test status
Simulation time 1394574175 ps
CPU time 2.47 seconds
Started Jun 06 02:16:49 PM PDT 24
Finished Jun 06 02:16:54 PM PDT 24
Peak memory 213196 kb
Host smart-b61aa2c9-b924-42cf-9afe-217fd5600885
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125931795 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.1125931795
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.2377396645
Short name T364
Test name
Test status
Simulation time 44305431480 ps
CPU time 35.05 seconds
Started Jun 06 02:16:40 PM PDT 24
Finished Jun 06 02:17:16 PM PDT 24
Peak memory 205028 kb
Host smart-6b64e296-4a74-416e-9d89-6a61abfbbe1f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377396645 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
rv_dm_jtag_dmi_csr_bit_bash.2377396645
Directory /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.3454179963
Short name T388
Test name
Test status
Simulation time 1116385588 ps
CPU time 2.42 seconds
Started Jun 06 02:16:46 PM PDT 24
Finished Jun 06 02:16:50 PM PDT 24
Peak memory 204904 kb
Host smart-8ae6b0b0-bef0-4557-a1e9-1eefe9dc532d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454179963 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.3
454179963
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2972764098
Short name T403
Test name
Test status
Simulation time 774102418 ps
CPU time 2.86 seconds
Started Jun 06 02:16:40 PM PDT 24
Finished Jun 06 02:16:45 PM PDT 24
Peak memory 204628 kb
Host smart-dcaadeb9-eaa2-408b-a45b-cfdaf6fd25c0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972764098 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.2
972764098
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.743792841
Short name T94
Test name
Test status
Simulation time 1071616224 ps
CPU time 4.6 seconds
Started Jun 06 02:16:53 PM PDT 24
Finished Jun 06 02:16:59 PM PDT 24
Peak memory 205088 kb
Host smart-582566e0-ae8f-45ed-9738-803e5957f3e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743792841 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_c
sr_outstanding.743792841
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.269985464
Short name T334
Test name
Test status
Simulation time 65280136 ps
CPU time 2.64 seconds
Started Jun 06 02:16:43 PM PDT 24
Finished Jun 06 02:16:48 PM PDT 24
Peak memory 213380 kb
Host smart-f24ce726-6f45-4c7b-9a5f-6ff694503ee4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269985464 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.269985464
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.773729111
Short name T133
Test name
Test status
Simulation time 7260983701 ps
CPU time 23.75 seconds
Started Jun 06 02:16:45 PM PDT 24
Finished Jun 06 02:17:11 PM PDT 24
Peak memory 213436 kb
Host smart-b03f481e-f11f-4677-ba59-b99bdd431d6f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773729111 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.773729111
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.1249062967
Short name T360
Test name
Test status
Simulation time 141282840 ps
CPU time 2.66 seconds
Started Jun 06 02:16:48 PM PDT 24
Finished Jun 06 02:16:53 PM PDT 24
Peak memory 218008 kb
Host smart-605c4a81-9114-46f4-b009-a7609d56e87b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249062967 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.1249062967
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.921439102
Short name T105
Test name
Test status
Simulation time 116991868 ps
CPU time 2.29 seconds
Started Jun 06 02:16:47 PM PDT 24
Finished Jun 06 02:16:52 PM PDT 24
Peak memory 213204 kb
Host smart-8778226f-edc6-4e87-b886-adb85329f04f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921439102 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.921439102
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.3124322198
Short name T390
Test name
Test status
Simulation time 73300047098 ps
CPU time 102.06 seconds
Started Jun 06 02:16:57 PM PDT 24
Finished Jun 06 02:18:40 PM PDT 24
Peak memory 205016 kb
Host smart-abfd3d66-f3a9-4e14-ac8c-6958c2d88092
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124322198 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
rv_dm_jtag_dmi_csr_bit_bash.3124322198
Directory /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3198387206
Short name T399
Test name
Test status
Simulation time 2228431611 ps
CPU time 7.17 seconds
Started Jun 06 02:16:45 PM PDT 24
Finished Jun 06 02:16:54 PM PDT 24
Peak memory 204988 kb
Host smart-6ac6452d-fd96-436a-810b-d621c348c8fd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198387206 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.3
198387206
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1567727651
Short name T270
Test name
Test status
Simulation time 511637653 ps
CPU time 2.03 seconds
Started Jun 06 02:16:50 PM PDT 24
Finished Jun 06 02:16:54 PM PDT 24
Peak memory 204656 kb
Host smart-15e1e83b-d6b7-4ffa-b1b9-12a1c253f5fe
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567727651 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.1
567727651
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.4122462003
Short name T116
Test name
Test status
Simulation time 1285947217 ps
CPU time 4.28 seconds
Started Jun 06 02:16:49 PM PDT 24
Finished Jun 06 02:16:55 PM PDT 24
Peak memory 205120 kb
Host smart-17c46280-143e-41ed-b49e-bcb34bec222c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122462003 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.4122462003
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.3268359933
Short name T384
Test name
Test status
Simulation time 56154715090 ps
CPU time 69.11 seconds
Started Jun 06 02:16:47 PM PDT 24
Finished Jun 06 02:17:59 PM PDT 24
Peak memory 222452 kb
Host smart-6ecf2013-149c-4a7d-bb4a-061f9c5c9959
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268359933 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.3268359933
Directory /workspace/7.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.3199805622
Short name T79
Test name
Test status
Simulation time 281305639 ps
CPU time 4.44 seconds
Started Jun 06 02:16:48 PM PDT 24
Finished Jun 06 02:16:55 PM PDT 24
Peak memory 213368 kb
Host smart-4a80be5d-2a1a-496c-b77c-7f9f25f8e2aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199805622 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.3199805622
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2012183566
Short name T138
Test name
Test status
Simulation time 833784757 ps
CPU time 10.59 seconds
Started Jun 06 02:16:48 PM PDT 24
Finished Jun 06 02:17:00 PM PDT 24
Peak memory 213164 kb
Host smart-36700328-1797-4fe6-9f23-06167b51580c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012183566 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.2012183566
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1243549070
Short name T398
Test name
Test status
Simulation time 386407773 ps
CPU time 3.88 seconds
Started Jun 06 02:16:56 PM PDT 24
Finished Jun 06 02:17:01 PM PDT 24
Peak memory 218912 kb
Host smart-7c517fdd-97b2-45de-8142-f3bcaff5cf55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243549070 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.1243549070
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.3548194261
Short name T109
Test name
Test status
Simulation time 121488079 ps
CPU time 2.29 seconds
Started Jun 06 02:16:45 PM PDT 24
Finished Jun 06 02:16:49 PM PDT 24
Peak memory 213216 kb
Host smart-22be3249-9218-4933-93c7-8b504da83373
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548194261 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.3548194261
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.3056186995
Short name T283
Test name
Test status
Simulation time 3904440019 ps
CPU time 11.71 seconds
Started Jun 06 02:16:45 PM PDT 24
Finished Jun 06 02:16:59 PM PDT 24
Peak memory 204968 kb
Host smart-1e2c4730-7d43-490e-ab41-3268b7b02745
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056186995 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
rv_dm_jtag_dmi_csr_bit_bash.3056186995
Directory /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.263435304
Short name T307
Test name
Test status
Simulation time 2006033151 ps
CPU time 2.65 seconds
Started Jun 06 02:16:49 PM PDT 24
Finished Jun 06 02:16:53 PM PDT 24
Peak memory 204924 kb
Host smart-ebadaeac-45e7-44be-ba64-05f2e08ae7c6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263435304 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.263435304
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.484538289
Short name T73
Test name
Test status
Simulation time 272677242 ps
CPU time 0.9 seconds
Started Jun 06 02:16:50 PM PDT 24
Finished Jun 06 02:16:52 PM PDT 24
Peak memory 204708 kb
Host smart-b2781887-a135-4029-ba90-daf7bbcfbdfd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484538289 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.484538289
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.748590035
Short name T396
Test name
Test status
Simulation time 193587140 ps
CPU time 7.08 seconds
Started Jun 06 02:16:53 PM PDT 24
Finished Jun 06 02:17:02 PM PDT 24
Peak memory 205088 kb
Host smart-99806de2-25f3-475e-9297-f2b3f6074b3d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748590035 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_c
sr_outstanding.748590035
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.484248231
Short name T368
Test name
Test status
Simulation time 64055997629 ps
CPU time 93.15 seconds
Started Jun 06 02:16:46 PM PDT 24
Finished Jun 06 02:18:21 PM PDT 24
Peak memory 222784 kb
Host smart-ddd2f4b8-fc76-4b00-a145-95eb38834b71
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484248231 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.484248231
Directory /workspace/8.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.2092721955
Short name T312
Test name
Test status
Simulation time 158637810 ps
CPU time 3.61 seconds
Started Jun 06 02:16:53 PM PDT 24
Finished Jun 06 02:16:58 PM PDT 24
Peak memory 213368 kb
Host smart-a6ff4dc7-f9eb-4a01-b71f-e1a7966018ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092721955 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.2092721955
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.1546469026
Short name T408
Test name
Test status
Simulation time 3934024143 ps
CPU time 17.95 seconds
Started Jun 06 02:16:46 PM PDT 24
Finished Jun 06 02:17:07 PM PDT 24
Peak memory 213376 kb
Host smart-68f669fb-dc91-4716-827e-6eee5250eb7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546469026 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.1546469026
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.1833642373
Short name T311
Test name
Test status
Simulation time 1479605949 ps
CPU time 6.13 seconds
Started Jun 06 02:16:50 PM PDT 24
Finished Jun 06 02:16:58 PM PDT 24
Peak memory 219240 kb
Host smart-36d7a8d2-02d9-4755-bd59-617c88bed809
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833642373 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.1833642373
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.3555238549
Short name T102
Test name
Test status
Simulation time 125326521 ps
CPU time 1.61 seconds
Started Jun 06 02:16:46 PM PDT 24
Finished Jun 06 02:16:50 PM PDT 24
Peak memory 213224 kb
Host smart-66deb8b9-86ad-497c-90b7-448346ac76c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555238549 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.3555238549
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.2288824526
Short name T330
Test name
Test status
Simulation time 29861506306 ps
CPU time 24.07 seconds
Started Jun 06 02:16:46 PM PDT 24
Finished Jun 06 02:17:13 PM PDT 24
Peak memory 205044 kb
Host smart-6a398f76-917f-452b-b8a9-37068045815a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288824526 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
rv_dm_jtag_dmi_csr_bit_bash.2288824526
Directory /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.1967575338
Short name T410
Test name
Test status
Simulation time 9621676207 ps
CPU time 26.21 seconds
Started Jun 06 02:16:47 PM PDT 24
Finished Jun 06 02:17:15 PM PDT 24
Peak memory 205000 kb
Host smart-dd22225b-8f0c-45f9-a5cb-2b50cf004207
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967575338 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.1
967575338
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.3966264258
Short name T74
Test name
Test status
Simulation time 184907700 ps
CPU time 1.06 seconds
Started Jun 06 02:16:53 PM PDT 24
Finished Jun 06 02:16:55 PM PDT 24
Peak memory 204712 kb
Host smart-39a65a16-ab7c-49ec-992c-329e95e7a14c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966264258 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.3
966264258
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.1821164784
Short name T331
Test name
Test status
Simulation time 29798645997 ps
CPU time 42.71 seconds
Started Jun 06 02:16:46 PM PDT 24
Finished Jun 06 02:17:31 PM PDT 24
Peak memory 221124 kb
Host smart-d741ac7d-2f63-42c4-a808-ce446259eaee
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821164784 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.1821164784
Directory /workspace/9.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.430935249
Short name T335
Test name
Test status
Simulation time 979337283 ps
CPU time 5.38 seconds
Started Jun 06 02:16:46 PM PDT 24
Finished Jun 06 02:16:53 PM PDT 24
Peak memory 213324 kb
Host smart-1928ffad-d63a-499f-97c2-2d3386267e61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430935249 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.430935249
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.1684680253
Short name T135
Test name
Test status
Simulation time 3380129466 ps
CPU time 25.89 seconds
Started Jun 06 02:16:58 PM PDT 24
Finished Jun 06 02:17:25 PM PDT 24
Peak memory 213252 kb
Host smart-d2b5cd6a-3aca-42f8-be95-3ef339d01ce4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684680253 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.1684680253
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.121733117
Short name T177
Test name
Test status
Simulation time 52438223 ps
CPU time 0.74 seconds
Started Jun 06 01:56:20 PM PDT 24
Finished Jun 06 01:56:22 PM PDT 24
Peak memory 204812 kb
Host smart-54be9992-cb03-4253-93eb-f6138404888d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121733117 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.121733117
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.3401689993
Short name T202
Test name
Test status
Simulation time 65759084694 ps
CPU time 56.47 seconds
Started Jun 06 01:56:22 PM PDT 24
Finished Jun 06 01:57:20 PM PDT 24
Peak memory 213424 kb
Host smart-6ce6eff8-a3dc-477e-a465-f8b497b2937a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401689993 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.3401689993
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.3946579494
Short name T252
Test name
Test status
Simulation time 2343670293 ps
CPU time 7.71 seconds
Started Jun 06 01:56:17 PM PDT 24
Finished Jun 06 01:56:26 PM PDT 24
Peak memory 205212 kb
Host smart-e68c9f1c-0e56-4363-9536-6b3ab771c0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946579494 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.3946579494
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.3320084330
Short name T13
Test name
Test status
Simulation time 7552867455 ps
CPU time 8.83 seconds
Started Jun 06 01:56:16 PM PDT 24
Finished Jun 06 01:56:26 PM PDT 24
Peak memory 204992 kb
Host smart-1a75017f-20cd-4c8f-b411-fdf8d9ddbf0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320084330 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.3320084330
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.2170678292
Short name T147
Test name
Test status
Simulation time 3668737020 ps
CPU time 3.92 seconds
Started Jun 06 01:56:24 PM PDT 24
Finished Jun 06 01:56:29 PM PDT 24
Peak memory 204988 kb
Host smart-8d2de441-2657-40ff-86c2-d45e3337ad0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170678292 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.2170678292
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.2284489713
Short name T247
Test name
Test status
Simulation time 181677525 ps
CPU time 1.24 seconds
Started Jun 06 01:56:17 PM PDT 24
Finished Jun 06 01:56:19 PM PDT 24
Peak memory 204716 kb
Host smart-c52fc912-4617-4c18-8132-43a55cc1d8d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284489713 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.2284489713
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.1332597328
Short name T234
Test name
Test status
Simulation time 5922770108 ps
CPU time 5.79 seconds
Started Jun 06 01:56:18 PM PDT 24
Finished Jun 06 01:56:25 PM PDT 24
Peak memory 205212 kb
Host smart-78ff0841-b28d-4680-a55c-9b9772b1c5b7
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1332597328 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t
l_access.1332597328
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.2520262256
Short name T17
Test name
Test status
Simulation time 612221117 ps
CPU time 2.65 seconds
Started Jun 06 01:56:10 PM PDT 24
Finished Jun 06 01:56:14 PM PDT 24
Peak memory 204720 kb
Host smart-4d9eb370-fece-41bb-a753-a7b284cf8c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520262256 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.2520262256
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.1302406536
Short name T193
Test name
Test status
Simulation time 222657090 ps
CPU time 0.91 seconds
Started Jun 06 01:56:21 PM PDT 24
Finished Jun 06 01:56:23 PM PDT 24
Peak memory 204572 kb
Host smart-7624c88c-7127-486c-8fc8-fe8c1a7163fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302406536 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.1302406536
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.863550783
Short name T189
Test name
Test status
Simulation time 1583637285 ps
CPU time 2.17 seconds
Started Jun 06 01:56:22 PM PDT 24
Finished Jun 06 01:56:26 PM PDT 24
Peak memory 204512 kb
Host smart-454e1730-2538-4f0f-b11a-5d6cf8bf8f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863550783 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.863550783
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.4124178355
Short name T250
Test name
Test status
Simulation time 1352618292 ps
CPU time 2.59 seconds
Started Jun 06 01:56:22 PM PDT 24
Finished Jun 06 01:56:26 PM PDT 24
Peak memory 204584 kb
Host smart-bf2e754a-4f12-46bc-b9e3-435ab532fea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124178355 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.4124178355
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.3770153280
Short name T194
Test name
Test status
Simulation time 1614206087 ps
CPU time 1.51 seconds
Started Jun 06 01:56:10 PM PDT 24
Finished Jun 06 01:56:13 PM PDT 24
Peak memory 204588 kb
Host smart-9bf5cfb7-db7f-46a6-be28-dbecb16d28b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770153280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.3770153280
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.2201013002
Short name T237
Test name
Test status
Simulation time 135613313 ps
CPU time 0.74 seconds
Started Jun 06 01:56:23 PM PDT 24
Finished Jun 06 01:56:25 PM PDT 24
Peak memory 204604 kb
Host smart-c8318175-a7da-4dd1-81e3-954614101041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201013002 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.2201013002
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.1483456599
Short name T69
Test name
Test status
Simulation time 310090623 ps
CPU time 1.51 seconds
Started Jun 06 01:56:10 PM PDT 24
Finished Jun 06 01:56:13 PM PDT 24
Peak memory 204712 kb
Host smart-42f3c032-07f9-4ae5-b8fb-371ab8d9a0ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483456599 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.1483456599
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.4200305132
Short name T21
Test name
Test status
Simulation time 2198698796 ps
CPU time 3.05 seconds
Started Jun 06 01:56:15 PM PDT 24
Finished Jun 06 01:56:19 PM PDT 24
Peak memory 204980 kb
Host smart-1647d673-26d8-4eff-8300-e2345987f690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200305132 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.4200305132
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.2553717858
Short name T11
Test name
Test status
Simulation time 94376006 ps
CPU time 0.81 seconds
Started Jun 06 01:56:15 PM PDT 24
Finished Jun 06 01:56:17 PM PDT 24
Peak memory 212904 kb
Host smart-dcd26d4a-39f9-4c0e-b490-bba7a739b773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553717858 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.2553717858
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.1470057452
Short name T254
Test name
Test status
Simulation time 1456006613 ps
CPU time 5.16 seconds
Started Jun 06 01:56:24 PM PDT 24
Finished Jun 06 01:56:31 PM PDT 24
Peak memory 205132 kb
Host smart-55a9c6c0-8a5e-4bc9-a7af-1c5f8313cf62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470057452 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.1470057452
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.3554555897
Short name T43
Test name
Test status
Simulation time 2673991278 ps
CPU time 2.92 seconds
Started Jun 06 01:56:21 PM PDT 24
Finished Jun 06 01:56:25 PM PDT 24
Peak memory 229428 kb
Host smart-89560e82-3f60-4c26-8442-e2a67223ea66
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554555897 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.3554555897
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.2172994650
Short name T201
Test name
Test status
Simulation time 2954918661 ps
CPU time 2.74 seconds
Started Jun 06 01:56:08 PM PDT 24
Finished Jun 06 01:56:12 PM PDT 24
Peak memory 204880 kb
Host smart-ab1d841f-8d61-4cc1-bb88-dab9b1c95796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172994650 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.2172994650
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all.3778024749
Short name T8
Test name
Test status
Simulation time 22800848778 ps
CPU time 43.26 seconds
Started Jun 06 01:56:18 PM PDT 24
Finished Jun 06 01:57:03 PM PDT 24
Peak memory 213264 kb
Host smart-54118924-0fbd-484c-aac3-afa7440dd158
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778024749 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.3778024749
Directory /workspace/0.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.1957838859
Short name T26
Test name
Test status
Simulation time 8850213286 ps
CPU time 27.33 seconds
Started Jun 06 01:56:25 PM PDT 24
Finished Jun 06 01:56:55 PM PDT 24
Peak memory 204948 kb
Host smart-78097e7e-0ff6-433d-be38-69a951939c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957838859 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.1957838859
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.1024730682
Short name T38
Test name
Test status
Simulation time 186608573 ps
CPU time 0.75 seconds
Started Jun 06 01:56:21 PM PDT 24
Finished Jun 06 01:56:22 PM PDT 24
Peak memory 204664 kb
Host smart-c4aa0bb1-41f1-4ded-9c5f-e6570013fc8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024730682 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.1024730682
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.2964058321
Short name T123
Test name
Test status
Simulation time 82985768 ps
CPU time 0.74 seconds
Started Jun 06 01:56:25 PM PDT 24
Finished Jun 06 01:56:27 PM PDT 24
Peak memory 204644 kb
Host smart-3cc3a39e-48b7-4c54-9126-3360d41a2127
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964058321 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.2964058321
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.3952934400
Short name T187
Test name
Test status
Simulation time 13980703512 ps
CPU time 20.19 seconds
Started Jun 06 01:56:22 PM PDT 24
Finished Jun 06 01:56:43 PM PDT 24
Peak memory 213440 kb
Host smart-010bc7cf-1648-4086-af36-5a412ef5515b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952934400 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.3952934400
Directory /workspace/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.1007682848
Short name T216
Test name
Test status
Simulation time 1234382792 ps
CPU time 4.42 seconds
Started Jun 06 01:56:17 PM PDT 24
Finished Jun 06 01:56:22 PM PDT 24
Peak memory 205056 kb
Host smart-dd4ef8bd-cbe2-419c-bff3-50b6125a87f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007682848 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.1007682848
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.29359724
Short name T140
Test name
Test status
Simulation time 5412524096 ps
CPU time 15.32 seconds
Started Jun 06 01:56:23 PM PDT 24
Finished Jun 06 01:56:45 PM PDT 24
Peak memory 205020 kb
Host smart-ecc04b64-db4a-4f8d-816b-e7d69af61365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29359724 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.29359724
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.3454586259
Short name T36
Test name
Test status
Simulation time 299803871 ps
CPU time 1.54 seconds
Started Jun 06 01:56:22 PM PDT 24
Finished Jun 06 01:56:25 PM PDT 24
Peak memory 204700 kb
Host smart-280d71f7-3bc7-4005-bbb7-d9ca439242c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454586259 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.3454586259
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.2985400346
Short name T32
Test name
Test status
Simulation time 2081756466 ps
CPU time 5.9 seconds
Started Jun 06 01:56:21 PM PDT 24
Finished Jun 06 01:56:28 PM PDT 24
Peak memory 204524 kb
Host smart-45221dcd-d7b9-4bb8-921f-b8c811c99bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985400346 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.2985400346
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.2164468959
Short name T151
Test name
Test status
Simulation time 248247181 ps
CPU time 0.87 seconds
Started Jun 06 01:56:27 PM PDT 24
Finished Jun 06 01:56:30 PM PDT 24
Peak memory 204708 kb
Host smart-c6dfe493-7ac5-473f-9a8f-cfcc9d9341a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164468959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.2164468959
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.3897795755
Short name T195
Test name
Test status
Simulation time 11719334692 ps
CPU time 35.7 seconds
Started Jun 06 01:56:18 PM PDT 24
Finished Jun 06 01:56:55 PM PDT 24
Peak memory 205232 kb
Host smart-413cd503-87a1-4ba8-aa90-55e6eb355dca
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3897795755 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.3897795755
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.527090568
Short name T63
Test name
Test status
Simulation time 728428663 ps
CPU time 2.72 seconds
Started Jun 06 01:56:34 PM PDT 24
Finished Jun 06 01:56:38 PM PDT 24
Peak memory 204744 kb
Host smart-287cb141-9e47-4b04-be2c-58872e29fb49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527090568 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.527090568
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.3133653024
Short name T243
Test name
Test status
Simulation time 179722322 ps
CPU time 0.8 seconds
Started Jun 06 01:56:22 PM PDT 24
Finished Jun 06 01:56:24 PM PDT 24
Peak memory 204552 kb
Host smart-43a9acc1-c335-4c36-b505-4dbe199aa2d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133653024 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.3133653024
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.847690038
Short name T213
Test name
Test status
Simulation time 278653831 ps
CPU time 0.9 seconds
Started Jun 06 01:56:26 PM PDT 24
Finished Jun 06 01:56:29 PM PDT 24
Peak memory 204620 kb
Host smart-eb4712e1-1892-4d3b-bdbb-610a65eb9aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847690038 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.847690038
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.1710309042
Short name T19
Test name
Test status
Simulation time 1039763585 ps
CPU time 2.98 seconds
Started Jun 06 01:56:25 PM PDT 24
Finished Jun 06 01:56:29 PM PDT 24
Peak memory 204520 kb
Host smart-33bf2328-7ccb-4897-b4ca-fd7962596f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710309042 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.1710309042
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.3353752492
Short name T44
Test name
Test status
Simulation time 1990205191 ps
CPU time 2.93 seconds
Started Jun 06 01:56:27 PM PDT 24
Finished Jun 06 01:56:32 PM PDT 24
Peak memory 204060 kb
Host smart-8f944a53-e8f9-4ad7-b50e-07abcbc912c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353752492 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.3353752492
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.874003290
Short name T190
Test name
Test status
Simulation time 89547440 ps
CPU time 0.77 seconds
Started Jun 06 01:56:24 PM PDT 24
Finished Jun 06 01:56:26 PM PDT 24
Peak memory 204568 kb
Host smart-22696245-0623-46f3-bbbb-04df507b271d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874003290 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.874003290
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.358120442
Short name T142
Test name
Test status
Simulation time 284737025 ps
CPU time 1.48 seconds
Started Jun 06 01:56:21 PM PDT 24
Finished Jun 06 01:56:24 PM PDT 24
Peak memory 204680 kb
Host smart-9f272887-9c93-4b55-8c5f-4c1380f07593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358120442 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.358120442
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.2191052254
Short name T152
Test name
Test status
Simulation time 3618087626 ps
CPU time 2.23 seconds
Started Jun 06 01:56:20 PM PDT 24
Finished Jun 06 01:56:24 PM PDT 24
Peak memory 205104 kb
Host smart-6796f7d8-9d42-48a1-93c9-fcc2f0fd9213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191052254 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.2191052254
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.2935042549
Short name T20
Test name
Test status
Simulation time 397440702 ps
CPU time 1.62 seconds
Started Jun 06 01:56:24 PM PDT 24
Finished Jun 06 01:56:27 PM PDT 24
Peak memory 204636 kb
Host smart-4fa062f6-e9d6-41ed-9890-dc89fb373f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935042549 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.2935042549
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.4009790489
Short name T35
Test name
Test status
Simulation time 2298814192 ps
CPU time 7.12 seconds
Started Jun 06 01:56:21 PM PDT 24
Finished Jun 06 01:56:30 PM PDT 24
Peak memory 204832 kb
Host smart-0fe9e246-319c-4b98-933d-d17c8eaa8623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009790489 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.4009790489
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.1392554286
Short name T37
Test name
Test status
Simulation time 271426273 ps
CPU time 0.96 seconds
Started Jun 06 01:56:16 PM PDT 24
Finished Jun 06 01:56:17 PM PDT 24
Peak memory 204700 kb
Host smart-98717e91-6aec-4b2f-bfd1-d04d1957f18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392554286 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.1392554286
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.553715512
Short name T236
Test name
Test status
Simulation time 940882244 ps
CPU time 3.44 seconds
Started Jun 06 01:56:19 PM PDT 24
Finished Jun 06 01:56:23 PM PDT 24
Peak memory 205048 kb
Host smart-1c7f07e9-0974-4cf3-a628-6b60453cf070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553715512 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.553715512
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.501848281
Short name T64
Test name
Test status
Simulation time 1709474555 ps
CPU time 1.63 seconds
Started Jun 06 01:56:19 PM PDT 24
Finished Jun 06 01:56:22 PM PDT 24
Peak memory 229628 kb
Host smart-75ce88a6-202b-4929-8d1b-a1336d232b29
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501848281 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.501848281
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.916808453
Short name T238
Test name
Test status
Simulation time 2356328236 ps
CPU time 3.78 seconds
Started Jun 06 01:56:18 PM PDT 24
Finished Jun 06 01:56:24 PM PDT 24
Peak memory 204704 kb
Host smart-5aa12305-722c-4dd5-ae45-7b0bf22c47de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916808453 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.916808453
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.704736114
Short name T153
Test name
Test status
Simulation time 73945736 ps
CPU time 0.93 seconds
Started Jun 06 01:56:29 PM PDT 24
Finished Jun 06 01:56:32 PM PDT 24
Peak memory 204788 kb
Host smart-4a556fe6-f5d4-435d-a6fa-48ecfc836563
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704736114 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.704736114
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.3575094738
Short name T211
Test name
Test status
Simulation time 22674112983 ps
CPU time 59.52 seconds
Started Jun 06 01:56:33 PM PDT 24
Finished Jun 06 01:57:34 PM PDT 24
Peak memory 205268 kb
Host smart-e70e181f-b9ea-4d9d-9b86-9e3dcb6c1a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575094738 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.3575094738
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.2582831104
Short name T224
Test name
Test status
Simulation time 1714287370 ps
CPU time 5.34 seconds
Started Jun 06 01:56:36 PM PDT 24
Finished Jun 06 01:56:42 PM PDT 24
Peak memory 205104 kb
Host smart-210e03bf-4bbd-4df2-b697-888881448cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582831104 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.2582831104
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.91630598
Short name T184
Test name
Test status
Simulation time 3910013496 ps
CPU time 7.71 seconds
Started Jun 06 01:56:28 PM PDT 24
Finished Jun 06 01:56:37 PM PDT 24
Peak memory 205236 kb
Host smart-4945decf-151a-421b-836a-b611335d6f3f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=91630598 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_tl
_access.91630598
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.3053426755
Short name T225
Test name
Test status
Simulation time 3486074348 ps
CPU time 10.57 seconds
Started Jun 06 01:56:32 PM PDT 24
Finished Jun 06 01:56:44 PM PDT 24
Peak memory 205252 kb
Host smart-152276ad-a442-4c65-987c-4e26d4d46687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053426755 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.3053426755
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_stress_all.2424489278
Short name T144
Test name
Test status
Simulation time 11875957424 ps
CPU time 18.47 seconds
Started Jun 06 01:56:29 PM PDT 24
Finished Jun 06 01:56:49 PM PDT 24
Peak memory 205092 kb
Host smart-63a10bd9-865f-4e10-a018-9378c91e460c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424489278 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.2424489278
Directory /workspace/10.rv_dm_stress_all/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.1959942317
Short name T172
Test name
Test status
Simulation time 37062549 ps
CPU time 0.76 seconds
Started Jun 06 01:56:29 PM PDT 24
Finished Jun 06 01:56:31 PM PDT 24
Peak memory 204660 kb
Host smart-9114330c-f2f0-4d51-83fc-75b269a8a722
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959942317 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.1959942317
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.932469010
Short name T245
Test name
Test status
Simulation time 7506756882 ps
CPU time 7.66 seconds
Started Jun 06 01:56:29 PM PDT 24
Finished Jun 06 01:56:38 PM PDT 24
Peak memory 213440 kb
Host smart-9b791a0b-1d29-49a7-b115-3bdcdf7afdc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932469010 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.932469010
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.2728623142
Short name T24
Test name
Test status
Simulation time 11908135409 ps
CPU time 4.55 seconds
Started Jun 06 01:56:28 PM PDT 24
Finished Jun 06 01:56:34 PM PDT 24
Peak memory 205196 kb
Host smart-c80b5cb7-ff35-4a6d-b593-93e4b38e94a1
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2728623142 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_
tl_access.2728623142
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.1471061312
Short name T248
Test name
Test status
Simulation time 4002353956 ps
CPU time 3.21 seconds
Started Jun 06 01:56:30 PM PDT 24
Finished Jun 06 01:56:35 PM PDT 24
Peak memory 205176 kb
Host smart-89a263e6-c482-40d9-8be5-f5946847bbad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471061312 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.1471061312
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.1106758067
Short name T209
Test name
Test status
Simulation time 81698883 ps
CPU time 0.73 seconds
Started Jun 06 01:56:38 PM PDT 24
Finished Jun 06 01:56:40 PM PDT 24
Peak memory 204848 kb
Host smart-2f7b73d1-4350-4d90-b51d-6879febfa7b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106758067 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.1106758067
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.1336630422
Short name T215
Test name
Test status
Simulation time 32692524406 ps
CPU time 83.89 seconds
Started Jun 06 01:56:34 PM PDT 24
Finished Jun 06 01:57:59 PM PDT 24
Peak memory 213392 kb
Host smart-cfe307ad-0f2a-4ec8-893e-3812b8a6f058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336630422 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.1336630422
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.2483362106
Short name T241
Test name
Test status
Simulation time 5835127188 ps
CPU time 18.12 seconds
Started Jun 06 01:56:45 PM PDT 24
Finished Jun 06 01:57:05 PM PDT 24
Peak memory 205304 kb
Host smart-857a5849-b8bf-4b88-81e3-c9c6089ae968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483362106 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.2483362106
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.1588263850
Short name T229
Test name
Test status
Simulation time 2684447216 ps
CPU time 8.01 seconds
Started Jun 06 01:56:35 PM PDT 24
Finished Jun 06 01:56:44 PM PDT 24
Peak memory 205200 kb
Host smart-def8b851-e693-4cbe-ba6f-552f27b5ceb1
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1588263850 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.1588263850
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.4010010440
Short name T78
Test name
Test status
Simulation time 6478906031 ps
CPU time 5.76 seconds
Started Jun 06 01:56:34 PM PDT 24
Finished Jun 06 01:56:41 PM PDT 24
Peak memory 205208 kb
Host smart-96012483-ad82-4f55-8986-1328da0ecce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010010440 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.4010010440
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_stress_all.2431689993
Short name T146
Test name
Test status
Simulation time 8314447571 ps
CPU time 21.2 seconds
Started Jun 06 01:56:36 PM PDT 24
Finished Jun 06 01:56:58 PM PDT 24
Peak memory 205020 kb
Host smart-f6d9ebf8-378d-480e-8bf5-87a55cd36856
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431689993 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.2431689993
Directory /workspace/12.rv_dm_stress_all/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.1095073552
Short name T167
Test name
Test status
Simulation time 40368955 ps
CPU time 0.78 seconds
Started Jun 06 01:56:44 PM PDT 24
Finished Jun 06 01:56:46 PM PDT 24
Peak memory 204840 kb
Host smart-ce4e1553-3488-4ea7-b7c5-81c68a1db477
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095073552 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.1095073552
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.3136173023
Short name T51
Test name
Test status
Simulation time 4034432959 ps
CPU time 3.71 seconds
Started Jun 06 01:56:32 PM PDT 24
Finished Jun 06 01:56:37 PM PDT 24
Peak memory 205220 kb
Host smart-cc686382-7089-4760-874d-e4946f8f01db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136173023 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.3136173023
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.114297907
Short name T239
Test name
Test status
Simulation time 7105047992 ps
CPU time 2.71 seconds
Started Jun 06 01:56:36 PM PDT 24
Finished Jun 06 01:56:40 PM PDT 24
Peak memory 205256 kb
Host smart-de6f7bcd-4431-4303-8e7f-9407d9070b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114297907 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.114297907
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.2199082786
Short name T29
Test name
Test status
Simulation time 3792829905 ps
CPU time 12.5 seconds
Started Jun 06 01:56:59 PM PDT 24
Finished Jun 06 01:57:12 PM PDT 24
Peak memory 205248 kb
Host smart-4f87b43a-3ab6-4385-b766-33f6d2b9c7ee
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2199082786 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_
tl_access.2199082786
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.407224977
Short name T206
Test name
Test status
Simulation time 2388910313 ps
CPU time 2.87 seconds
Started Jun 06 01:56:42 PM PDT 24
Finished Jun 06 01:56:46 PM PDT 24
Peak memory 205252 kb
Host smart-94a4e571-0ac6-4211-bdb1-43d5ddc0f413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407224977 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.407224977
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_stress_all.3500988071
Short name T18
Test name
Test status
Simulation time 20509065149 ps
CPU time 29.4 seconds
Started Jun 06 01:56:51 PM PDT 24
Finished Jun 06 01:57:22 PM PDT 24
Peak memory 204988 kb
Host smart-15c209d7-4296-496d-ba1b-2ac859f0152d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500988071 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.3500988071
Directory /workspace/13.rv_dm_stress_all/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.1822728494
Short name T47
Test name
Test status
Simulation time 194790798 ps
CPU time 0.76 seconds
Started Jun 06 01:56:33 PM PDT 24
Finished Jun 06 01:56:35 PM PDT 24
Peak memory 204844 kb
Host smart-df7ec5dd-a91b-4628-aa52-5f427f44fa9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822728494 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.1822728494
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.2356315649
Short name T246
Test name
Test status
Simulation time 53988368119 ps
CPU time 149.4 seconds
Started Jun 06 01:56:38 PM PDT 24
Finished Jun 06 01:59:08 PM PDT 24
Peak memory 221368 kb
Host smart-706cd230-1530-4cb3-a558-c7fd32ca6d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356315649 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.2356315649
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.3306518973
Short name T199
Test name
Test status
Simulation time 7787049006 ps
CPU time 5.94 seconds
Started Jun 06 01:56:38 PM PDT 24
Finished Jun 06 01:56:45 PM PDT 24
Peak memory 205244 kb
Host smart-5c956793-d60d-4616-930a-05676fdf85a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306518973 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.3306518973
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.900355930
Short name T121
Test name
Test status
Simulation time 1115925935 ps
CPU time 2.98 seconds
Started Jun 06 01:56:37 PM PDT 24
Finished Jun 06 01:56:41 PM PDT 24
Peak memory 205064 kb
Host smart-be274dc8-433e-4bd1-9db5-f38fad35e2c5
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=900355930 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_t
l_access.900355930
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.2491506352
Short name T181
Test name
Test status
Simulation time 3534097290 ps
CPU time 5.21 seconds
Started Jun 06 01:56:33 PM PDT 24
Finished Jun 06 01:56:39 PM PDT 24
Peak memory 205152 kb
Host smart-eb6f2279-3d20-42a0-bac1-af6c01960a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491506352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.2491506352
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.1480474791
Short name T163
Test name
Test status
Simulation time 43344462 ps
CPU time 0.71 seconds
Started Jun 06 01:56:52 PM PDT 24
Finished Jun 06 01:56:53 PM PDT 24
Peak memory 204852 kb
Host smart-d2dd9b07-e55a-4dc3-bd87-5bc9db42a38c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480474791 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.1480474791
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.765386791
Short name T72
Test name
Test status
Simulation time 14072719694 ps
CPU time 21.07 seconds
Started Jun 06 01:56:36 PM PDT 24
Finished Jun 06 01:56:58 PM PDT 24
Peak memory 216788 kb
Host smart-a4de92b8-2ec1-4419-92c1-63e36b1a0b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765386791 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.765386791
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.1493336144
Short name T210
Test name
Test status
Simulation time 1353416779 ps
CPU time 4.38 seconds
Started Jun 06 01:56:44 PM PDT 24
Finished Jun 06 01:56:50 PM PDT 24
Peak memory 205072 kb
Host smart-74e80907-c73f-48f5-b202-bd0578168ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493336144 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.1493336144
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.2954272292
Short name T53
Test name
Test status
Simulation time 1906941720 ps
CPU time 2.6 seconds
Started Jun 06 01:56:38 PM PDT 24
Finished Jun 06 01:56:42 PM PDT 24
Peak memory 205012 kb
Host smart-f813ccd8-65c6-4e4f-8a52-d7338d32ec0b
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2954272292 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_
tl_access.2954272292
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.857274596
Short name T67
Test name
Test status
Simulation time 1349070164 ps
CPU time 1.95 seconds
Started Jun 06 01:56:35 PM PDT 24
Finished Jun 06 01:56:38 PM PDT 24
Peak memory 205056 kb
Host smart-db8dc714-53c8-482b-a82d-2f38e51d44d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857274596 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.857274596
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.2725286115
Short name T170
Test name
Test status
Simulation time 117807138 ps
CPU time 0.71 seconds
Started Jun 06 01:56:33 PM PDT 24
Finished Jun 06 01:56:35 PM PDT 24
Peak memory 204720 kb
Host smart-087891f8-ead1-4fc1-9314-d7e01ceeb052
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725286115 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.2725286115
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.3910115202
Short name T258
Test name
Test status
Simulation time 81990777116 ps
CPU time 65.72 seconds
Started Jun 06 01:56:35 PM PDT 24
Finished Jun 06 01:57:42 PM PDT 24
Peak memory 214480 kb
Host smart-d73a6df8-05e7-468a-9d30-73944115483d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910115202 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.3910115202
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.1617817336
Short name T40
Test name
Test status
Simulation time 4303030412 ps
CPU time 6.01 seconds
Started Jun 06 01:56:42 PM PDT 24
Finished Jun 06 01:56:49 PM PDT 24
Peak memory 205172 kb
Host smart-626c2b4d-2083-4e00-856d-8f0bb009798f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617817336 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.1617817336
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.1684420327
Short name T256
Test name
Test status
Simulation time 3179298786 ps
CPU time 10.95 seconds
Started Jun 06 01:56:52 PM PDT 24
Finished Jun 06 01:57:03 PM PDT 24
Peak memory 205220 kb
Host smart-8b127db8-866d-4fb4-b1c1-39180514662b
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1684420327 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_
tl_access.1684420327
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.3318750272
Short name T180
Test name
Test status
Simulation time 8617869471 ps
CPU time 14.12 seconds
Started Jun 06 01:56:35 PM PDT 24
Finished Jun 06 01:56:55 PM PDT 24
Peak memory 205452 kb
Host smart-feb03cee-4a25-4327-aa44-d6c8a2185c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318750272 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.3318750272
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_stress_all.725569600
Short name T34
Test name
Test status
Simulation time 15227693110 ps
CPU time 18.71 seconds
Started Jun 06 01:56:33 PM PDT 24
Finished Jun 06 01:56:53 PM PDT 24
Peak memory 204988 kb
Host smart-21b49c73-5977-483f-b4fd-2f98bf12e8b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725569600 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.725569600
Directory /workspace/16.rv_dm_stress_all/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.3199812930
Short name T3
Test name
Test status
Simulation time 187518436 ps
CPU time 0.82 seconds
Started Jun 06 01:57:04 PM PDT 24
Finished Jun 06 01:57:06 PM PDT 24
Peak memory 204844 kb
Host smart-2a1d43b6-cf29-4f70-9fb8-58699831028f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199812930 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.3199812930
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.1541328073
Short name T217
Test name
Test status
Simulation time 11016315796 ps
CPU time 31.88 seconds
Started Jun 06 01:56:36 PM PDT 24
Finished Jun 06 01:57:08 PM PDT 24
Peak memory 213420 kb
Host smart-5728a1ba-e732-4ecc-8caa-c7857eb71688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541328073 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.1541328073
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.224069943
Short name T231
Test name
Test status
Simulation time 2073319310 ps
CPU time 2.47 seconds
Started Jun 06 01:56:50 PM PDT 24
Finished Jun 06 01:56:53 PM PDT 24
Peak memory 205100 kb
Host smart-fc2cfd5e-fd06-4e25-8fe4-59a06e7ad42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224069943 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.224069943
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.1968929437
Short name T230
Test name
Test status
Simulation time 1961546895 ps
CPU time 2.61 seconds
Started Jun 06 01:56:52 PM PDT 24
Finished Jun 06 01:56:56 PM PDT 24
Peak memory 205112 kb
Host smart-e4b30527-0cc8-468e-b912-a4a2844a4775
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1968929437 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_
tl_access.1968929437
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.3387326340
Short name T259
Test name
Test status
Simulation time 3605844422 ps
CPU time 3.57 seconds
Started Jun 06 01:56:38 PM PDT 24
Finished Jun 06 01:56:43 PM PDT 24
Peak memory 205220 kb
Host smart-ed528b74-7700-4a30-8bbb-cb28b70dc720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387326340 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.3387326340
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.501874295
Short name T52
Test name
Test status
Simulation time 57930830 ps
CPU time 0.72 seconds
Started Jun 06 01:56:36 PM PDT 24
Finished Jun 06 01:56:38 PM PDT 24
Peak memory 204820 kb
Host smart-9f6f7524-9129-41f2-8d50-4660c10ab4d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501874295 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.501874295
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.19087528
Short name T5
Test name
Test status
Simulation time 23851856598 ps
CPU time 27.83 seconds
Started Jun 06 01:56:38 PM PDT 24
Finished Jun 06 01:57:07 PM PDT 24
Peak memory 213460 kb
Host smart-38be14ad-380c-40e6-8e74-12a606223698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19087528 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.19087528
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.1074922493
Short name T192
Test name
Test status
Simulation time 3651701442 ps
CPU time 2.38 seconds
Started Jun 06 01:56:41 PM PDT 24
Finished Jun 06 01:56:45 PM PDT 24
Peak memory 205268 kb
Host smart-d3d6bdc7-e178-4199-9388-61de39d6f689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074922493 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.1074922493
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.3096871929
Short name T200
Test name
Test status
Simulation time 2236889852 ps
CPU time 1.61 seconds
Started Jun 06 01:56:39 PM PDT 24
Finished Jun 06 01:56:42 PM PDT 24
Peak memory 205152 kb
Host smart-4305dd20-6323-41ae-93bc-d66aa35d5dec
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3096871929 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_
tl_access.3096871929
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.555811024
Short name T219
Test name
Test status
Simulation time 1604472260 ps
CPU time 4.95 seconds
Started Jun 06 01:56:38 PM PDT 24
Finished Jun 06 01:56:44 PM PDT 24
Peak memory 205044 kb
Host smart-a49b4ee3-8e2b-4fe9-b27c-ba8b315b3cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555811024 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.555811024
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_stress_all.3032644760
Short name T141
Test name
Test status
Simulation time 14800497911 ps
CPU time 14.55 seconds
Started Jun 06 01:56:40 PM PDT 24
Finished Jun 06 01:56:55 PM PDT 24
Peak memory 205104 kb
Host smart-719ddc11-8438-4cbc-b585-96c9ab425a94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032644760 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.3032644760
Directory /workspace/18.rv_dm_stress_all/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.2965657434
Short name T77
Test name
Test status
Simulation time 38869845 ps
CPU time 0.77 seconds
Started Jun 06 01:56:38 PM PDT 24
Finished Jun 06 01:56:40 PM PDT 24
Peak memory 204784 kb
Host smart-f3f7b70e-80b3-4060-a49c-b3fa8c2f3796
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965657434 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.2965657434
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.3039435118
Short name T197
Test name
Test status
Simulation time 7104949529 ps
CPU time 11.76 seconds
Started Jun 06 01:56:49 PM PDT 24
Finished Jun 06 01:57:02 PM PDT 24
Peak memory 205132 kb
Host smart-5b181666-87b1-44c5-bc27-f5d92d16d9dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039435118 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.3039435118
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.565246581
Short name T129
Test name
Test status
Simulation time 15033144152 ps
CPU time 38.87 seconds
Started Jun 06 01:56:47 PM PDT 24
Finished Jun 06 01:57:27 PM PDT 24
Peak memory 213416 kb
Host smart-e8ed1ff0-2091-4a61-bdc7-40363209b1b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565246581 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.565246581
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.953992453
Short name T196
Test name
Test status
Simulation time 5521260776 ps
CPU time 8.93 seconds
Started Jun 06 01:56:40 PM PDT 24
Finished Jun 06 01:56:50 PM PDT 24
Peak memory 205224 kb
Host smart-2ec20a25-e607-4bef-aca4-2d3965c160d3
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=953992453 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_t
l_access.953992453
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.3558670652
Short name T50
Test name
Test status
Simulation time 2544337798 ps
CPU time 2.22 seconds
Started Jun 06 01:56:55 PM PDT 24
Finished Jun 06 01:56:58 PM PDT 24
Peak memory 205184 kb
Host smart-1bad2784-afc9-464f-8510-ef4d8a218134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558670652 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.3558670652
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.1852056483
Short name T173
Test name
Test status
Simulation time 70249392 ps
CPU time 0.85 seconds
Started Jun 06 01:56:16 PM PDT 24
Finished Jun 06 01:56:17 PM PDT 24
Peak memory 204816 kb
Host smart-646bea3e-92e5-46b5-b886-b50a457b12d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852056483 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.1852056483
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.3004971453
Short name T222
Test name
Test status
Simulation time 4152209197 ps
CPU time 6.47 seconds
Started Jun 06 01:56:14 PM PDT 24
Finished Jun 06 01:56:22 PM PDT 24
Peak memory 205192 kb
Host smart-3e6ee330-31b8-4427-8d3f-a4a9c6c9940f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004971453 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.3004971453
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.1835434585
Short name T198
Test name
Test status
Simulation time 4184358299 ps
CPU time 3.75 seconds
Started Jun 06 01:56:27 PM PDT 24
Finished Jun 06 01:56:33 PM PDT 24
Peak memory 205212 kb
Host smart-eb569466-e095-4a19-9e86-1491125f46f2
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1835434585 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.1835434585
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.2582667616
Short name T218
Test name
Test status
Simulation time 194461010 ps
CPU time 0.93 seconds
Started Jun 06 01:56:24 PM PDT 24
Finished Jun 06 01:56:27 PM PDT 24
Peak memory 204504 kb
Host smart-9c0b596d-c022-4752-a2a9-f1e176b88b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582667616 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.2582667616
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.438612466
Short name T191
Test name
Test status
Simulation time 1516699563 ps
CPU time 3.16 seconds
Started Jun 06 01:56:26 PM PDT 24
Finished Jun 06 01:56:32 PM PDT 24
Peak memory 205080 kb
Host smart-224c3ac1-a682-4570-bf75-cf884f42e929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438612466 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.438612466
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.2014934371
Short name T168
Test name
Test status
Simulation time 85638717 ps
CPU time 0.77 seconds
Started Jun 06 01:56:36 PM PDT 24
Finished Jun 06 01:56:41 PM PDT 24
Peak memory 204844 kb
Host smart-79d06f06-8037-4023-8750-036e3437cbac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014934371 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.2014934371
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.1810885105
Short name T156
Test name
Test status
Simulation time 39023230 ps
CPU time 0.71 seconds
Started Jun 06 01:56:52 PM PDT 24
Finished Jun 06 01:56:53 PM PDT 24
Peak memory 204852 kb
Host smart-191af8e0-73b3-430c-b9e9-72e18a6eaa35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810885105 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.1810885105
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.4252459965
Short name T178
Test name
Test status
Simulation time 78607857 ps
CPU time 0.73 seconds
Started Jun 06 01:56:46 PM PDT 24
Finished Jun 06 01:56:48 PM PDT 24
Peak memory 204824 kb
Host smart-d3fba1ed-916c-4011-b294-0a7aa35b1d08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252459965 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.4252459965
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.2386025059
Short name T227
Test name
Test status
Simulation time 266549749 ps
CPU time 0.75 seconds
Started Jun 06 01:56:50 PM PDT 24
Finished Jun 06 01:56:52 PM PDT 24
Peak memory 204836 kb
Host smart-4d33a245-2812-40af-828e-f7c1fd54beba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386025059 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.2386025059
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.2560237920
Short name T157
Test name
Test status
Simulation time 140395880 ps
CPU time 0.7 seconds
Started Jun 06 01:56:43 PM PDT 24
Finished Jun 06 01:56:45 PM PDT 24
Peak memory 204824 kb
Host smart-6ba199a6-091d-4ab6-ad4a-da38023de8ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560237920 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.2560237920
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.1026756049
Short name T48
Test name
Test status
Simulation time 52487400 ps
CPU time 0.78 seconds
Started Jun 06 01:56:54 PM PDT 24
Finished Jun 06 01:56:56 PM PDT 24
Peak memory 204620 kb
Host smart-56e0869b-229f-4184-b6bf-0ba745c980f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026756049 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.1026756049
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_stress_all.3025692659
Short name T148
Test name
Test status
Simulation time 12234022624 ps
CPU time 35.33 seconds
Started Jun 06 01:56:44 PM PDT 24
Finished Jun 06 01:57:25 PM PDT 24
Peak memory 205152 kb
Host smart-d00b9912-8741-44f9-9fb0-d66123bbbeb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025692659 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.3025692659
Directory /workspace/25.rv_dm_stress_all/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.1686151629
Short name T125
Test name
Test status
Simulation time 31443722 ps
CPU time 0.77 seconds
Started Jun 06 01:56:54 PM PDT 24
Finished Jun 06 01:56:56 PM PDT 24
Peak memory 204860 kb
Host smart-0afcef33-4b00-4584-b5fa-17aabc6863f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686151629 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.1686151629
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.900460502
Short name T162
Test name
Test status
Simulation time 41031527 ps
CPU time 0.74 seconds
Started Jun 06 01:56:55 PM PDT 24
Finished Jun 06 01:56:57 PM PDT 24
Peak memory 204896 kb
Host smart-31b2ccc9-60ba-44a2-b831-a696b8f72d7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900460502 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.900460502
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.162269868
Short name T249
Test name
Test status
Simulation time 49292181 ps
CPU time 0.74 seconds
Started Jun 06 01:56:39 PM PDT 24
Finished Jun 06 01:56:41 PM PDT 24
Peak memory 204820 kb
Host smart-35e8d0b0-4a69-404c-a0e7-4d79190db5ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162269868 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.162269868
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.1227714686
Short name T87
Test name
Test status
Simulation time 32603995 ps
CPU time 0.75 seconds
Started Jun 06 01:56:16 PM PDT 24
Finished Jun 06 01:56:18 PM PDT 24
Peak memory 204860 kb
Host smart-805ed97a-206a-4ca0-a042-2a2aa426be87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227714686 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.1227714686
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.478475250
Short name T207
Test name
Test status
Simulation time 44563076350 ps
CPU time 35.03 seconds
Started Jun 06 01:56:22 PM PDT 24
Finished Jun 06 01:56:58 PM PDT 24
Peak memory 213484 kb
Host smart-01b95178-791c-48ce-8d6c-f19233257cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478475250 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.478475250
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.1149743002
Short name T242
Test name
Test status
Simulation time 6478490690 ps
CPU time 11.32 seconds
Started Jun 06 01:56:15 PM PDT 24
Finished Jun 06 01:56:28 PM PDT 24
Peak memory 205320 kb
Host smart-c06eed79-30f5-4145-8dbf-167d061146f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149743002 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.1149743002
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.4536556
Short name T188
Test name
Test status
Simulation time 8653457119 ps
CPU time 25.83 seconds
Started Jun 06 01:56:29 PM PDT 24
Finished Jun 06 01:56:57 PM PDT 24
Peak memory 205124 kb
Host smart-f3303e79-5219-4ed4-a164-51c59db80af6
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4536556 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_tl_a
ccess.4536556
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.2143910851
Short name T12
Test name
Test status
Simulation time 134001606 ps
CPU time 0.81 seconds
Started Jun 06 01:56:27 PM PDT 24
Finished Jun 06 01:56:30 PM PDT 24
Peak memory 204132 kb
Host smart-80a777cd-8565-4ddd-9c66-3504010fd10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143910851 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.2143910851
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.3563218990
Short name T186
Test name
Test status
Simulation time 2678911032 ps
CPU time 6.57 seconds
Started Jun 06 01:56:23 PM PDT 24
Finished Jun 06 01:56:31 PM PDT 24
Peak memory 205224 kb
Host smart-ce2dda33-ddcc-46df-b61e-34ce282224fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563218990 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.3563218990
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.729140819
Short name T41
Test name
Test status
Simulation time 280453498 ps
CPU time 1.1 seconds
Started Jun 06 01:56:27 PM PDT 24
Finished Jun 06 01:56:31 PM PDT 24
Peak memory 228920 kb
Host smart-8fe2c42d-2e67-4648-905b-a032cf5407b5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729140819 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.729140819
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.1951079244
Short name T158
Test name
Test status
Simulation time 157217415 ps
CPU time 0.79 seconds
Started Jun 06 01:56:54 PM PDT 24
Finished Jun 06 01:56:57 PM PDT 24
Peak memory 204852 kb
Host smart-af3545e7-0316-492f-9922-6f1554d85fd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951079244 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.1951079244
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.3463080935
Short name T155
Test name
Test status
Simulation time 81276350 ps
CPU time 0.85 seconds
Started Jun 06 01:56:56 PM PDT 24
Finished Jun 06 01:56:58 PM PDT 24
Peak memory 204812 kb
Host smart-460e3cf5-6a90-4a6e-864e-520abda240b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463080935 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.3463080935
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.3206539537
Short name T27
Test name
Test status
Simulation time 124099244 ps
CPU time 0.82 seconds
Started Jun 06 01:56:53 PM PDT 24
Finished Jun 06 01:56:55 PM PDT 24
Peak memory 204856 kb
Host smart-17cda754-b3b5-42e1-8f70-933f8217d92c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206539537 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.3206539537
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.1015306059
Short name T122
Test name
Test status
Simulation time 105066792 ps
CPU time 0.76 seconds
Started Jun 06 01:56:53 PM PDT 24
Finished Jun 06 01:57:00 PM PDT 24
Peak memory 204808 kb
Host smart-bc88f7e2-809b-43aa-8e16-a3b3fbe855b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015306059 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.1015306059
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.4191953208
Short name T212
Test name
Test status
Simulation time 46834224 ps
CPU time 0.74 seconds
Started Jun 06 01:57:16 PM PDT 24
Finished Jun 06 01:57:18 PM PDT 24
Peak memory 204756 kb
Host smart-3d6fc900-f45e-4bd3-b160-1e1859b1966e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191953208 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.4191953208
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_stress_all.1927192852
Short name T23
Test name
Test status
Simulation time 13058890625 ps
CPU time 11.3 seconds
Started Jun 06 01:56:54 PM PDT 24
Finished Jun 06 01:57:06 PM PDT 24
Peak memory 205032 kb
Host smart-c2a2b1e2-2cfc-4399-968c-607c52147ece
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927192852 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.1927192852
Directory /workspace/35.rv_dm_stress_all/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.1980511993
Short name T66
Test name
Test status
Simulation time 66331913 ps
CPU time 0.71 seconds
Started Jun 06 01:56:55 PM PDT 24
Finished Jun 06 01:56:58 PM PDT 24
Peak memory 204860 kb
Host smart-6db7e62c-63c0-4032-aec5-b09f637cf823
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980511993 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.1980511993
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.1766080185
Short name T179
Test name
Test status
Simulation time 38036773 ps
CPU time 0.78 seconds
Started Jun 06 01:56:54 PM PDT 24
Finished Jun 06 01:56:56 PM PDT 24
Peak memory 204836 kb
Host smart-01b1d37b-5db2-44ac-a5e5-299313ad6fe1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766080185 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.1766080185
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.3700088117
Short name T175
Test name
Test status
Simulation time 160649067 ps
CPU time 0.75 seconds
Started Jun 06 01:56:55 PM PDT 24
Finished Jun 06 01:56:57 PM PDT 24
Peak memory 204840 kb
Host smart-a5c206ad-09da-4048-ba33-28e6630771cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700088117 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.3700088117
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.217943145
Short name T174
Test name
Test status
Simulation time 109742085 ps
CPU time 0.68 seconds
Started Jun 06 01:56:50 PM PDT 24
Finished Jun 06 01:56:52 PM PDT 24
Peak memory 204808 kb
Host smart-344fcd33-4155-4765-895a-c5363ae134d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217943145 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.217943145
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_stress_all.1643747233
Short name T150
Test name
Test status
Simulation time 21352229149 ps
CPU time 32.98 seconds
Started Jun 06 01:56:56 PM PDT 24
Finished Jun 06 01:57:30 PM PDT 24
Peak memory 213232 kb
Host smart-1931de93-f9f4-45c6-ac3b-d14165237260
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643747233 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.1643747233
Directory /workspace/39.rv_dm_stress_all/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.1573370288
Short name T76
Test name
Test status
Simulation time 98172479 ps
CPU time 0.77 seconds
Started Jun 06 01:56:25 PM PDT 24
Finished Jun 06 01:56:27 PM PDT 24
Peak memory 204772 kb
Host smart-c44cb2d7-75dd-431a-8b24-a0ba308476a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573370288 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.1573370288
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.1369320959
Short name T223
Test name
Test status
Simulation time 5846433026 ps
CPU time 5.44 seconds
Started Jun 06 01:56:24 PM PDT 24
Finished Jun 06 01:56:30 PM PDT 24
Peak memory 213364 kb
Host smart-f078f9ab-ec4b-47c8-b154-eedb2bb76806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369320959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.1369320959
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.255838424
Short name T251
Test name
Test status
Simulation time 2224955390 ps
CPU time 2.37 seconds
Started Jun 06 01:56:25 PM PDT 24
Finished Jun 06 01:56:28 PM PDT 24
Peak memory 205128 kb
Host smart-3aec0c7d-7c79-4c5e-90e4-b649c2c66d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255838424 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.255838424
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.3007880712
Short name T185
Test name
Test status
Simulation time 3177495604 ps
CPU time 3.68 seconds
Started Jun 06 01:56:25 PM PDT 24
Finished Jun 06 01:56:30 PM PDT 24
Peak memory 205152 kb
Host smart-a68e3765-e8db-403c-a05e-3f7c3ae748c8
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3007880712 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.3007880712
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.3496330061
Short name T183
Test name
Test status
Simulation time 323994765 ps
CPU time 0.75 seconds
Started Jun 06 01:56:24 PM PDT 24
Finished Jun 06 01:56:26 PM PDT 24
Peak memory 204544 kb
Host smart-667d2ccb-95da-434e-ad5a-466cbb0cc4b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496330061 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.3496330061
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.4259127091
Short name T255
Test name
Test status
Simulation time 958330183 ps
CPU time 1.59 seconds
Started Jun 06 01:56:14 PM PDT 24
Finished Jun 06 01:56:16 PM PDT 24
Peak memory 205104 kb
Host smart-3741bfb4-d31d-4c83-9110-57982943dd99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259127091 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.4259127091
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.804680926
Short name T42
Test name
Test status
Simulation time 2604803318 ps
CPU time 7.5 seconds
Started Jun 06 01:56:22 PM PDT 24
Finished Jun 06 01:56:31 PM PDT 24
Peak memory 229068 kb
Host smart-75cc0d2e-68af-4ae7-a654-f628516bdf4b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804680926 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.804680926
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.4015202691
Short name T154
Test name
Test status
Simulation time 65051892 ps
CPU time 0.77 seconds
Started Jun 06 01:57:01 PM PDT 24
Finished Jun 06 01:57:03 PM PDT 24
Peak memory 204784 kb
Host smart-96b15e18-1614-483a-9953-cc6178becab1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015202691 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.4015202691
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.3725135018
Short name T165
Test name
Test status
Simulation time 40974670 ps
CPU time 0.73 seconds
Started Jun 06 01:56:53 PM PDT 24
Finished Jun 06 01:56:55 PM PDT 24
Peak memory 204836 kb
Host smart-729ae63d-a3a6-4b2b-a54b-bc0b1dde4a1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725135018 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.3725135018
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.3226408438
Short name T68
Test name
Test status
Simulation time 129160592 ps
CPU time 0.71 seconds
Started Jun 06 01:57:01 PM PDT 24
Finished Jun 06 01:57:03 PM PDT 24
Peak memory 204784 kb
Host smart-3380b2a4-3205-4350-b01d-40415309a21f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226408438 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.3226408438
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_stress_all.2329723922
Short name T33
Test name
Test status
Simulation time 4803097899 ps
CPU time 4.14 seconds
Started Jun 06 01:56:54 PM PDT 24
Finished Jun 06 01:57:00 PM PDT 24
Peak memory 205084 kb
Host smart-08d6b18d-56f6-4823-bfcf-eeb2f937b592
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329723922 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.2329723922
Directory /workspace/42.rv_dm_stress_all/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.4216196534
Short name T28
Test name
Test status
Simulation time 64544118 ps
CPU time 0.84 seconds
Started Jun 06 01:56:53 PM PDT 24
Finished Jun 06 01:56:55 PM PDT 24
Peak memory 204824 kb
Host smart-175a7b6b-2e94-4f63-8bb0-ebefe25943bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216196534 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.4216196534
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.3841002135
Short name T124
Test name
Test status
Simulation time 81374891 ps
CPU time 0.74 seconds
Started Jun 06 01:56:55 PM PDT 24
Finished Jun 06 01:56:57 PM PDT 24
Peak memory 204852 kb
Host smart-975a313b-3146-4fce-9d29-0047e372a1f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841002135 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.3841002135
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.3396752028
Short name T169
Test name
Test status
Simulation time 122439085 ps
CPU time 0.89 seconds
Started Jun 06 01:56:54 PM PDT 24
Finished Jun 06 01:56:56 PM PDT 24
Peak memory 204788 kb
Host smart-2cb9e3b9-432f-49f4-ad16-d8db89c5d474
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396752028 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.3396752028
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_stress_all.741473294
Short name T145
Test name
Test status
Simulation time 26536201199 ps
CPU time 67.02 seconds
Started Jun 06 01:56:57 PM PDT 24
Finished Jun 06 01:58:05 PM PDT 24
Peak memory 213252 kb
Host smart-489a1d98-8d12-474e-9d43-29ae07565c03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741473294 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.741473294
Directory /workspace/45.rv_dm_stress_all/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.2277470658
Short name T166
Test name
Test status
Simulation time 71818097 ps
CPU time 0.89 seconds
Started Jun 06 01:57:07 PM PDT 24
Finished Jun 06 01:57:09 PM PDT 24
Peak memory 204836 kb
Host smart-79b46d59-64eb-4144-bb6f-59fbff54c14e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277470658 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.2277470658
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_stress_all.1956233625
Short name T143
Test name
Test status
Simulation time 22541984000 ps
CPU time 61.6 seconds
Started Jun 06 01:56:55 PM PDT 24
Finished Jun 06 01:57:58 PM PDT 24
Peak memory 205108 kb
Host smart-46085821-c506-41f9-b66e-ad50464c3422
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956233625 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.1956233625
Directory /workspace/46.rv_dm_stress_all/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.1484609296
Short name T164
Test name
Test status
Simulation time 116947913 ps
CPU time 0.72 seconds
Started Jun 06 01:56:53 PM PDT 24
Finished Jun 06 01:56:54 PM PDT 24
Peak memory 204824 kb
Host smart-155f4697-ba70-4c57-b106-946c34c9d398
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484609296 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.1484609296
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.3463269617
Short name T176
Test name
Test status
Simulation time 159849489 ps
CPU time 0.86 seconds
Started Jun 06 01:56:56 PM PDT 24
Finished Jun 06 01:56:58 PM PDT 24
Peak memory 204824 kb
Host smart-b4f770cf-a51a-472c-95a0-953bcfa474c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463269617 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.3463269617
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.2076781095
Short name T160
Test name
Test status
Simulation time 42863607 ps
CPU time 0.76 seconds
Started Jun 06 01:56:57 PM PDT 24
Finished Jun 06 01:57:00 PM PDT 24
Peak memory 204836 kb
Host smart-fa061870-1ac8-4446-a3de-4d80bd665930
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076781095 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.2076781095
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.3947949353
Short name T171
Test name
Test status
Simulation time 114700946 ps
CPU time 0.74 seconds
Started Jun 06 01:56:27 PM PDT 24
Finished Jun 06 01:56:30 PM PDT 24
Peak memory 204804 kb
Host smart-3d69f164-4d8c-42f8-9510-669adb3d19d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947949353 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.3947949353
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.1093492358
Short name T228
Test name
Test status
Simulation time 3442799823 ps
CPU time 6.11 seconds
Started Jun 06 01:56:28 PM PDT 24
Finished Jun 06 01:56:37 PM PDT 24
Peak memory 205268 kb
Host smart-246ffef8-dded-40b2-8cbf-538d15433552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093492358 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.1093492358
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.1317838505
Short name T4
Test name
Test status
Simulation time 8199518443 ps
CPU time 8.11 seconds
Started Jun 06 01:56:23 PM PDT 24
Finished Jun 06 01:56:33 PM PDT 24
Peak memory 205204 kb
Host smart-8623d07c-95a1-4c97-ae38-4d8647fe6e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317838505 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.1317838505
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.2343430236
Short name T226
Test name
Test status
Simulation time 3109174016 ps
CPU time 2.75 seconds
Started Jun 06 01:56:29 PM PDT 24
Finished Jun 06 01:56:34 PM PDT 24
Peak memory 205272 kb
Host smart-8794abbc-fc93-4333-ba82-b103fbe583e0
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2343430236 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t
l_access.2343430236
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.2494658534
Short name T182
Test name
Test status
Simulation time 2251634801 ps
CPU time 2.01 seconds
Started Jun 06 01:56:22 PM PDT 24
Finished Jun 06 01:56:26 PM PDT 24
Peak memory 205188 kb
Host smart-f21b3130-e1fb-4b17-9871-5f7040e771e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494658534 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.2494658534
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.1301718928
Short name T161
Test name
Test status
Simulation time 104317659 ps
CPU time 0.97 seconds
Started Jun 06 01:56:26 PM PDT 24
Finished Jun 06 01:56:30 PM PDT 24
Peak memory 204772 kb
Host smart-ceeddead-05e0-4afa-a1d6-7af11155b5b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301718928 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.1301718928
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.3292838492
Short name T244
Test name
Test status
Simulation time 7819566359 ps
CPU time 20.31 seconds
Started Jun 06 01:56:23 PM PDT 24
Finished Jun 06 01:56:44 PM PDT 24
Peak memory 205220 kb
Host smart-da6d1583-49a9-4df2-a5d9-360148ad2c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292838492 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.3292838492
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.4032374457
Short name T221
Test name
Test status
Simulation time 12109694231 ps
CPU time 33.15 seconds
Started Jun 06 01:56:26 PM PDT 24
Finished Jun 06 01:57:01 PM PDT 24
Peak memory 213428 kb
Host smart-2f58a807-a040-45ba-be79-977082ff933c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032374457 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.4032374457
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.4182601923
Short name T70
Test name
Test status
Simulation time 2787919979 ps
CPU time 3.95 seconds
Started Jun 06 01:56:29 PM PDT 24
Finished Jun 06 01:56:35 PM PDT 24
Peak memory 205188 kb
Host smart-597ba87d-9243-458e-a371-38d5c914bb36
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4182601923 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t
l_access.4182601923
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.2567250145
Short name T220
Test name
Test status
Simulation time 10348369152 ps
CPU time 15.36 seconds
Started Jun 06 01:56:26 PM PDT 24
Finished Jun 06 01:56:44 PM PDT 24
Peak memory 205152 kb
Host smart-aa36d762-075a-4d83-82d1-a4e9ba91fb4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567250145 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.2567250145
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.270418343
Short name T233
Test name
Test status
Simulation time 150225506 ps
CPU time 0.84 seconds
Started Jun 06 01:56:44 PM PDT 24
Finished Jun 06 01:56:46 PM PDT 24
Peak memory 204792 kb
Host smart-e3845df3-4474-4e96-91dc-26c7cc28776a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270418343 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.270418343
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.3657850889
Short name T205
Test name
Test status
Simulation time 43263266597 ps
CPU time 84.11 seconds
Started Jun 06 01:56:28 PM PDT 24
Finished Jun 06 01:57:54 PM PDT 24
Peak memory 220252 kb
Host smart-1fd33170-f103-43ea-bd78-bccbf613df04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657850889 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.3657850889
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.3601126319
Short name T203
Test name
Test status
Simulation time 7219714252 ps
CPU time 18.54 seconds
Started Jun 06 01:56:28 PM PDT 24
Finished Jun 06 01:56:49 PM PDT 24
Peak memory 205608 kb
Host smart-cb19cc0a-1d37-4b44-b18d-99801286fe6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601126319 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.3601126319
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.2030516504
Short name T49
Test name
Test status
Simulation time 6453773837 ps
CPU time 3.58 seconds
Started Jun 06 01:56:28 PM PDT 24
Finished Jun 06 01:56:34 PM PDT 24
Peak memory 205236 kb
Host smart-8cb5a3ef-68c7-48a0-8d97-6f39d0d92ffa
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2030516504 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.2030516504
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.3373315640
Short name T253
Test name
Test status
Simulation time 1072838279 ps
CPU time 3.64 seconds
Started Jun 06 01:56:33 PM PDT 24
Finished Jun 06 01:56:38 PM PDT 24
Peak memory 205100 kb
Host smart-431b9eb8-8c30-4383-a188-cf9b9ad31dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373315640 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.3373315640
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.3233094263
Short name T214
Test name
Test status
Simulation time 97315638 ps
CPU time 0.79 seconds
Started Jun 06 01:56:28 PM PDT 24
Finished Jun 06 01:56:30 PM PDT 24
Peak memory 204844 kb
Host smart-da3f6406-1b19-4ffc-b851-411bfc7d3395
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233094263 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.3233094263
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.2296510658
Short name T22
Test name
Test status
Simulation time 49676842180 ps
CPU time 21.86 seconds
Started Jun 06 01:56:33 PM PDT 24
Finished Jun 06 01:56:56 PM PDT 24
Peak memory 213372 kb
Host smart-9b584492-95ca-4d1f-aaf1-400f4d2ea36e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296510658 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.2296510658
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.588209102
Short name T235
Test name
Test status
Simulation time 2097496400 ps
CPU time 6.81 seconds
Started Jun 06 01:56:28 PM PDT 24
Finished Jun 06 01:56:36 PM PDT 24
Peak memory 205068 kb
Host smart-8dd74165-abea-4149-a6e2-7a69e1dfc853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588209102 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.588209102
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.3733207873
Short name T1
Test name
Test status
Simulation time 1823633333 ps
CPU time 3.77 seconds
Started Jun 06 01:56:25 PM PDT 24
Finished Jun 06 01:56:31 PM PDT 24
Peak memory 205172 kb
Host smart-44482918-c88c-44fd-b1df-91ac1e99a35b
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3733207873 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t
l_access.3733207873
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.1799191429
Short name T240
Test name
Test status
Simulation time 2673226981 ps
CPU time 2.59 seconds
Started Jun 06 01:56:28 PM PDT 24
Finished Jun 06 01:56:33 PM PDT 24
Peak memory 205144 kb
Host smart-b1ad4abd-c79a-4108-b7e1-79aeb9c21302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799191429 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.1799191429
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.1705169444
Short name T159
Test name
Test status
Simulation time 196999831 ps
CPU time 0.82 seconds
Started Jun 06 01:56:31 PM PDT 24
Finished Jun 06 01:56:33 PM PDT 24
Peak memory 204836 kb
Host smart-989451e2-4f7b-40fe-992c-904fa063880f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705169444 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.1705169444
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.3930723310
Short name T208
Test name
Test status
Simulation time 724054272 ps
CPU time 1.47 seconds
Started Jun 06 01:56:25 PM PDT 24
Finished Jun 06 01:56:27 PM PDT 24
Peak memory 205124 kb
Host smart-c7ce74c7-a432-420f-8bf9-8e5c44d82fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930723310 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.3930723310
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.3382851232
Short name T257
Test name
Test status
Simulation time 8332633334 ps
CPU time 6.89 seconds
Started Jun 06 01:56:26 PM PDT 24
Finished Jun 06 01:56:36 PM PDT 24
Peak memory 213352 kb
Host smart-f08d868a-2241-4e5f-964a-aff458c4cb02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382851232 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.3382851232
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.528421701
Short name T232
Test name
Test status
Simulation time 1633153514 ps
CPU time 3.76 seconds
Started Jun 06 01:56:28 PM PDT 24
Finished Jun 06 01:56:34 PM PDT 24
Peak memory 205004 kb
Host smart-44f60c77-440f-4db1-801b-de8441144876
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=528421701 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_tl
_access.528421701
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.3407908551
Short name T204
Test name
Test status
Simulation time 9335891172 ps
CPU time 7.2 seconds
Started Jun 06 01:56:35 PM PDT 24
Finished Jun 06 01:56:43 PM PDT 24
Peak memory 205400 kb
Host smart-c2684fc8-df56-421f-9148-aef6f731b2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407908551 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.3407908551
Directory /workspace/9.rv_dm_sba_tl_access/latest
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