Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 193200 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 522910 1 T2 11 T8 24 T6 6



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 463032 1 T8 16 T6 6 T4 14
values[0x0] 124035 1 T2 15 T8 8 T6 6
values[0x1] 129043 1 T2 21 T8 8 T6 2



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 145879 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 570231 1 T2 14 T8 27 T6 6



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 2472 1 T4 1 T28 5 T142 3
valid_sources[0x01] 3045 1 T28 5 T10 1 T40 1
valid_sources[0x02] 2482 1 T5 1 T143 1 T144 1
valid_sources[0x03] 2411 1 T4 2 T33 1 T10 2
valid_sources[0x04] 2324 1 T28 2 T10 1 T145 1
valid_sources[0x05] 2693 1 T10 1 T146 1 T144 1
valid_sources[0x06] 2300 1 T10 1 T147 12 T36 1
valid_sources[0x07] 2728 1 T2 1 T33 1 T148 1
valid_sources[0x08] 2646 1 T33 2 T144 1 T149 1
valid_sources[0x09] 2515 1 T34 33 T150 1 T53 88
valid_sources[0x0a] 2415 1 T151 1 T145 1 T152 1
valid_sources[0x0b] 3042 1 T8 1 T144 3 T53 21
valid_sources[0x0c] 2569 1 T2 1 T36 1 T41 2
valid_sources[0x0d] 3015 1 T8 1 T17 2 T144 1
valid_sources[0x0e] 2905 1 T4 1 T11 1 T37 4
valid_sources[0x0f] 2558 1 T53 23 T50 19 T54 3
valid_sources[0x10] 2563 1 T36 1 T146 4 T143 2
valid_sources[0x11] 2744 1 T36 3 T150 1 T142 3
valid_sources[0x12] 3565 1 T145 3 T36 1 T153 1
valid_sources[0x13] 2865 1 T10 1 T145 2 T36 2
valid_sources[0x14] 2331 1 T4 2 T11 2 T142 1
valid_sources[0x15] 2541 1 T8 1 T38 1 T11 2
valid_sources[0x16] 2992 1 T4 1 T33 2 T147 2
valid_sources[0x17] 2339 1 T2 1 T10 2 T151 2
valid_sources[0x18] 3030 1 T4 1 T148 3 T146 1
valid_sources[0x19] 2759 1 T33 1 T146 2 T142 1
valid_sources[0x1a] 2578 1 T146 1 T53 24 T50 18
valid_sources[0x1b] 2959 1 T38 1 T33 2 T10 1
valid_sources[0x1c] 2613 1 T2 1 T147 12 T36 1
valid_sources[0x1d] 2865 1 T43 2 T149 1 T53 13
valid_sources[0x1e] 2641 1 T4 3 T28 1 T14 1
valid_sources[0x1f] 2552 1 T4 1 T34 1 T11 1
valid_sources[0x20] 2773 1 T150 1 T37 3 T53 2
valid_sources[0x21] 2472 1 T2 1 T4 3 T33 1
valid_sources[0x22] 2440 1 T145 3 T11 1 T37 1
valid_sources[0x23] 3054 1 T4 1 T151 1 T11 1
valid_sources[0x24] 2816 1 T28 1 T154 12 T11 1
valid_sources[0x25] 2688 1 T10 1 T40 1 T145 2
valid_sources[0x26] 2191 1 T2 1 T147 9 T11 1
valid_sources[0x27] 2994 1 T33 2 T36 1 T153 1
valid_sources[0x28] 2417 1 T2 2 T8 1 T28 7
valid_sources[0x29] 2476 1 T4 1 T5 2 T11 3
valid_sources[0x2a] 2675 1 T151 1 T40 1 T37 1
valid_sources[0x2b] 2472 1 T4 1 T28 4 T36 1
valid_sources[0x2c] 2655 1 T4 1 T146 1 T153 1
valid_sources[0x2d] 2505 1 T145 1 T146 1 T153 1
valid_sources[0x2e] 2917 1 T4 1 T152 2 T43 1
valid_sources[0x2f] 2774 1 T8 1 T28 1 T146 1
valid_sources[0x30] 2496 1 T4 3 T11 1 T36 1
valid_sources[0x31] 2824 1 T28 2 T144 2 T149 2
valid_sources[0x32] 2157 1 T38 1 T33 3 T11 1
valid_sources[0x33] 2219 1 T2 1 T28 4 T152 1
valid_sources[0x34] 3318 1 T10 2 T40 1 T152 2
valid_sources[0x35] 2738 1 T4 1 T40 1 T155 93
valid_sources[0x36] 4080 1 T10 1 T11 1 T36 1
valid_sources[0x37] 2351 1 T38 3 T53 24 T50 23
valid_sources[0x38] 2682 1 T2 1 T156 3 T53 35
valid_sources[0x39] 2769 1 T39 11 T153 1 T144 1
valid_sources[0x3a] 3067 1 T8 1 T10 1 T11 6
valid_sources[0x3b] 2530 1 T33 4 T146 2 T150 1
valid_sources[0x3c] 2477 1 T4 1 T28 3 T152 1
valid_sources[0x3d] 2605 1 T4 2 T11 2 T146 2
valid_sources[0x3e] 2244 1 T2 1 T28 1 T40 2
valid_sources[0x3f] 2909 1 T28 1 T144 1 T53 29
valid_sources[0x40] 2945 1 T10 1 T11 2 T53 47
valid_sources[0x41] 2750 1 T4 1 T148 2 T151 1
valid_sources[0x42] 3032 1 T2 1 T36 1 T153 1
valid_sources[0x43] 2699 1 T148 4 T14 1 T50 24
valid_sources[0x44] 3079 1 T2 2 T4 1 T28 1
valid_sources[0x45] 2896 1 T2 1 T145 1 T11 1
valid_sources[0x46] 2934 1 T28 5 T36 1 T149 1
valid_sources[0x47] 2608 1 T151 1 T11 1 T152 2
valid_sources[0x48] 2572 1 T144 2 T53 38 T50 28
valid_sources[0x49] 2606 1 T22 1 T151 3 T36 1
valid_sources[0x4a] 2228 1 T8 1 T33 2 T10 1
valid_sources[0x4b] 3010 1 T4 3 T152 1 T153 1
valid_sources[0x4c] 2379 1 T53 18 T50 17 T52 1
valid_sources[0x4d] 2708 1 T2 1 T8 2 T4 3
valid_sources[0x4e] 2665 1 T2 1 T152 3 T37 1
valid_sources[0x4f] 2624 1 T151 3 T11 1 T37 3
valid_sources[0x50] 3082 1 T10 3 T36 1 T142 2
valid_sources[0x51] 2580 1 T2 1 T33 2 T145 2
valid_sources[0x52] 2113 1 T36 1 T153 1 T53 16
valid_sources[0x53] 3093 1 T8 1 T33 1 T151 3
valid_sources[0x54] 3245 1 T153 1 T53 3 T50 27
valid_sources[0x55] 3184 1 T4 1 T36 1 T53 31
valid_sources[0x56] 2730 1 T149 1 T53 42 T50 28
valid_sources[0x57] 2720 1 T20 107 T10 1 T36 2
valid_sources[0x58] 2814 1 T151 1 T42 2 T144 1
valid_sources[0x59] 3107 1 T4 2 T153 1 T37 1
valid_sources[0x5a] 2876 1 T10 1 T53 12 T50 25
valid_sources[0x5b] 2542 1 T53 29 T50 20 T75 5
valid_sources[0x5c] 2814 1 T146 1 T157 1 T53 13
valid_sources[0x5d] 2933 1 T10 1 T145 1 T152 4
valid_sources[0x5e] 2413 1 T28 1 T149 2 T53 32
valid_sources[0x5f] 2683 1 T4 1 T28 1 T10 1
valid_sources[0x60] 2997 1 T8 1 T10 3 T142 1
valid_sources[0x61] 2365 1 T38 1 T11 1 T142 1
valid_sources[0x62] 2510 1 T151 1 T11 1 T36 2
valid_sources[0x63] 2576 1 T10 1 T144 1 T149 2
valid_sources[0x64] 3168 1 T36 1 T149 2 T53 14
valid_sources[0x65] 2393 1 T153 1 T53 38 T50 24
valid_sources[0x66] 2498 1 T151 2 T146 1 T42 1
valid_sources[0x67] 2580 1 T148 2 T36 1 T146 2
valid_sources[0x68] 3598 1 T8 1 T151 1 T146 2
valid_sources[0x69] 2920 1 T152 2 T53 10 T50 24
valid_sources[0x6a] 2601 1 T53 36 T50 23 T52 1
valid_sources[0x6b] 2614 1 T4 1 T11 1 T153 1
valid_sources[0x6c] 2701 1 T4 1 T148 1 T151 2
valid_sources[0x6d] 2969 1 T4 1 T33 2 T146 2
valid_sources[0x6e] 2870 1 T151 2 T145 1 T153 1
valid_sources[0x6f] 2760 1 T2 2 T148 1 T36 1
valid_sources[0x70] 2724 1 T151 1 T152 1 T146 2
valid_sources[0x71] 3151 1 T4 4 T17 9 T53 62
valid_sources[0x72] 3026 1 T34 5 T145 2 T36 1
valid_sources[0x73] 3061 1 T2 1 T158 10 T153 1
valid_sources[0x74] 3363 1 T33 1 T151 1 T147 4
valid_sources[0x75] 2933 1 T145 1 T144 1 T53 48
valid_sources[0x76] 2629 1 T4 1 T40 1 T153 1
valid_sources[0x77] 2781 1 T152 2 T146 5 T53 29
valid_sources[0x78] 3081 1 T11 1 T153 1 T149 2
valid_sources[0x79] 3705 1 T4 1 T53 12 T50 29
valid_sources[0x7a] 3159 1 T11 1 T149 1 T53 11
valid_sources[0x7b] 3108 1 T36 1 T152 2 T41 1
valid_sources[0x7c] 4577 1 T10 1 T151 2 T145 1
valid_sources[0x7d] 2656 1 T4 2 T153 1 T144 1
valid_sources[0x7e] 3207 1 T4 1 T147 23 T11 1
valid_sources[0x7f] 3746 1 T8 1 T145 1 T36 1
valid_sources[0x80] 2360 1 T36 1 T50 24 T52 2



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 279066 1 T8 8 T6 4 T4 10
values[0x0] all_enables biggest_size 122092 1 T2 7 T8 8 T6 2
values[0x1] all_enables biggest_size 121752 1 T2 4 T8 8 T4 10


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 4413 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 21491 1 T3 1 T23 1 T24 1



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 9599 1 T53 48 T50 35 T52 107
values[0x0] 7914 1 T3 2 T23 2 T24 1
values[0x1] 8391 1 T3 3 T23 2 T24 4



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 3288 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 22616 1 T3 2 T23 2 T24 1



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 100 1 T56 1 T159 1 T160 1
valid_sources[0x01] 107 1 T52 1 T75 2 T78 2
valid_sources[0x02] 74 1 T52 3 T75 1 T87 1
valid_sources[0x03] 70 1 T53 1 T50 1 T52 1
valid_sources[0x04] 123 1 T52 4 T51 1 T75 1
valid_sources[0x05] 78 1 T46 1 T53 1 T52 3
valid_sources[0x06] 77 1 T55 1 T161 1 T52 5
valid_sources[0x07] 98 1 T24 5 T162 1 T50 1
valid_sources[0x08] 61 1 T162 3 T159 1 T163 1
valid_sources[0x09] 91 1 T53 2 T51 1 T75 2
valid_sources[0x0a] 86 1 T164 1 T52 2 T75 2
valid_sources[0x0b] 56 1 T56 1 T52 4 T51 1
valid_sources[0x0c] 151 1 T164 1 T53 1 T52 1
valid_sources[0x0d] 111 1 T52 2 T80 2 T122 2
valid_sources[0x0e] 103 1 T162 4 T165 1 T166 6
valid_sources[0x0f] 80 1 T46 1 T55 1 T167 2
valid_sources[0x10] 151 1 T52 3 T51 1 T75 1
valid_sources[0x11] 144 1 T46 1 T161 1 T75 3
valid_sources[0x12] 105 1 T52 1 T78 1 T80 1
valid_sources[0x13] 60 1 T168 1 T52 1 T82 1
valid_sources[0x14] 201 1 T53 3 T52 1 T75 4
valid_sources[0x15] 138 1 T55 1 T50 1 T75 4
valid_sources[0x16] 65 1 T50 2 T52 3 T75 2
valid_sources[0x17] 77 1 T52 1 T75 1 T78 1
valid_sources[0x18] 113 1 T50 6 T89 1 T83 3
valid_sources[0x19] 82 1 T52 1 T75 3 T87 4
valid_sources[0x1a] 65 1 T169 1 T170 1 T52 1
valid_sources[0x1b] 401 1 T55 1 T52 3 T29 350
valid_sources[0x1c] 116 1 T171 1 T52 4 T51 2
valid_sources[0x1d] 77 1 T162 2 T52 1 T80 3
valid_sources[0x1e] 52 1 T52 5 T75 1 T78 1
valid_sources[0x1f] 59 1 T55 1 T52 1 T75 1
valid_sources[0x20] 109 1 T52 2 T75 3 T78 2
valid_sources[0x21] 82 1 T166 4 T52 2 T75 1
valid_sources[0x22] 75 1 T172 1 T160 1 T53 2
valid_sources[0x23] 166 1 T3 5 T160 1 T52 2
valid_sources[0x24] 99 1 T173 3 T52 2 T75 2
valid_sources[0x25] 66 1 T53 2 T75 1 T80 1
valid_sources[0x26] 56 1 T52 1 T54 1 T75 3
valid_sources[0x27] 90 1 T52 1 T75 2 T80 1
valid_sources[0x28] 58 1 T159 1 T163 1 T52 2
valid_sources[0x29] 103 1 T174 1 T52 5 T75 1
valid_sources[0x2a] 48 1 T167 5 T75 1 T80 1
valid_sources[0x2b] 105 1 T175 1 T176 1 T53 1
valid_sources[0x2c] 96 1 T52 5 T54 2 T82 3
valid_sources[0x2d] 87 1 T52 3 T75 1 T78 1
valid_sources[0x2e] 88 1 T56 1 T163 3 T53 1
valid_sources[0x2f] 63 1 T52 1 T75 1 T78 1
valid_sources[0x30] 70 1 T174 2 T52 4 T75 1
valid_sources[0x31] 74 1 T52 2 T75 3 T82 3
valid_sources[0x32] 90 1 T161 7 T75 3 T82 9
valid_sources[0x33] 47 1 T56 1 T75 1 T80 2
valid_sources[0x34] 124 1 T75 3 T80 1 T81 1
valid_sources[0x35] 51 1 T52 1 T75 1 T81 1
valid_sources[0x36] 76 1 T177 1 T168 9 T52 1
valid_sources[0x37] 62 1 T52 4 T51 1 T75 6
valid_sources[0x38] 79 1 T52 1 T75 4 T78 1
valid_sources[0x39] 145 1 T177 1 T50 2 T52 3
valid_sources[0x3a] 59 1 T52 2 T51 1 T75 2
valid_sources[0x3b] 89 1 T75 1 T78 1 T82 2
valid_sources[0x3c] 84 1 T53 3 T52 1 T51 1
valid_sources[0x3d] 139 1 T52 3 T51 1 T75 3
valid_sources[0x3e] 110 1 T165 1 T52 2 T75 1
valid_sources[0x3f] 120 1 T52 3 T75 4 T78 1
valid_sources[0x40] 60 1 T174 1 T75 8 T80 2
valid_sources[0x41] 77 1 T178 2 T179 2 T52 2
valid_sources[0x42] 177 1 T52 2 T51 5 T75 2
valid_sources[0x43] 62 1 T52 1 T78 1 T80 3
valid_sources[0x44] 92 1 T52 3 T51 1 T75 3
valid_sources[0x45] 62 1 T177 1 T52 2 T75 5
valid_sources[0x46] 85 1 T52 4 T75 3 T78 1
valid_sources[0x47] 84 1 T53 1 T52 2 T75 2
valid_sources[0x48] 222 1 T50 1 T52 1 T75 1
valid_sources[0x49] 121 1 T52 1 T51 2 T75 2
valid_sources[0x4a] 72 1 T75 3 T78 1 T87 1
valid_sources[0x4b] 61 1 T174 1 T52 1 T75 2
valid_sources[0x4c] 90 1 T53 2 T52 1 T75 3
valid_sources[0x4d] 60 1 T50 2 T52 2 T75 5
valid_sources[0x4e] 186 1 T52 2 T78 1 T82 2
valid_sources[0x4f] 69 1 T165 2 T52 1 T51 1
valid_sources[0x50] 141 1 T52 1 T75 5 T29 59
valid_sources[0x51] 117 1 T172 1 T52 4 T75 2
valid_sources[0x52] 59 1 T52 1 T80 2 T122 1
valid_sources[0x53] 194 1 T177 1 T53 1 T52 1
valid_sources[0x54] 444 1 T167 2 T50 2 T52 3
valid_sources[0x55] 71 1 T164 1 T52 1 T75 6
valid_sources[0x56] 63 1 T75 2 T78 3 T83 1
valid_sources[0x57] 63 1 T53 3 T50 1 T52 1
valid_sources[0x58] 95 1 T55 1 T159 1 T52 3
valid_sources[0x59] 71 1 T180 8 T125 12 T50 1
valid_sources[0x5a] 81 1 T75 3 T80 1 T83 1
valid_sources[0x5b] 180 1 T53 1 T52 1 T75 2
valid_sources[0x5c] 62 1 T52 5 T78 1 T82 1
valid_sources[0x5d] 79 1 T167 1 T52 4 T75 3
valid_sources[0x5e] 110 1 T53 3 T52 2 T75 4
valid_sources[0x5f] 63 1 T167 1 T53 1 T52 3
valid_sources[0x60] 60 1 T52 2 T75 2 T80 2
valid_sources[0x61] 70 1 T56 1 T159 1 T122 1
valid_sources[0x62] 220 1 T75 4 T82 1 T83 1
valid_sources[0x63] 88 1 T160 1 T52 3 T87 1
valid_sources[0x64] 46 1 T50 1 T52 5 T85 2
valid_sources[0x65] 63 1 T53 1 T75 3 T29 1
valid_sources[0x66] 53 1 T50 1 T78 1 T97 6
valid_sources[0x67] 117 1 T52 3 T75 6 T78 1
valid_sources[0x68] 121 1 T181 2 T53 2 T52 3
valid_sources[0x69] 78 1 T53 1 T52 1 T78 4
valid_sources[0x6a] 76 1 T68 15 T53 1 T52 1
valid_sources[0x6b] 112 1 T52 2 T75 1 T82 1
valid_sources[0x6c] 78 1 T75 2 T87 1 T80 1
valid_sources[0x6d] 60 1 T52 2 T75 1 T78 2
valid_sources[0x6e] 86 1 T168 1 T52 1 T75 1
valid_sources[0x6f] 95 1 T53 1 T52 1 T51 2
valid_sources[0x70] 106 1 T160 1 T53 1 T50 1
valid_sources[0x71] 45 1 T87 1 T81 3 T123 2
valid_sources[0x72] 66 1 T53 1 T75 1 T78 2
valid_sources[0x73] 107 1 T171 3 T51 1 T75 3
valid_sources[0x74] 207 1 T55 1 T75 3 T78 1
valid_sources[0x75] 51 1 T53 1 T75 1 T80 1
valid_sources[0x76] 227 1 T52 1 T75 1 T29 158
valid_sources[0x77] 95 1 T182 14 T52 1 T51 1
valid_sources[0x78] 89 1 T52 3 T51 1 T75 1
valid_sources[0x79] 95 1 T52 2 T75 2 T82 1
valid_sources[0x7a] 77 1 T53 6 T52 4 T75 2
valid_sources[0x7b] 76 1 T53 1 T52 1 T75 2
valid_sources[0x7c] 49 1 T77 2 T52 1 T75 2
valid_sources[0x7d] 60 1 T52 2 T78 1 T89 1
valid_sources[0x7e] 55 1 T53 2 T50 1 T52 4
valid_sources[0x7f] 71 1 T55 1 T162 4 T50 2
valid_sources[0x80] 81 1 T176 1 T163 1 T52 4



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 6997 1 T53 48 T50 11 T52 103
values[0x0] all_enables biggest_size 7242 1 T46 1 T47 1 T58 1
values[0x1] all_enables biggest_size 7252 1 T3 1 T23 1 T24 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%