SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[rv_dm_mem_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[rv_dm_regs_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 741467 | 1 | T2 | 36 | T8 | 32 | T6 | 14 | |||
auto[1] | 22588 | 1 | T36 | 80 | T37 | 80 | T50 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 763852 | 1 | T2 | 36 | T8 | 32 | T6 | 14 | |||
values[1] | 22 | 1 | T50 | 2 | T81 | 1 | T137 | 1 | |||
values[2] | 7 | 1 | T135 | 1 | T129 | 1 | T132 | 1 | |||
values[3] | 92 | 1 | T50 | 1 | T123 | 6 | T137 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 763846 | 1 | T2 | 36 | T8 | 32 | T6 | 14 | |||
values[1] | 30 | 1 | T50 | 1 | T81 | 1 | T123 | 1 | |||
values[2] | 8 | 1 | T123 | 1 | T137 | 1 | T128 | 2 | |||
values[3] | 99 | 1 | T50 | 2 | T81 | 4 | T123 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 763745 | 1 | T2 | 36 | T8 | 32 | T6 | 14 | |||
auto[TlIntgErrCmd] | 101 | 1 | T50 | 5 | T81 | 4 | T123 | 8 | |||
auto[TlIntgErrData] | 107 | 1 | T50 | 4 | T81 | 4 | T123 | 6 | |||
auto[TlIntgErrBoth] | 102 | 1 | T50 | 1 | T81 | 2 | T123 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | |||
auto[0] | 46200 | 0 | T3 | 5 | T23 | 4 | T24 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 45987 | 1 | T3 | 5 | T23 | 4 | T24 | 5 | |||
values[1] | 19 | 1 | T81 | 1 | T123 | 1 | T137 | 2 | |||
values[2] | 4 | 1 | T123 | 1 | T139 | 2 | T140 | 1 | |||
values[3] | 97 | 1 | T50 | 1 | T81 | 4 | T123 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 45996 | 1 | T3 | 5 | T23 | 4 | T24 | 5 | |||
values[1] | 22 | 1 | T50 | 1 | T81 | 1 | T123 | 3 | |||
values[2] | 5 | 1 | T139 | 1 | T138 | 1 | T133 | 1 | |||
values[3] | 96 | 1 | T50 | 2 | T81 | 4 | T123 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 45890 | 1 | T3 | 5 | T23 | 4 | T24 | 5 | |||
auto[TlIntgErrCmd] | 106 | 1 | T50 | 2 | T81 | 5 | T123 | 7 | |||
auto[TlIntgErrData] | 97 | 1 | T50 | 6 | T81 | 2 | T123 | 7 | |||
auto[TlIntgErrBoth] | 107 | 1 | T50 | 2 | T81 | 3 | T123 | 6 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |