Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	239078	1		T2	25		T8	8		T6	8
full_word	524977	1		T2	11		T8	24		T6	6

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	763745	1		T2	36		T8	32		T6	14
auto[TlIntgErrCmd]	101	1		T50	5		T81	4		T123	8
auto[TlIntgErrData]	107	1		T50	4		T81	4		T123	6
auto[TlIntgErrBoth]	102	1		T50	1		T81	2		T123	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	465750	1		T8	16		T6	6		T4	14
auto[1]	298305	1		T2	36		T8	16		T6	8

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER
[auto[TlIntgErrBoth]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	186307	1		T8	8		T6	2		T4	4
auto[TlIntgErrNone]	partial	auto[1]	52484	1		T2	25		T6	6		T4	57
auto[TlIntgErrNone]	full_word	auto[0]	279313	1		T8	8		T6	4		T4	10
auto[TlIntgErrNone]	full_word	auto[1]	245641	1		T2	11		T8	16		T6	2
auto[TlIntgErrCmd]	partial	auto[0]	36	1		T50	1		T81	1		T123	2
auto[TlIntgErrCmd]	partial	auto[1]	56	1		T50	2		T81	3		T123	6
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T128	1		T129	1		T130	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1		T50	2		T128	1		T131	2
auto[TlIntgErrData]	partial	auto[0]	47	1		T50	3		T81	1		T123	1
auto[TlIntgErrData]	partial	auto[1]	51	1		T50	1		T81	2		T123	5
auto[TlIntgErrData]	full_word	auto[0]	5	1		T132	1		T133	1		T134	2
auto[TlIntgErrData]	full_word	auto[1]	4	1		T81	1		T135	1		T136	2
auto[TlIntgErrBoth]	partial	auto[0]	39	1		T50	1		T81	1		T123	1
auto[TlIntgErrBoth]	partial	auto[1]	58	1		T81	1		T123	5		T137	3
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T137	2		T128	1		T138	1