Module Definition
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Module Instance : tb.dut.u_reg_regs.u_chk.u_tlul_data_integ_dec.u_data_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_tlul_data_integ_dec


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.tl_adapter_host_sba.u_rsp_chk.gen_rsp_data_intg_check.u_tlul_data_integ_dec.u_data_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 gen_rsp_data_intg_check.u_tlul_data_integ_dec


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk.u_tlul_data_integ_dec.u_data_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_tlul_data_integ_dec


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_secded_inv_39_32_dec
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 160 160 100.00
Total Bits 0->1 80 80 100.00
Total Bits 1->0 80 80 100.00

Ports 4 4 100.00
Port Bits 160 160 100.00
Port Bits 0->1 80 80 100.00
Port Bits 1->0 80 80 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[38:0] Yes Yes T1,T2,T9 Yes T1,T2,T3 INPUT
data_o[31:0] Yes Yes T1,T2,T9 Yes T1,T2,T3 OUTPUT
syndrome_o[6:0] Yes Yes T1,T2,T15 Yes T1,T2,T9 OUTPUT
err_o[1:0] Yes Yes T1,T2,T9 Yes T1,T2,T15 OUTPUT

Toggle Coverage for Instance : tb.dut.u_reg_regs.u_chk.u_tlul_data_integ_dec.u_data_chk
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 160 160 100.00
Total Bits 0->1 80 80 100.00
Total Bits 1->0 80 80 100.00

Ports 4 4 100.00
Port Bits 160 160 100.00
Port Bits 0->1 80 80 100.00
Port Bits 1->0 80 80 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[38:0] Yes Yes T16,T46,T47 Yes T3,T16,T23 INPUT
data_o[31:0] Yes Yes T16,T46,T47 Yes T3,T16,T23 OUTPUT
syndrome_o[6:0] Yes Yes T16,T8,T47 Yes T16,T47,T4 OUTPUT
err_o[1:0] Yes Yes T16,T47,T4 Yes T16,T47,T4 OUTPUT

Toggle Coverage for Instance : tb.dut.tl_adapter_host_sba.u_rsp_chk.gen_rsp_data_intg_check.u_tlul_data_integ_dec.u_data_chk
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 160 160 100.00
Total Bits 0->1 80 80 100.00
Total Bits 1->0 80 80 100.00

Ports 4 4 100.00
Port Bits 160 160 100.00
Port Bits 0->1 80 80 100.00
Port Bits 1->0 80 80 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[38:0] Yes Yes T1,T2,T9 Yes T1,T2,T9 INPUT
data_o[31:0] Yes Yes T1,T2,T9 Yes T1,T2,T9 OUTPUT
syndrome_o[6:0] Yes Yes T1,T2,T15 Yes T1,T2,T15 OUTPUT
err_o[1:0] Yes Yes T1,T15,T16 Yes T1,T2,T15 OUTPUT

Toggle Coverage for Instance : tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk.u_tlul_data_integ_dec.u_data_chk
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 160 160 100.00
Total Bits 0->1 80 80 100.00
Total Bits 1->0 80 80 100.00

Ports 4 4 100.00
Port Bits 160 160 100.00
Port Bits 0->1 80 80 100.00
Port Bits 1->0 80 80 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[38:0] Yes Yes T2,T8,T6 Yes T2,T13,T8 INPUT
data_o[31:0] Yes Yes T2,T8,T6 Yes T2,T13,T8 OUTPUT
syndrome_o[6:0] Yes Yes T2,T8,T6 Yes T2,T9,T8 OUTPUT
err_o[1:0] Yes Yes T2,T9,T13 Yes T2,T8,T6 OUTPUT

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